JP3302937B2 - Video signal switching circuit and video signal switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for switching video signals.

[0002]

2. Description of the Related Art At present, for example, in satellite broadcasting, a program is broadcast by a video signal of a multi-video format (a plurality of video formats). 12G in Japanese satellite broadcasting
The standard television (digital subcarrier N
TSC system) Broadcasting and Hi-Vision (MUSE system)
Broadcasting is taking place.

[0003] Also, video signals from external devices such as VTRs and DVDs include signals in a plurality of video formats (systems). Therefore, the conventional video receiving apparatus may not be able to normally display a screen with the received video signal. Here, a conventional technique will be described.

FIG. 5 is a diagram showing a configuration of a conventional component signal input correspondence switching circuit. In FIG. 5, reference numeral 101 denotes an output unit. The output unit 101 displays an image, and is, for example, a CRT or an LCD. 102 is a signal processing circuit. The signal processing circuit 102 converts the input component signal (for example, composed of a Y signal, an RY signal, and a BY signal) into a signal to be displayed on the output unit 101, and outputs the signal. This is output to the unit 101.

[0005] Reference numeral 105 denotes a color demodulation circuit. Color demodulation circuit 1
Numeral 05 converts an input composite (or YC) signal into a component signal and outputs it. 13
0 is an input unit. The input unit 130 receives information from the user to switch the video signal, and is, for example, a push button switch, a mouse, or the like.

Reference numeral 131 denotes a CPU. The CPU 131
The control is performed to switch the video input from the outside to the video desired by the user based on the information indicating that the video signal input to the input unit 130 by the user is to be switched. 1
32 is a synchronization separation circuit. The synchronization separation circuit 132 separates a synchronization signal from an input component signal, and outputs the synchronization signal to the output unit 101.

137 is an external input terminal. The external input terminal 137 is a terminal to which a multi-format video signal is supplied from outside. Here, it is assumed that the external input terminal 137 is supplied with a component signal from the outside. 138 and 139 are external input terminals.
The external input terminal 138 and the external input terminal 139 are terminals to which a composite (or YC) signal which is a video signal of a predetermined format is supplied from outside.

Reference numeral 106 denotes a switch (SW). SW1
Reference numeral 06 includes an a terminal, a b terminal, and a common e terminal, and the e terminal is a SW (switch) connected to either the a terminal or the b terminal. And the CPU 131
SW 106 receives the instruction (control) from
The terminal is connected to the terminal, or the terminal e is connected to the terminal b. The external input terminal 137 is connected to the terminal a. b
A component signal output from the color demodulation circuit 105 is connected to the terminal. The e terminal is connected to the signal processing circuit 102 and the synchronization separation circuit 132.

Reference numeral 107 denotes a SW (switch). SW1
07 is a SW (switch) connected to a c terminal, a d terminal, and a common f terminal, and the f terminal is connected to either the c terminal or the d terminal. And the CPU 131
SW 107 receives the instruction (control) from
The terminal is connected to the terminal, or the terminal f is connected to the terminal d. The external input terminal 138 is connected to the terminal c. d
An external input terminal 139 is connected to the terminal. And f
The terminal is connected to the color demodulation circuit 105.

Next, the operation of a circuit for switching a component signal in the conventional video receiving apparatus will be described. For example, when displaying the component signal supplied to the external input terminal 137, the user needs to
Is transmitted to the CPU 131 via the external input terminal 137 via the. CP that received the information
U131 instructs SW106 to connect the e terminal of SW106 to the a terminal. Thereby, the signal processing circuit 10
The component signal of the external input terminal 137 is supplied to the second and the sync separation circuit 132 via the SW 106, and an image is displayed on the output unit 101.

When displaying a composite signal (for example, a signal from a VTR) supplied to the external input terminal 138, the user inputs, via the input unit 130, information indicating switching to the signal of the external input terminal 138 to the CPU 131. Send to Upon receiving the information, the CPU 131 switches SW10
7, the terminal f of the SW 107 is connected to the terminal c. Thus, the composite signal supplied to the external input terminal 138 is supplied to the color demodulation circuit 1 via the SW 107.
05 is input. Then, the CPU 131 sets the SW 106
To connect the e terminal of the SW 106 to the b terminal.
Thereby, the signal processing circuit 102 and the synchronization separation circuit 1
32, the component signal of the external input terminal 138 is supplied via the SW 106, and the output unit 101 displays an image.

[0012]

However, there are cases where the video receiving apparatus receives a television signal of a broadcast system that cannot be decoded and a signal of an external device that cannot be decoded. In this case, when a component signal that cannot be decoded by the signal processing circuit 102 and the synchronization separation circuit 132 is input, the signal processing circuit 102 and the synchronization separation circuit 13
Circuit operation is not performed normally because 2 cannot be decoded.
Display on the output unit 101 is not performed normally. Therefore, conventionally, the user has confirmed the abnormality of the screen display of the output unit 101,
It is determined that the signal cannot be decoded by the video receiver. Then, as a result of the determination, the user cannot decode with the signal, and the display cannot be normally displayed on the screen. Switching to a signal that can be displayed.

For this reason, in this prior art, since the user checks the screen state by himself and switches to a signal that can be decoded by manual operation, an unnecessary state such as video muting occurs on the screen. The present invention, when receiving the component signal of the television signal or an external device of the signal broadcasting system that can not be decoded, it is an object to provide a switching technique of the video signal to eliminate unnecessary operations and unwanted screen state .

[0014]

An object of the present invention is to provide a multi-video format video signal which is input to an output unit.
A video signal switching circuit in a device for displaying
The video signal switching circuit, and a control unit, the multi-image
A component signal, which is a video signal
The output section displays the input terminals and component signals.
Signal processing that converts the signal into a signal that can be displayed and outputs the signal to the output unit
Circuit and the components that this signal processing circuit can decode.
Storage means information of the frequency of the cement signal is stored, the
The video signal of the multi video format is NTSC, P
Down-converted to AL or SECAM
A signal is input, and the input signal is
A color demodulation circuit that converts the signal into a signal and outputs the signal, and the color demodulation circuit
And the component signal output from
The component signal output from the
Signal of the input signal specified by the signal
To the signal processing circuit, and the terminal
Input the component signal output via
HD pulse from the force the component signal (Horiz
internal driving pulse: horizontal drive pulse
Luz) separating, before Symbol control hand the HD pulses this separation
Separation means for outputting to a stage, wherein the control means comprises:
The HD pulse output from the separation means is input, and this input
Counting the the HD pulse, the frequency of the HD pulse
Means for detecting, and the component signal
Or the information of the frequency of issue said storage means et read, the read
Of the detected frequency and the frequency of the detected HD pulse
Based of the information, means for determining whether it is possible to decode the component signal, the result of the determination, if it is determined that can be decoded, is input from the terminal
A control signal designating a component signal is output to the switch , and as a result of the determination, when it is determined that the component signal cannot be decoded, the color demodulation circuit outputs
Means for outputting a control signal specifying the input component signal to said switch.
This is solved by a video signal switching circuit .

[0015]

[0016] In particular, the separating means may include the input con- troller.
VD pulse (Vertical D)
separating the driving pulse (vertical drive pulse)
And outputs the separated VD pulse to the control means.
Means for detecting the frequency of the HD pulse
, The control means is outputted from said separating means VD
Enter the pulse, in response to the input the VD pulse, before
Means for detecting the frequency of the HD pulse within the vertical retrace interval
It is . Further, the video signal switching circuit includes a multi video
Format video signals can be converted to NTSC, PAL or
It is characterized by having means for down-converting to the SE CAM system . Further, the video signal switching circuit, Mar
Has a receiving means for receiving video signals in the
It is characterized by doing.

Accordingly, when a television signal of a broadcast system which cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted.

[0018]

[0019]

Alternatively, the above-described problem is solved by the video signal switching circuit.
Using the road, a video signal switching method for outputting a video signal, the video signal of the input multi-picture format
From a certain component signal , an HD pulse (Horizo
ntal Driving pulse: Horizontal driving pal
) And VD pulse (Vertical Driven)
g pulse : vertical drive pulse), the control means counts the HD pulse immediately after the VD pulse a predetermined number of times, and detects the frequency of the HD pulse, and the control means decodes the component signal which can be decoded.
The frequency information of the signal is read from the storage means, and the read
And the frequency of the information, information of frequency of HD pulse that the detected
Determining whether the component signal can be decoded , based on the information, and, if the result of the determination is that the component signal can be decoded , holding the component signal that is the input multi-video format video signal
And if the result of the determination is that decoding is not possible, the input multi-video format
Format video signal is NTSC, PAL or S
A component downconverted to ECAM format
To the component signal and switch to the component signal
It is solved by the video signal switching method characterized by a step of outputting Te.

Thus, when a television signal of a broadcast system which cannot be decoded or a component signal of a signal of an external device is received, unnecessary operations and unnecessary screen states can be omitted.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described. FIG. 1 is a diagram showing the configuration of the component signal input corresponding switching circuit of the first embodiment. In FIG. 1, reference numeral 1 denotes an output unit. The output unit 1 displays an image.
RT or LCD.

Reference numeral 2 denotes a signal processing circuit. Signal processing circuit 2
Is the input component signal (eg, Y signal,
(Composed of the RY signal and the BY signal) into a signal to be displayed on the output unit 1, and the signal is output to the output unit 1.
Is output to Reference numeral 3 denotes a multi-horizontal-frequency-corresponding synchronization separation circuit. Multi-horizontal frequency compatible sync separation circuit 3
Is to separate a synchronization signal from component signals having different input frequencies and output the synchronization signal to the output unit 1. When a component signal is input to the multi-horizontal-frequency-corresponding sync separation circuit 3, an HD pulse (Horizontal Driving pulse
e: horizontal drive pulse) and VD pulse (Vertical Driv
ing pulse: vertical drive pulse) is separated and output.

Reference numeral 4 denotes a CPU (central processing unit). CP
U4 has storage means and counter means for counting the pulses input to the CPU 4 and detecting the frequency of the pulses based on the counted number and the count time. Therefore, the CPU 4 includes a multi-horizontal frequency-compatible synchronization separation circuit 3.
The HD pulse and the VD pulse output from are input. Then, the CPU 4 causes the counter means to count the HD pulse immediately after the VD pulse to detect the frequency of the HD pulse. Further, the CPU 4 stores an upper limit value and a lower limit value of a frequency (frequency of the HD pulse) at which the signal processing circuit 2 can decode.

Reference numeral 5 denotes a color demodulation circuit. The color demodulation circuit 5
This is a color demodulation circuit for a composite (or YC) signal. The color demodulation circuit 5 receives the input composite (or
YC) signal is converted into a component signal and output. Reference numeral 6 denotes a SW (switch). SW6 is a
A terminal, a b terminal, and a common e terminal, and e
The terminal is a SW connected to either the a terminal or the b terminal
(Switch). The SW 6 is connected to the CPU 4, and upon receiving an instruction from the CPU 4, the SW 6 sets the e terminal to a
The terminal is connected to the terminal, or the terminal e is connected to the terminal b. The component signal output from the color demodulation circuit 5 is connected to the terminal b of the SW 6. Further, the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 are connected to the e terminal of the SW 6.

Reference numeral 7 denotes a SW (switch). SW7 is
It comprises a c terminal, a d terminal, and a common f terminal,
The f terminal is connected to either the c terminal or the d terminal.
W (switch). The SW 7 is connected to the CPU 4, and upon receiving an instruction from the CPU 4, the SW 7 connects the f terminal to the c terminal or connects the f terminal to the d terminal. The f terminal of SW7 is connected to the color demodulation circuit 5.

Reference numeral 10 denotes an external input terminal. The external input terminal 10 is a terminal to which a component signal which is a video signal of a multi video format is supplied from outside.
The external input terminal 10 is connected to the terminal a of the switch SW6. Note that, for the sake of specific description, it is assumed that a component signal has already been input to the external input terminal 10 from the outside.

Reference numeral 11 denotes an external input terminal. The external input terminal 11 is connected to an NTSC system, a PAL system, and an SE
A composite signal or a YC signal (a composite signal is a video signal of a predetermined format in the CAM system)
Y: a terminal for supplying a luminance signal and C: a signal separated into a color signal). And the external input terminal 11
Connected to terminal c of SW7. Here, for the sake of specific description, it is assumed that a downconverted NTSC composite signal having the same content as the component signal of the external input terminal 10 is input to the external input terminal 11.

Reference numeral 12 denotes an external input terminal. The external input terminal 12 is externally supplied with NTSC, PAL, and SEC
A terminal for supplying a composite signal or a YC signal in the AM system. And the external input terminal 12
Connected to d side of SW7. Next, the operation of the first embodiment will be described. As an initial setting, the external input terminal 11
The component signal is downconverted to N
Information indicating that the composite signal of the TSC system is connected is stored in the storage unit of the CPU 4.

FIG. 2 is a diagram showing a flowchart of the first embodiment. First, the CPU 4 sets the e terminal to a
Instruct SW6 to connect to the terminal. The SW 6 receiving this instruction connects the e terminal to the a terminal. As a result, the component signal of the external input terminal 10 is input to the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 via the SW 6 (step S1).

The multi-horizontal frequency synchronous separation circuit 3 to which the component signal of the external input terminal 10 is inputted.
Separates the HD pulse and the VD pulse from the component signal and outputs it to the CPU 4. Upon receiving the HD pulse and the VD pulse, the CPU 4 causes the counter means of the CPU 4 to count the HD pulse immediately after the VD pulse several times, and to detect the frequency of the HD pulse within the vertical retrace period (step S2). .

Then, the CPU 4 determines the detected frequency of the HD pulse and the upper limit value and the lower limit value of the frequency (frequency of the HD pulse) which can be decoded by the signal processing circuit 2 and stored in the storage means of the CPU 4. Based on this, it is determined whether or not the signal processing circuit 2 can decode (hereinafter, also referred to as frequency determination) (step S3). When the signal processing circuit 2 determines that decoding can be performed as a result of the frequency determination, the CPU 4 sets the terminal e, which is the current state, to a
Keep the state connected to the terminal. That is, the component signal of the external input terminal 10 is kept in a state of being input to the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 from the e terminal of SW6. Then, the component signal is converted into a signal to be displayed on the output unit 1 based on the component signal by the signal processing circuit 2 and output to the output unit 1. The component signal is converted into a synchronization signal for display on the output unit 1 based on the component signal by the multi-horizontal frequency synchronization separation circuit 3 and output to the output unit 1. Then, the video of the component signal supplied to the external input terminal 10 is displayed on the output unit 1 (step S4).

If the signal processing circuit 2 determines that decoding is not possible as a result of the frequency discrimination, the CPU 4 transmits the component signal to the external input terminal 11 stored in the storage means in an NTSC composite. The terminal b and the terminal e are connected to SW6 based on the information that the signal is connected, and c is connected to SW7.
An instruction is output to each of the terminals to connect the terminal and the f terminal. Here, the timing for outputting the instruction is determined by the CPU.
4, the next input HD pulse is the trigger timing. As a result, a downconverted NTSC composite signal having the same content as the component signal of the external input terminal 10 connected to the external input terminal 11 is connected to the color demodulation circuit 5 via the SW7. Then, the NTSC composite signal is converted into a component signal by the color demodulation circuit 5. The converted component signal is connected to the signal processing circuit 2 and the multi-horizontal frequency synchronization separation circuit 3 via the SW 6. Then, the component signal connected to the signal processing circuit 2 is converted into a signal to be displayed on the output unit 1 by the signal processing circuit 2 and output to the output unit 1.
Further, the component signals connected to the multi-horizontal frequency synchronous separation circuit 3 are subjected to synchronous separation of the HD pulse and the VD pulse by the multi-horizontal frequency synchronous separation circuit 3 and output to the output unit 1. The output unit 1 performs a display based on the signals output from the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3 (step 5).

Thus, even when a component signal that cannot be decoded is input, a signal obtained by down-converting the component signal can be displayed. When a component signal that can be decoded by performing the above-described steps (1 to 5) at predetermined intervals is input, the component signal is displayed. When a component signal that cannot be decoded is input, the component signal is displayed. Can display the downconverted signal.

Next, a second embodiment will be described. FIG. 3 is a diagram illustrating a configuration of a component signal input correspondence switching circuit based on video format identification information according to the second embodiment. In the description of the second embodiment, a description of the same parts as in the first embodiment will be omitted, and only different parts will be described.

In FIG. 3, reference numeral 8 denotes a multi-video format receiving circuit. The multi-video format receiving circuit 8 receives video signals having different frequencies, demodulates the video signals into component signals, and outputs the component signals. Further, the multi-video format receiving circuit 8 outputs to the CPU 4 a format identification signal that is format identification information for identifying the type of the format of the received video signal.

Reference numeral 9 denotes a down-converter circuit. The down converter circuit 9 is a multi video format receiving circuit 8
Supplies a component signal, and down-converts the component signal into a composite signal of NTSC / PAL / SECAM signal or YC signal. The multi-video format receiving circuit 8 is connected to the a terminal of the SW 6 and supplies a component signal to the a terminal of the SW 6. The multi video format receiving circuit 8 is connected to the down converter circuit 9 and supplies a component signal to the down converter circuit 9.

The down-converter circuit 9 is connected to the terminal c of the switch SW7 and outputs a composite signal or a YC signal to the terminal c of the switch SW7. Next, the operation of the second embodiment will be described. Multi video format receiving circuit 8
Is supplied to the terminal a of the SW 6 and the down-converter circuit 9.

The down-converter circuit 9 down-converts the input signal into a composite signal of NTSC / PAL / SECAM signal or YC signal, and outputs the down-converted signal to the terminal c of SW7. Here, the signal output from the down converter circuit 9 is NT
It is assumed to be an SC composite signal. The CPU 4 determines whether or not the signal processing circuit 2 can decode based on the format identification signal received from the multi-video format receiving circuit 8.

When the signal processing circuit 2 determines that decoding can be performed, the CPU 4 sets SW6 to SW6.
An instruction is output to connect the e terminal 6 to the a terminal. Upon receiving the instruction, the SW 6 connects the e terminal to the a terminal. Thus, the component signal supplied from the multi-video format receiving circuit 8 is converted into a signal for display on the output unit 1 based on the component signal by the signal processing circuit 2 via the SW 6 and output to the output unit 1. .
The component signal is converted into a synchronization signal for display on the output unit 1 based on the component signal by the multi-horizontal frequency synchronization separation circuit 3 and output to the output unit 1.

If the signal processing circuit 2 determines that decoding is not possible, the CPU 4 outputs the NTSC composite signal obtained by down-converting the component signal to the terminal c of SW7 stored in the storage means. Are output to SW6 to connect the b terminal side and the e terminal side, and SW7 to the SW terminal to connect the c terminal side and the f terminal side. Thus, the downconverted NTSC composite signal having the same content as the component signal supplied from the multi-video format receiving circuit 8 is connected to the color demodulation circuit 5 via the downconverter circuit 9 and SW7. Then, the NTSC composite signal is converted into a component signal by the color demodulation circuit 5. The converted component signal is connected to the signal processing circuit 2 and the multi-horizontal frequency synchronization separation circuit 3 via the SW 6. Then, the component signal connected to the signal processing circuit 2 is converted into a signal to be displayed on the output unit 1 by the signal processing circuit 2 and output to the output unit 1. Further, the component signals connected to the multi-horizontal frequency synchronous separation circuit 3 are subjected to synchronous separation of the HD pulse and the VD pulse by the multi-horizontal frequency synchronous separation circuit 3 and output to the output unit 1. The output unit 1
The display is performed based on the signals output from the signal processing circuit 2 and the multi-horizontal frequency synchronous separation circuit 3.

Next, a third embodiment will be described. FIG. 4 is a diagram illustrating a configuration of a component signal input corresponding switching circuit according to the third embodiment. In the description of the third embodiment, a description of parts similar to those of the first embodiment and the second embodiment will be omitted, and only different parts will be described.

The CPU 4 receives a VD pulse and an HD pulse from the multi-horizontal frequency sync separation circuit 3 and a video format identification signal from the multi-video format receiving circuit 8. When the video format identification signal is input from the multi video format receiving circuit 8, the CPU 4 determines whether or not the signal processing circuit 2 can decode based on the video format identification signal.

When the video format identification signal is not input from the multi video format receiving circuit 8, the CPU 4 determines whether or not the signal processing circuit 2 can decode the signal from the multi-horizontal frequency sync separation circuit 3. The determination is made based on the received VD pulse and HD pulse.

[0045]

As described above, according to the present invention, unnecessary operations by the user can be eliminated, and unnecessary screen states (video mute) can be eliminated. In a broadcast such as a digital broadcast in which the video format changes depending on the time zone, the user does not need to switch the signal during viewing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a component signal input correspondence switching circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of a first embodiment according to the present invention.

FIG. 3 is a diagram showing a configuration of a component signal input correspondence switching circuit based on video format identification information according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a component signal input corresponding switching circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional component signal input correspondence switching circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Output part 2 Signal processing circuit 3 Multi-horizontal frequency synchronous separation circuit 4 CPU 5 Color demodulation circuit 6, 7 SW (switch) 8 Multi video format receiving circuit 9 Down converter circuit 10, 11, 12 External input terminal

Claims (5)

(57) [Claims] (1)Multi videoFormat video signal
EmpoweredAnd display the video on the output unitProjection on equipment
An image signal switching circuit,The video signal switching circuit, Control means; A component which is a video signal of the multi
Input signal Terminals Convert component signals to signals that can be displayed by the output unit
The output unit A signal processing circuit for outputting the Component signal that this signal processing circuit can decode
Frequency information A stored storage means; The video signal of the multi video format is NTSC
Formula, PAL system or Down converted to SECAM system
The input signal is input and this input Compose the signal
A color demodulation circuit for converting the A component signal output from the color demodulation circuit;
Through the terminal The output component signal
Input by the control signal. Of the signals
Switch for outputting the signal obtained by the signal processing to the signal processing circuit
When , Input the component signal output through the terminal
And this entered HD pulse from component signal
(Horizontal Driven g pulses
e: horizontal drive pulse) and the separated HD pulse
In front of Separation means for outputting to the control means, The control means includes: The HD pulse output from the separation means is input, and
HD pal input And count the frequency of the HD pulse.
Means for detecting the number; Information on the frequency of the component signal that can be decoded
Is the storage means And read the frequency information
And the frequency of the detected HD pulse Based on the information
And the component signal Determine if decoding is possible
InterruptionMeans to Said Judgment result,If you determine that you can decode,Previous
Input from the Component signalSystem to specify
Control signal to the switch, and the result of the judgment,
Component signalWhen it is determined that decoding is not possible
IsComponent signal input from the color demodulation circuit
Means for outputting a control signal specifying
A video signal switching circuit, comprising: (2)The separation means, From the input component signal, a VD pulse (Ve
rtical D driving pulse: vertical drive
Pulse) and the separated VD Pulse control
Means for outputting to the means, The means for detecting the frequency of the HD pulse includes: The control means outputs the VD pallets output from the separation means.
Enter this In response to the input VD pulse,
The frequency of the D pulse Within the vertical retrace intervalMeans to detect
ToThe video signal switching circuit according to claim 1, wherein
Road. 3. The video signal switching circuit converts a video signal of a multi-video format into an NTSC system,
Hand to down convert to AL system or SE CAM system
The video signal switching circuit according to claim 1 or 2, further comprising a stage . (4)The video signal switching circuit,  Receiving means for receiving a video signal in a multi-video format
Characterized by havingAny of claims 1 to 3
Described inVideo signal switching circuit. Claim 5.The image according to any one of claims 1 to 4.
Using the image signal switching circuit,Video signal to output video signal
A switching method,Entered Multi-video format video signalWhich is
Component signalTo HD pulse(Horizonta
l Driving pulse: Horizontal driving pulse Lus)
And VD pulse (Vertical Driving)
pulse:Vertical drive pulse), andControl means, The HD pulse immediately after the VD pulse is counted a predetermined number of times.
Counting, and detecting the frequency of the HD pulse;The control means outputs a component signal which can be decoded.
Frequency information is read from the storage means, and the read frequency
Number information and said Frequency of detected HD pulseInformation and
Based on the component signalCan you decode
Determining whether or not decoding is possible, if it is determined that decoding is possible,Previous
EnteredMulti-video format video signalIs
Component signalRetentionAnd output it,  If it is determined that decoding cannot be performed,
When the input video signal of the multi-video format is N
Downgrade to TSC, PAL or SECAM
Convert the converted signal to a component signal,
For component signalsswitchingOutput processWith
A video signal switching method.