JP3300412B2 - Image playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reproducing apparatus, and more particularly to an image reproducing apparatus capable of reproducing and displaying a still image of high quality.

[0002]

2. Description of the Related Art A still video camera capable of recording and reproducing a still image using a video floppy is known.
An example of a technology for recording and reproducing a still image of a high definition, for example, a 1000-pixel × 1000-pixel level (hereinafter, referred to as an HD level) using a video floppy is described in the ITEJ Technical Report. Vol. 14,
No.76, PP.1-6, CE'90-97, DEC, 1990, ITEJ Technical Re
port Vol. 14, No. 76, PP. 7-12, CE'90-98, DEC, 1990).

According to the above prior art, it is difficult to record all pixel data of the HD level on the video floppy due to the characteristics of the video floppy, so that the pixel data of the sub-sampled pixel (hereinafter referred to as a transmission pixel) is obtained. Only the video floppy is recorded. That is, pixels constituting a still image of one frame of HD level are sub-sampled by a predetermined sampling pattern,
Pixel data of the sub-sampled pixels is recorded on four tracks of the video floppy.

At the time of reproduction, pixel data of a transmission pixel is reproduced, and based on this pixel data, pixels that are thinned without being sampled (hereinafter referred to as non-transmission pixels).
Are interpolated. As a result, a still image of one frame at the HD level can be restored.

[0005]

In such a conventional image reproducing apparatus, much time is required for the interpolation processing. In general, in a still video camera, the process of recording / reproducing must be considered as a sample value analog transmission system, so that not only interpolation processing but also waveform equalization is required, which takes time. During this time, there is a problem that the image cannot be displayed on the monitor, and it is impossible to search for another desired image. For this reason, there is a problem that a user feels a long time for the interpolation processing and the waveform equalization.

An object of the present invention is to provide an image reproducing apparatus capable of retrieving and displaying an arbitrary image during interpolation processing.

[0007]

According to a first aspect of the present invention, there is provided an image reproducing apparatus for reproducing a video signal from a recording medium on which a sub-sampled video signal is recorded, and for holding the video signal as pixel data. And a means for selectively outputting pixel data from the storage means, wherein the storage means controls writing and reading of the pixel data independently. First storage means and second storage means, wherein the first storage means holds supplied pixel data, and the second storage means stores at least one of the supplied pixel data. It is configured to control so as to selectively hold the sections.

[0008] An image reproducing apparatus according to a second aspect is the first aspect.
The image reproducing apparatus according to claim 1, wherein the first storage unit includes:
The pixel data of the transmission pixel is written to an address corresponding to the position of the transmission pixel, and the pixel data of the transmission pixel is sequentially written in the second storage unit.

According to a third aspect of the present invention, there is provided an image reproducing apparatus.
The image reproducing apparatus described above, wherein the vertical and horizontal length of an image formed by the pixel data of the transmission pixel read from the second storage means is reduced and displayed at the same ratio.

According to a fourth aspect of the present invention, there is provided an image reproducing apparatus.
The image reproducing apparatus according to claim 1, wherein a frequency of a pixel data read clock signal for said second storage means is set to a predetermined ratio with respect to a frequency of a pixel data read clock signal for said first storage means. I have. Contract
The image reproducing apparatus according to claim 5, wherein the sub-sampled
The above video signal is transferred from the recording medium on which the video signal is recorded.
Means for reproducing, and holding the video signal as pixel data
Storage means for selectively outputting pixel data from the storage means.
An image reproducing apparatus comprising:
The storage means controls writing and reading of the pixel data.
Storage means and second storage means in which
And the first storage means stores the supplied pixel data.
And the second storage means stores the supplied pixel data.
Control to selectively retain at least part of the data
The first storage means stores the pixel data of the transmission pixel.
Data to the address corresponding to the position of the transmission pixel.
The second storage means stores the pixel data of the transmission pixel.
Are sequentially written. Claim 6
The image reproducing apparatus according to
To reproduce the video signal from the recording medium on which the signal is recorded.
Means for converting the video signal reproduced from the recording medium
First and second storage means for holding as data,
The pixel based on the pixel data held in the first storage means
A pixel data interpolation means for performing data interpolation processing;
The video signal reproduced for the search is stored in the second storage means.
Search image supply means for supplying as pixel data,
In the first and second storage means, the pixel data
Write and read control is performed independently
I have.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and 2 show the configuration of the main part of an image reproducing apparatus according to one embodiment of the present invention.

In the configuration shown in FIG.
2, the recording medium 13, for example, a video floppy, is driven to rotate. A video signal reproduced from the recording medium 13 by the magnetic head 14 passes through the reproduction amplifier 15 and outputs a luminance signal reproduction processing circuit 16 of the luminance system 45, an RY signal reproduction processing circuit 116 of the RY system 145, and a BY system. 24
5 is supplied to the BY signal reproduction processing circuit 216. In the following description, the luminance system 45 will be mainly described. The drive of the spindle motor 12 is controlled by a driver 33.

In the video floppy as the recording medium 13, a video signal of one field is recorded over two tracks. Therefore, the video signal of one frame is recorded over four tracks.

The luminance signal reproduction processing circuit 16 performs processes such as limiter, FM demodulation, and de-emphasis on the reproduced video signal. This luminance signal reproduction processing circuit 1
The video signal output from 6 is supplied to an A / D conversion circuit 17 and a synchronization signal separation circuit 18.

In the A / D conversion circuit 17, a video signal is converted into a digital signal, and pixel data is formed. This pixel data is supplied to the main memory 20 and the search memory 21. On the other hand, in the synchronizing signal separation circuit 18, a vertical synchronizing signal, a horizontal synchronizing signal, a burst signal, and the like are separated from the video signal, and the synchronizing signal and the burst signal are supplied to the clock reproducing circuit 41. In the clock recovery circuit 41, based on the supplied synchronization signal and burst signal,
The clock signal is reproduced, and the clock signal is supplied to the memory control circuit 22 and the system control circuit 23.

The system control circuit 23 is a block for controlling the entire image reproducing apparatus. The system control circuit 23 controls each circuit block. A key switch 25 is connected to the system control circuit 23. When the key switch 25 is operated by a user, a signal corresponding to the key operation is supplied to the system control circuit 23. The system control circuit 23 controls the operation of the entire image reproducing apparatus based on this signal. Based on the control of the system control circuit 23,
The aforementioned driver 33 is controlled.

As shown in FIGS. 3 and 4, the main memory 20 is composed of a memory 20a for storing pixel data of the first field and a memory 20b for storing pixel data of the second field. Memory 20a, 2
0b is for holding the pixel data constituting the high-definition image such as the HD level described above.

In these memories 20a and 20b, FIG.
As shown in FIG. 4 and FIG. 4, the pixel data of the transmission pixel represented by the mark “あ る い は” or “X” is written into the address corresponding to the position of the sampled pixel. Further, the interpolated pixel data is written in the address corresponding to the position of the non-transmission pixel represented by the mark.

The memory control circuit 22 includes a main memory 2
0, a timing signal and a control signal for writing and reading, necessary address data, and the like are supplied to the search memory 21, the A / D conversion circuit 17, the D / A conversion circuit 27, the interpolation processing circuit 28, and the like. Thus, the operation of each circuit block described above is controlled.

The memory control circuit 22 uses a clock signal supplied from the clock reproduction circuit 41 when writing pixel data. This clock signal is supplied to the A / D conversion circuit 17, the main memory 20, the search memory 21, and the like. At the same time, a control signal for writing, address data and the like are stored in the main memory 20 and the search memory 21.
Supplied to As a result, the above-described pixel data is written in the main memory 20 and the search memory 21.

In the memory control circuit 22, when interpolating or reading out pixel data, the synchronization signal generating circuit 2
9 is used. This clock signal is supplied to the main memory 20, the search memory 21, the interpolation processing circuit 28, the D / A conversion circuit 27, and the like.
At the same time, control signals and address data for interpolation or reading are stored in the main memory 20 and the search memory 21.
Supplied to

Thus, for example, at the time of the interpolation processing, based on the pixel data read from the main memory 20,
Interpolation processing of non-transmission pixels is sequentially performed by the interpolation processing circuit 28. The pixel data subjected to the interpolation processing is supplied to the main memory 20 and is taken into the main memory 20.

At the time of reading pixel data, the pixel data of the transmission pixel and the interpolated pixel are read from the main memory 20, and the pixel data of the transmission pixel are read from the search memory 21, and are subjected to D / A conversion. The signal is supplied to the circuit 27.

The main memory 20 and the search memory 2
The control of writing and reading of pixel data for 1 is independently performed by the memory control circuit 22 under the control of the system control circuit 23. Accordingly, the search memory 21 can be independently controlled while the pixel data of the non-transmitted pixel is subjected to the interpolation processing in the interpolation processing circuit 28.

The interpolation processing circuit 28 performs interpolation of non-transmission pixels, waveform equalization, and the like based on the control of the memory control circuit 22 described later. Then, the interpolated pixel data is supplied to the main memory 20 and is taken into the main memory 20.

In the synchronizing signal generating circuit 29, a vertical synchronizing signal and a horizontal synchronizing signal are formed, and a clock signal is formed based on these synchronizing signals. The clock signal and the synchronization signal are transmitted to the memory control circuit 22, the system control circuit 23,
The signal is supplied to the blanking / sync mix circuit 30.

The D / A conversion circuit 27 converts the pixel data into an analog video signal. This analog video signal is supplied to the blanking / sync mix circuit 30.

In the blanking / sync mix circuit 30, a vertical synchronizing signal and a horizontal synchronizing signal supplied from the synchronizing signal generating circuit 29 are added to an analog video signal to form a video signal. This video signal is sent to the signal processing circuit 31.
Is supplied to the display 32 after being subjected to impedance conversion processing. The display 32 displays an image by interlaced scanning, and can display a high-definition image such as the above-described HD level or high definition.

Next, a process in which the video signal reproduced from the recording medium 13 is written into the memory 20 and the search memory 21 and read out from the main memory 20 and the search memory 21 will be described with reference to FIGS. explain.

The pixel data of the first and second fields is written into the main memory 20. Since the pixel data is sub-sampled, each pixel data is written at an address corresponding to the position of each sampled pixel. FIG. 3 shows a state of arrangement of transmission pixels and non-transmission pixels in the first field in the memory 20a.
FIG. 4 shows the arrangement of the transmission pixels and the non-transmission pixels in the second field in the memory 20b.

3 to 7, in the Y-axis direction, a field F (i) (i = 1, 2) and a horizontal scanning line H (i) (i
= 1 to 472) are displayed as a pair, and pixels PD (i) (i = 1) in each horizontal scanning line H (i) are displayed in the X-axis direction.
1024).

The transmission pixel taken into the memory 20a is
As shown in FIG. 3, in each horizontal scanning line H (i) in the first field F (1), an odd-numbered pixel PD (i) (i = 1, 3, 5,. , 1023). Then, the non-transmission pixels correspond to the first field F in FIG.
In each horizontal scanning line H (i) in (1), an even-numbered pixel PD (i) (i = 2, 4, 6,..., 1)
024).

The transmission pixel taken into the memory 20b is
As shown in FIG. 4, in each horizontal scanning line H (i) in the second field F (2), an even-numbered pixel PD (i) (i = 2, 4, 6,. , 1024). The non-transmitted pixels correspond to the second field F in FIG.
In each horizontal scanning line H (i) in (2), an odd-numbered pixel PD (i) (i = 1, 3, 5,..., 1)
023).

As shown in FIGS. 3 and 4, the positional relationship between the transmission pixel and the non-transmission pixel is opposite to each other between the fields. Further, as is clear from FIG. 5, the sampling pattern is in a state of a diagonal lattice. In FIG. 5, non-transmitted pixels represented by the mark are subjected to interpolation processing by the interpolation processing circuit 28 based on the pixel data of the surrounding transmitted pixels.

For example, (F (1) -H (2), PD
Non-transmission pixels in (4)) are (F (1) -H (2),
PD (3)), (F (1) -H (2), PD (5)),
(F (2) -H (1), PD (4)), (F (2) -H
(2), PD (4)). The pixel data obtained by this interpolation is taken into the main memory 20 and held. By this interpolation processing, pixel data of one frame shown in FIG. 5 is formed.

FIG. 5 shows a state in which pixel data stored in the main memory 20 is projected on the display 32. On the display 32, an image is displayed by interlaced scanning. Therefore, first,
In the first field, an image based on the pixel data of the transmission pixel and the interpolated pixel is displayed. Next, in the second field, an image based on the pixel data of the transmission pixel and the interpolated pixel is displayed.

When the pixel data of the transmission pixel is written in the main memory 20 under the control of the memory control circuit 22, the pixel data of the same transmission pixel is also written in the search memory 21. Memory control circuit 22
Of the main memory 20 and the search memory 21 are independently performed.

6 and 7, the search memory 21 is used.
In this embodiment, the capacity of (1)
/ 4), and the pixel data of the transmission pixels for one field can be written. Therefore, as shown in FIGS. 3 and 6, each horizontal scanning line H (i) (i = 1 to 4) of the first field F (1) is stored in the search memory 21.
72), the odd-numbered pixel PD (i)
Only pixel data of (i = 1, 3, 5,..., 1023) are captured as transmission pixels. The pixel data taken into the search memory 21 is recorded over two tracks of the recording medium 13.

A screen search for searching the contents of the search memory 21 will be described. When the user operates the key switch 25 to set a state for performing a screen search, a signal instructing a screen search process is supplied to the system control circuit 23.

The system control circuit 23 controls the memory control circuit 22 to perform a screen search. As described above, the memory control circuit 22 controls the main memory 20 and the search memory 21 independently, so that when the screen search is performed,
Write to search memory 21 or search memory 21
Are not limited to fields stored in the main memory 20 and subjected to interpolation processing. For example, while the pixel data of a non-transmitted pixel in a certain field is being interpolated, the pixel data of a transmitted pixel in another field can be written to the search memory 21 and sequentially read out and displayed on the display 32.

In the memory control circuit 22, the main memory 2
0, after writing the pixel data into the search memory 21,
The interpolation processing circuits 28 are independently controlled. In this interpolation processing circuit 28, interpolation processing of non-transmission pixels is performed based on the pixel data of transmission pixels supplied from the main memory 20. At the same time, the memory control circuit 2
2, a clock signal, a read signal, address data, and the like are supplied to the search memory 21, and pixel data is sequentially read from the search memory 21.

The pixel data read from the memory 21 is
The signal is converted into an analog video signal by the D / A conversion circuit 27. This analog video signal is supplied with a vertical synchronizing signal and a horizontal synchronizing signal by a blanking / sync mix circuit 30, and is supplied to a display 32 through a signal processing circuit 31. On the display 32, as shown in FIG. 7, an image formed based on the pixel data of only the transmission pixels in the first field is displayed.

In this display, as shown in FIGS. 6 and 7, for example, since an image composed of pixel data of the first field F (1) is displayed on the display 32, X
The number of pixels in the axial direction is (1/2), and the number of lines in the Y-axis direction is (1/2).
It is displayed in a reduced state at the same ratio of 2).

Hereinafter, the display of the display 32 and the screen search will be described with reference to FIGS. In step 101, a desired reproduction screen number is changed from the key switch 25 to the system control circuit 23 by a key operation of the user.
Supplied to

In this embodiment, in the direction from the outer peripheral side to the inner peripheral side of the recording medium 13, that is, the video floppy disk, a reproduction screen number is assigned to one set of four tracks. It is assumed that this playback screen number is recorded on the outermost periphery in each group.

In each set of four tracks, video signals for two fields are recorded in a direction from the outer peripheral side to the inner peripheral side of the video floppy disk. In this case, the first track on the outer peripheral side has the first track.
A video signal of the upper half of the field, a video signal of the lower half of the first field on the second track, a video signal of the upper half of the second field on the third track,
On the fourth track on the inner circumference side, the video signal of the lower half of the second field is recorded.

The system control circuit 23 controls the memory control circuit 22 to perform a screen search. In this screen search, the fields written to or read from the search memory 21 are not limited to the fields stored in the main memory 20 and subjected to the interpolation processing. For example, while the pixel data of a non-transmission pixel in a certain field is interpolated, the pixel data of another field is
, And sequentially read out and displayed on the display 32.

The system control circuit 23 controls a drive circuit (not shown). As a result, the magnetic head 14 is moved to the track on which the video signal corresponding to the desired reproduction screen number is recorded, and the video signal is reproduced.

In step 102, the reproduced video signal is converted into pixel data. Then, the pixel data is written into the main memory 20 and the search memory 21 under the control of the memory control circuit 22. In this writing, as described above, the pixel data of the transmission pixel is written in the main memory 20 in field units. Also,
In the search memory 21, for example, only the pixel data of the transmission pixel in the first field is written.

The movement of the magnetic head 14 and the reproduction of the video signal in step 101 are performed in cooperation with step 102. That is, the operation of reproducing the video signal for one track, converting it into pixel data, and writing the pixel data into the main memory 20 and the search memory 21 is repeated over four tracks. Then, the process proceeds to step 103.

In step 103, the interpolation processing circuit 28 starts interpolation processing for non-transmitted pixels and waveform equalization for analog transmission of sample values. After the pixel data is written into the main memory 20 and the search memory 21, the interpolation processing circuit 28 is controlled. In the interpolation processing circuit 28, interpolation processing of non-transmission pixels is sequentially performed based on pixel data of transmission pixels supplied from the main memory 20. The interpolation processing is performed independently based on a flowchart (not shown), but the description thereof is omitted.

In step 104, it is determined whether or not a key operation for searching for an image has been performed by the user. If an image is to be searched, step 110
The process proceeds to step 105 if the image is not searched.

In steps subsequent to step 105, processing when no image is retrieved is shown. That is, in step 105, it is determined whether or not the interpolation processing and the waveform equalization processing for all the non-transmission pixels have been completed in the interpolation processing circuit. If the interpolation and waveform equalization processing have been completed, the process proceeds to step 106, and if the interpolation and waveform equalization processing has not been completed, the process returns to step 105.

In step 106, pixel data is read from the main memory 20 with a clock signal having a predetermined frequency fRM, and is converted into an analog video signal by the D / A conversion circuit 27. As can be seen, the main memory 20
The readout of pixel data from and the D / A conversion are performed based on a clock signal having the same frequency fRM. Then, this video signal is displayed on the display 32. This ends the flow.

Step 110 is the case of searching for an image, and the processing after step 110 indicates a screen search processing. In step 110, it is assumed that the pixel data of the current field that has been subjected to the interpolation / waveform equalization processing is written in the search memory 21.

In step 110, the pixel data is read from the search memory 21 by the clock signal of the predetermined frequency fRS, and the pixel data is converted into the analog signal by the D / A conversion circuit 27 by the clock signal of the predetermined frequency fRS. It is converted to a video signal. At the same time, a clock signal, a read signal, address data, and the like are supplied to the search memory 21, and pixel data is sequentially read from the search memory 21.

The pixel data read from the search memory 21 is converted by the D / A conversion circuit 27 into an analog video signal. This analog video signal is
The vertical synchronizing signal and the horizontal synchronizing signal are added by the sync mix circuit 30 and supplied to the display 32 via the signal processing circuit 31. On the display 32, an image formed based on the pixel data of only the transmission pixels in the first field is displayed.

In this display, as shown in FIGS. 6 and 7, for example, since an image composed of pixel data of the first field F (1) is displayed on the display 32, X
The number of pixels in the axial direction is (1/2), and the number of lines in the Y-axis direction is (1/2).
2) The image is displayed in a reduced state at the same ratio.

As is clear from this, the timing of reading pixel data from the search memory 21 and the timing of D / A conversion are performed based on a clock signal of the same frequency fRS. The relationship between the predetermined frequencies fRM and fRS of the clock signal shown in this embodiment is (fRM = fRS).

In step 111, it is determined whether or not the image selected and displayed is a desired image from the state of the key operation by the user. If it is a desired image, the process proceeds to step 112, and if it is not a desired image, the process proceeds to step 121.

In step 112, the flag FCHG is set
("1") is set. Next, in step 113, the screen number corresponding to the desired image is changed from the key switch 25 to the system control circuit 2 by the key operation of the user.
3 is supplied. The system control circuit 23 controls a drive circuit (not shown). As a result, the magnetic head 14 is moved to the track on which the video signal of the desired reproduction screen number is recorded, and the video signal is reproduced.

At step 114, the reproduced video signal is converted into pixel data. Then, the pixel data is written into the search memory 21. This step 1
The movement of the magnetic head 14 and the reproduction of the video signal in steps 12 and 113 are performed in cooperation between steps 112 and 113.

That is, the operation of reproducing the video signal, converting it into pixel data, and writing the pixel data into the search memory 21 is repeated over two tracks. Therefore,
At the stage when step 114 is completed, the pixel data of the video signal for two tracks of the first field is stored in the search memory 2.
Written to 1. Thereafter, the process returns to step 110.

On the other hand, in step 121, the flag FCH
It is determined whether or not G (= 1). If the flag is FCHG (= 1), the process proceeds to step 122, and if the flag is FCHG (= 0), the process proceeds to step 1
Return to 04.

At step 122, a desired reproduction screen number is supplied from the key switch 25 to the system control circuit 23 by a key operation of the user.

The system control circuit 23 controls a drive circuit (not shown). As a result, the magnetic head 14 is moved to the outermost track among the four tracks constituting the desired screen number, and the video signal is reproduced.

In step 123, the reproduced video signal is converted into pixel data. Then, the pixel data is written into the main memory 20 and the search memory 21 under the control of the memory control circuit 22. In this writing, as described above, the pixel data of the transmission pixel is written in the main memory 20 in field units. Also,
In the search memory 21, for example, only the pixel data of the transmission pixel in the first field is written.

The movement of the magnetic head 14 and the reproduction of the video signal in step 122 are performed in cooperation with step 123. That is, the operation of reproducing the video signal for one track, converting it into pixel data, and writing the pixel data into the main memory 20 and the search memory 21 is repeated over four tracks. That is, step 101,
The same operation as 102 is performed.

In step 124, the flag FCHG (=
0), and the process returns to step 103. by this,
The flow ends.

In the above description, the luminance system 45 is mainly described, but the same processing is performed in the RY system 145 and the BY system 245 as shown in FIG. The difference between the configuration of the RY system 145 and the BY system 245 shown in FIG. 2 and the configuration of the luminance system 45 shown in FIG. 1 is as follows.

First, A / D conversion circuits 117 and 217, search memories 121 and 221 and main memories 120 and 22
A clock signal for writing pixel data to 0, search memories 121 and 221, and main memories 120 and 22.
0, and the clock signal for reading the pixel data to the D / A conversion circuits 127 and 227 are the color difference signals RY and BY.
And the frequency corresponding to.

In FIG. 2, the interpolation processing of the non-transmitted pixels is performed by the interpolation processing circuit 28 shown in FIG. The target of the signal processing is the color difference signal RY,
BY.

As described above, except for the points described above and matters related to this point, the RY system 145 and the BY system 24
The configuration and operation of 5 are almost the same as the configuration and operation of the luminance system 45. In FIG. 2, a reproduced video signal is supplied to a terminal 111. Also, terminals 135 and 23
5, the color difference signals RY and BY subjected to the signal processing are extracted and supplied to the display 32.

According to this embodiment, the main memory 20
And the pixel data of the transmission pixels in the first field F (1) or the desired field F (i) is written in the search memory 21. Then, interpolation and waveform equalization of non-transmitted pixels are performed based on the pixel data held in the main memory 20. Utilizing the time of interpolation and waveform equalization of the non-transmitted pixels, the pixel data fetched into the search memory 21 is converted into a video signal, and displayed on the display 32 by reducing the length and width in the same ratio. Therefore, it is possible to prevent the user from feeling long the time of the interpolation processing of the non-transmitted pixels and the waveform equalization.

According to this embodiment, the search memory 21
Since the pixel data of an arbitrary field can be fetched, a desired screen can be searched without losing the pixel data in the main memory 20.

9 to 11 show another embodiment. Hereinafter, the present invention will be described with reference to other illustrated embodiments.
The other embodiment differs from the above-described embodiment in the following points. In the drawings, common portions are denoted by the same reference numerals, and redundant description is omitted.

First, the search memory 21 is composed of the search memories 21a and 21b, and the capacity of the search memory 21 is set to (1/2) of that of the main memory 20. . In this case, the transmission pixels of the first field are written into the search memory 21a as shown in FIG. 9, and the transmission pixels of the second field are written into the search memory 21b as shown in FIG. .

Next, the first and second fields F
(1) The relationship between the predetermined frequencies fRS and fRM when the transmission pixels of F (2) are displayed on the display 32 can be changed.

That is, as shown in FIG. 9, in the search memory 21a, in each horizontal scanning line H (i) of the first field F (1), an odd-numbered pixel PD (i) to be a transmission pixel. (I = 1, 3, 5,..., 1023) only. In the search memory 21b, in each horizontal scanning line H (i) of the second field F (2), even-numbered pixels PD (i) (i =
2, 4, 6,..., 1024).

When the pixel data of the transmission pixel is read from the search memory 21 and the main memory 20, the relationship between the predetermined frequencies fRS and fRM of the clock signal is (fRS
= (1/2) fRM). The relationship between the predetermined frequencies fRM and fRS of the clock signal at the time of the D / A conversion in the D / A conversion circuit 27 is (fRS = fRM or fRS = (1/2) fRM).

In the display 32, the first field F
(1) The video signal is interlacedly scanned in the order of the second field F (2), whereby the display on the screen shown in FIG. 10 is performed. That is, in each horizontal scanning line H (i) of the first field F (1), the odd-numbered pixel PD (i) (i = 1, 3, 5,.
The display is performed in a state where each pixel data of 3) is held for a display period of two pixels and the video signal is elongated.

Similarly, in the second field F (2), in each horizontal scanning line H (i) of the second field F (2), an even-numbered pixel PD (i) to be a transmission pixel is used.
(I = 2, 4, 6,... 1024) each pixel data is 2
The display is performed in a state where the video signal is stretched by being held over the display period for the pixels.

According to the other embodiment, the search memory 2
The pixel data of two fields is fetched into 1 and the frequency fRS of the clock signal used for reading out the pixel data from the search memory 21 and for D / A conversion is stored in the main memory 20.
(1/2) compared to the frequency fRM of the clock signal used for reading out pixel data from the pixel and for D / A conversion, or only the frequency fRS of the clock signal for D / A conversion is equal to the frequency fRM of the clock signal. Therefore, the pixel data of one pixel can be extended and displayed in the display period of two pixels.

[0084]

As described above, according to the present invention, it is possible to prevent the user from feeling the time during which the interpolation processing of non-transmitted pixels and the waveform equalization are performed for a long time.
In addition, a desired screen can be searched without losing pixel data in the memory. Also, 1
The pixel data for the pixels can be extended and displayed in the display period for two pixels.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an image reproducing apparatus according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an image reproducing apparatus according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing patterns of a transmission pixel and a non-transmission pixel of a first field which are captured in a memory.

FIG. 4 is an explanatory diagram showing patterns of a transmission pixel and a non-transmission pixel of a second field stored in a memory.

FIG. 5 is an explanatory diagram showing patterns of transmission pixels and non-transmission pixels in first and second fields.

FIG. 6 is an explanatory diagram showing only transmission pixels of a first field taken into a search memory;

FIG. 7 is an explanatory diagram showing a display state of a search screen on a display.

FIG. 8 is a flowchart for explaining the operation of one embodiment.

FIG. 9 is a flowchart for explaining the operation of one embodiment.

FIG. 10 is an explanatory diagram of another embodiment showing only transmission pixels of a first field taken into a search memory.

FIG. 11 is an explanatory diagram of another embodiment showing only transmission pixels in a second field taken into a search memory;

FIG. 12 is an explanatory diagram of another embodiment showing a display state of first and second fields of a search screen on a display.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 13 Recording medium 14 Magnetic head 15 Reproduction amplifier 16 Luminance signal reproduction processing circuit 20, 120, 220 Main memory 20a, 20b Memory 21, 121, 221 Search memory 21a, 21b Memory 22 Memory control circuit 23 System control circuit 25 Key switch 28 Interpolation processing circuit 29 Synchronous signal generation circuit 30 Blanking / sync mix circuit 31 Signal processing circuit 32 Display

Claims (6)

(57) [Claims] 1. A means for reproducing a video signal from a recording medium on which a sub-sampled video signal is recorded; a storage means for holding the video signal as pixel data; And a means for outputting the pixel data, wherein the storage means comprises a first storage means and a second storage means for independently controlling writing and reading of the pixel data. The first storage unit stores supplied pixel data, and the second storage unit selectively stores at least a part of the pixel data supplied to the first storage unit. An image reproducing apparatus characterized by being controllable. 2. The image reproducing apparatus according to claim 1, wherein said first storage means writes pixel data of a transmission pixel at an address corresponding to a position of said transmission pixel, and said second storage means. Wherein the pixel data of the transmission pixel is sequentially written. 3. The image reproducing apparatus according to claim 2, wherein the vertical and horizontal lengths of an image formed by the pixel data of the transmission pixels read from the second storage unit are reduced at the same ratio and displayed. An image reproducing apparatus, characterized in that: 4. The image reproducing apparatus according to claim 3, wherein the frequency of the pixel data read clock signal for the second storage means is higher than the frequency of the pixel data read clock signal for the first storage means. An image reproducing apparatus characterized by being set to a predetermined ratio. 5. A sub-sampled video signal is recorded.
For reproducing the video signal from a recorded recording medium
Storage means for holding the video signal as pixel data
And means for selectively outputting pixel data from the storage means.
And an image reproducing apparatus comprising: a step for controlling the writing and reading of the pixel data;
First storage means and second storage means in which control is independently performed
Consists of a, the first storage means, storing a pixel data to be supplied
However, the second storage means stores a small amount of supplied pixel data.
Also be controlled to selectively retain a part and, said first memory means, the pixel data of the transmission pixel, said transmission
The pixel data of the transmission pixel is written in the address corresponding to the position of the pixel to be transmitted, and the pixel data of the transmission pixel is sequentially stored in the second storage unit.
Next, an image reproducing apparatus characterized by writing. 6. A sub-sampled video signal is recorded.
For reproducing the video signal from a recorded recording medium
And the video signal reproduced from the recording medium as pixel data.
First and second storage means for storing and storing pixel data based on the pixel data stored in the first storage means.
The pixel data interpolation means for performing the interpolation processing of the pixel data and the second storage means store the video signal reproduced for the search.
And a search image supply means for supplying the image data as pixel data.
In the first and second storage means, the pixel data
It is characterized in that writing and reading of data are controlled independently.
Image reproducing device.