JP3298377B2 - Clamping device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image signal processing, and more particularly to a clamp device for stabilizing the level of an image signal.

[0002]

2. Description of the Related Art In recent years, digitalization and multimedia have been advanced in television receivers for processing image signals. In this case, in order to perform stable image processing on a plurality of image signals, a clamp device that stably holds the levels of the image signals is required.

[0003] A conventional clamping device will be described below. FIG. 9A shows the configuration of a conventional clamping device.

[0004] Reference numeral 71 denotes a U clamp circuit which holds the level of the input U image signal during the clamp period at the level output from the U loop filter 75 and outputs it.

After the clamped U image signal is converted into a digital signal by the AD converter 72, the data during the clamp period is extracted and averaged in the horizontal or vertical direction by the averaging circuit 73.

Reference numeral 74 denotes a U-clamp control circuit which inputs the averaged data, compares the averaged data with reference data, and varies the duty ratio of an output pulse according to the result, and outputs the result to the U-loop filter 75. The V image signal includes a V clamp circuit 76, an AD 77, an averaging circuit 78, a V clamp control circuit 79, and a V loop filter 80.

FIG. 9B shows the configuration of a conventional clamp control circuit. A comparison circuit 711 inputs the averaged clamp data and reference data, compares the data values, and outputs a result indicating which data value is larger. Reference numeral 712 denotes a correction value creation circuit which is a comparison circuit 71.
A specific correction value is output for the result of 1. 713 is P
The WM control circuit outputs a PWM waveform that varies the duty ratio of the output pulse according to the correction value.

[0008]

However, in the above configuration, since all components are required for each image signal, if the number of image signals to be processed increases, the number of components increases as it is, thus increasing the overall circuit scale. There was a problem that it would be.

Further, the stability and the convergence time of the clamp loop are opposite to each other, and it is difficult to design them properly, and the deterioration of the stability may cause the deterioration of the image quality and the increase of the convergence time. There was a problem.

[0010] In addition, there has been a problem that vibration peculiar to the loop occurs at the clamp loop stable point, which may cause deterioration in image quality.

An object of the present invention is to provide a clamping device which solves the above-mentioned conventional problems.

[0012]

In order to achieve this object, a clamp device according to the present invention comprises a clamp circuit for inputting an image signal and holding the level of a clamp period at the level of a control signal; A switching circuit for inputting an output image signal, multiplexing and outputting these signals for each field, and averaging data in a clamp period of the multiplexed signal in the horizontal or vertical direction in the field, and An averaging circuit that holds and outputs the average result of the input image signal for each field and a clamp control circuit that compares each average result with reference data and outputs a control signal that corrects the clamp circuit according to the result. It is characterized by having. Further, the switching circuit multiplexes the signals of the respective input image signals in the clamp period for each field, and includes a switching circuit for multiplexing and outputting the period other than the clamp period for each specific pixel.

Further, the clamp control circuit is characterized in that it has means for varying the degree of correction according to the degree of the comparison result. In addition to the above, there is provided a means for preventing the correction when the comparison result is equal, and a means for determining the number of effective bits for the averaged clamp data and the reference data. It has a configuration including means for comparing respective effective values and means for preventing correction when the results are equal.

In the clamp control circuit, means for determining the number of effective bits for the averaged clamp data and reference data, means for comparing the respective effective values determined thereby, and the results are equal. In such a case, there is provided a configuration including means for not performing correction.

[0015]

With this configuration, even when a plurality of image signals are clamped, the AD converter and the averaging circuit can be shared.

In a configuration having a switching circuit characterized in that a signal of a clamp period of an input image signal is multiplexed for each field and an image period other than the clamp period is multiplexed for each specific pixel. An AD converter for processing can be shared.

Further, the clamp control circuit has means for varying the degree of control in accordance with the degree of the comparison result, so that the degree of control is small when the clamping error is small, and the control is performed when the error is large. The degree can be increased.

Further, if the comparison results are equal, no correction is performed at the clamp stable point so that no correction is performed.

In the clamp control circuit, means for determining the number of effective bits for the averaged clamp data and reference data, means for comparing the respective effective values determined thereby, and the results are equal. In such a case, by not performing the correction, the correction can be prevented from being performed near the clamp stable point. Further, a range in which the correction is not performed can be set.

[0020]

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) In FIG. 1, reference numeral 11 denotes a U-clamp circuit which changes the level of a clamp pulse period outputted from a clamp pulse generating circuit 19 of an input U image signal to U-clamp.
Hold at the level output from the loop filter and output. Reference numeral 12 denotes a V clamp circuit which holds the level of a clamp pulse period output from the clamp pulse generation circuit 19 of the input V image signal at the level output from the V loop filter and outputs the same.

The clamped U image signal and V image signal are input to the switching circuit 13, and are multiplexed and output by a switching signal output from the field inversion signal generation circuit 18 for each field. After the output signal is digitally converted by the AD converter 17, the clamp data in the clamp period is extracted by the averaging circuit 14, and then the U-clamp data and the V-clamp data are respectively averaged in the horizontal direction or the vertical direction. Data is retained for each field.

Reference numeral 15 denotes a U-clamp control circuit which is an averaging circuit 14.
The averaged U-clamp data output from the above is input, compared with the reference data, and according to the result, the output pulse dut is output.
The y ratio is varied and output to the U loop filter.

Numeral 16 denotes a V clamp control circuit.
The averaged V-clamp data output from the above is input, compared with the reference data, and according to the result, the output pulse dut is output.
The y ratio is varied and output to the V loop filter.

In the clamp device configured as described above, the AD converter and the averaging circuit can be configured as one circuit even when two types of image signals are clamped.

(Embodiment 2) In FIG. 2, reference numeral 21 denotes a U-clamp circuit which changes the level of a clamp pulse period outputted from a clamp-pulse generating circuit 27 of an input U image signal to U-clamp.
Hold at the level output from the loop filter and output. Reference numeral 22 denotes a V clamp circuit which holds the level of a clamp pulse period output from the clamp pulse generation circuit 27 of the input V image signal at the level output from the V loop filter and outputs the same.

The clamped U image signal and V image signal are input to the switching circuit 23, multiplexed by the switching signal output from the switching signal generation circuit 24, and output. An embodiment of the switching signal generation circuit 24 will be described with reference to FIGS.
In FIG. 3, reference numeral 211 denotes an AD sampling clock input by a 1/4 frequency dividing circuit which is divided by 4 and output. Reference numeral 212 denotes a switching circuit which receives the output of the quarter frequency divider 211 and the field inversion signal output from the field inversion signal generation circuit 25 of FIG. 2, and clamps those signals to the clamp pulse generation circuit 27 of FIG. The output is switched at the pulse timing. FIG. 4 shows their operation waveforms.

As can be seen from the switching signal waveform, the U image signal and the V image signal are multiplexed in two clock cycles during the image signal period, and the U image signal and the V image signal are multiplexed for each field during the clamp signal period. Become

In the clamp device configured as described above, by multiplexing the image signal at the same time in the switching circuit 23, it is possible to selectively use the image data and the clamp data with the output signal of the AD converter. This allows the AD converter to be used for both the image signal and the clamp signal.

(Embodiment 3) In FIG. 5, reference numeral 31 inputs the clamp data and the reference data averaged by the comparison circuit 1, takes the difference between them and outputs the absolute value. A comparison circuit 32 receives the difference result of the comparison circuit 1 and the correction reference data, compares the data values, and outputs a result indicating which data value is larger.

A switching circuit 33 selects a correction value 1 or a correction value 2 and outputs a correction value to be output based on the result of the comparison circuit 32. Numeral 34 varies the duty ratio of the output pulse in accordance with the correction value input by the PWM control circuit.

In the clamping device configured as described above, the degree of correction can be varied depending on the degree of clamping error. The degree of the error at that time is determined by setting the correction reference data. The degree of correction based on the degree of error is determined by setting the correction value 1 and the correction value 2.

(Embodiment 4) In FIG. 6, reference numeral 41 inputs the clamp data and the reference data averaged by the comparison circuit 1, and outputs the result obtained by taking the difference between them as an absolute value. Reference numeral 42 denotes a comparison circuit 2 which receives the difference result of the comparison circuit 1 and the correction reference data, compares the data values, and outputs a result indicating which data value is larger and a result indicating whether the data value is equal.

A switching circuit 43 selects a correction value 1 or a correction value 2 and outputs a correction value to be output, depending on which data value of the comparison circuit 42 is larger. Reference numeral 45 inputs a signal indicating whether or not the correction value output from the switching circuit 43 and the comparison result output from the comparison circuit 2 are equal. If the comparison results are equal, the correction value is canceled and output.

Reference numeral 44 changes the duty ratio of the output pulse in accordance with the correction value input by the PWM control circuit.

In the clamping device configured as described above, the degree of correction can be varied depending on the degree of clamping error. The degree of the error at that time is determined by setting the correction reference data. The degree of correction based on the degree of error is determined by setting the correction value 1 and the correction value 2. If there is no clamping error, the correction value can be canceled.

(Embodiment 5) In FIG. 7, reference numeral 51 denotes the clamp data and the reference data averaged by the comparison circuit 1, and outputs the absolute value of the difference between them. A comparison circuit 52 receives the difference result of the comparison circuit 1 and the correction reference data, compares the data values, and outputs a result indicating which data value is larger.

Reference numeral 53 denotes a switching circuit for selecting a correction value 1 or a correction value 2 and outputting a correction value to be output based on which data of the comparison circuit 42 is larger.

Numeral 55 inputs the averaged clamp data and the set value of the number of effective bits, and outputs clamp data in which the number of bits according to the set value of the number of effective bits of the clamp data is set as an effective value.

Reference numeral 56 inputs the reference data and the set value of the number of effective bits, and outputs reference data in which the number of bits according to the set value of the number of effective bits of the reference data is set as an effective value.

Reference numeral 57 inputs the clamp data and the reference data, each of which has been made effective by the comparison circuit 3, and outputs a result indicating whether or not the comparison result is equal.

Reference numeral 58 inputs a signal indicating whether or not the correction value output from the switching circuit 53 and the comparison result output from the comparison circuit 3 are equal. If the comparison results are equal, the correction value is canceled and output.

Numeral 54 varies the duty ratio of the output pulse in accordance with the correction value input by the PWM control circuit.

In the clamp device configured as described above, the degree of correction can be varied depending on the degree of error in clamping. The degree of the error at that time is determined by setting the correction reference data. The degree of correction based on the degree of error is determined by setting the correction value 1 and the correction value 2. Further, when there is no or small clamping error, the correction value can be canceled. The range of the error at that time can be set by the effective bit number setting value.

(Embodiment 6) In FIG. 8, reference numeral 61 denotes input of clamp data and reference data averaged by a comparison circuit, compares those data values, and outputs a result indicating which data value is larger. . Reference numeral 65 denotes a correction value generation circuit which outputs a specific correction value for the result of the comparison circuit 61.

Reference numeral 63 inputs the averaged clamp data and the set value of the number of effective bits, and outputs clamp data in which the number of bits according to the set number of effective bits of the clamp data is set as an effective value.

Reference numeral 62 inputs the reference data and the set value of the number of effective bits, and outputs reference data in which the number of bits according to the set value of the number of effective bits of the reference data is set as an effective value.

Numeral 64 inputs the clamp data and the reference data, each of which has been made effective by the comparison circuit 2, and outputs a result indicating whether or not the comparison result is equal.

Reference numeral 67 denotes a signal for inputting whether or not the correction value output from the correction value generation circuit 65 and the comparison result output from the comparison circuit 2 are equal. If the comparison results are equal, the correction value is canceled and output.

The reference numeral 66 changes the duty ratio of the output pulse in accordance with the correction value input by the PWM control circuit.

In the clamping device configured as described above, the correction value can be canceled when there is no or little error in the clamping. The range of the error at that time can be set by the effective bit setting value.

[0052]

As described above, the clamp device of the present invention can be used to share the A / D converter and the averaging circuit even when a plurality of image signals are clamped. In a configuration having a switching circuit characterized in that the image period other than the clamp period is multiplexed for each specific pixel, the A / D converter for image processing can be shared. When the loop processing is performed, the configuration of the circuit can be simplified.

Further, the clamp control circuit has means for varying the degree of control according to the degree of the comparison result, so that the degree of control is small when the clamping error is small, and the degree of control is large when the error is large. By increasing, the stability of the clamp loop can be increased near the clamp stable point where the error is small, and the convergence time can be shortened when the distance from the clamp stable point where the clamp error is large can be increased. It is possible to solve the problem of the convergence time and avoid the deterioration of the image quality.

Further, when the comparison results are equal, no correction is performed so that no correction is performed at the clamp stable point, thereby further improving the stability at the clamp stable point.

In the clamp control circuit, the means for determining the number of effective bits for the averaged clamp data and the reference data, and the means for comparing the respective effective values determined thereby, have the same result. In such a case, by performing no correction in the vicinity of the clamp stable point by not performing the correction, the stability can be further increased near the clamp stable point. And
Since the range can be set, the optimum setting for the stability of the application can be set.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clamp device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a clamp device according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a switching circuit according to a second embodiment of the present invention;

FIG. 4 is a diagram showing operation waveforms in a second embodiment of the present invention.

FIG. 5 is a block diagram of a clamp device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a clamp device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram of a clamp device according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram of a clamp device according to a sixth embodiment of the present invention.

FIG. 9 is a block diagram of a conventional clamping device.

[Explanation of symbols]

 Reference Signs List 13 switching circuit 14 averaging circuit 18 field inversion signal generation circuit, 23 switching circuit 24 switching signal generation circuit 25 field inversion signal generation circuit 212 switching circuit 32 comparison circuit 2 33 switching circuit 42 comparison circuit 2 43 switching circuit 45 gate circuit 52 comparison circuit 2 53 switching circuit, 55, 56, 58 gate circuit 57 comparison circuit 3 62, 63, 67 gate circuit 64 comparison circuit 2

Claims (6)

(57) [Claims] 1. A plurality of clamp circuits for holding the levels of a plurality of input image signals during a clamp period at a level of a control signal, and image signals output from the plurality of clamp circuits are input, and these signals are input to each field. A switching circuit for multiplexing and outputting, and averaging data in a clamp period of the multiplexed signal in a horizontal or vertical direction in a field, and holding and outputting an average result of the plurality of input image signals for each field A clamping device comprising: an averaging circuit; and a clamp control circuit that compares each averaging result with reference data and outputs a control signal for correcting each clamping circuit according to the result. 2. The switching circuit according to claim 1, wherein the switching circuit multiplexes a signal of the input image signal in a clamp period for each field, and multiplexes and outputs a period other than the clamp period for each specific pixel. Clamping device. 3. The clamp device according to claim 1, wherein the clamp control circuit has means for varying a degree of correction according to a degree of the comparison result. 4. The clamp device according to claim 1, wherein the clamp control circuit includes means for preventing correction when the comparison results are equal. 5. A clamp control circuit comprising: means for determining the number of valid bits for the averaged clamp data and reference data; means for comparing the respective valid values determined thereby; 2. The clamping device according to claim 1, further comprising means for preventing correction in a case. 6. The clamp control circuit determines a number of effective bits for the averaged clamp data and the reference data, and compares the respective effective values determined by the means. 2. The clamping device according to claim 1, further comprising means for preventing correction in a case.