JP3295564B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for very high-speed analog-to-digital conversion. The present invention is suitable for use in a sampling oscilloscope. The present invention is suitable for use in an LSI tester. In particular, the present invention relates to a technique for downsizing and simplifying an analog / digital conversion circuit.

[0002]

2. Description of the Related Art A parallel type analog-to-digital converter (Flash ADC) is known as a structure of an analog-to-digital converter that operates at a very high speed, and performs analog-to-digital conversion in one clock. is there. But,
This results in an enormous circuit scale, power consumption, and input capacity.

On the other hand, a loopback / interpolation type analog
The digital converter performs analog-to-digital conversion with one clock in the same manner as the parallel type analog-to-digital converter, and can perform ultra-high-speed analog-to-digital conversion.
Also, there is an advantage that the circuit scale, power consumption, and input capacity are drastically reduced as compared with the parallel type analog-digital converter. For this reason, various types of aliasing / interpolating analog-to-digital converters have been realized (see JJ Corcoran et al., "A 400MHz 6b ADC," ISSCC,
Feb.1984./RJGrift,et al., "An 8b Video ADC Inco
rporating Foldingand Interpolation Techniques, "Jo
f Solid-State Circuits, Dec.1987. / RJPlassche e
t.al., "An 8b 100MHz Full-Nyquist ADC," J.of Solid-S
tate Circuits, Dec.1988. / J.Valburg and RJPlassc
he, "An 8b 650MHz Folding ADC," J.of Solid-State Circ
uits, Dec.1992. / W.Colleran and AAAbidi, "A 10b 7
5MHz Two-Stage Pipelined Bipolar ADC, "J.of Solid-St
ate Circuits, Dec.1993. / REJvan de Grift, "Anal
og-to-Digital Converter Circuit, "US Patent Number
4,456,904, Jun. 1984.).

In a loopback / interpolation type analog / digital converter, it is necessary to correct a delay when an input signal propagates from a loopback circuit to an interpolation circuit. This error algorithm has been proposed and implemented for an early type of aliasing / interpolating analog-to-digital converter (not necessarily suitable for high speed) (RJGrift, et a).
l., "An 8b Video ADC Incorporating Folding and Inte
rpolation Techniques, "J. of Solid-State Circuits, De
c.1987./PGBaltus,et.al.,"Circuit for Synchronizi
ng Transitions of Bits in a Digital Code, "US Paten
t Number 4,939,517, Jul. 1990). This conventional example is shown in FIG.
This will be described with reference to FIG. FIG. 18 is a diagram showing an example of a chip configuration of a conventional folded / interpolated analog-to-digital converter (W. Colleran and AAAbidi, "A 10b 75 MHz Two-
Stage Pipelined Bipolar ADC, "J. Of Solid-State Circuit
its, Dec. 1993.).

[0005]

Recently, a folded / interpolated analog-to-digital converter (suitable for high speed) proposed and realized has a large chip area for error correction, as shown in FIG. Used.

The present invention has been made in such a background, and provides an analog-to-digital converter capable of implementing a folding / interpolation type analog-to-digital conversion with a small and simple circuit configuration. The purpose is to:

[0007]

Means for Solving the Problems The present invention is an analog signal
To the input V _in, is Gray encoded in upper m bits
A digital signal, the least significant of the upper m bits
The period of the most significant bit has a period equal to the interval between bit transitions.
Each transition point [pi / 4 by deviation signal Q, the folding operation means for outputting an I (3), the signal Q, the I
Between auxiliary to generate a lower bit to interpolate the upper m bits
Means for correcting the hand stage (5, 7), the error due to the processing time difference between the turn-back operation means and said auxiliary mate <br/> stage (9)
And an analog-to-digital converter for outputting a gray-coded m + n-bit digital signal.

[0008] Here, it is an aspect of the present invention, before
The interpolation means calculates the processing time difference from the signals Q and I.
If it is assumed that there is not, the most significant bit qi
N + 1 bits corresponding to the least significant bit qf of the arithmetic means
A gray-coded digital signal of
A periodic function having the same cycle as the bit qi,
Assuming that there is no difference,
Transition point that matches the transition point of bits other than the least significant bit
Comprises means for generating the redundant bit ii with, the means for correcting the least significant bit of the folded operation means
Redundant bits if representing transition points of bits other than
Tsu DOO qi, according combination pattern of qf and ii, according to preset logic includes means for adding +1 or -1 to the generated upper m-1-bit digital signals of the folded operation means, the
The added upper m-1 bits and n +
One bit is a digital signal output .

[0009] The means for adding includes the redundant bit i
f, qf and ii, qi according to the combination pattern.
The m-bit signal output from the loopback calculation means.
Means for inverting the value of one corresponding bit of a signal
It is desirable to include

[0010] comprising means (4) for outputting a detection signal when the analog signal input is or not reached the minimum value when the value exceeds the maximum value of the input a predetermined range, the complement
During means and means to said correction, it is desirable to include a means for setting all "0" except the most significant bit of the digital signal output according to the detection signal.

[0011]

A redundant bit is generated, and attention is paid to the fact that the generated pattern has regularity. Based on the generated pattern, an error is generated by, for example, a simple algorithm for adding or subtracting "1" to or from the upper m bits. Make corrections. Since it is a gray code output, adding or subtracting "1" can be done by inverting any one bit of "0" or "1". Since the algorithm is simple, the circuit configuration can be simplified. In addition, the size can be reduced.

When an input exceeding the maximum input range or an input below the minimum input range is detected, the lower bit is set to "0". For example, in a 6-bit gray code, the maximum value is (1, 0, 0, 0, 0, 0) and the minimum value is (0, 0, 0, 0, 0, 0). That is, in each case, the lower bit is “0”. Thus, by setting the lower bit to “0”,
The maximum value is output for an input beyond the maximum input range, and the minimum value is output for an input below the minimum input range.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

[0014] The present invention is, with respect to the analog signal input V _in
Where the upper m = 3 bits of gray coded digital data
Loopback operation to output signals gf5, gf4, gf3
A circuit 3 ₁ to 3 _3, the least significant bits of the upper m bits
Most significant bit having a period equal to the interval between transitions of gf3
a signal Q shifted by π / 4 from the transition point of gf5,
Folding operation circuit 3 ₄ for outputting a I, 3 and _5, the signal
Generate lower bits to interpolate the upper m bits from Q and I
An interpolation calculation circuit 5 and an interpolation error correction circuit 7
Folding operation circuit 3 ₁ to 3 ₃ and the interpolation calculation circuit 5 and interpolation
Error due to processing time difference with error correction circuit 7 is corrected
And an error correction circuit 9 for outputting 6-bit gray-coded digital signals g5 to g0 .

[0015] Here, it is an aspect of the present invention, auxiliary
The error correction circuit 7 supplies the signals Q and I to the
Assuming that there is no time difference, the most significant bit g3 = q
least significant bit gf that i is the output of the folding operation circuit 3 ₃
3 = gray coding of n + 1 = 4 bits corresponding to qf
Digital signal g3 to g0, and the most significant bit
qi is a periodic function having the same cycle as qi, and there is no processing time difference.
If it is assumed that the output of the folding operation circuits 3 ₁ and 3 ₂
And a redundant bit ii having a transition point that matches the transition point
The error correction circuit 9 includes a loopback operation.
The redundant bit if indicating the transition point of the output of the circuits 3 ₁ and 3 ₂
Combination pattern with bits qi, qf and ii
According to the preset logic,
The upper 2 bits of data generated by the folding operation circuits 3 ₁ and 3 ₂
Add +1 or -1 to the digital signal
Upper 2 bits and n + 1 from complementary error correction circuit 7
4 bits are used as a digital signal output .

When the analog signal input exceeds the maximum value of the predetermined input range or does not reach the minimum value, an input range detection circuit 4 is provided as a means for outputting a detection signal. The correction circuit 9 includes a unit for setting all lower multiple bits of the digital signal output to “0” according to the detection signal.

The structure of each part will be described with reference to FIGS. FIG. 2 shows a block configuration of the differential input resistor string 1. In the differential input resistor string 1, an input analog signal is extracted as voltages ± vi0 to ± vi9 using a plurality of resistors having different resistance values stepwise. FIG.
Shows a block schematic of the folding operation circuit 3 _1. The folding operation circuit 3 _1, enter the voltage ± vi0 from the differential input resistor string 1, it generates a signal gf5 corresponding to MSB of the digital signal. FIG. 4 shows the folding operation circuit 3
₂ shows a block configuration. The folding operation circuit 3 _2,
Voltages ± vi0, ± vi from differential input resistor string 1
4 to generate a signal gf4 corresponding to the digital signal MSB-1. Figure 5 shows a block configuration of the folding operation circuit 3 _3. The folding operation circuit 3 _3, voltage ± vi0 from differential input resistor string 1, ± vi2, ± v
i4, ± vi6, and the digital signal MSB-2
Are generated here as redundant bits qf. Figure 6 shows a block configuration of the folding operation circuit 3 _4. The folding operation circuit 3 _4, the voltage from the differential input resistor string 1 -vi0, + vi1, -vi2,
+ Vi3, -vi4, + vi5, -vi6, + vi7,
-Vi8 and + vi9 are input to generate a signal Q used for interpolation calculation. FIG. 7 shows the folding operation circuit 3 ₅
The block configuration of FIG. The folding operation circuit _35, voltage from the differential input resistor string 1 + vi0, -vi
1, + vi2, -vi3, + vi4, -vi5, + vi
6, -vi7, + vi8, and -vi9, and generates a signal I used in the interpolation operation. FIG. 8 shows a block configuration of the interpolation operation circuit 5. In the interpolation operation circuit 5,
The signals having phases shifted by the differential input resistor string 1 are generated using Q, [1], I, [2], and the output voltages vo0 to vof are generated using the comparators. FIG. 9 shows a block configuration of the input range detection circuit 4. The input range detection circuit 4 receives the voltages ± vi0 and ± vi8 from the differential input resistor string 1 and detects whether the input signal is within the signal input range, that is, detects an overflow or an underflow. "1" when overflow or underflow is detected
Is output as the detection signal out-rng. FIG. 10 shows a block configuration of the error correction circuit 9. The error correction circuit 9 corrects the error of the upper two-bit signals g4 and g5 using the signals qf (= gf3), if and ii and outputs the corrected signals. FIG. 11 shows a block configuration of the interpolation error correction circuit 7. The interpolation error correction circuit 7 receives the output voltages vo0 to vof output from the interpolation operation circuit 5, and corrects the lower four bits of the signals g0 to g3 for error output. Here, error correction of the signal g3 using the redundant bit qi and correction of overflow or underflow using the detection signal out-rng are performed.

[0018]

[Outside 1]

[0019]

[Outside 2] Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 12 is a diagram showing the state of the waveform of each part. The folding operation circuits 3 ₁ and 3 ₂ generate upper two-bit signals g5 and g4, respectively. Folding operation circuit 3 ₃ generates a signal having redundant bits qf (= g3). Further folding operation circuit 3 ₄ and 3 _5, generates a wave [pi / 2 phase shifted. They, Q = a cos [[2πV _in / (8RI _b)] + (5/4) π] I = cos [(2πV in / (8RI b) ] + (3/4) π]. Figure 8 The interpolation arithmetic circuit 5 generates gray codes of the signals g3 to g5 corresponding to the upper 3 bits when the phase is shifted by π / 8 degrees from Q and I. The interpolation error correction circuit 7 shown in FIG. The gray codes of the signals g0 to g2 corresponding to the lower three bits are generated from the signal generated by the interpolation operation circuit 5. In this manner, each waveform is generated as shown in FIG. the input signal V _in
Digital signal gray code g0 generated for
It is a signal waveform of g5.

[0020] Here, the input signal V _in (t) is a signal delay from the folding operation circuit 3 _4, 3 ₅ to the interpolation computation circuit 5 .DELTA.t
Exists. That is, assuming that the loopback operation circuits 3 ₁ and 3 ₂ convert the V _in (nT) from analog to digital to obtain the upper 2 bits, the interpolation operation circuit 5 determines that V _in (nT + δ).
t) is converted from analog to digital to obtain the lower 3 bits. Therefore, it is necessary to correct the error in the result.

An error correction algorithm according to the embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 17 to FIG. 17 are tables showing redundant bit generation patterns. In Figure _{14, V in (nT + δt} ) -V in (nT) = - V in (nT + δt) when the 3LSBs, shows a gray code pattern of V _in (nT). Error correction can be conventionally performed for such a delay. Figure 15 shows a _{V in (nT + δt) V} in (nT + δt) when the -V _in (nT) = 2LSBs, Gray code pattern of V _in (nT). Error correction can be conventionally performed for such a delay. _{16, V in (nT + δt)} -V in (nT) = - V in (nT + δt) when the 9LSBs, shows a gray code pattern of V _in (nT). With such a delay, error correction cannot be conventionally performed. Figure 17 shows a _{V in (nT + δt) V} in (nT + δt) when the -V _in (nT) = 10LSBs, Gray code pattern of V _in (nT). With such a delay, error correction cannot be conventionally performed.

In the embodiment of the present invention, the return operation circuit 3 is based on the signals gf, if, qi and ii within the range of | V _in (nT + δt) −V _in (nT) | ≦ 8 LSBs from FIGS. _{1-3 3} generated by the signal GF5,
Error correction can be performed on gf4 and gf3 (= qf). In the embodiment of the present invention, the signals gf, if, q
When the generation patterns of i and ii are case 1, 2, 3, and 4, the gray coat (g5, g4, g3) = gray coat (gf5, g
f4, gf3) +1, and in case 5, 6, 7, and 8, the clean coat (g5, g4, g3) = the clean coat (gf5, g)
Error correction can be performed by setting f4, gf3) -1. At this time, focusing on the properties of the gray code, case
In the case of 1, 2, 3, 7, g5 = gf5, g4 = gf4, g3 = qi, and in case 2,6,

[0023]

(Equation 1) And in cases 4 and 8,

[0024]

(Equation 2) And it is sufficient. A circuit that realizes this is the error correction circuit shown in FIG. In this example, g3 = qi
Therefore, there is no need to invert the signal qi, as shown in FIG.
It is not necessary that the terminal of the signal qi be connected to the circuit of FIG.
No.

When the input is out of the range of the input range, it is necessary to output a minimum value when an underflow occurs, and to output a maximum value when an overflow occurs. The upper two bits generated by the folding operation circuits 3 ₁ and 3 ₂ are automatically set to the minimum value or the maximum value. However, since the output signal of the interpolation operation circuit 5 has a periodic property, Not set automatically.

Therefore, it is necessary to detect the overflow or the underflow, and to set the output signal of the interpolation operation circuit 5 of FIG. 8 to a correct value when the overflow or the underflow occurs. In the 6-bit gray code, the maximum value is (1, 0, 0, 0, 0, 0) and the minimum value is (0, 0, 0, 0, 0, 0). Paying attention to "0", it can be understood that the lower bit should be set to "0" when overflow or underflow is detected. The input range detection circuit 4 outputs "1" when detecting an overflow or an underflow. At this time, the interpolation error correction circuit 7 sets the lower three bits to “0”.

[0027]

As described above, according to the present invention,
An aliasing / interpolation type error correction circuit for analog / digital conversion can be realized with a small and simple circuit configuration. An ultra-high-speed analog / digital converter can be reduced in size and power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a differential input resistor string.

FIG. 3 is a block diagram of a folding operation circuit.

FIG. 4 is a block diagram of a folding operation circuit.

FIG. 5 is a block diagram of a folding operation circuit.

FIG. 6 is a block diagram of a folding operation circuit.

FIG. 7 is a block diagram of a folding operation circuit.

FIG. 8 is a block diagram of an interpolation operation circuit.

FIG. 9 is a block diagram of an input range detection circuit.

FIG. 10 is a block diagram of an error correction circuit.

FIG. 11 is a block diagram of an interpolation error correction circuit.

FIG. 12 is a diagram showing a state of a waveform of each unit.

FIG. 13 is a signal waveform of a digital signal gray code generated for an input signal.

FIG. 14 is a table showing a redundant bit generation pattern;

FIG. 15 is a table showing a redundant bit generation pattern;

FIG. 16 is a table showing a redundant bit generation pattern;

FIG. 17 is a table showing a redundant bit generation pattern;

FIG. 18 is a diagram showing an example of a chip configuration of a conventional folded / interpolated analog-to-digital converter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Differential input resistance string 3 _{1 to} 3 ₅ Return operation circuit 4 Input range detection circuit 5 Interpolation operation circuit 7 Interpolation error correction circuit 9 Error correction circuit

Continuation of the front page (56) References IEEE Journal of Solid-State Circuits, vol. 28, no. 12, Dec. 1993, USA, P.M. 1187-1199 (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 INSPEC (DIALOG)

Claims (3)

(57) [Claims] 1. An analog signalSignal input V _in AgainstTop m
Bit ofGray codedWith digital signals,this
Equal to the transition interval of the least significant bit of the upper m bits
Π / 4 from the transition point of the most significant bit
Shifted byReturn operation means for outputting signals Q and I
(3) and the signals Q and IInterpolates the upper m bits fromLower order
ToGenerate aSupplementPoor manStep (5, 7), The folding operation means and the complementPoor manFor processing time difference with step
Means for correcting errors caused by(9) And, Gray coded m + n bit digital
Output signalAnalog-digital converter smell
hand,The interpolation means calculates the processing time difference from the signals Q and I.
Assuming that there is no
N + 1 bits matching the least significant bit qf of the return operation means
The gray coded digital signal of the
A periodic function having the same cycle as the order bit qi.
If it is assumed that there is no difference,
Transitions coincident with transition points of bits other than the least significant bit
Means for generating redundant bits ii with points,  The means for correcting is provided by theThe bottom
Redundant bits if representing transition points of bits other than
The bits qi, qf and iiCombined putter with
According to the preset logic.
And the higher order generated by the loopback operation means.m-1bit
Means for adding +1 or -1 to the digital signal of
Only, The sum of the upper m-1 bits and the value of the
n + 1 bits as digital signal output Features
Analog-to-digital converter. Wherein said means for summing is pre millet Tsu bets if,
According to a combination pattern of qf and ii, qi,
2. The analog-to-digital converter according to claim 1, further comprising means for inverting the value of one corresponding bit among the higher-order m-1 bit signals output from said aliasing means. Wherein comprising means (4) for outputting a detection signal when the analog signal input is or not reached the minimum value when the value exceeds the maximum value of the input range determined in advance, the
Interpolation means and means to said correction, according to claim 1 or 2 analog to digital converter as claimed includes means for setting other than the most significant bit of the digital signal output to all "0" in accordance with the detection signal.