JP3294489B2 - Random number generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a battery-driven portable electronic device equipped with a microcomputer,
When data is transmitted to and from a device equipped with a microcomputer, random number generation is provided in each of these portable electronic devices and devices and used to encrypt data to be transmitted from the viewpoint of confidentiality. It is related to the circuit.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram of a conventional random number generation circuit, and FIG. 3 is a diagram showing the encryption processing of FIG.
The random number generating circuit of FIG. 2 includes an oscillation circuit (hereinafter, referred to as “OSC”) 1 that oscillates at a constant frequency, and a clock that divides an output signal of the OSC 1 to output output data (that is, random number data) DA. And the like. The output data DA of the self-propelled counter 2 is read by a central processing unit (hereinafter, referred to as “CPU”), which performs arithmetic processing, encrypts data to be transmitted, and transmits the data to the outside. It has become. In FIG.
This shows that the CPU reads the output data DA of the self-running counter 2 at an arbitrary time. When power is supplied to the device equipped with the random number generation circuit shown in FIG. 2, the self-running counter 2 starts counting at an arbitrary time when the power is supplied, and further, at an arbitrary time when the device is used. From C
After certain program processing by the PU, the CPU reads the output data DA (for example, D _{n + 1} ) of the self-running counter 2 to obtain random number data. The CPU performs arithmetic processing on the read random number data to encrypt data to be transmitted, and transmits the data to the outside from a transmitting unit (not shown).

[0003]

However, the conventional random number generating circuit has the following problems, and it is difficult to solve them. (A) In the random number generation circuit of FIG. 2, in order to obtain random output data DA, that is, random number data, the OSC 1 and the free-running counter 2 must always be operated by supplying power to the power supply. Therefore, when the device equipped with the random number generation circuit of FIG. 2 is driven by a battery, for example, there is a problem that the life of the battery is shortened, that is, the power consumption is large. (B) In order to reduce the power consumption of (a), for example, a method of supplying power to the power supply only when the apparatus is used may be considered. In this method, the CPU sets the output data D
The timing of reading A starts when the power is turned on.
There is a certain regularity because the PU performs certain program processing in preparation for reading. Also, the value of the output data DA of the self-running counter 2 has a certain regularity after a certain period of time after the power is turned on. Therefore, the output data D read by the CPU
The value of A has a certain regularity, and does not become a sufficient random number. The present invention solves the problems of the prior art, and provides, for example, a random number generation circuit capable of reducing power consumption by turning on power only at the time of use and obtaining highly reliable random number data. Is what you do.

[0004]

According to a first aspect of the present invention, there is provided a random number generating circuit provided in various devices such as a data transmission device. Means (eg, oscillation circuit)
A clock generating means (for example, composed of a multi-stage frequency dividing circuit or the like) for generating and outputting a clock signal having a jitter width larger than a half cycle of the output signal based on the output signal of the oscillating means; Sampling means (for example, a flip-flop circuit or the like) which samples an output signal of the oscillation means by jitter in an output signal of the clock generation means and outputs random number data composed of logical signals (for example, "1", "0") ). The second invention is
In a random number generation circuit, first oscillating means oscillating at a constant frequency when power is turned on, and second oscillating means oscillating at a frequency which is a non-integer multiple of the first oscillating means when the power is turned on. Clock generating means for generating and outputting a clock signal having a jitter width larger than a half cycle of an output signal of the first oscillation means based on an output signal of the second oscillation means; And a sampling means for sampling the output signal of the first oscillation means according to the jitter in the output signal and outputting random number data composed of a logic signal. According to a third aspect, there is provided the random number generation circuit according to the first or second aspect, and a scramble circuit for scrambling the output data of the sampling means and outputting the scrambled random number data.

According to the first aspect of the present invention, since the random number generating circuit is configured as described above, when the power is turned on, the oscillating means oscillates at a constant frequency and the oscillation output signal is sent to the clock generating means and the sampling means. Sent. The clock generating means receives the output signal of the oscillating means, generates a clock signal containing, for example, jitter, amplifies the jitter, and generates a clock signal having a jitter width larger than a half cycle of the output signal. To the sampling means. The sampling means samples the output signal of the oscillating means using jitter in the output signal of the clock generation means and outputs random number data. According to the second invention, when the power is turned on, the first oscillating means and the second oscillating means oscillate asynchronously, and the output signal of the first oscillating means is sent to the sampling means, The output signal of the oscillating means is sent to the clock generating means. The clock generation means receives the output signal of the second oscillation means, generates a clock signal having a jitter width larger than a half cycle of the output signal of the first oscillation means, and sends the clock signal to the sampling means. The sampling means samples the output signal of the first oscillating means according to the jitter in the output signal of the clock generation means and outputs random number data. According to the third invention, the output data output from the sampling means of the first or second invention when the power is turned on is sent to the scramble circuit, and the output data is scrambled by the scramble circuit.
Random number data is output.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of a random number generating circuit according to a first embodiment of the present invention. The random number generating circuit includes an oscillating means (for example, OSC) 10 and clock generating means (for example, a plurality of (n) stages of divide-by-2 circuits) 20-1 to 20-n connected to the output side of the OSC 10. , And a sampling means (for example, a D-type flip-flop circuit, hereinafter referred to as “D-FF”) 30 connected to the output side of the OSC 10 and the last-stage divide-by-two circuit 20-n. . OS
C10 is a circuit that oscillates at a constant frequency when the power is turned on and outputs an output signal S10, and is configured by a crystal oscillation circuit or the like. The n-stage divide-by-2 circuits 20-1 to 20-n constituting the clock generation means receive the output signal S10 and generate the clock signal S20 having a jitter width larger than a half cycle of the output signal S10. This is a circuit to be applied to the D-FF 30.
20-n are composed of the same circuit.

For example, the first-stage divide-by-two circuit 20-1 forms a CR integration circuit including a resistor 21 and a capacitor 22 for integrating the output signal S10 in a triangular waveform, and a waveform of the integration signal S22 output from the CR integration circuit. And a divide-by-2 counter (for example, D-FF) 23 that divides the frequency by 2 for shaping. The D-FF 23 has a data input terminal D, a clock input terminal T, a data output terminal Q for outputting an output signal S23, and an inverted data output terminal Q /, and the clock input terminal T connects the resistor 21 and the capacitor 22. And the data input terminal D is connected to the inverted data output terminal Q
/It is connected to the. Data output terminal Q of D-FF23
Is connected to a resistor in the next-stage divide-by-2 circuit 20-2. Similarly, the other divide-by-2 circuits 20-3 to 20-n are cascaded, and the DF in the final stage divide-by-2 circuit 20-n is connected.
The data output terminal of F is connected to D-FF30.
The D-FF 30 has a data input terminal D, a clock input terminal T, and a data output terminal Q.
Is connected to the output side of the OSC 10, the clock input terminal T is connected to the data output terminal of the D-FF in the final-stage divide-by-2 circuit 20-n, and "1" is output from the data output terminal Q.
This is a circuit that outputs the output data DA of “0” (that is, random number data).

FIGS. 4 and 5 are operation waveform diagrams of the random number generation circuit shown in FIG. 1. The operation of the random number generation circuit of FIG. 1 will be described with reference to these drawings. When the power is turned on,
The SC10 starts an oscillating operation, and an output signal S10 having a constant frequency is output from the OSC10 and sent to the D-FF 30 and the first-stage divide-by-2 circuit 20-1. In the first-stage divide-by-2 circuit 20-1, the input output signal S10 is integrated into a triangular waveform by a CR integration circuit including a resistor 21 and a capacitor 22, and the integration signal S2 is output from the CR integration circuit.
2 is output. In the CR integration circuit, if the resistance value of the resistor 21 is increased and the capacitance value of the capacitor 22 is reduced, the impedance is increased and ambient noise is easily picked up. Therefore, the output signal S10 is integrated by the resistor 21 and the capacitor 22 into a triangular-wave-shaped integrated signal S22, so that a signal including jitter due to ambient noise is present at the conversion point when viewed from the clock input terminal T of the D-FF 23. Becomes The D-FF 23 outputs an integrated signal S22 including jitter.
Is divided by 2 for waveform shaping. As a result, D-FF
Output signal S23 output from the data output terminal Q
Is also a signal containing jitter. This output signal S23
Is sent to the next-stage divide-by-2 circuit 20-2, and the jitter is further increased and output as in the first-stage divide-by-2 circuit 20-1. Can be In this manner, the jitter is amplified, and the final stage divide-by-2 circuit 20
From -n, a clock signal S20 having a jitter width larger than a half cycle of the output signal S10 is output and sent to the clock input terminal T of the D-FF 30.

The D-FF 30 samples the output signal S10 of the OSC 10 due to the jitter of the clock signal S10. That is, the output signal S10 is sampled by one of the rising edges of the jitter at the rising portion of the clock signal S20 shown in FIG. 5, and the output data DA is output from the data output terminal Q of the D-FF 30. In the output data DA, for example, in response to the rising of any jitter in the clock signal S20, data D ₁ and D
_Since the boundary of ₂ is determined, the output data DA becomes random number data. That is, since the clock signal S20 input has a jitter over the section of “1” and “0” of the output signal S10 input to the data input terminal D of the D-FF 30, the data output of the D-FF 30 The output data DA output from the terminal Q becomes random number data. D-FF3
The random number data output from 0 is read by a CPU or the like (not shown), data to be transmitted is encrypted by arithmetic processing of the CPU or the like, and the encrypted data is output from a transmitting unit (not shown) to the outside. You.

As described above, in the first embodiment,
There are the following advantages. (I) By the n-stage divide-by-2 circuits 20-1 to 20-n,
Amplify constantly existing noise as jitter at the conversion point,
Due to this amplified jitter, the OSC1
0 is sampled from the D-FF 30
Is configured to output randomized randomized data of "0" or "1" from the data output terminal Q of the. For this reason, even if the random number data is read by a CPU or the like for encryption a certain time after the power is turned on, for example, new random number data can be obtained every time the power is turned on without regularity due to the read timing. Therefore, the power can be turned off when the device is not in use,
The battery life can be extended when the device is driven by a battery, and low power consumption can be achieved. (Ii) Using a CR integration circuit including a resistor 21 and a capacitor 22, a triangular-wave-shaped integration signal S2 having jitter
2 is generated and the D-FF 23 performs waveform shaping to generate a clock signal, so that a clock signal including jitter can be easily and accurately generated.

Second Embodiment FIG. 6 is a block diagram showing a random number generating circuit according to a second embodiment of the present invention. The elements common to those in FIG. 1 showing the first embodiment are the same as those shown in FIG. Are given. In this random number generation circuit, two first oscillating means (for example, OSC) 10 which operate asynchronously, instead of one OSC 10 of FIG.
-1 and a second oscillating means (for example, OSC) 10-2 are provided, and an output signal S10-1 output from the first OSC 10-1 is supplied to a data input terminal D of the D-FF 30, and a second A configuration in which the output signal S10-2 of the OSC 10-2 is applied to the resistor 21 in the first-stage frequency-dividing circuit 20-1 to make the input clock and the input clock of the D-FF 30 for extracting the random number data as the output data DA asynchronous. It has become.
The second OSC 10-2 oscillates at a frequency that is a non-integer multiple of that of the first OSC 10-1, and preferably has a low-precision circuit configuration in which the stability of the oscillation frequency is low and the jitter is large. . The reason for using the OSC 10-2 is that jitter is easily generated due to low stability of the oscillation frequency, and as a result, the reliability of the random number data extracted by the D-FF 30 is improved.

In the random number generating circuit according to the second embodiment,
When the power is turned on, the first and second OSCs 10-1, 10-1
0-2 oscillates asynchronously, and the first OSC 10-1
Is sent to the data input terminal D of the D-FF 30, and the output signal S10-2 of the second OSC 10-2 is sent to the first-stage divide-by-2 circuit 20-1. The first-stage divide-by-2 circuit 20-1 amplifies the output signal S10-2 including the jitter of the OSC 10-2 itself, and outputs the output signal S23 composed of the clock signal to the subsequent-stage divide-by-2 circuits 20-2 to 20-2. -N. Therefore, the jitter contained in the output signal S10-2 increases sequentially,
The clock signal S20 having a jitter width larger than a half cycle of the output signal S10-1 is supplied to the final stage divide-by-2 circuit 20-.
n and sent to the clock input terminal T of the D-FF 30. The D-FF 30 asynchronously samples the output signal S10-1 of the OSC 10-1 based on the clock signal S20 and outputs output data DA, that is, random number data.

The second embodiment has the following advantages in addition to the advantages of the first embodiment. (iii) In the first embodiment, since there is one oscillation source called the OSC 10, the data input and the clock input to the D-FF 30 are synchronized. Therefore, depending on the distribution of jitter, a series of “0” and “1” may occur, and the reliability of the obtained random number data may be low. Therefore, in the second embodiment, the oscillation sources are OSCs 10-1 and 10-1.
-2, the data input to the D-FF 30 and the clock input are made asynchronous, and the jitter contained in the clock signal S20 is also increased by using the OSC 10-2 with low accuracy. Accordingly, random number data can be obtained more reliably than in the first embodiment.

Third Embodiment FIG. 7 is a configuration diagram of a random number generation circuit according to a third embodiment of the present invention. In this random number generation circuit, in order to further ensure randomization with respect to the first or second embodiment, a scramble is further provided on the output side of the random number generation circuit 40 of the first or second embodiment. The circuit 50 is connected. This scramble circuit 50 has a function of further randomizing the output data DA output from the D-FF 30 in the random number generation circuit 40 and outputting random number data DAT. For example, the generator polynomial is 1 + X ⁻⁶ + X ⁻⁷ . It is composed of circuits.

For example, when the generating polynomial is 1 + X ^-6 + X ^-7 , the scramble circuit 50 includes two exclusive OR gates (hereinafter, referred to as “Ex-OR”) 51, 53, and 1
It is composed of two shift registers 52. Ex-OR
One of the two input terminals 51 is connected to the data output terminal Q of the D-FF 30 in the random number generation circuit 40, and the other input terminal is connected to the output terminal of the other Ex-OR 53. ing. The output terminal of the Ex-OR 51 is
This terminal outputs the random number data DAT, and is connected to the data input terminal D of the shift register 52. The clock input terminal T of the shift register 52 has a random number generation circuit 4
0, and the two data output terminals Q6 and Q7 of the shift register 52 are input.
Are connected to two input terminals of the Ex-OR 53. In the random number generation circuit of the third embodiment, the output data DA and the clock signal S20 are output from the random number generation circuit 40 when the power is turned on, and the output data DA is sent to the scramble circuit 50. The output signal of the Ex-OR 51 in the scramble circuit 50 becomes "1" when the two input signals do not match, and the output signal becomes "0" when the two input signals match.
2 data input terminal D. Shift register 52
Then, the clock signal S input to the clock input terminal T
20, the output signals of the Ex-OR 51 are sequentially taken and shifted, and the two data output terminals Q6, Q7
Output from The output signals of the two data output terminals Q6 and Q7 are input to the Ex-OR 53, and the Ex-OR 53
The output signal of 53 is fed back to the input terminal of Ex-OR 51. Thus, random number data DAT randomized by the scramble circuit 50 represented by the generator polynomial 1 + X ^-6 + X ^-7 is output from the output terminal of the Ex-OR 51.
Is output.

The third embodiment has the following advantages in addition to the advantages of the first and second embodiments. (Iv) As in the second embodiment, two OSCs 10-
Even if 1 and 10-2 are provided, there is a possibility that the OSCs 10-1 and 10-2 have a frequency ratio that is an integral multiple of each other due to the fluctuation of the oscillation frequency. Even in such a case, since the continuous generation of "0" or "1" is randomized by the added scrambling circuit 50, the random number data DAT can be obtained more reliably than in the second embodiment. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) Each divide-by-2 circuit 20 of FIGS. 1 and 6
Each of -1 to 20-n includes a CR integration circuit including a resistor 21 and a capacitor 22, and a divide-by-2 counter including a D-FF 23. However, the CR integration circuit may include another circuit. Alternatively, the divide-by-2 circuit may be constituted by another flip-flop circuit or the like. Further, the clock generating means including the n-stage divide-by-2 circuits 20-1 to 20-n
Since this circuit generates a clock signal including jitter and amplifies the jitter, the circuit may be changed to another circuit configuration capable of performing such a function. Also, the D-FF 30
It may be constituted by sampling means such as another flip-flop circuit. (B) The scramble circuit 50 shown in FIG. 7 has a generator polynomial of 1 + X ^-6 + X ^-7 . However, by increasing the number of these stages, a circuit configuration of another generator polynomial is used to improve the scramble accuracy. Can be further improved. Also,
These scramble circuits 50 may be constituted by circuits other than those shown. (C) In the above embodiment, the random number generation circuits for encrypting the transmission data have been described. However, these random number generation circuits can be used for various uses other than encryption.

[0018]

As described in detail above, the first and fourth embodiments are described.
According to the fifth aspect of the present invention, the noise which steadily exists is amplified as jitter by the clock generation means, the clock signal having the amplified jitter is supplied to the sampling means, and the output signal of the oscillation means is converted by the sampling means. Since sampling is performed to extract random number data, for example, even if the random number data is read for encryption or the like after a certain period of time after the power is turned on, the power is turned on without any regularity due to the read timing. New random data is obtained every time. Therefore, when the apparatus is not used, the power can be turned off. For example, when the apparatus is driven by a battery, the battery life can be extended, and the power consumption can be reduced. According to the second, fourth and fifth aspects of the present invention, two first and second oscillating units having different precisions are provided, and the data input and the clock input to the sampling unit are asynchronous. The random number data can be obtained more reliably than in the invention of (1). According to the third aspect, the scrambling circuit is provided on the output side of the random number generating circuit of the first or second aspect. Therefore, the random number data obtained by the first or second aspect can be further randomized. , Random number data can be obtained more reliably than in the second invention.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a random number generation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional random number generation circuit.

FIG. 3 is a diagram showing an encryption process of FIG. 2;

FIG. 4 is an operation waveform diagram of FIG.

FIG. 5 is an operation waveform diagram of FIG.

FIG. 6 is a configuration diagram of a random number generation circuit according to a second embodiment of the present invention.

FIG. 7 is a random number generation circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 10, 10-1, 10-2 OSC (oscillation circuit) 20-1 to 20-n 2 frequency dividing circuit 21 resistor 22 capacitor 23, 30 D-FF 40 random number generating circuit 50 scrambling circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/58 H03K 3/84

Claims (5)

(57) [Claims] 1. An oscillating means for oscillating at a constant frequency when a power is turned on, and a clock for generating and outputting a clock signal having a jitter width larger than a half cycle of the output signal based on an output signal of the oscillating means. A random number generation circuit comprising: a generation unit; and a sampling unit that samples an output signal of the oscillation unit based on a jitter in an output signal of the clock generation unit and outputs random number data including a logic signal. 2. A first oscillating means which oscillates at a constant frequency when the power is turned on, and a second oscillating means which oscillates at a frequency which is a non-integer multiple of the first oscillating means when the power is turned on. A clock generation unit that generates and outputs a clock signal having a jitter width larger than a half cycle of an output signal of the first oscillation unit based on an output signal of the second oscillation unit; Sampling means for sampling the output signal of said first oscillation means by jitter in said output signal and outputting random number data composed of a logic signal. 3. A random number generator, comprising: the random number generation circuit according to claim 1; and a scramble circuit that scrambles output data of the sampling means and outputs the scrambled random number data. circuit. 4. The random number generation circuit according to claim 1, wherein said clock generation means comprises a plurality of frequency divider circuits, and wherein said frequency divider circuit of each stage comprises: An integrating circuit comprising a resistor and a capacitor for integrating the output signal of the second oscillating means or the output signal of the second oscillating means of claim 2, and a frequency dividing counter for dividing the output signal by using the output signal of the integrating circuit as a clock input. And a random number generating circuit. 5. The random number generation circuit according to claim 1, wherein the sampling means receives an output signal of the clock generation means as a clock input, and outputs the output signal of the oscillation means of claim 1 or the sampling signal of claim 2. A random number generation circuit comprising a flip-flop circuit which receives an output signal of a first oscillation means and outputs the random number data.