JP3289851B2 - Wireless device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial application Conventional technology (FIG. 5) Problems to be solved by the invention (FIG. 5) Means for solving the problems (FIGS. 1, 2 and 4) Operation (FIGS. 1, 2 and 4) Embodiments (1) Overall configuration of the embodiment (FIG. 1) (2) Synchronization establishment processing (FIGS. 1 to 3) (3) Effects of the embodiment (4) Other embodiments (FIG. 4) Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio device, and can be applied to, for example, a digital cellular phone which encodes and transmits a voice signal.

[0003]

2. Description of the Related Art Conventionally, in a digital cellular phone which is one of radio telephones, one channel is simultaneously transmitted and received by a plurality of terminal devices by applying a time division multiplexing technique by encoding and transmitting a voice signal. It has been made usable.

That is, when the power is turned on, this type of terminal device sequentially scans a preset 124 channels to detect a channel having the highest electric field intensity. As a result, the terminal device transmits a BCCH (broadcast control channel) assigned to the area to which the terminal device belongs.
And receives this BCCH.

[0005] The BCCH forms a time slot to transmit various information, so that the digital cellular receives the BCCH at each terminal device and transmits information of the base station which transmits the BCCH. It is configured to transmit information on a base station, and further call information on a terminal device. For this reason, the terminal device executes the processing procedure shown in FIG. 5 to synchronize the entire operation with the base station.

[0006] That is, when receiving the detected channel, the terminal device proceeds from step SP1 to step SP1.
The process proceeds to step 2, where an FCCH (frequency correction channel) inserted at a predetermined cycle in the channel is detected. Here, the FCCH is a synchronization signal to which a bit pattern is assigned so that data of a value “0” is continuous by a predetermined number of bits when demodulated.
This data is transmitted by SK modulation. As a result, the terminal device roughly detects the timing of the FCCH by detecting the correlation value between the predetermined reference signal and the received signal, and roughly outlines the entire operation with respect to the base station based on the FCCH. Synchronize with.

Subsequently, in step SP3, the terminal device corrects the frequency error based on the received data of the FCCH. Here, the FCCH has a value “0” when demodulated.
When the reception result obtained by quadrature detection is sampled at the correct timing by forming a synchronization signal to which a bit pattern is assigned so that the data of the bit sequence continues for a predetermined number of bits, the reception result is expressed by an IQ plane.
It sequentially circulates on the axis and the Q axis at a phase of 90 degrees.

On the other hand, if the terminal apparatus receives the FCCH in a state where the timing is shifted with respect to the base station, there is a frequency error in the timing shift (that is, the processing frequency of the terminal apparatus with respect to the carrier frequency of the FCCH). ), The received data slightly deviates from the I axis and the Q axis. As a result, the terminal device detects the deviation of the received data based on the result of receiving the FCCH, and thereby detects the frequency error.

Further, when the frequency error is detected in this way, the terminal device corrects the frequency error in the following step SP4. The correction of the frequency error can be performed by controlling the operation of the reference signal generation circuit that generates the clock of the terminal device, and can also be performed by correcting the received data by applying a complex arithmetic technique. .

When the frequency error is corrected as described above,
Subsequently, the terminal device proceeds to step SP5, where the SC
H (synchronization channel) is detected and this SCH
A state completely synchronized with the base station is formed based on the detection result.

Here, the SCH is a synchronization signal of a predetermined bit pattern inserted into the channel similarly to the FCCH. In the terminal device, the SCH is detected based on the timing detection result of the FCCH. It has been made like that. Thus, when the entire operation is synchronized with the base station, the terminal device proceeds to the next step SP6, completes the process of establishing the synchronization, and monitors a predetermined time slot of the BCCH.

[0012]

However, as described above, S
When detecting the CH and synchronizing the entire operation with the base station,
It is assumed that the FCCH is correctly detected and roughly synchronized based on the FCCH. On the other hand, in an actual terminal device, the BCCH may be received in a state where the reception state is deteriorated. May occur. Further, in this case, the carrier frequency itself of the received signal may be displaced due to the Doppler shift.

[0013] For this reason, in the conventional terminal device, the timing of the FCCH may not be accurately detected due to this kind of disturbance, and in this case, there is a problem that it is difficult to detect the subsequent SCH. Similarly, when the clock frequency of the terminal device is largely displaced from the base station, the FCCH
Has a problem that the timing cannot be accurately detected. Incidentally, as described above, in this type of terminal device, the FCC
By detecting H and correcting the clock frequency, F
There is a characteristic that this clock frequency shift cannot be avoided during CCH detection.

In this case, the terminal device detects the SCH repeatedly and many times, and it takes a long time before the communication can be started.

The present invention has been made in consideration of the above points, and detects a second synchronization signal based on a result of detecting a timing of a first synchronization signal, and based on the result of detection of the second synchronization signal. It is intended to propose a wireless device capable of reliably detecting the second synchronization signal when synchronization is established.

[0016]

According to the present invention, there is provided a radio apparatus for receiving a transmission signal on the basis of first and second synchronization signals interposed in a transmission signal at a predetermined period. The first synchronization signal is detected to detect the timing of the first synchronization signal, and the frequency error of the internal clock with respect to the first synchronization signal is detected. Means for roughly synchronizing (SP11, SP12, SP13)
And means SP16 for detecting the second synchronization signal for a predetermined period based on the timing detection result, and the entire operation is synchronized with the transmission signal based on the detection result of the second synchronization signal. Means SP17 for forming a state, receiving the transmission signal, and correcting the period for detecting the second synchronization signal in accordance with the frequency error is provided.

Further, in the second invention, when the frequency error is large, the period for detecting the second synchronization signal SCH is accelerated, and the period for detecting the second synchronization signal SCH is corrected.

Further, in the third invention, when the frequency error is large, the period for detecting the second synchronization signal SCH is switched to be longer to correct the period for detecting the second synchronization signal SCH.

Further, in the fourth aspect, when the frequency error is small, the period for detecting the second synchronization signal SCH is switched short.

[0020]

When the detection timing of the first synchronization signal FCCH changes according to the frequency error, the period during which the second synchronization signal SCH is detected is corrected according to the detection result of the frequency error, so that it is ensured. The second synchronization signal SCH can be detected.

That is, when the frequency error is large, the period for detecting the second synchronizing signal SCH is increased, and the period for detecting the second synchronizing signal SCH is switched to be longer, so that the second synchronizing signal SCH is surely detected. Conversely, when the frequency error is small, the period for detecting the second synchronization signal SCH can be switched to be shorter to improve the detection accuracy.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Overall Configuration of the Embodiment In FIG. 1, reference numeral 1 denotes a digital cellular terminal device as a whole. A transmission signal transmitted from a base station is received by an antenna 2, and a reception signal obtained as a result is received by an antenna. The signal is output to the amplifier circuit 3 via a duplexer (not shown).

Here, the amplification circuit 3 amplifies the received signal with a predetermined gain, and outputs the amplified signal to a high frequency processing circuit (RF processing) 4. The high frequency processing circuit 4 uses the predetermined local oscillation signal to output the received signal. Is frequency-converted. As a result, the terminal device 1 can selectively receive a desired channel by switching the frequency of the local oscillation signal.

Further, the high-frequency processing circuit 4 demodulates the I signal synchronized with the reference phase of the received signal by performing quadrature detection on the frequency-converted received signal, and also Q signal having a phase difference of 90 degrees with respect to the I signal. Are demodulated, and the I and Q signals are converted into digital values by a built-in analog digital conversion circuit.

The data processing circuit 5 outputs the I data and Q
It is formed by a digital signal processor that processes data, and reduces the effects of fading and multipath by correcting distortion of I data and Q data by waveform equalization. Further, the data processing circuit 5 detects the FCCH based on the I data and the Q data, detects a frequency error based on the detection result, and corrects the frequency error of the received signal based on the detection result. .

At this time, the data processing circuit 5 detects the SCH based on the FCCH detection result, and synchronizes the entire operation with the base station based on the detection result (that is, the processing for establishing synchronization). In this state, the terminal device 1 further receives the BCCH and demodulates the IQ data.

In addition to this series of processing, the data processing circuit 5
Performs convolutional decoding on the demodulated data, performs error correction processing, and selectively outputs the resulting decoded data to the audio processing circuit 6 or the central processing unit 8.

Here, the audio processing circuit 6 performs audio expansion processing on the decoded data to demodulate the audio data, and converts this audio data into an audio signal by a built-in digital-to-analog conversion circuit. Further, the voice processing circuit 6 drives the speaker 7 with the voice signal, so that the terminal device 1 can receive the voice signal of the call target transmitted from the base station.

On the other hand, the central processing unit 8 receives predetermined information transmitted from the base station based on the decoded data, and switches the frequency of the local oscillation signal based on the reception result, thereby obtaining a predetermined information. The frequency is switched to the communication channel, whereby the terminal device 1 can receive a predetermined reception channel and receive an audio signal.

On the other hand, the transmission system of the terminal device 1 converts the audio signal output from the microphone 9 into audio data by the audio processing circuit 6, and then performs audio compression processing. The data processing circuit 5 generates transmission data by convolution-encoding the output data of the audio processing circuit 6, and various control codes output from the central processing unit 8 in place of the output data of the audio processing circuit 6. Is convolutionally encoded to generate transmission data.

The RF processing circuit 4 orthogonally modulates the transmission data to generate an I signal and a Q signal, and then combines the I signal and the Q signal to generate a transmission signal. Perform frequency conversion. Further, the RF processing circuit 4
Outputs the frequency-converted transmission signal to the antenna 2 via the amplifier circuit 10, so that the terminal device 1 can transmit the voice signal of the talker, the call signal to the base station, and the like. ing.

At this time, the terminal device 1 is connected to the data processing circuit 5
The transmission and reception timings are switched based on a predetermined timing detection result detected in the above, whereby the transmission signal transmitted from the base station to a plurality of terminal devices by applying the time-division multiplexing technique. The time slot assigned to the own station is selectively received, and voice data or the like is transmitted to the base station using the time slot assigned to the own station.

For this reason, the central processing unit 8 secures a work area in the random access memory (RAM) 13 and executes the treatment program stored in the read-only memory circuit (ROM) 11, thereby making it necessary. In response, a control code is output to each circuit block to control the overall operation. For example, when a predetermined operator of the display key input unit 12 is pressed, a call signal is sent to the base station in response to this operation. Is transmitted, and when a call signal is further input from the base station, the receiving channel and the like are switched.

(2) Processing for Establishing Synchronization The terminal device 1 performs frame synchronization on the basis of the FCCH,
Further, the frequency error is corrected, and subsequently, the entire operation is accurately synchronized with the base station on the basis of the SCH, and then the time slot is received to receive desired information. That is, when the power of the terminal device 1 is turned on and the area to which the terminal device belongs is switched, the terminal device 1 executes the processing procedure shown in FIG.

That is, the terminal device 1 executes step SP11.
Then, the operation proceeds to step SP12, where the operation of the RF processing circuit 4 is switched based on the control code output from the central processing unit 8, whereby a desired channel is received. This FC
The detection of the CH is executed by generating a predetermined reference signal in the data processing circuit 5 and detecting a correlation value between the reference signal and the received signal. The rising edge is detected to detect the FCCH.

When the terminal device 1 detects the timing of the FCCH, the terminal device 1 sets a time base counter incorporated in the data processing circuit 5 based on the timing, thereby synchronizing the entire operation with the frame. Subsequently, the terminal device 1 proceeds to step SP13, outputs a control code to the data processing circuit 5, and detects a frequency error.

When detecting the timing of the FCCH, the data processing circuit 5 stores the sequentially demodulated IQ data in a predetermined memory circuit. Of the IQ data stored in this memory circuit, This frequency error is detected from the IQ data. That is, this type of reception result can be represented by a vector, and when the reception result is obtained by sampling the reception result for each bit, the sampling timing deviation with respect to the base station (that is, the clock deviation of the terminal device). Is represented by θ _e [rad], a reception result at a predetermined timing obtained by orthogonal detection is a vector S ₀ (α ₀ , β ₀ ), and a vector S ₄ (α ₄ , β ₄ ), which is expressed by the following equation using the amplitude angle display:

(Equation 1)

(Equation 2) In this case, the phase error θ _e can be expressed by the following equation.

(Equation 3)

Accordingly, the following equations are obtained from the equations (1) and (2).

(Equation 4) Can be obtained.

Where:

(Equation 5) When the relational expression of

(Equation 6) In this case, it can be understood that the phase error θ _e can be detected by solving the imaginary part of the equation (4).

That is, from equation (4),

(Equation 7) Can be obtained.

Thus, the terminal device 1 can detect the frequency error by executing the arithmetic processing of the equation (7) based on the reception result. Note that the data processing circuit 5 further performs an averaging process to remove the influence of noise or the like, and performs phase error θ.
_e has been made to detect.

That is, within one slot, the amplitude of the reception result does not change significantly, so that the data processing circuit 5

(Equation 8) And the phase error θ _e is detected.

Upon detecting the phase error θ _e in this manner, the terminal device 1 proceeds to step SP14 and corrects the frequency error of the received data based on the frequency error detection result.

That is, the data processing circuit 5 converts the phase error θ _e obtained by executing the arithmetic processing of equation (8) into a phase error θ ₀₀ per bit, and then stores the IQ data sequentially stored in the memory circuit. For (α, β), the following equation

(Equation 9) Is performed, and thereby required reception data is processed to correct the frequency error.

Subsequently, the terminal device 1 proceeds to step SP15, and sets the SCH detection timing based on the FCCH timing detection result and the frequency error detection result. In other words, in this type of terminal equipment, an error of about ± 3 [ppm] cannot be avoided as a frequency error of the clock source.
Is set in the 900 [MHz] frequency band, the frequency error is ± 27 with respect to the BCCH frequency.
00 [Hz].

Therefore, as shown in FIG. 3, the frequency error is set to 0 [Hz], ± 1 [kHz], ± 2 [kHz], ± 3 [kHz].
And the relationship between the frequency error and the timing of FCCH detection was simulated. As a result, it was found that when the frequency error became large, the timing of FCCH detection was delayed. In this case, 400
The FCCH was set to start from the bit, and the FCCH was detected 100 times under each condition, and the average value of the detection positions and the variance of the detection result were detected.

Here, the fading type of ra100 is a fading model generated when the vehicle travels in a rural scene at 100 [km] per hour, and the fading type of ht100 is in a hilly area at 100 [km] per hour. Means a model of fading that occurs when the vehicle runs. As a result, it can be seen that the timing of FCCH detection is delayed when the frequency error increases, regardless of the presence or absence of fading (that is, the frequency error is detected with a delay of 2 to 10 bits at ± 3 [kHz]).

In this simulation result, the case where the frequency error becomes large and the variance becomes small is also tabulated. In this simulation, if the timing of FCCH detection is greatly delayed, it is determined that an error has occurred. With such a setting, it has been found that the actual variance increases as the frequency error increases. Further, it has been found that such a tendency that the timing is delayed and a tendency that the variance increases are applicable to all the systems that detect the FCCH based on the correlation value in this way.

Thus, when the frequency error is large, if the timing of FCCH detection is corrected as detected several bits before the actually detected timing, the SCH detection probability can be improved accordingly. Understand. Also, when the frequency error is large, if the detection range of the SCH detection is expanded, the SCH detection probability can be improved accordingly.

By setting the detection range of the SCH detection to a small value in advance, when the frequency error is small, the amount of arithmetic processing can be reduced, the SCH can be detected easily, and the detection accuracy can be improved. Understand. Further, in this case, in the data processing circuit 5 composed of a digital signal processor,
The power consumption can be reduced by the reduced amount of arithmetic processing, and thus the power consumption of the entire terminal device 1 can be reduced.

Thus, in the case of this embodiment, the terminal device 1
In the following step SP16, step SP15
At the detection timing set in, the IQ data obtained by receiving the BCCH is stored in a memory circuit, and the SCH is detected based on a comparison result between the stored IQ data and a predetermined reference pattern.

At this time, when the frequency error is large, the data processing circuit 5 switches the SCH detection timing so that the SCH detection period is shortened so as to compensate for the late detection of the FCCH. The SCH detection timing is corrected based on the result. As a result, the data processing circuit 5 sets the SC based on the comparison result.
When H is detected, the overall processing timing is corrected based on this SCH, and as a result, B
After establishing synchronization with the base station in synchronization with the CCH, the process proceeds to step SP17 to complete the processing procedure.

(3) Effects of Embodiment According to the above configuration, based on the frequency error detection result,
If the frequency error is large, the SCH detection period is corrected so as to compensate for the late detection of the FCCH, and the SCH detection timing is corrected based on the frequency error detection result to thereby correct the SCH detection probability. Can be improved.

(4) Other Embodiments In the above-described embodiment, when the frequency error is large, the SCCH is compensated for to compensate for the late detection of the FCCH.
Although the case where the H detection period is corrected has been described, the present invention is not limited to this, and the SCH detection range may be expanded by switching the length of the detection period when the frequency error is large. That is, as shown in FIG. 4, in this case, in the terminal device, the process proceeds from step SP21 to step SP22, and when the FCCH is detected here, the frequency error is detected in the subsequent step SP24.

Further, the terminal device performs the following step SP24
After correcting the frequency error at step SP25, the SCH
Correct the detection timing. This allows the terminal device to:
In the following step SP26, S
CH is detected, and at this time, the number of data to be detected is switched based on the frequency error detected in step SP23. As a result, when the frequency error is large, the detection probability of the SCH can be further improved, and the terminal device can perform the step S
Moving to P27, the processing procedure is completed.

Further, in the above embodiment, the case where the frequency error is large has been described. However, the present invention is not limited to this, and the SCH detection range may be reduced when the frequency error is small. In this way, the processing time can be reduced when the frequency error is small.

Further, in the above-described embodiment, the case where the present invention is applied to a digital cellular to correct a frequency error has been described. The present invention can be widely applied to a wireless device that receives a transmission signal based on the second synchronization signal.

[0059]

As described above, according to the present invention, the timing of the first synchronizing signal is detected to detect the frequency error of the internal clock, and the second synchronizing signal is generated based on the frequency error detection result. By correcting the detection timing, it is possible to obtain a wireless device that can reliably detect the second synchronization signal even when the frequency error is large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital cellular terminal device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the SCH detection.

FIG. 3 is a table provided for explaining a relationship between a frequency error and FCCH detection;

FIG. 4 is a flowchart for explaining another embodiment.

FIG. 5 is a flowchart for explaining conventional SCH detection.

[Description of Signs] 1 ... terminal device, 2 ... antenna, 3, 10 ... amplifying circuit, 4 ... RF processing circuit, 5 ... data processing circuit, 6 ...
... Sound processing circuit, 8 ... Central processing unit.

Claims (4)

(57) [Claims] 1. A with respect to the first and second synchronization signals interposed transmission signal at a predetermined cycle wireless device for receiving the transmission signal, the first detecting the synchronization signal the first It detects the timing of the synchronization signal, and the first to detect the frequency error of the internal clock for the synchronizing signal, means for, based on Symbol timing detection result Ru is roughly synchronize the entire operation in the transmission signal, Subsequently, means for detecting the second synchronization signal for a predetermined period based on the timing detection result, and the entire operation is synchronized with the transmission signal based on the detection result of the second synchronization signal. receiving said transmission signal to form a state, in accordance with the above Symbol frequency error, the wireless apparatus characterized by comprising a means for correcting the time of detecting the second synchronization signal. 2. The detecting means according to claim 1, wherein when the frequency error is large, a period for detecting the second synchronizing signal is accelerated, and a period for detecting the second synchronizing signal is corrected. The wireless device according to claim 1, wherein: 3. The detecting means according to claim 2, wherein when the frequency error is large, the period for detecting the second synchronizing signal is switched to be longer to correct the period for detecting the second synchronizing signal. The wireless device according to claim 1 or 2, wherein 4. The apparatus according to claim 1, wherein the detecting means switches a period for detecting the second synchronization signal to be short when the frequency error is small. Wireless device.