JP3286283B2 - Radio clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio-controlled timepiece,
More specifically, the present invention relates to a radio-controlled timepiece that corrects time and the like based on data obtained by receiving a standard radio wave.

[0002]

2. Description of the Related Art In Japan, a long-wave standard radio wave on which a time code is superimposed is transmitted. The standard time signal is 40
Using a frequency of kHz, data such as accumulated days, hours, minutes, and the like from January 1 are transmitted in binary code with 60 seconds as one cycle. One bit is formed by one hertz rectangular pulse, and data contents are set by different pulse widths. Radio clocks are commercially available that receive this standard radio wave, correct the time so that the correct time is displayed (or instructed) based on the reception result, and can display the correct time.

FIG. 5 shows a configuration of a conventional radio-controlled timepiece.

A conventional radio timepiece has a 40 kHz receiving circuit 1.
0, a time data decoding circuit 20 connected to the 40 kHz receiving circuit 10, a clock circuit 30 connected to the time data decoding circuit 20, and an antenna 40.

The 40 kHz receiving circuit 10 includes an amplifier 11 for amplifying a radio wave received by the antenna 40, a detector 12 for detecting the signal amplified by the amplifier 11, and a TTL level time code TC based on the signal detected by the detector 12. (A signal sent in units of one second.
(Corresponding to the start of a second). Further, the time data decoding circuit 20 has a frequency of 40 kHz.
A signal detection circuit 21 for separating a reference 1-second signal and a data signal from the time code TC from the reception circuit 10, a control circuit 2
2. It is provided with a buffer memory 23. The clock circuit 30 further includes an oscillator 31 that oscillates a signal having a frequency of 32768 Hz, a frequency divider 32 that divides the oscillation frequency of the oscillator 31 to obtain a one-second timing, This is a quartz clock including an hour / minute / second counter 33 for obtaining seconds and a time display 34 for displaying a count result.

Next, the operation of the radio controlled timepiece having the configuration shown in FIG. 5 will be described.

The 40 kHz receiving circuit 10 starts operating when the power switch of the radio-controlled timepiece is turned on, when a battery is inserted in the battery box, or when a reset is performed.
After the reception signal amplified by the amplifier 11 is detected by the detector 12, the time code TC is demodulated by the demodulator 13.
The time code TC has a sufficiently high radio wave reception intensity,
Normal demodulation is performed when the apparatus is not affected by noise, and noise is mixed in when the radio wave is weak or when external noise is generated.

Next, the time data decoding circuit 20 will be described. Time code T output from demodulator 13
C is the signal detection circuit 21 of the time data decode circuit 20
Is input to The signal detection circuit 21 samples the time code TC, detects a rising edge, generates a second signal, and decodes a data signal from the time code TC. When detecting the rising edge of the time code TC, the signal detection circuit 21 makes the following determination and outputs it to the control circuit 22. (1) After the high level for 0.8 seconds ± 5 m seconds,
When the low level continues for 2 seconds ± 5 ms, “0”
Judgment. (2) After the high level has been reached for 0.5 seconds ± 5 m seconds,
When the low level continues for 5 seconds ± 5 ms, “1”
Judgment. (3) After the high level for 0.2 seconds ± 5 m seconds,
When the low level continues for 8 seconds ± 5 ms, the determination of “position (P)” is made. (4) If the previous data is “Position (P)” and the current data is also at the high level for 0.2 seconds ± 5 ms, and then continuously at the low level for 0.8 seconds ± 5 ms, Marker (M) ". (5) Other than the above (1) to (4), and 1 second ± 1
If the next rising edge cannot be detected within 0 ms, it is determined as "error".

The control circuit 22 stores the data from the signal detection circuit 21 in the buffer memory 23 and increments the memory address pointer by one. If an error occurs, the memory address pointer is set to 0, and the state returns to the state where the first rising edge is detected. When data is stored in the buffer memory 23, "marker (M)" data is detected. When this state is first detected, the memory address is stored in the marker address pointer. Further, the buffer memory 23
, And when the number thereof becomes 120 including the “marker (M)” data, a time code TC continuous for two minutes is obtained. If an error occurs on the way, clear the marker address pointer and set the memory address pointer to 0.
To return to the state where the first rising edge is detected.

When the time code TC for two consecutive minutes is stored in the buffer memory 23, the data of the time code TC of the first minute and the second minute is taken out from the buffer memory 23. At this time, since the address of the marker address pointer is not constant, the time code TC is used based on the address stored in the marker address pointer.
Let the position of the second of the offset be the offset. By adding the base and offset, the first minute, hour, and parity PA
1 and PA2 can be extracted from the buffer memory 23. The second minute data can be similarly extracted by using the address stored in the marker address pointer plus 60 as a base.

The time code TC data of the first minute and the second minute are compared, and it is confirmed that the data other than the minute, hour, and PA1 and PA2 are the same. Make sure that your eyes are +1 minute at the first minute. And,
Parities are calculated from the minute and hour data, and the first and second minutes are calculated.
It is confirmed whether the values are equal to the values of PA1 and PA2 at the minute. If all are OK, the received time code TC is regarded as valid. If the time code TC is valid, data of "minutes" and "hours" obtained by adding +1 minute to the second time code TC are prepared, and the display of the clock circuit is corrected simultaneously with the next second communication.

Next, the clock circuit 30 will be described.

An oscillator 31 having a built-in oscillation circuit has 327
Oscillates at a frequency of 68 Hz. The 32768 Hz signal is frequency-divided by the frequency divider 32 to generate a one-second signal (second signal). The second signal is input to the hour / minute / second counter 33, and a time display signal is generated. The hour / minute / second counter 33 corrects the hour / minute / second data in response to an instruction from the time data decoding circuit 20 and causes the time indicator 34 to display the corrected data.

Here, the time correction operation of the radio controlled timepiece will be described. The control circuit 22 of the time data decoding circuit 20 receives the radio wave once at every hour and corrects and displays the built-in clock, thereby eliminating an error in the displayed time. One reception is for a minimum of two time codes TC (two consecutive minutes), and reception is continued until a correct time code TC can be continuously received. Reception is continued for a maximum of 10 minutes (pre-installed time), but if the correct time code TC cannot be obtained, the time display is not corrected. Then, reception is performed again at the next hour after the built-in clock. At this time, if the correct time code TC is received, the time of the built-in clock is corrected.

If the signal is received in a state where noise is superimposed on the standard radio wave, the time cannot be corrected or the time is incorrectly corrected. Therefore, re-reception is performed on the assumption that reception has failed for one or more cycles as a reception error. Further, two cycles (two minutes) of continuous reception are performed, and the two cycles before and after are compared and inspected to check the reliability of radio wave reception. Further, when reception is not possible from 00 seconds, continuous reception is performed for a maximum of 180 seconds (3 minutes).

[0016]

However, according to the conventional radio timepiece, two cycles (two minutes) are continuously received, and the preceding and following cycles are compared and inspected to determine whether the received data is correct or not.
Furthermore, when the signal cannot be received from 0 seconds due to the fact that the signal is received with noise on the standard radio wave, a maximum of 180 seconds (3
Minutes) continuous reception is required. For this reason, it takes time until the time is adjusted, and the number of re-receptions increases.

Accordingly, it is an object of the present invention to provide a radio timepiece capable of shortening the time from the start of reception of the standard radio wave to the time correction and reducing the number of times of reception.

[0018]

In order to achieve the above object, the present invention provides a receiving circuit for receiving a standard radio wave and generating a time code, sampling the time code from the receiving circuit, and sampling the time code. 1 based on the result
A signal detection unit that outputs time correction data such as a second signal, minute data, hour data, and parity data, a memory that stores the time correction data with a predetermined storage capacity, and the time from the signal detection unit. After storing the correction data in the memory, calculate the minute and hour parity,
The control unit compares the calculation result with the parity data stored in the memory, and determines whether the time code is normal when they match, oscillates a reference signal of a predetermined frequency, and separates the reference signal. There is provided a radio controlled timepiece including a timepiece that performs time display based on a circulated signal and corrects the display content based on information from the control unit.

According to this configuration, the time code is demodulated by the receiving circuit from the received standard radio wave, and various data are decoded by the signal detecting circuit. The obtained data is stored in the memory via the control unit. When the time correction data is stored, the parity calculation is performed for each of the minute and the hour, and the result is compared with the parity data stored in the memory. Is determined to be normal without being affected by. Therefore, even when one cycle of data cannot be received continuously, the time can be adjusted using the minute and hour data and the parity data, so that the time until the time is adjusted and the number of receptions can be reduced.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a radio controlled timepiece according to the present invention. In FIG. 1, the same components as those shown in FIG. 5 are denoted by the same reference numerals.

The radio timepiece according to the present invention has a 40 kHz receiving circuit 1.
0, a time data decoding circuit 50 connected to the 40 kHz receiving circuit 10, a clock circuit 30 connected to the time data decoding circuit 50, and an antenna 40.

As described with reference to FIG.
The H receiving circuit 10 includes an amplifier 11, a detector 12, a demodulator 1
3. The clock circuit 30 includes the oscillator 3
1, a frequency divider 32, an hour-minute-second counter 33, and a time display 34.

The time data decoding circuit 50 has a frequency of 40 kHz.
A signal detection circuit 21, a counter memory 51, and a signal detection circuit 21 that output a reference one-second signal (hereinafter, referred to as a one-second signal) and a data signal from the time code TC from the reception circuit 10.
Data is written / read through a control circuit 52 that processes each signal from the controller, a comparison / determination unit 53 provided in the control circuit 52, a parity calculation unit 54 also provided in the control circuit 52, and the control circuit 52. It is configured with a ring buffer memory 55.

FIG. 2 shows the format of the time code TC generated by the 40 kHz receiving circuit 10. During the period from 0 to 60 seconds, minute data, time data, total date data, parity data, spare bits, year data, day of the week data, and the like are continuously transmitted.

Next, each block of the configuration of FIG. 1 will be described. Since the configurations of the 40 kHz receiving circuit 10 and the clock circuit 30 are the same as those described with reference to FIG. 5, the description will be omitted, and only the time data decoding circuit 50 will be described here.

In the time data decode circuit 50, the signal detection circuit 21 samples the time code TC input from the demodulator 13 and detects a rising edge to generate a one-second signal. At the same time, the data signal is decoded from the time code TC. Signal detection circuit 21
Generates a data signal according to the condition described in [0007] when detecting a rising edge.

Each of the above signals is transmitted from the signal detection circuit 21 to the control circuit 52. If the next rising edge cannot be detected within 1 second ± 10 msec when sampling the time code TC, the signal detection circuit 21
And returns to the initial state of detecting the rising edge. When data "0", "1" or "position (P)" is detected, the value of the counter at the sampling position for one second is stored in the counter memory 51, and the next rising edge of TC is detected. When you can't,
One second stored in the counter memory 51 is used as a one-second signal.

The control circuit 52 writes the data of the signal detection circuit 21 into the ring buffer memory 55 in synchronization with the one-second signal of the signal detection circuit 21. In the case of an error, the data "error (E)" is similarly stored in the ring buffer memory 55.
Write to. The ring buffer memory 55 allocates 60 storage areas from address 0 to address 59. When data is written to address 0 of the ring buffer memory 55, the ring buffer memory 55 shifts the data from address 1 to address 59 to the next higher storage area. Then, the data at address 0 is shifted to address 59.

When writing data to the ring buffer memory 55, "marker (M)" data is detected. When the "marker (M)" data is detected, the data has been written to the ring buffer memory 55, so the addresses of the minute data, the hour data, and the data of the parities PA1 and PA2 are determined. Therefore, the control circuit 52
Can refer to these data. When the control circuit 52 determines that there is no “error (E)” in the minute and hour data,
The parity calculation is started, and it is determined whether the minute data and the hour data are correct. If the time code TC is normal without being affected by noise or the like, +1 is added to the time code TC.
The display contents of the clock circuit 30 are corrected based on the divided minute data and hour data.

When the minute data and the hour data are incorrect as a result of the parity calculation, the process waits until data up to PA2 39 seconds later is stored in the ring buffer memory 55. On the ring buffer memory 55, minute data, hour data, and PA1 and PA2 data are stored at positions shifted by 39 seconds from the previous time. At this stage, the control circuit 52 can refer to the data in the ring buffer memory 55. The control circuit 52 confirms that there is no “error (E)” in the minute and hour data, performs parity calculation, and determines whether the minute and hour data are correct. If the time code TC is valid, the clock circuit 30 corrects the content to be displayed next based on the minute data and hour data of the time code TC.

As described above, even when data other than the hour data, minute data, and parity (PA) data of the time code TC cannot be received, the minute and hour time data can be corrected. Further, the time can be corrected by receiving the data of the time code TC in a shorter time (minimum 39 seconds) than that of a normal radio clock.

FIG. 3 shows an example of calculation of the storage contents of the ring buffer memory 55 and the parity check when the minute data, hour data, and parity data are normal.

A long wave standard radio wave having a frequency of 40 kHz (JJ
In Y), parity data of time data and minute data is transmitted. The even parity of 6 bits of time data and 7 bits of minute data is converted into parity PA1,
It is represented by one bit of PA2. Hereinafter, a calculation method by the parity calculation unit 54 will be described.

PA1 = (h20 + h10 + h8 + h4 +
Hour 2 + hour 1) mod2 PA2 = (min 40 + min 20 + min 10 + min 8 + min 4 + min 2
+ Minute 1) mod2 (mod2 is the remainder after dividing by 2 and its value is 1 or 0). For example, at 17:25, at 17:00, hour 20 = 0, hour 10 = 1, hour 8 = 0, hour 4 = 1, hour 2 =
1, the remainder of the time 1 = 1 + 1 + 1 + 0 + 1 + 1 + 1 = 44 ÷ 2 is zero. Therefore, PA1 = 0. On the other hand, the parity PA1 stored in the ring buffer memory 55 is 00h (= 0), which matches the parity calculation value of 0. Therefore, the time data is determined to be correctly received.

Next, for 25 minutes, minutes 40 = 0, minutes 20 =
1, minute 10 = 0, minute 8 = 0, minute 4 = 1, minute 2 = 0, minute 1
= 1 10 + 1 + 0 + 0 + 1 + 0 + 1 = 33 The remainder of 3 ÷ 2 is 1. Therefore, PA2 = 1. On the other hand, the parity PA2 stored in the ring buffer memory 55 is 01h (= 1), which matches the parity calculation value of 1. Therefore, it is determined that the minute data has been correctly received.

The parity PA calculated as described above
1 and PA2, it can be determined whether the minute data and the hour data are correct.

FIG. 4 shows an example of the storage contents and the parity check of the ring buffer memory 55 in which a parity error has occurred due to erroneous reception of hours or minutes due to noise or the like. Here, a case will be described in which the actual reception time of 17:25 is received as 15:25.

First, as described with reference to FIG. 3, 25 minutes are as follows: minute 40 = 0, minute 20 = 1, minute 10 = 0, minute 8 = 0, minute 4
= 1, minute 2 = 0, minute 1 = 1 0 + 1 + 0 + 0 + 1 + 0 + 1 = 33 ÷ 2, the remainder is 1 (PA2 = 1), and the parity PA2 stored in the ring buffer memory 55 is 01h.
Since (= 1), it is determined that the minute data has been correctly received.

At 15:00, hour 20 = 0, hour 10 = 1, hour 8 = 0, hour 4 = 1, hour 2 =
0, hour 1 = 1 10 + 1 + 0 + 1 + 0 + 1 = 33 The remainder of 33 ÷ 2 is 1. Therefore, the parity value (parity calculated value) calculated based on the data at the time of reception is 1. However, since the value of PA2 stored in the ring buffer memory 55 is 00h (= 0), it is determined that the time data is an error. Therefore, the data at this time is not used for correcting the clock display.

As described above, according to the present invention, even when data cannot be received continuously for 60 seconds, data such as "minutes" and "hours" necessary for displaying a clock can be normally received. If it can be confirmed, the time is displayed based on the received data without causing a communication error, so that the number of times of re-receiving and the like is reduced, and the time until the time is corrected can be shortened.

[0042]

As described above, according to the radio timepiece of the present invention, the time code is demodulated by the receiving circuit from the received standard radio wave, and various data are decoded by the signal detecting circuit. , Hour, each data of the parity is stored in the memory, a parity calculation is performed for each of the minute and the hour, and the calculation result is compared with the parity data stored in the memory to determine whether the parity data matches.
Since it is configured to determine whether the hour data and minute data are normal or error, even if continuous reception cannot be performed for 60 seconds,
Time display is enabled by the received data. Therefore, the time until the time is adjusted and the number of receptions can be reduced, and the number of re-receptions is also reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a radio controlled timepiece according to the present invention.

FIG. 2 is a configuration diagram showing a format of a time code TC generated by a 40 kHz receiving circuit of FIG. 1;

FIG. 3 is an explanatory diagram showing an example of calculation of a storage content and a parity check of a ring buffer memory when minute data, hour data, and parity data are normal.

FIG. 4 is an explanatory diagram showing a storage content of a ring buffer memory and a calculation example of a parity check in which a parity error has occurred due to erroneous reception of hours or minutes due to noise or the like.

FIG. 5 is a block diagram showing a configuration of a conventional radio-controlled timepiece.

[Explanation of symbols]

 Reference Signs List 10 40 kHz receiving circuit 11 Amplifier 12 Detector 13 Demodulator 21 Signal detection circuit 22, 52 Control circuit 23 Buffer memory 30 Clock circuit 31 Oscillator 32 Divider 33 Hour / minute / second counter 34 Hour display 40 Antenna 50 Hour data decoding circuit 51 Counter memory 53 Comparison / determination unit 54 Parity calculation unit 55 Ring buffer memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G04G 5/00 G04G 7/02 G04C 9/02

Claims (3)

(57) [Claims] 1. A receiving circuit for receiving a standard radio wave to generate a time code, sampling the time code from the receiving circuit, and based on a result of the sampling, a 1 second signal, minute data, hour data, and parity. a signal detection unit for outputting a time correction data of the data such as a ring buffer memory for storing the time correction data with a predetermined storage capacity, the said time correction data from the signal detector ring
After being stored in the buffer memory , the minute and hour parities are calculated, the calculation result is compared with the parity data stored in the ring buffer memory , and when they match, it is determined that the time code is normal. A control unit;
A clock unit for oscillating a reference signal of a predetermined frequency, performing time display based on a signal obtained by dividing the reference signal, and correcting the display content based on information from the control unit is provided. Radio clock. 2. The apparatus according to claim 1, wherein said signal detecting unit includes a counter memory for storing a count value of a sampling position of one second, and when a rising edge of said time code is not detected, said one second stored in said counter memory. 2. The radio-controlled timepiece according to claim 1, wherein the data is used as a second signal. 3. The control unit adds all data of the minute data and adds all data of the time data,
The remainder 1 or 0 obtained after individually dividing each of the added values by 2 is used as a parity calculation result, and the determination is made based on whether or not the parity calculation result matches each of the received parity data. The radio timepiece according to claim 1, wherein: