JP3285375B2 - Computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Object of the invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer,
In particular, the present invention relates to a computer in which processing circuits for executing instructions for a plurality of processing blocks included in a processing device are sequentially constructed before executing instructions included in a program.

[0003]

2. Description of the Related Art Conventionally, as this kind of computer,
(i) The instruction word and the data are held in the same storage device, and when executing the instruction included in the program, the instruction word and the data are read out from the storage device via a common bus and given to the processing device. And (ii) a pipeline that executes instructions contained in a program to speed up processing, and (iii) move data and instructions as packets via the bus. The thing which processes while doing it has been proposed.

[0004]

Therefore, in the conventional computer, (i) when the instruction word and the data are held in the same storage device, the instruction word and the data are moved through the same bus, so that the processing speed is reduced. It has the disadvantage that it is affected by the transfer speed of command words and data via the bus.
i) When the instructions included in the program are executed by the pipeline method, various processes must be completed within the same time, so there is a disadvantage that the processing time must be aligned with the longest processing time. iii) When processing data and instructions as packets while moving them through the bus, there is a disadvantage that the processing speed is affected by the transfer speed of data and instructions through the bus.

[0005] In order to eliminate these drawbacks, the present invention provides a processing circuit for executing instructions for a plurality of processing blocks included in a processing device prior to executing the instructions contained in a program. Are to be provided.

[0006]

Configuration of the Invention

[0007]

A computer according to the present invention comprises a program holding device for holding a program, a processing device having a plurality of processing blocks connected in a ring, and a processing device for executing processing included in the program. In the execution, the logic for performing the processing is rewritten, and in parallel with this, for the processing block in which the logic is rewritten, the processing based on the logic is executed according to the connection order of the processing blocks. A control device independently controlling each of the plurality of processing blocks included in the processing device, wherein each of the plurality of processing blocks performs an arithmetic operation based on the program. A number of gate circuits capable of constructing an arithmetic circuit for executing processing, and a plurality of gate circuits provided between the gate circuits. And a changeover switch for constructing the arithmetic circuit is controlled by the control device,
A re-programmable logic array, wherein the control device includes a storage element for controlling the changeover switch ;
Program counter, construction counter, and processing pointer
And the program counter from the program holding device.
The program counter reads the instruction indicated by the
Means for updating , wherein the storage element has a plurality of bits connected in advance for each one of the changeover switches, and always switches the contents of one bit of the plurality of bits. A selector is provided to control the on / off of the switch by transmitting the signal to the switch .
And the selector responds to the read instruction.
Provided in the processing block indicated by the construction pointer
The on / off state of all the changeover switches is determined by the read command
Control according to the instruction, and log the processing contents corresponding to the instruction.
To build a trick into the processing block.
The control device further controls the changeover switch in parallel with the control of the changeover switch.
In the processing block indicated by the processing pointer,
The processing based on the constructed logic is performed by the processing block.
Means to execute the
When the construction of the logic is completed,
The block of the next processing block after the relevant processing block in the connection
If the trick is already processed, the next
Update the construction pointer to indicate a block,
Execution of processing based on the logic in the processing block
When a row is complete, those in the annular connection at that time
The logic of the next processing block after this processing block has been built
If so, as shown in the next processing block,
Means for updating the processing pointer .

[0008]

The computer according to the present invention stores the program as specified in the above-mentioned [Solution to Problem] section.
Program holding device and multiple connected in a ring
Processing device having processing blocks of
In causing the processing device to execute the process included in
While rewriting the logic for performing the above processing,
In parallel with the rewritten processing block
The process based on the logic is
To the processing unit so that the processing is executed in accordance with the connection order of
Each of the included processing blocks is independently controlled.
Control unit to control one of the processing blocks.
While the other processing block
Performing the transposed operation is a
Can be performed in parallel with independent timing for each lock
It becomes possible. In addition, the log of these multiple processing blocks
Switching of processing and processing operations as described above
Conventional FPLA etc.
Equivalent processing with fewer processing blocks than when using
Can be performed. This makes it possible to use
Data paths can be separated from each other and processed
Eliminating wasted time (such as waiting for job execution)
The effect is that the processing speed is increased.
Can be achieved.

[0009]

Next, a computer according to the present invention will be described in detail with reference to preferred embodiments.

However, the embodiments described below are:
It is described for the purpose of facilitating or facilitating the understanding of the present invention and is not described for limiting the present invention.

In other words, each element disclosed in the embodiments described below includes all design changes and equivalent replacements that fall within the spirit and scope of the present invention.

(Description of the accompanying drawings)

FIG. 1 is a block circuit diagram showing a first embodiment of a computer according to the present invention. A switch controller 12A is provided between a controller 13 and processing blocks 11A to 11D of a processor 11. The case where ~ 12D is provided is shown.

FIG. 2A and FIG. 2B are block circuit diagrams for exemplarily showing a part of the embodiment shown in FIG. 1 in an enlarged manner. Fields constituting processing blocks 11A to 11D of the processing unit 11 are shown in FIG. A part of the programmable gate array FPGA is shown in an enlarged manner.

FIGS. 3A and 3B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG.

FIGS. 4A and 4B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG.

FIGS. 5A and 5B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG. 1, and show a processing block 11C of the processing device 11.

FIGS. 6A and 6B are block circuit diagrams showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and show a processing block 11D of the processing unit 11.

FIG. 7 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1, and shows the switch control device 12A.

FIG. 8 is a block circuit diagram showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and shows a switch control device 12B.

FIG. 9 is a block circuit diagram showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and shows a switch control device 12C.

FIG. 10 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1 and shows a switch control device 12D.

FIGS. 11A and 11B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG.

FIG. 12 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
Is shown in FIG.

FIG. 13 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
Is shown in FIG.

FIG. 14 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
Is shown in FIG.

FIG. 15 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
Is shown in FIG.

FIG. 16 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
3 shows the control signal generation circuit 313A.

FIG. 17 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
The control signal generation circuit 313B of FIG.

FIG. 18 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
3 shows a control signal generation circuit 313C.

FIG. 19 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
3 shows a control signal generation circuit 313D.

FIG. 20 is a block circuit diagram for showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and shows a construction pointer 413.

FIG. 21 is a block circuit diagram showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and shows a processing pointer 513.

FIG. 22 is a block circuit diagram showing a part of the embodiment shown in FIG. 1 in an enlarged manner, and shows a program counter 613.

FIG. 23 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 1, and shows a load instruction processing circuit 211X (X = A to D).

FIG. 24 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 1, and shows an addition instruction processing circuit 211Y (Y = A to D).

FIG. 25 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 1, and shows a load effective address instruction processing circuit 211Z (Z = A to D).
.

FIG. 26 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 1, and shows an arithmetic left shift instruction processing circuit 211W (W = A to D).

FIG. 27 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 1, and shows a store instruction processing circuit 211V (V = A to D).

FIG. 28 is an explanatory diagram showing instruction words included in the program processed in the embodiment shown in FIGS.

FIG. 29 is a block circuit diagram showing a second embodiment of the computer according to the present invention. A switch control device is provided between the control device 23 and the processing blocks 21A to 21D of the processing device 21. The case where it is not arranged is shown.

FIGS. 30A and 30B are block circuit diagrams for enlarging and showing a part of the embodiment shown in FIG. 29, and show a processing block 21A of the processing device 21.

FIGS. 31A and 31B are block circuit diagrams for enlarging and showing a part of the embodiment shown in FIG. 29, and show a processing block 21B of the processing device 21.

FIGS. 32A and 32B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG. 29, and show a processing block 21C of the processing device 21.

FIGS. 33A and 33B are block circuit diagrams for enlarging and showing a part of the embodiment shown in FIG. 29, and show a processing block 21D of the processing device 21.

FIGS. 34A and 34B are block circuit diagrams for exemplarily showing a part of the embodiment shown in FIG. 29 in an enlarged manner, and show a processing circuit 221A in a processing block 21A.

FIGS. 35A and 35B are block circuit diagrams for exemplifying and enlarging a part of the embodiment shown in FIG. 29, and show a processing circuit 221B in a processing block 21B.

FIGS. 36A and 36B are block circuit diagrams for illustrating a part of the embodiment shown in FIG. 29 in an enlarged manner, and show a processing circuit 221C in a processing block 21C.

FIGS. 37A and 37B are block circuit diagrams for exemplarily showing a part of the embodiment shown in FIG. 29 in an enlarged manner, and show a processing circuit 221D in a processing block 21D.

FIGS. 38A and 38B are block circuit diagrams showing an enlarged part of the embodiment shown in FIG. 29, and show the control device 23.

FIG. 39 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows an instruction decoder 223A.

FIG. 40 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows an instruction decoder 223B.

FIG. 41 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows an instruction decoder 223C.

FIG. 42 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows an instruction decoder 223D.

FIG. 43 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows a control signal generation circuit 323A.

FIG. 44 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows a control signal generation circuit 323B.

FIG. 45 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows a control signal generation circuit 323C.

FIG. 46 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG.
23 shows a control signal generation circuit 323D.

FIG. 47 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner, and shows a construction pointer 423.

FIG. 48 is a block circuit diagram for enlarging and showing a part of the embodiment shown in FIG. 29, and shows a processing pointer 523.

FIG. 49 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29, and shows a program counter 623.

[0062] Figure 50 is a block circuit diagram for showing an enlarged part of the embodiment shown in FIG. 29 shows a load instruction processing circuit 221X ₁ (X = A~D).

[0063] Figure 51 is a block circuit diagram for showing an enlarged part of the embodiment shown in FIG. 29 shows a store instruction processing circuit 221X ₂ (X = A~D).

[0064] Figure 52 is a block circuit diagram for showing an enlarged part of the embodiment shown in FIG. 29 shows a load effective address instruction processing circuit 221X ₃ (X = A~
D).

[0065] Figure 53 is a block circuit diagram for showing an enlarged part of the embodiment shown in FIG. 29 shows an add instruction processing circuit 221X ₄ (X = A~D).

[0066] Figure 54 is a block circuit diagram for showing an enlarged part of the embodiment shown in FIG. 29 shows an arithmetic left shift instruction processing circuit 221X ₅ (X = A~D) .

FIGS. 55A and 55B are block circuit diagrams for exemplarily showing a part of a third embodiment of the computer according to the present invention, and are included in the embodiment shown in FIG. 29. A processing circuit 231A that can be replaced with the processing circuit 221A in the processing block 21A is shown.

FIG. 56 and FIG. 56B are block circuit diagrams for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner, and are included in the embodiment shown in FIG. A processing circuit 231B that can replace the processing circuit 221B in the processing block 21B is shown.

FIG. 57 and FIG. 57B are block circuit diagrams for exemplarily showing a part of a third embodiment of the computer according to the present invention in an enlarged manner, and are included in the embodiment shown in FIG. A processing circuit 231C that can be replaced with the processing circuit 221C in the processing block 21C is shown.

FIGS. 58 and 58B are block circuit diagrams for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner, and are included in the embodiment shown in FIG. 29. A processing circuit 231D that can be replaced with the processing circuit 221D in the processing block 21D is shown.

(Configuration of the First Embodiment)

First, the configuration of the first embodiment of the computer according to the present invention will be described in detail with reference to FIGS. 1 to 28. Here, for the purpose of simplifying the description, a case where the program shown in Table 1 is executed (that is, a case where a load instruction, a load instruction, an addition instruction, an arithmetic left shift instruction and a store instruction are sequentially executed) will be mainly described. However, there is no intention to limit the invention to this.

Overall Configuration (See FIG. 1)

Reference numeral 10 denotes a computer according to the present invention, and an appropriate number (here, “four”) of processing blocks 11 A
And a processing unit 11 for executing the program while sequentially constructing an arithmetic circuit required for executing the program in the processing blocks 11A to 11D, and processing blocks 11A to 11D included in the processing unit 11. The output terminals are respectively connected to the processing blocks 11A to 11D, and are provided with switch control devices 12A to 12D for sequentially constructing required arithmetic circuits in the processing blocks 11A to 11D in the arithmetic processing by the processing device 11.

The computer 10 according to the present invention also
First to fourth output terminals (specifically, first output terminals of instruction decoders 213A to 213D) are connected to input terminals of the switch control devices 12A to 12D, respectively, and the first to fourth output terminals are connected to the input terminals of the switch control devices 12A to 12D.
(Specifically, the second of the instruction decoders 213A to 213D
To the sixth to sixth output terminals, the second to fourth output terminals and third input terminals of the control signal generating circuits 313A to 313D, and the first to fourth input terminals of the processing pointer 513).
A to 11D input / output terminals (Specifically, input data selection circuit 11
1A to 111D and the first to third input terminals and third output terminals of the processing circuits 211A to 211D, respectively, and the switch control devices 12A to 12D are appropriately connected. By controlling the processing blocks 11A to 11D, necessary arithmetic circuits are sequentially constructed in the processing blocks 11A to 11D as described later.
And an output terminal connected to an input terminal of the control device 13 (specifically, first input terminals of the instruction registers 113A to 113D) and an input terminal.
(Specifically, an address input terminal) is connected to a fifth output terminal of the control device 13 (specifically, an output terminal of the program counter 613), and a program for controlling the control device 13 is provided.
(And a program holding device 14 for holding the program for the arithmetic processing in the processing blocks 11A to 11D of the processing device 11 and outputting the program to the control device 13 in response to a request from the control device 13). I have.

The computer 10 according to the present invention further comprises:
Input / output terminals of processing blocks 11A to 11D of processing device 11 (specifically, address signal output terminals AD _AOUT of processing circuits 211A to 211D)
ADA _DOUT , a bus control signal output terminal BCNT _AOUT BBCNT _DOUT and a data input / output terminal D _{A DD D} ) to pass unprocessed data to the processing blocks 11A 1111D of the processing device 11; Processing blocks 11A to 11D of the processing device 11
A data bus 15 for receiving processed data from the data bus 15, an input / output terminal connected to the data bus 15, and a data holding device 16 for holding unprocessed data and processed data; The data input / output terminals are connected to each other, and the unprocessed data held in the data holding device 16 is received in advance from an external device (not shown) via the data bus 15 and then sent to the data holding device 16 via the data bus 15. An input / output device 17 is provided for receiving processed data provided and held in the data holding device 16 via the data bus 15 and then sending the processed data to an external device (not shown). Incidentally, the input / output device 17 is a reset for generating a reset signal used in the control device 13 (specifically, the control signal generation circuits 313A to 313D, the configuration pointer 413, the processing pointer 513, and the program counter 613). A signal source (not shown) is built in and generates a reset signal when power is turned on and when a reset button is pressed.

Configuration of processing unit 11 (see FIGS. 1 to 6B)

The processing device 11 is, for convenience of explanation, 4
Although it is assumed that the processing block is constituted by one processing block 11A to 11D, the present invention is not limited to this, and includes all processing blocks constituted by a plurality of processing blocks.

Each of the processing blocks 11A to 11D has an appropriate number to construct an arithmetic circuit required for executing the program.
(For example, 10000) gate circuits (for example, an appropriate number of exclusive OR circuits, an appropriate number of AND circuits, an appropriate number of OR circuits, and an appropriate number of NAND circuits) are connected to an appropriate number of changeover switches SWNG _A1. ~ SWNG _Am ; ・ ・ ・; Field-programmable gate array configured by appropriately (eg, matrix) arrangement via SWNG _{D1 to} SWNG _Dm
It is composed of FPGA. The field programmable gate array FPGA includes, for example, two exclusive OR circuits EXOR ₁ and EXOR ₂ , two AND circuits AND ₁ and AND ₂ , two OR circuits OR ₁ and OR _2, and three NAND circuits NAND _{1 to} NAND _3. And 20 crosspoint switches CSW _{11 to} CSW ₁₄ ; ・ ・ ・; CS
It may be created by arranging them in a matrix via cutting switches SW _{1112 to} SW ₄₄₅₄ of W _{51 to} CSW ₅₄ and W 22 (FIG. 2A)
And FIG. 2B). Incidentally, the cross-point switch _{CSW 11 ~CSW 14; ···; CSW} 51 ~CSW 54 and disconnect switch SW ₁₁₁₂ to SW ₄₄₅₄ is switched switch SWNG _A1 ~SWNG _Am; ··
. SWNG _{D1 to} SWNG _Dm are appropriately arranged.

Processing block 11A (see FIGS. 3A and 3B)

The processing block 11A of the processing device 11
The second input terminal is the second input terminal of the instruction decoder 213A of the control device 13.
The input data S _D1 to S _D1 ... Applied to the third to fifth input terminals according to the input data selection signals SIA ₀ and SIB ₀ supplied from the instruction decoder 213A of the control device 13 and connected to the third output terminal. S _D3 from selecting a desired input data the data output terminal D _AAOUT, D _ABOUT input data from the S _AAIN, and the input data selecting circuit 111A for outputting as S _ABIN, the data input D _AAIN the input data selecting circuit 111A Data output terminal D
_AAOUT and a data input terminal D _ABIN are connected to a data output terminal D _ABOUT of the input data selection circuit 111A, and a processing start signal input terminal STRT _A is connected to a second output terminal of the control signal generation circuit 313A of the control device 13. connected to the fifth output terminal of the connected and the instruction decoder of the address signal input terminal AD _a is connected to a sixth output of the instruction decoder 213A of the control unit 13 and the index modification signal input IXS _a control unit 13 213A And the processing end signal output terminal END _A is the third input terminal of the control signal generation circuit 313A of the control device 13 and the first input terminal of the processing pointer 513.
And the address signal output terminal AD _AOUT is connected to the data bus 15 and the bus control signal output terminal BCNT _AOUT
Input There processing start signal STRT ₀ given from the data connected to the bus 15 and the data input and output terminals D _A is connected to and control the data bus 15 13, the address signal AD _0, in response to the index modification signal IXS ₀ The input data S _AAIN , S _{ABIN supplied} from the data selection circuit 111A or the unprocessed data S _{ABS supplied} from the data bus 15 are appropriately processed to _{generate a} first output terminal (that is, a data output terminal D _AOUT ) or a data input terminal. _A processing circuit 211A for outputting the output data S _A or the processed data S _ABS ^* from the output terminal DA, and a first to third input terminals connected to a first output terminal of the processing circuit 211A (that is, the data output terminal D _ABS) ^. _AOUT ) and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 411D (that is, the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ), and the seventh input terminal is connected to the instruction decoder 213A of the control device 13. A control device connected to the fourth output end;
13 output data S _A and the register circuit RG fourth to hold circuit 411D to the input terminal of the sixth processing circuit 211A in response to the output data selection signal SO ₀ provided from the instruction decoder 213A of
Input data S _D1 to S _D1 given from S _{D1 to} RGS _D3 , respectively.
An output data selection circuit 311A for outputting the first to third data output selects the desired data from the S _D3 as output data S _A1 to S _A3, writing to the second output terminal of the processing circuit 211A Signal input terminals (that is, register circuits RGS _{A1 to} RG
A write signal input terminal WT of S _A3 is connected to each of the first to third data output terminals of the output data selection circuit 311A.
The data input terminals D) of RGS _{A1 to} RGS _A3 are connected to each other, and the output data S _{A1 to} S _A3 given from the output data selection circuit 311A are written into the write signal WT given from the processing circuit 211A.
A holding circuit 411A for holding the register circuits RGS _{A1 to} RGS _A3 in response to ₀ is included.

In the input data selection circuit 111A, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 411D (that is, the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ). connected and the control input is the control device 13 and the second register circuit of the holding circuit 411D according to the input data selection signal SIA ₀ provided from the instruction decoder 213A of connected and the control device 13 to the output terminal of the instruction decoder 213A of RGS _D1 input given from ～RGS _D3 data S _D1 to S _D3
And a selector circuit SEL _A1 for selecting one of them and outputting the selected data from the data output terminal D _AAOUT, and a first to third data output terminal of the holding circuit 411D.
(I.e., the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ) and the control input terminal is connected to the third output terminal of the instruction decoder 213A of the control device 13. register circuits holding circuit 411D according to the input data selection signal SIB ₀ given RGS _D1 ~
A selector circuit SEL _A2 for selecting one of the input data S _{D1 to} S _D3 given from RGS _{D 3} and outputting it from the data output terminal D _ABOUT is included.

[0083] Output data selection circuit 311A includes a decode the output data selection signal SO ₀ supplied from the fourth connection to which instruction decoder 213A to the output terminal of the instruction decoder 213A of input control unit 13 decodes the result _A decoder DEC _A for outputting the selection signals SO _{A1 to} SO _A3 , a first data input terminal connected to the data output terminal D _AOUT of the processing circuit 211A, and a second data input terminal connected to the first data input terminal of the holding circuit 411D. the data output (i.e. the data output terminal Q of the register circuit RGS _D1) the selection signal SO _A1 that is connected to and controlled input to is given from the decoder DEC _a is connected to the first output of the decoder DEC _a When active (ie, “1”), the output data S _A given from the processing circuit 211A is selected and output as output data S _A1 , and the selection signal SO _A1 given from the decoder DEC _A is inactive (ie, “0”). ”) Holds circuit 411D The selector circuit SELT _A1 for selecting and outputting the input data S _D1 supplied from the register circuit RGS _D1 as output data S _A1
When the first data input terminal connected to the data output terminal D _AOUT processing circuit 211A and the second data input terminal holding circuit 41
1D second data output terminal (ie, register circuit RGS _D2
And the control input is connected to the second output of the decoder DEC _A , and processing is performed when the selection signal SO _A2 supplied from the decoder DEC _A is active (ie, “1”). The output data S _A given from the circuit 211A is selected and output as output data S _A2 , and when the selection signal SO _A2 given from the decoder DEC _A is inactive (ie, “0”), the register circuit of the holding circuit 411D is selected. A selector circuit SELT _A2 for selecting the input data S _D2 given from RGS _D2 and outputting it as output data S _A2 ; a first data input terminal connected to the data output terminal D _AOUT of the processing circuit 211A; 2
Is the third data output terminal of the holding circuit 411D.
(I.e. register circuit RGS _D3 data output terminal Q of) is connected to and the third is connected to an output end decoder DEC selection signal given from the _A SO control input end decoder DEC _{A
When A3} is active (ie, "1"), it selects the output data S _A given from the processing circuit 211A and outputs it as output data S _A3 , and the selection signal SO _A3 given from the decoder DEC _A
Is inactive (ie, “0”), the selector circuit SE for selecting the input data S _D3 given from the register circuit RGS _D3 of the holding circuit 411D and outputting it as output data S _A3.
LT _A3 .

Processing block 11B (see FIGS. 4A and 4B)

The processing block 11B of the processing device 11
The second input terminal is the second input terminal of the instruction decoder 213B of the control device 13.
The input data S _A1 ... Applied to the third to fifth input terminals in accordance with the input data selection signals SIA ₁ and SIB ₁ supplied from the instruction decoder 213B of the control device 13 and connected to the third output terminal. An input data selection circuit 111B for selecting desired input data from S _A3 and outputting it as input data S _BAIN and S _BBIN from data output terminals D _BAOUT and D _BBOUT , and a data input terminal D _BAIN for input data selection circuit 111B Data output terminal D
To the second output terminal of the control signal generating circuit 313B of connected to _BAOUT and data input D _BBIN is connected to the data output terminal D _BBOUT the input data selecting circuit 111B and process start signal input terminal STRT _B control unit 13 connected to the fifth output terminal of the connected and the instruction decoder of the address signal input terminal AD _B is connected to a sixth output of the instruction decoder 213B of the controller 13 and the index modification signal input IXS _B control unit 13 213B The processing end signal output terminal END _B is connected to the third input terminal of the control signal generation circuit 313B of the control device 13 and the first input terminal of the processing pointer 513.
And the address signal output terminal AD _BOUT is connected to the data bus 15 and the bus control signal output terminal BCNT _BOUT
Input There processing start signal STRT ₁ given from the data connected to the bus 15 and the data input and output terminals D _B are controlled device connected to the data bus 15 13, the address signal AD _1, in response to the index modification signal IXS ₁ The input data S _BAIN and S _{BBIN supplied} from the data selection circuit 111B or the unprocessed data S _{BBS supplied} from the data bus 15 are appropriately processed to output a first output terminal (that is, a data output terminal _DBOUT ) or a data input terminal. a processing circuit 211B for outputting from the output terminal D _B as output data S _B or already processed data S _BBS ^*, the first output of the first to third input end processing circuit 211B (i.e. data output terminal D _BOUT ) and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 411A (that is, the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ), and the seventh input terminal is connected to the instruction decoder 213B of the control device 13. A control device connected to the fourth output end;
13 output data S _B and the register circuit RG fourth to holding circuit 411A to the input terminal of the sixth processing circuit 211B in response to the output data selection signal SO ₁ given from the instruction decoder 213B of
S _A1 ~RGS _A3 input data S _A1 ~ given each from
An output data selection circuit 311B for selecting desired data from S _A3 and outputting it from the first to third data output terminals as output data S _{B1 to} S _B3 , and writing to a second output terminal of the processing circuit 211B Signal input end (that is, register circuits RGS _{B1 to} RG
Write signal input of S _B3 WT) is first to third data input to the first to third data output of each connected and the output data selection circuit 311B (i.e. register circuit
The data input terminals D) of RGS _{B1 to} RGS _B3 are connected to each other, and the output data S _{B1 to} S _B3 given from the output data selection circuit 311B are written into the write signal WT given from the processing circuit 211B.
A holding circuit 411B for holding the register circuits RGS _{B1 to} RGS _B3 in accordance with ₁ is included.

In the input data selection circuit 111B, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 411A (that is, the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ). connected and the control input is the control device 13 and the second register circuit of the holding circuit 411A according to the input data selection signal SIA ₁ given from the instruction decoder 213B of connected and the control device 13 to the output terminal of the instruction decoder 213B of RGS _A1 input data given from ~RGS _A3 S _A1 ~S _A3
And a selector circuit SEL _B1 for selecting one of them and outputting it from the data output terminal D _BAOUT, and a first to third data output terminal of the holding circuit 411A as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ) and the control input terminal is connected to the third output terminal of the instruction decoder 213B of the control device 13. register circuits holding circuit 411A according to the given input data selection signal SIB ₁ RGS _A1 ~
And a selector circuit SEL _B2 for choosing one of RGS _{A 3} input data given from the S _A1 to S _A3 output from the data output terminal D _BBOUT, are inclusions.

[0087] Output data selection circuit 311B is a decodes the output data selection signal SO ₁ given from the connected and instruction decoder 213B to the fourth output of the instruction decoder 213B of input control unit 13 decodes the result selection signal SO _B1 to SO and a decoder DEC _B for outputting as _B3, first the first data input terminal connected to the data output terminal D _BOUT processing circuit 211B and a second data input terminal holding circuit 411A the data output (i.e. the data output terminal Q of the register circuit RGS _A1) selection signal SO _B1 that is connected to and controlled input to is given from the decoder DEC _B is connected to the first output of the decoder DEC _B is active (i.e. "1") processing circuit 211B given output data by selecting the S _B from the outputs as output data S _B1 and selection signals SO _B1 provided from the decoder DEC _B is inactive (i.e., when the "0 ”) Holds circuit 411A The selector circuit SELT _B1 for selecting and outputting the input data S _A1 supplied from the register circuit RGS _A1 as output data S _B1
When the first data input terminal connected to the data output terminal D _BOUT processing circuit 211B and a second data input terminal holding circuit 41
1A second data output terminal (ie, register circuit RGS _A2
Process when the selection signal SO _B2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _B is connected to the second output terminal of the decoder DEC _B of the active (i.e., "1") register circuits holding circuits 411A when the output is and the selection signal SO _B2 is inactive given from the decoder DEC _B selects the output data S _B supplied from circuit 211B as the output data S _B2 (i.e. "0") A selector circuit SELECT _B2 for selecting the input data S _A2 given from RGS _A2 and outputting it as output data S _B2 , a first data input terminal connected to the data output terminal D _BOUT of the processing circuit 211B, and 2
Is the third data output terminal of the holding circuit 411A.
(I.e. register circuit RGS _A3 data output terminal Q of) it is connected to and the third is connected to an output end decoder DEC selection signal given from _B SO control input end decoder DEC _B
B3 is active (i.e. "1") when the processing circuit 211B outputs data S _B given selected and from output as output data S _B3 and the decoder DEC selection signal given from the _B SO _B3
Is inactive (ie, “0”), a selector circuit SE for selecting the input data S _A3 given from the register circuit RGS _A3 of the holding circuit 411A and outputting it as output data S _B3.
LT _B3 .

Processing block 11C (see FIGS. 5A and 5B)

The processing block 11C of the processing device 11 includes
The second input terminal is the second input terminal of the instruction decoder 213C of the control device 13.
The input data S _B1 to S _B1 ... Applied to the third to fifth input terminals according to the input data selection signals SIA ₂ and SIB ₂ provided from the instruction decoder 213C of the control device 13 and connected to the third output terminal. It desired select input data to the data output terminal D _CAOUT from S _B3, input data S _CAIN from D _CBOUT, input data selection circuit 111C for outputting the S _Cbin, the data input D _CAIN is the input data selection circuit 111C Data output terminal D
To the second output terminal of the control signal generating circuit 313C of being connected to _CAOUT and data input D _Cbin is connected to the data output terminal D _CBOUT the input data selection circuit 111C and process start signal input terminal STRT _C the control unit 13 connected to the fifth output terminal of the connected and the instruction decoder of the address signal input terminal AD _C is connected to a sixth output of the instruction decoder 213C of control device 13 and the index modification signal input IXS _C control unit 13 213C And the processing end signal output terminal END _C is connected to the third input terminal of the control signal generation circuit 313C of the control device 13 and the first input terminal of the processing pointer 513.
And the address signal output terminal AD _COUT is connected to the data bus 15 and the bus control signal output terminal BCNT _COUT
Input There processing start signal STRT ₂ provided from which the controller 13 is connected to the connected and the data input and output terminals D _C is the data bus 15 to the data bus 15, address signals AD _2, in response to the index modification signals IXS ₂ The input data S _CAIN and S _{CBIN supplied} from the data selection circuit 111C or the unprocessed data S _{CBS supplied} from the data bus 15 are appropriately processed to _{generate a} first output terminal (that is, a data output terminal D _COUT ) or a data input terminal. a processing circuit 211C for outputting from the output terminal D _C as output data S _C or already processed data S _CBS ^*, the first output of the first to third input end processing circuit 211C (i.e. the data output terminal D _COUT ) and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 411B (that is, the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ), and the seventh input terminal is connected to the instruction decoder 213C of the control device 13. A control device connected to the fourth output end;
13 output data S _C and the register circuit RG fourth to hold circuit 411B to the input terminal of the sixth processing circuit 211C according to the output data selection signal SO ₂ given from the instruction decoder 213C of
Input data S _B1 to S _B1 given from S _{B1 to} RGS _B3 respectively
An output data selection circuit 311C for selecting desired data from S _B3 and outputting it as output data S _{C1 to} S _C3 from first to third data output terminals, and writing to a second output terminal of processing circuit 211C Signal input terminal (that is, register circuits RGS _{C1 to} RG
Write signal input terminal WT) is first to third data input to the first to third data output of each connected and the output data selection circuit 311C of S _C3 (i.e. register circuit
The data input terminals D) of the RGS _{C1 to} RGS _C3 are connected to each other, and the output data S _{C1 to} S _C3 given from the output data selection circuit 311C are written into the write signal WT given from the processing circuit 211C.
₂ and a holding circuit 411C for holding the data in the register circuits RGS _{C1 to} RGS _C3 .

In the input data selection circuit 111C, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 411B (that is, the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ). connected and the control input is the control device 13 and the second register circuit of the holding circuit 411B according to the input data selection signal SIA ₂ given from the instruction decoder 213C outputs the connected and the control device to end 13 of the instruction decoder 213C of RGS _B1 input given from ~RGS _B3 data S _B1 ~S _B3
And a selector circuit SEL _C1 for selecting one of them and outputting it from the data output terminal D _CAOUT, and a first to third data output terminal of the holding circuit 411B as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ), and the control input terminal is connected to the third output terminal of the instruction decoder 213C of the control device 13. register circuits holding circuit 411B according to the given input data selection signal SIB ₂ RGS _B1 ~
A selector circuit SEL _C2 for selecting one of the input data S _{B1 to} S _B3 given from the RGS _{B 3} and outputting it from the data output terminal D _CBOUT is included.

[0091] Output data selection circuit 311C is the fourth of the connected and given from the instruction decoder 213C outputs data selected output signal SO ₂ decode decodes the result of the instruction decoder 213C of input control unit 13 a decoder DEC _C for outputting a selection signal SO _C1 ~SO _C3, first the first data input terminal connected to the data output terminal D _COUT processing circuit 211C and the second data input terminal holding circuit 411B the data output (i.e. register circuit RGS _B1 data output terminal Q) of the selection signal SO _C1 that is connected to and controlled input to is given from the decoder DEC _C is connected to the first output of the decoder DEC _C is active (i.e. "1") processing circuits given output data S _C to select from 211C outputs as output data S _C1 and the selection signal SO _C1 is inactive given from the decoder DEC _C (that is, when "0 ”) When the holding circuit 411B The selector circuit SELT _C1 to select the input data S _B1 supplied from the register circuit RGS _B1 and outputs it as output data S _C1
When the first data input terminal connected to the data output terminal D _COUT processing circuit 211C and the second data input terminal holding circuit 41
1B second data output terminal (ie, register circuit RGS _B2
Process when the selection signal SO _C2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _C is connected to the second output terminal of the decoder DEC _C of the active (i.e., "1") register circuits holding circuits 411B when the outputs and selectively signal SO _C2 is inactive given from the decoder DEC _C selects the output data S _C given from the circuit 211C as output data S _C2 (i.e. "0") A selector circuit SELECT _C2 for selecting input data S _B2 given from RGS _B2 and outputting it as output data S _C2 ; a first data input terminal connected to a data output terminal D _COUT of the processing circuit 211C; 2
Is connected to the data output terminal Q of the register circuit RGS _B3 of the holding circuit 411B, and the control input terminal is connected to the decoder DE.
C _C third selection signal SO _C3 supplied from the connected and the decoder DEC _C to the output terminal of the active (i.e. "1") to select the output data S _C supplied from the processing circuit 211C when the output It outputs as the data S _C3 and selects and outputs the input data S _B3 given from the register circuit RGS _B3 of the holding circuit 411B when the selection signal SOC ₃ given from the decoder DEC _C is inactive (ie, “0”). And a selector circuit SELECT _C3 for outputting as data S _C3 .

Processing block 11D (see FIGS. 6A and 6B)

The processing block 11D of the processing device 11 includes the first
The second input terminal is the second input terminal of the instruction decoder 213D of the control device 13.
The input data S _C1 ... Provided to the _third to fifth input terminals in accordance with the input data selection signals SIA ₃ and SIB ₃ which are connected to the third output terminal and supplied from the instruction decoder 213D of the control device 13. An input data selection circuit 111D for selecting desired input data from S _C3 and outputting it as input data S _DAIN and S _DBIN from data output terminals D _DAOUT and D _DBOUT , and a data input terminal D _DAIN for input data selection circuit 111D Data output terminal D
To the second output terminal of the control signal generating circuit 313D of the connected to the _DAOUT and data input D _DBIN is connected to the data output terminal D _DBOUT the input data selecting circuit 111D and process start signal input terminal STRT _D control unit 13 connected to the fifth output terminal of the connected and the instruction decoder of the address signal input terminal AD _D is connected to a sixth output of the instruction decoder 213D of the control unit 13 and the index modification signal input IXS _D control unit 13 213D And the processing end signal output terminal END _D is connected to the third input terminal of the control signal generation circuit 313D of the control device 13 and the first input terminal of the processing pointer 513.
And the address signal output terminal AD _DOUT is connected to the data bus 15 and the bus control signal output terminal BCNT _DOUT
Input There data bus 15 connected to and data output terminals D _D starts processing given from which the control unit 13 is connected to the data bus 15 signals STRT _3, the address signal AD _3, in response to the index modification signal IXS ₃ The input data S _DAIN and D _{DBIN supplied} from the data selection circuit 111D or the unprocessed data S _{DBS supplied} from the data bus 15 are appropriately processed to _{generate a} first output terminal (that is, a data output terminal D _DOUT ) or a data input terminal. a processing circuit 211D for outputting from the output terminal D _D as output data S _D or already processed data S _DBS ^*, the first output of the first to third input processing circuit 211D (i.e. data output terminal D _DOUT ) And the fourth to sixth input terminals are connected to the first to third data output terminals of the holding circuit 411C.
(I.e., the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ) and the seventh input terminal is connected to the fourth output terminal of the instruction decoder 213D of the control device 13.
Output data selection signal given from the instruction decoder 213D of
Output data S _D and the fourth processing circuit 211D according to SO ₃
Or a register circuit RGS of the holding circuit 411C at the sixth input terminal.
_C1 input given from each of ~RGS _C3 data S _C1 ~
An output data selection circuit 311D for selecting desired data from S _C3 and outputting it from the first to third data output terminals as output data S _{D1 to} S _D3 , and writing to a second output terminal of the processing circuit 211D Signal input end (that is, register circuits RGS _{D1 to} RG
Write signal input terminal WT) is first to third data input to the first to third output terminals of each connected and the output data selection circuit 311D of S _D3 (i.e. register circuit RGS _D1
To RGS _D3 are connected to each other, and the output data S _D1 given from the output data selection circuit 311D is connected.
A holding circuit 411D for holding the register circuit RGS _D1 ~RGS _D3 in response to the write signal WT ₃ that received to S _D3 from the processing circuit 211D, are inclusions.

In the input data selection circuit 111D, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 411C (that is, the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ). connected and the control input is the control device 13 and the second register circuit of the holding circuit 411C according to the input data selection signal SIA ₃ given from the instruction decoder 213D of connected and the control device 13 to the output terminal of the instruction decoder 213D of RGS _C1 input given from ~RGS _C3 data S _C1 ~S _C3
And a selector circuit SEL _D1 for selecting one of them and outputting the selected data from the data output terminal D _DAOUT, and a first to third data output terminal of the holding circuit 411C as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ) and the control input terminal thereof is connected to the third output terminal of the instruction decoder 213D of the control device 13. register circuit RGS _C1 of the holding circuit 411C according to the given input data selection signal SIB ₃ ~
A selector circuit SEL _D2 for selecting one of the input data S _{C1 to} S _C3 given from the RGS _{C 3} and outputting it from the data output terminal D _DBOUT is included.

[0095] Output data selection circuit 311D is a decrypts the fourth output data selection signal SO ₃ provided from the connected and instruction decoder 213D to the output terminal of the instruction decoder 213D of the input end control unit 13 decodes the result selection signal SO _D1 and decoder DEC _D for outputting as to SO _D3, first the first data input terminal connected to the data output terminal D _DOUT processing circuit 211D and a second data input terminal holding circuit 411C the data output (i.e. register circuit RGS data output terminal Q of the _C1) selection signal SO _D1 that is connected to and controlled input to is given from the decoder DEC _D is connected to the first output of the decoder DEC _D is active (i.e. "1") processing circuit selects the output data S _D supplied from 211D outputs as output data S _D1 and selection signals SO _D1 supplied from the decoder DEC _D is inactive (i.e., when the "0 ”) When the holding circuit 411C The selector circuit SELT _D1 for outputting the register circuits RGS input data S _C1 applied from _C1 as selects and outputs data S _D1
The first data input terminal is connected to the data output terminal _DOUT of the processing circuit 211D, and the second data input terminal is connected to the holding circuit 41.
1C second data output terminal (ie, register circuit RGS _C2
Process when the selection signal SO _D2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _D is connected to the second output terminal of the decoder DEC _D of the active (i.e., "1") register circuits holding circuits 411C when the output is and the selection signal SO _D2 is inactive given from the decoder DEC _D selects the output data S _D provided from the circuit 211D as output data S _D2 (i.e. "0") A selector circuit SELT _D2 for selecting the input data S _C2 given from the RGS _C2 and outputting it as output data S _D2 , a first data input terminal connected to the data output terminal D _DOUT of the processing circuit 211D, and the third data output (i.e. the data output terminal Q of the register circuit RGS _C3) is connected to and the control input of the second data input terminal holding circuit 411C is connected to the third output terminal of the decoder DEC _D Given from the cage decoder DEC _D Selected signal
When SO _D3 is active (that is, “1”), the output data _SD provided from the processing circuit 211D is selected and output as the output data _SD3 , and the selection signal SO provided from the decoder DEC _{D is} selected.
_{When D3} is inactive (ie, "0"), a selector circuit for selecting the input data S _C3 given from the register circuit RGS _C3 of the holding circuit 411C and outputting it as output data S _D3
SELT _D3 .

Configuration of Switch Control Devices 12A to 12D (FIG. 7)
(See Fig. 10)

The switch control device 12A includes a plurality of sets (for convenience, “n”) each of which holds one set of switch connection information.
A connection information holding circuit 112A consisting holding circuit 112A ₁ ~112A _n of the set "), the is connected to an input end to the output end of the connection information holding circuit 112A and the output terminal is processing circuit 211A of the processing blocks 11A 1st to m-th changeover switches SWNG _{A1 to} SWNG
_Am and a control input connected to the first output of the command recorder 213A of the controller 13
The circuit selection signal SC ₀ given from the thirteen instruction decoders 213A.
And selecting one of a plurality of sets of switch connection information provided from the connection information holding circuit 112A in accordance with the processing block
A desired arithmetic circuit (for example, an addition instruction processing circuit) given to the changeover switches SWNG _{A1 to} SWNG _Am in the 11A processing circuit 211A
And a connection information selection circuit 212A for appropriately switching the switching switches SWNG _{A1 to} SWNG _Am so as to construct

The holding circuits 112A ₁ to 112A of the connection information holding circuit 112A
112A _n are first to m-th memory elements M _{A11 to} M _A1m for holding switch connection information, respectively;
_{An1 to} M _Anm are included. Memory elements M _{A11 to} M
_A1m : _Hold switch connection information for M _{An1 to} M _Anm may be executed in an appropriate manner before starting use.

The connection information selection circuit 212A includes first to n-th
_Are input terminals of the memory elements M _{A1 1 to} M _An1 ;
_{A1m to} M _Anm are connected to output terminals of the control circuit _{13A, and} the output terminal is connected to the first to m-th changeover switches SWNG _{A1 to} SWNG _{Am in} the processing circuit 211A of the processing block 11A. memory devices M _A11 in response to the circuit selection signal SC ₀ provided from the instruction decoder 213A of the instruction decoder 213A first output connected to and control the end 13 of ~M _{An 1;} · ·
·; M _A1m ~M selector circuit for providing the change-over switch SWNG _A1 ~SWNG _Am during processing apparatus 211A of select switch connection information processing block 11A given from _Anm 212A ₁ ~
The 212A _m, are inclusions.

The switch control device 12B has a plurality of sets (“n” for convenience) for holding one set of switch connection information.
A connection information holding circuit 112B consisting holding circuit 112B ₁ ~112B _n of the set "), the is connected to an input end to the output end of the connection information hold circuit 112B and the output terminal is processing circuit 211B of the processing block 11B 1st to m-th changeover switches SWNG _{B1 to} SWNG
_Bm and a control input connected to the first output of the instruction decoder 213B of the controller 13
Circuit selection signal SC ₁ given from thirteen instruction decoders 213B
And selecting one of a plurality of sets of switch connection information given from the connection information holding circuit 112B according to the processing block
A desired arithmetic circuit (for example, an addition instruction processing circuit) given to the changeover switches SWNG _{B1 to} SWNG _Bm in the processing circuit 211B of the 11B
And a connection information selection circuit 212B for appropriately switching the switching switches SWNG _{B1 to} SWNG _Bm so as to construct the connection information.

[0101] holding circuit 112B ₁ ~ of connection information holding circuit 112B
112B _n are each memory device M _B11 of the first to m for holding the switch connection information ~M _B1m; ···; M
_{Bn1 to MBnm} . Memory elements _{MB11 to} M
_B1m : _Hold switch connection information for M _{Bn1 to} M _Bnm may be executed in an appropriate manner before starting use.

The connection information selection circuit 212B includes first to n-th
Each input memory device M _{B1 1} of ~M _Bn1; ···; M
_{B1m to} M _Bnm are connected to the output terminals of the control circuit _{13B, and} the output terminal is connected to the first to m-th changeover switches SWNG _{B1 to} SWNG _{Bm in} the processing circuit 211B of the processing block 11B, and the control input terminal of the control device 13 memory devices M _B11 in response to the circuit selection signal SC ₁ given from the instruction decoder 213B of the first is connected to the output terminal control unit 13 of the instruction decoder 213B ~M _Bn1; · ·
A selector circuit 212B ₁ to select the switch connection information given from M _{B1m to} M _{Bnm and} to give the selected switch connection information to the changeover switches SWNG _{B1 to} SWNG _Bm in the processing circuit 211B of the processing block 11B;
212B _m .

The switch control device 12C includes a plurality of sets (“n” for convenience) for holding one set of switch connection information.
A connection information holding circuit 112C made of a holding circuit 112C ₁ ~112C _n of the set "), the and having an output terminal is connected to the input end to the output end of the connection information holding circuit 112C is processing circuit 211C of the processing block 11C 1st to m-th changeover switches SWNG _{C1 to} SWNG
_Cm and a control input connected to the first output of the instruction decoder 213C of the controller 13
The circuit selection signal SC ₂ given from the thirteen instruction decoders 213C.
And selecting one of a plurality of sets of switch connection information provided from the connection information holding circuit 112C according to the processing block
A desired arithmetic circuit (e.g., an addition instruction processing circuit) given to the changeover switches SWNG _{C1 to} SWNG _Cm in the 11C processing circuit 211C
And a connection information selection circuit 212C for appropriately switching the switching switches SWNG _{C1 to} SWNG _Cm so as to construct

Holding circuits 112C ₁ to 112C of connection information holding circuit 112C
112C _n are first to m-th memory elements M _{C11 to} M _C1m for holding switch connection information, respectively;
Are inclusions the _Cn1 ~M _Cnm. Memory elements M _{C11 to} M _C
C1m; ···; M _Cn1 holding the switch connection information for ~M _Cnm, prior to the start of use, may be performed in an appropriate manner.

The connection information selection circuit 212C includes first to n-th
Respective inputs of memory device _{M C1 1 ~M Cn1; ···;} M
_{C1m to} M _Cnm are connected to the output terminals of the control device 13 and the output terminal is connected to the first to m-th changeover switches SWNG _{C1 to} SWNG _{Cm in} the processing circuit 211C of the processing block 11C, and the control input terminal of the control device 13 memory devices M _C11 in response to the circuit selection signal SC ₂ given from the instruction decoder 213C of the first is connected to the output terminal control unit 13 of the instruction decoder 213C ~M _Cn1; · ·
·; M _C1m ~M _Cnm selector circuits 212C ₁ ~ to give the changeover switch SWNG _C1 ~SWNG _Cm during processing circuit 211C of select switch connection information processing block 11C given from
It has 212 _cm .

The switch control device 12D has a plurality of sets (for convenience, "n") for holding one set of switch connection information.
A connection information holding circuit 112D consisting holding circuit 112D ₁ ~112D _n of the set "), the connection information hold circuit input terminal to the output terminal of the 112D is connected and the output terminal is processing circuit 211D processing block 11D 1st to m-th changeover switches SWNG _{D1 to} SWNG
_Dm and a control input connected to the first output of the instruction decoder 213D of the controller 13
The circuit selection signal SC ₃ given from the thirteen instruction decoders 213D
And selecting one of a plurality of sets of switch connection information provided from the connection information holding circuit 112D in accordance with the processing block
A desired arithmetic circuit (for example, an addition instruction processing circuit, etc.) given to the changeover switches SWNG _{D1 to} SWNG _Dm in the 11D processing circuit 211D
And a connection information selection circuit 212D for appropriately switching the switching switches SWNG _{D1 to} SWNG _Dm so as to establish

Holding circuits 112D ₁ to 112D of connection information holding circuit 112D
112D _n are each memory device M _D11 of the first to m for holding the switch connection information ~M _D1m; ···; M
Are inclusions the _Dn1 ~M _Dnm. Memory elements _{MD11 to} M
_D1m : _Hold switch connection information for M _{Dn1 to} M _Dnm may be executed in an appropriate manner before starting use.

The connection information selection circuit 212D includes first to n-th
_Are input terminals of the memory elements M _{D1 1 to} M _Dn1 ;
_{D1m to} M _Dnm are connected to the output terminals, and the output terminal is connected to the first to m-th changeover switches SWNG _{D1 to} SWNG _{Dm in} the processing circuit 211D of the processing block 11D, and the control input terminal is connected to the control device 13. memory devices M _D11 in response to the circuit selection signal SC ₃ given from the instruction decoder 213D of the first is connected to the output terminal control unit 13 of the instruction decoder 213D ~M _Dn1; · ·
·; M _D1m ~M _Dnm selector circuits 212D ₁ ~ for providing switch connection information given to the changeover switch SWNG _D1 ~SWNG _Dm processing circuit in 211D selected by process block 11D from
212D _m .

[0109]Configuration of control device 13 (see FIGS. 11A to 22)
See)

The control device 13 has a data input terminal connected to a data output terminal DATA of the program holding device 14, and commands INST _{0 to} IN given from the program holding device 14.
Instruction registers 113A to 113D for holding ST ₃ respectively
And a data input terminal is connected to a data output terminal of each of the instruction registers 113A to 113D.
The instructions INST _{0 to} INST ₃ held in the memory are decoded, and various decoding signals (that is, address signals AD _{0 to} AD ₃ , index modification signals IXS _{0 to} IXS ₃ , circuit selection signals SC _{0 to} SC ₃ , input data selection) signal _{SIA 0 ~SIA 3; SIB 0 ~SIB} 3, the output data selection signal SO ₀ to SO ₃₎ an instruction decoder for generating 213A
213D and write signal input terminals of the instruction registers 113A to 113D are connected to first output terminals (that is, write signal output terminals), and the first input terminals are connected to the processing circuits 211A to 113D of the processing blocks 11A to 11D. Various control signals (e.g., the processing end signals END _{0 to} END _3, which are connected to the processing end signal output terminals END _{A to} END _D of 211D and given from the processing circuits 211A to 211D of the processing blocks 11A to 11D, respectively). That is, the write signals WT _{0 to} W
T ₃ , processing start signals STRT _{0 to} STRT ₃ , increment signal INC
P _{0 to} INCP ₃ and shift signal SFTC _{0 to} SFTC ₃ ), and control signal generation circuits 313A to 313D for generating and outputting from the first to fourth output terminals, respectively.
The first to fourth input terminals are connected to the fourth output terminal of 313D, respectively, and the first to fourth output terminals are connected to the second input terminals of the control signal generation circuits 313A to 313D, respectively. construction command signal instructs the construction of a desired arithmetic circuit in the processing circuit 211A~211D block 11A ~11D CPQ ₀ ~
A construction pointer 413 for generating the CPQ ₃ and giving it to the control signal generation circuits 313A to 313D and first to fourth processing end signals END _{A to} END _D of the processing end signals END _{A to} END _D of the processing circuits 211A to 211D of the processing blocks 11A to 11D. Are connected to the respective input terminals and the first to fourth output terminals are connected to the third input terminals of the control signal generation circuits 313A to 313D, respectively.
Processing circuit 211A of the processing blocks 11A ～11D when D is processing circuit 211A~211D from processing end signal END ₀ ~END ₃ of a given
Processing command signals PPQ _{0 to} PPQ ₃ for processing in ~ 211D
And a processing pointer 513 for generating the control signal generation circuits 313A to 313D, and connecting the first to fourth input terminals to the third output terminals of the control signal generation circuits 313A to 313D, respectively. Address input terminal of program holding circuit 14
And a program counter 613 for providing announce read end of the instruction is connected to the AD INST ₀ ~INST ₃ and the program holding unit 14 to generate an address signal PC to request a read of the next instruction, inclusion are doing.

The instruction registers 113A to 113D store a plurality of bits (for example, 32 bits) given from the program holding device 14.
INST _{0 to} INST ₃ may be provided, and a well-known register may be employed as desired.

[0112] Instruction decoder 213A is output to the processing circuit 211A of the processing block 11A from the sixth output terminal as it is as the address signal AD ₀ the first bit to the 16th bit of the instruction INST ₀ given from the instruction register 113A And the instruction IN
The 17th bit to the 20th bit is treated with the OR circuit OR _3A outputs toward the fifth output After generating an index modified signal IXS ₀ to a processing circuit 211A of the processing block 11A of ST _0, instruction INST ₀ the 17th bit to the 20th bit as the input data selection signal SIB ₀ towards the input data selection circuit 111A of the processing block 11A from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₀ output data selection circuit as input data selection signal SIA ₀ as a second output towards the input data selection circuit 111A of the processing block 11A from the output end and the processing from the fourth output terminal as an output data selection signal SO ₀ blocks 11A and output to the 311A, the first output to generate a circuit selection signal SC ₀ from the data output terminal dATA giving the address inputs AD of the 25th bit to 32nd bit conversion table circuit TBL _3A instruction INST ₀ Towards the connection information selection circuit 212A of the switching control device 12A has a configuration in which outputs from the.

The instruction decoder 213B outputs the _first to sixteenth bits of the instruction INST ₁ given from the instruction register 113B as it is as an address signal AD1 from the sixth output terminal to the processing circuit 211B of the processing block 11B. And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₁ in OR circuit OR _3B outputs toward the fifth output After generating an index modified signal IXS ₁ to the processing circuit 211B of the processing block 11B, the instruction INST ₁ the 17th bit to the 20th bit as the input data selection signal SIB ₁ toward the input data selection circuit 111B of the processing block 11B from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₁ output data selection circuit as input data selection signal SIA ₁ as a second output towards the input data selection circuit 111B of the processing block 11B from the output end and the output data selection signal SO ₁ as a fourth output from the processing blocks 11A and output to the 311B, a first output to generate a circuit selection signal SC ₁ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₁ to the address input AD of the conversion table circuit TBL _3B Towards the connection information selection circuit 212B of the switch control device 12B has a configuration in which outputs from the.

[0114] Instruction decoder 213C is output to the sixth output terminal of the first bit to the 16th bit of the instruction INST ₂ given from the instruction register 113C as it address signal AD ₂ to the processing circuit 211C of the processing block 11C And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₂ in OR circuit OR _3C outputs toward the fifth output After generating an index modified signal IXS ₂ to the processing circuit 211C of the processing block 11C, the instruction INST ₂ the 17th bit to the 20th bit as the input data selection signal SIB ₂ towards the input data selection circuit 111C of the processing block 11C from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₂ output data selection circuit as the input data selection signal SIA ₂ as a second output towards the input data selection circuit 111C of the processing block 11C from the output end and the processing from the fourth output terminal as an output data selection signal SO ₂ blocks 11C and output to the 311C, a first output to generate a circuit selection signal SC ₂ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₂ to an address input terminal AD of the conversion table circuit TBL _3C Towards the connection information selection circuit 212C of the switching control device 12C has a structure to be output from.

[0115] Instruction decoder 213D is outputted to the sixth output terminal of the first bit to the 16th bit of the instruction INST ₃ given from the instruction register 113D as it is as the address signal AD ₃ to the processing circuit 211D processing block 11D And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₃ in OR circuit OR _3D output toward the fifth output After generating an index modified signal IXS ₃ to the processing circuit 211D of the processing block 11D, the instruction INST ₃ the 17th bit to the 20th bit as the input data selection signal SIB ₃ toward the input data selection circuit 111D processing block 11D from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₃ output data selection circuit as the input data selection signal SIA ₃ as a second input data selecting circuit towards 111D and output of the processing block 11D from an output end and a fourth processing from the output terminal block 11D as an output data selection signal SO ₃ and output to the 311D, a first output to generate a circuit selection signal SC ₃ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₃ in the conversion table circuit TBL _3D the address inputs AD Towards the connection information selection circuit 212D of the switch control unit 12D has a structure to be output from.

The control signal generating circuit 313A has an AND circuit AND _3A1 having one input terminal connected to the first output terminal of the construction pointer 413, a data input terminal A connected to the output terminal of the AND circuit AND _3A1 , and a shift register SR _3A to the clock input terminal CK is a clock signal source connected to a (not shown) and the clear input connected to a reset signal source (not shown),
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3A of the shift register SR _3A Write signal WT ₀ and increment signal
AND circuit the AND _3A2 for providing INCP ₀ the output from the output end instruction register 113A and the program counter 613, respectively, the second output terminal Q ₂ and the third inverting output terminal of the shift register SR _3A Q ₃ ^* in the aND circuit for providing the second output and the third inverting output is outputted from the output terminal of the shift signal SFTC ₀ which becomes high level when both the high-level construction pointer 413 of the shift register SR _3A is connected _3A3 and one input terminal is a third output terminal of the processing circuit 211A of the processing block 11A (that is, the processing end signal output terminal EN
D _A ) and the other input terminal is connected to the reset signal source, and the processing end signal END ₀ or the reset signal RESET given from the processing circuit 211A of the processing block 11A is at a high level (that is, “1”). when the OR circuit OR _3A1 for delivering high-level output signal from the output terminal, without a clock input terminal CK is connected to the output terminal of the aND circuit the aND _3A3 and the data input D is high level signal source (not ) And the clear input terminal CLR is connected to the output terminal of the OR circuit OR _3A1 , and the constructed flag signal generating circuit CENDF _3A for outputting the constructed flag signal CENDF ₀ from the output terminal Q;
The clock input terminal CK is connected to the third output terminal of the processing circuit 211A of the processing block 11A (ie, the processing end signal output terminal END _A ), and the data input terminal is connected to a high-level signal source (not shown); Clear input terminal CLR is AND circuit AND
_3A3 is connected to the output terminal, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the AND circuit AND _3A1.
And a processed flag signal generating circuit PENDF _3A for generating a processed flag signal PENDF ₀ from an output terminal Q and an output terminal Q of a constructed flag signal generating circuit CENDF _3A . An input terminal is connected and the other input terminal is connected to the first output terminal of the processing pointer 513, and the processing start signal STRT which becomes high when the constructed flag signal CENDF ₀ and the processing command signal PPQ ₀ are high. _An AND circuit AND _3A4 for outputting ₀ from the output terminal to give to the processing circuit 211A of the processing block 11A is included.

[0117] Control signal generator circuit 313B includes an AND circuit the AND _3B1 connected to the second output terminal of the one input terminal configuration pointer 413, the data input terminal A to the output terminal of the AND circuit the AND _3B1 is connected and A shift register SR _3B having a clock input CK connected to a clock signal source (not shown) and a clear input connected to a reset signal source (not shown);
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3B of the shift register SR _3B Write signal WT ₁ and increment signal
AND circuit the AND _3B2 for providing instructions to output the INCP ₁ from the output end register 113B and the program counter 613, respectively, the second output terminal Q ₂ and the third inverting output terminal of the shift register SR _3B Q ₃ ^* in the aND circuit for providing the second output and the third inverting output is outputted from the output terminal of the shift signal SFTC ₁ together a high-level high when the structure pointer 413 of the shift register SR _3B is connected _3B3 and one input terminal is a third output terminal of the processing circuit 211B of the processing block 11B (that is, the processing end signal output terminal EN
D _B ) and the other input terminal is connected to the reset signal source, and the processing end signal END ₁ or the reset signal RESET given from the processing circuit 211B of the processing block 11B is at a high level (that is, “1”). An OR circuit OR _3B1 for transmitting a high-level output signal from the output terminal, a clock input terminal CK is connected to an output terminal of the AND circuit AND _3B3 , and a data input terminal D is connected to a high-level signal source (not shown). connected and clear input terminal and a built flag signal generating circuit CENDF _3B for outputting the constructed flag signal CENDF ₁ from the output terminal Q is connected to an output terminal of the OR circuit OR _3B1 in), the clock input CK Is the third of the processing circuit 211B of the processing block 11B.
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3B3 output (i.e. processing end signal output terminal END _B) is connected to and the data input terminal to a high level signal source (not shown) of Further, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the other input terminal of the AND circuit AND _{3 B1.}
Processed flag signal generation circuit PEND for generating PENDF ₁
F _3B and the output terminal Q of the constructed flag signal generation circuit CENDF _3B
Processing one input terminal is connected and the other second construction flag signal is connected to the output terminal CENDF ₁ and processing the command signal input end processing pointer 513 PPQ ₁ becomes the high level high level when the an aND circuit the aND _3B4 for providing to the processing circuit 211B outputs to the processing block 11B from the output end of the start signal STRT _1, are inclusions.

The control signal generation circuit 313C has an AND circuit AND _3C1 having one input terminal connected to the third output terminal of the configuration pointer 413, a data input terminal A connected to the output terminal of the AND circuit AND _3C1 , and a shift register SR _3C clock input CK is a clock signal source connected to a (not shown) and the clear input connected to a reset signal source (not shown),
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3C of the shift register SR _3C Write signal WT ₂ and increment signal
AND circuit the AND _3C2 for providing respectively the INCP ₂ into the instruction register 113C and the program counter 613 and outputs from an output terminal, a second output Q ₂ and the third inverting output terminal of the shift register SR _3C Q ₃ ^* in the aND circuit for providing the second output and the third inverting output outputs a shift signal SFTC ₂ together a high-level high-level when the output structure pointer 413 of the shift register SR _3C is connected _3C3 and one input terminal is a third output terminal of the processing circuit 211C of the processing block 11C (that is, the processing end signal output terminal EN
D _C ) and the other input terminal is connected to the reset signal source, and the processing end signal END ₂ or the reset signal RESET given from the processing circuit 211C of the processing block 11C is at a high level (that is, “1”). An OR circuit OR _3C1 for transmitting a high-level output signal from the output terminal, a clock input terminal CK is connected to an output terminal of the AND circuit AND _3C3 , and a data input terminal D is a high-level signal source (not shown). ) And the clear input terminal is connected to the output terminal of the OR circuit OR _3C1 , and the constructed flag signal generating circuit CENDF _3C for outputting the constructed flag signal CENDF ₂ from the output terminal Q, and the clock input terminal CK Is the third of the processing circuit 211C of the processing block 11C.
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3C3 output (i.e. processing end signal output terminal END _C) is connected to and the data input terminal to a high level signal source (not shown) of Further, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the other input terminal of the AND circuit AND _{3 C1.}
Processed flag signal generation circuit PEND for generating PENDF ₂
And F _3C, constructed flag signal generating circuit CENDF _3C one input terminal is connected and the other third of the connected and constructed flag signal to an output terminal of the input end processing pointer 513 to the output terminal of CENDF ₂ and processing instruction signal PPQ ₂ is an aND circuit the aND _3C4 for providing the processing circuit 211C outputs the processing block 11C from the output end of the process start signal STRT ₂ serving as a high-level high-level when, and inclusions.

The control signal generation circuit 313D has an AND circuit AND _3D1 having one input terminal connected to the fourth output terminal of the configuration pointer 413, a data input terminal A connected to an output terminal of the AND circuit AND _3D1 , and a shift register SR _3D clock input CK is a clock signal source connected to a (not shown) and the clear input connected to a reset signal source (not shown),
First output Q ₁ and the second inverting output terminal Q ₂ ^* in the connected and the first shift register SR _3D output and the second inverting output are both high-level high-level when the shift register SR _3D Write signal WT ₃ and increment signal
AND circuit AND that outputs INCP ₃ from the output terminal and applies it to the instruction register 113D and the program counter 613, respectively
_3D2 and the second output terminal Q ₂ and the third inverted output terminal Q ₃ ^* of the shift register SR _3D and the shift register
An AND circuit AN for outputting a shift signal SFTC ₃ which becomes a high level when both the second output and the third inverted output of the SR _3D are at a high level from an output terminal and gives it to the configuration pointer 413
_D3D3 , one input terminal of which is the processing circuit 21 of the processing block 11D.
Third output terminal of 1D (ie, processing end signal output terminal END _D )
And the other input terminal is connected to the reset signal source. When the processing end signal END ₃ or the reset signal RESET given from the processing circuit 211D of the processing block 11D is at a high level (that is, “1”), the output terminal is Circuit OR _3D1 for transmitting a high-level output signal from the OR, a clock input terminal CK is connected to an output terminal of an AND circuit AND _3D3 , and a data input terminal D is connected to a high-level signal source (not shown). And the clear input terminal CLR is connected to the output terminal of the OR circuit OR _3D1 , and the constructed flag signal generating circuit CENDF _3D for outputting the constructed flag signal CENDF ₃ from the output terminal Q and the clock input terminal CK are processed. Third processing circuit 211D of block 11D
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3D3 output (i.e. processing end signal output terminal END _D) is connected to and the data input terminal to a high level signal source (not shown) of The preset input terminal PR is connected to the reset signal source, the output terminal Q is connected to the other input terminal of the AND circuit AND _3D1 , and the processed flag signal is output from the output terminal Q.
Processed flag signal generation circuit PEND for generating PENDF ₃
F _3D and the output terminal Q of the constructed flag signal generation circuit CENDF _3D
Is connected to the fourth input terminal of the processing pointer 513, and has a high level when the constructed flag signal CENDF ₃ and the processing command signal PPQ ₃ are at a high level. an aND circuit the aND _3D4 for providing to the processing circuit 211D outputs the processing block 11D from the output end of the start signal STRT _3, are inclusions.

[0120] Construction pointer 413, a fourth output end (i.e. the AND circuit the AND _3A3 output end of ~AND _3D3) connected to it has control of the first to fourth input terminals respectively control signal generating circuit 313A~313D an oR circuit oR ₄ for outputting a high level signal when any one of the signal generating circuit shift signal given from 313A~313D SFTC ₀ ~SFTC ₃ became high, the clock input terminal CK is oR circuit The output terminal of OR ₄ and the preset input terminal PR are connected to a reset signal source (not shown).
A flip-flop FF ₄₀ for outputting the constructed command signal CPQ ₀ to command to build a desired operation circuit to the processing circuit 211A of the A, and clears the clock input terminal CK is connected to the output terminal of the OR circuit OR ₄ input CLR is connected to the reset signal source and the output terminal of the input terminal D flip-flop FF ₄₀ Q
Flip-flop FF ₄₁ for outputting the constructed command signal CPQ ₁ to command to build a desired operation circuit to the processing circuit 211B of the processing block 11B from a connected and an output terminal Q to
When the clock input terminal CK is OR circuit connected to the output terminal of the OR ₄ and the clear input terminal CLR is connected to the reset signal source and the connected and an output terminal Q to the output terminal Q of the input terminal D flip-flop FF ₄₁ To processing circuit 211C of processing block 11C
Desired flip-flop FF ₄₂ for outputting the constructed command signal CPQ ₂ for commanding to construct an arithmetic circuit, a clock input terminal CK is connected to the output terminal of the OR circuit OR ₄ and the clear input terminal CLR is reset processing circuit of the signal source connected to and input terminal D flip-flop FF ₄₂ output end is connected to the Q and the output terminal Q flip-flop processed from a connected and an output terminal Q to the input terminal D of the FF ₄₀ block 11D 211D Command CP for instructing the user to construct a desired arithmetic circuit
A flip-flop FF ₄₃ for outputting a Q _3, are inclusions.

The processing pointer 513 has a processing circuit 211A of the processing blocks 11A to 11D having first to fourth input terminals, respectively.
To the third output terminal (ie, the processing end signal output terminal EN
_{D A} ~END D) any one of the processing end signal END ₀ ~END ₃ given from the connected and processing circuitry 211A~211D to but OR circuit for outputting a high level signal when a high level The OR ₅ and the clock input terminal CK are connected to the output terminal of the OR circuit OR ₅ and the preset input terminal PR is connected to a reset signal source (not shown), and the output terminal Q is connected to the processing circuit 211A of the processing block 11A. A flip-flop FF ₅₀ for outputting a processing command signal PPQ ₀ for instructing execution of a desired arithmetic processing in the constructed arithmetic circuit, and a clock input terminal CK
Is connected to the output terminal of the OR circuit OR ₅ and the clear input terminal CL
R performs a desired operation processing by the arithmetic circuit connected and the input terminal D to the reset signal source is constructed from a connected and an output terminal Q to the output terminal Q of the flip-flop FF ₅₀ to the processing circuit 211B of the processing block 11B Processing command signal to command
A flip-flop FF ₅₁ for outputting the PPQ _1, a clock input terminal CK is connected to the output terminal of the OR circuit OR ₅ and clear input terminal CLR is connected to the reset signal source and the input terminal D
And outputs the processed command signals PPQ ₂ to command but to perform desired processing by the arithmetic circuit constructed from a connected and an output terminal Q to the output terminal Q to the processing circuit 211C of the processing block 11C of the flip-flop FF ₅₁ Flip-flops for FF ₅₂
If, connected and an output terminal Q to the output terminal Q of the clock input CK is connected to the output terminal of the OR circuit OR ₅ and clear input terminal CLR is connected to the reset signal source and the input terminal D flip-flop FF ₅₂ is processing circuit of the processing block 11D from a connected and an output terminal Q to the input terminal D of the flip-flop FF ₅₀
A flip-flop FF ₅₃ for outputting a processing instruction signal PPQ ₃ for commanding to perform a desired operation processing by the arithmetic circuit constructed 211D, are inclusions.

The program counter 613 has its first to fourth input terminals connected to the third output terminals of the control signal generation circuits 313A to 313D (ie, the output terminals of the AND circuits AND _{3A2 to} AND _3D2 ). An OR circuit OR ₆ for outputting a high-level signal when any one of the increment signals INCP _{0 to} INCP ₃ given from the signal generation circuits 313A to 313D becomes high level, and an OR circuit for clock input terminal CK.
The output terminal of OR ₆ and the clear input terminal CLR are connected to a reset signal source (not shown), and the first to sixteenth output terminals Q _{0 to} Q ₁₅ are connected to the address input terminal AD of the program holding circuit 14. Are connected and the output signals PC _{0 to} PC ₁₅ are used as the address signal PC as the address input terminal AD of the program holding circuit 14.
And a counter CNT ₆ for supplying the counter CNT.

Specific Examples of Processing Circuits 211A to 211D: Load Instruction
Processing circuit (see Fig. 23)

Instruction given from program holding circuit 14
The circuit selection signal SC _i obtained by decoding the 25th to 32nd bits (that is, the instruction code) of INST _i by the conversion table circuit TBL _3X of the instruction decoder 213X is “0” as shown in Table 4. Therefore, the switch control device 12X selects appropriate switch connection information, supplies the selected switch connection information to the processing circuit 211X of the processing block 11X, and appropriately switches the changeover switches SWNG _{X1 to} SWNG _{Xm so} that the processing circuit 211X of the processing block 11X
To construct a load instruction processing circuit (shown as "211X") (X = A to D; i = 0 to 3; the same applies hereinafter).

In the load instruction processing circuit 211X, the load input terminal LD is connected to the processing start signal input terminal STRT _{X, the} data input terminal D is connected to a constant generation source (not shown), and the output terminal Q is written. Signal output terminal WT _X and processing end signal output terminal
END _X , and is applied to the data input terminal D in response to the processing start signal STRT _i from the control signal generation circuit 313X of the control device 13 to the processing start signal input terminal STRT _X (hence, the load input terminal LD). each write signal WT _i and the output terminal Q when the subtraction operation captures and are constant started counting contents becomes "0" through the write signal output terminal WT _X and processing end signal output terminal eND _X A down counter DCNT _X for outputting the processing end signal END _i is included.

[0126] Load instruction processing circuit 211X also has and data input terminal A to the data input terminal D _XBIN is connected to the address signal input terminal AD _X is connected to the data input terminal B data input terminal D _XBIN ( That is, the input data S _{XBIN supplied} to the data input terminal A) and the address signal input terminal
An adder ADD _X for adding the address signal AD _i supplied to AD _X (that is, the data input terminal B) to each other and outputting the result from the output terminal F, and a first input terminal for the address signal input terminal
AD _X and a second input connected to the output F of the adder ADD _{X and} an output connected to the address signal output AD _XOUT and a switching signal input connected to the index modification signal input. The index modification signal IX connected to the terminal IXS _X and given from the instruction decoder 213X of the control device 13.
When _Si is active (i.e., "1"), the output of the adder ADD _X is output from the address signal output terminal AD _XOUT to the data bus 15 as the address signal AD _XBS and supplied from the instruction decoder 213X of the control device 13. When the index modification signal IXS _i is inactive (that is, “0”), the address signal AD _i given from the instruction decoder 213X of the control device 13 is used as it is as the address signal AD _{XBS from the} address signal output terminal AD _XOUT to the data bus 15. Selector circuit SELT for output to
_{And X.}

[0127] Load instruction processing circuit 211X is further for outputting a read signal READ _XBS to the bus control signal output terminal BCNT _XOUT is connected to the output terminal to the bus control signal output data bus 15 from the BCNT _XOUT Bus control signal generation circuit
BCNTL _X and data input / output terminal D connected to data bus 15
Raw data the data output terminal D _XOUT to _X is given from the data bus 15 is connected to the data input terminal D _X
DAT _XBS (i.e. S _{XI N)} and a data transfer circuit DTRF _X for outputting toward the data output D _XOUT to the output data selection circuit 311X as it is as the output data S _X, are inclusions.

Specific examples of processing circuits 211A to 211D: addition instruction processing
Logic circuit (see Fig. 24)

Instruction given from program holding circuit 14
The circuit selection signal SC _i obtained by decoding the 25th to 32nd bits (that is, the instruction code) of INST _i by the conversion table circuit TBL _3Y of the instruction decoder 213Y is “3” as shown in Table 4. Therefore, the switch control device 12Y selects appropriate switch connection information, supplies the selected switch connection information to the processing circuit 211Y of the processing block 11Y, and appropriately switches the changeover switches SWNG _{Y1 to} SWNG _{Ym so} that the processing circuit 211Y of the processing block 11Y
(Y = A to D; i = 0 to 3; the same applies hereinafter).

In addition instruction processing circuit 211Y, load input terminal LD is connected to processing start signal input terminal STRT _Y, data input terminal D is connected to a constant generation source (not shown), and output terminal Q is written. Signal output terminal WT _Y and processing end signal output terminal EN
D _Y and the processing start signal STRT _Y (and thus the load input LD) from the controller 13 to the processing start signal ST
Write signal output terminal WT _Y and processing end signal from the output terminal Q when the RT _i is counted contents starts a subtraction operation captures constants applied to data input terminal D when given becomes "0" Down counter DC for outputting a write signal WT _i and a processing end signal END _i via an output end END _Y , respectively
Has NT _Y.

The addition instruction processing circuit _211Y has an input data selection circuit _whose data input terminals D _YAIN and D _YBIN are connected to data input terminals A and B, respectively, and whose output terminal F is connected to a data output terminal D _YOUT. 111Y to data input terminal D _YAIN ,
The input data S _YAIN and S _YBIN given to D _YBIN (that is, the data input terminals A and B) are added to each other, and the addition result is output from the output terminal F as output data S _Y via the data output terminal D _YOUT and the output data selection circuit 311Y. the adder ADD _Y for output to, and inclusions.

Specific examples of the processing circuits 211A to 211D: Load effective
Address instruction processing circuit (see FIG. 25)

Instruction given from program holding circuit 14
The circuit selection signal SC _i obtained by decoding the 25th to 32nd bits of INST _i (that is, the instruction code) by the conversion table circuit TBL _3Z of the instruction decoder 213Z is “2” as shown in Table 4. Therefore, the switch control device 12Z selects appropriate switch connection information, supplies the selected switch connection information to the processing circuit 211Z of the processing block 11Z, and appropriately switches the changeover switches SWNG _{Z1 to} SWNG _Zm, thereby obtaining the processing circuit 211Z of the processing block 11Z.
To construct a load effective address instruction processing circuit (shown as "211Z") (Z = A to D; i = 0 to 3; the same applies hereinafter).

The load effective address instruction processing circuit 211Z
The load input terminal LD is connected to the processing start signal input terminal STRT _{Z, the} data input terminal D is connected to a constant generation source (not shown), and the output terminal Q is the write signal output terminal WT _Z and the processing end signal output. Terminal END _Z , processing start signal input terminal
When a processing start signal STRT _i is supplied from the control device 13 to STRT _Z (and, consequently, the load input terminal LD), the constant given to the data input terminal D is fetched, the subtraction operation is started, and the count value becomes “0”. From the output terminal Q to the write signal output terminal
It has a down counter DCNT _Z for outputting a write signal WT _i and a processing end signal END _i via WT _Z and a processing end signal output end END _Z , respectively.

The load effective address instruction processing circuit 211Z
The data input terminal A is connected to the data input terminal D _{ZBIN and the} data input terminal B is connected to the address signal input terminal AD _Z.
Are connected to the input data S _{ZBIN supplied} to the data input terminal D _ZBIN (that is, the data input terminal A) and the address signal AD _{i supplied} to the address signal input terminal AD _Z (that is, the data input terminal B). And an adder ADD _Z for adding the first and second outputs to an address signal input terminal AD _Z and a second input terminal to the output terminal of the adder ADD _Z. It is connected to F and the output terminal is a data output terminal D _ZO connected to _UT and the switching signal input terminal connected to and controlled device in the index modification signal input IXS _Z
Output data S output of the adder ADD _Z when the index modification signals IXS _i given from 13 active (i.e. "1")
Output data selection circuit 31 from data output terminal D _ZOUT as _Z
And output to the 1Z and controller index modification signal given from 13 IXS _i is inactive (i.e. "0") the data output as output data S _Z address signal AD _i supplied from the control unit 13 when the _And a selector circuit SELT _Z for outputting from D _ZOUT to the output data selection circuit 311Z.

Specific examples of processing circuits 211A to 211D: arithmetic left shift
Instruction processing circuit (see FIG. 26)

Instruction given from program holding circuit 14
INST 25th bit to 32nd bit (i.e. instruction code) conversion table circuit TBL _3W the circuit selection signal SC _i obtained by decoding of the instruction decoder 213W of _i is, is was as "4" shown in Table 4 Therefore, the switch control device 12W selects appropriate switch connection information, supplies the selected switch connection information to the processing circuit 211W of the processing block 11W, and appropriately switches the changeover switches SWNG _{W1 to} SWNG _Wm, thereby obtaining the processing circuit 211W of the processing block 11W.
To construct an arithmetic left shift instruction processing circuit (shown as "211W") (W = A to D; i = 0 to 3; the same applies hereinafter).

[0138] Arithmetic left shift instruction processing circuit 211W, the process start signal input STRT _W load input terminal LD is connected to and the data input terminal D _WAIN to the data input terminal D connected and shifted to the data input terminal D _WBIN The signal input terminal SFT is connected and the processing end signal output terminal END _W and the write signal output terminal WT _W
The processing end signal output terminal END is connected and the data output terminal D _WOUT to the output terminal F and the data input terminal D _WAIN is connected from which the control unit 13 by processing start signal STRT _i data input when given D _WAIN Input data S _WAIN given to
After the first bit to the fifteenth bit are taken in and held _therein , the input data S _applied to the data input terminal D _{WBIN
The data} is shifted to the left in accordance with _WBIN , output from the output terminal F, and output from the input data S _WAIN given to the data input terminal D _WAIN .
Add a 16-bit output to collectively process terminates via the output data S _W processing end signal output terminal END _W and the write signal output terminal WT _W from the processing end signal output terminal END after the output of the output data S _W the shift register SR _W for outputting a signal END _i and the write signal WT _i respectively, and inclusions.

Specific examples of processing circuits 211A to 211D: store instruction
Processing circuit (see Fig. 27)

Instruction given from program holding circuit 14
The circuit selection signal SC _i obtained by decoding the 25th to 32nd bits of INST _i (that is, the instruction code) by the conversion table circuit TBL _3V of the instruction decoder 213V is “1” as shown in Table 1. Therefore, the switch control device 12V selects appropriate switch connection information, supplies the selected switch connection information to the processing circuit 211V of the processing block 11V, and appropriately switches the changeover switches SWNG _{V1 to} SWNG _Vm, thereby obtaining the processing circuit 211V of the processing block 11V.
To construct a store instruction processing circuit (shown as "211 V") (V = A to D; i = 0 to 3; the same applies hereinafter).

In the store instruction processing circuit 211V, the load input terminal LD is connected to the processing start signal input terminal STRT _{V, the} data input terminal D is connected to a constant generation source (not shown), and the output terminal Q is processed. A constant connected to the signal output terminal END _V and given to the data input terminal D when the control device 13 supplies the processing start signal STRT _i to the processing start signal input terminal STRT _V (and thus the load input terminal LD). And a down counter DCNT _V for outputting a processing end signal END _i from the output terminal Q via the processing end signal output terminal END _V when the count content becomes “0”. are doing.

[0142] store instruction processing circuit 211V also has and data input terminal A to the data input terminal D _VBIN is connected to the address signal input terminal AD _V is connected to the data input terminal B data input terminal D _VBIN ( That is, the input data S _{VBIN supplied} to the data input terminal A) and the address signal input terminal
AD _V (i.e. data input B) and the address signal AD _i to be given an adder ADD _V for outputting an addition to the output terminal F to each other, the first input address signal input terminal
AD _V and a second input connected to the output F of the adder ADD _V, an output connected to the address signal output AD _VOUT , and a switching signal input connected to the index modification signal input. The output of the adder ADD _V is connected to the address signal AD _VBS when the index modification signal IXS _i connected to the terminal IXS _V and given from the controller 13 is active (ie, “1”).
Towards the address signal output terminal AD _VOUT to the data bus 15 and outputs a and controller index modification signal IXS _i given from 13 non-active (i.e. "0") address signal AD supplied from the control unit 13 when the A selector circuit SELT _V for outputting _i as an address signal AD _{VBS from the} address signal output terminal AD _VOUT to the data bus 15 is included.

[0143] store instruction processing circuit 211V is further to the bus control signal output terminal BCNT _VOUT data bus 15 from the output end is connected bus control signals output BCNT _VOUT with respect to output a write signal WT _VBS Control signal generation circuit BC for
NTL _V and data input / output terminal D _V connected to data bus 15
When the data input terminal D _VAIN is connected to the data input terminal D _VAIN , the input data S _VAIN is used as it is as processed data DAT _VBS ^* (that is, S _XOUT ) from the data output terminal _DVOUT to the data bus 15. a data transfer circuit DTRF _V for outputting toward, and inclusions.

(Operation of the First Embodiment)

Further, the operation of the first embodiment of the computer according to the present invention will be described in detail with reference to FIGS. Here, instructions INST _{0 to} INST
₃ is the data holding device 16 in the first bit to the 16th bit.
Of unprocessed data or processed data in
(Ie, address) information is held as operand 3 and the processing blocks 11A to 11A to 17th to 20th bits are stored.
Register circuit RGS of holding devices 411A to 411D included in 11D
_{A1 to} RGS _A3 ; ・ ・ ・; RGS _{D1 to} RGS _D3 operand 2
And the 21st to 24th bits of the register circuits RGS _{A1 to} RGS _{A3 of} the holding devices 411A to 411D included in the processing blocks 11A to 11D; the numbers of RGS _{D1 to} RGS _D3 as operand 1 It is assumed that the instruction codes in Table 4 are held in the 25th to 32nd bits (see FIG. 28).

Although only the case where the program shown in Table 1 is executed will be described here, the present invention is not intended to be limited to this. The program shown in Table 1 is
It is assumed that the data is stored in advance on a magnetic disk (not shown). Incidentally, “LD” indicates “load instruction”,
It is represented by an instruction code of “10”. “ADD”
Indicates an “addition instruction”, which is represented by an instruction code of “20”. “LEA” indicates a “load effective address instruction” and is expressed by an instruction code of “12”. “SLA” indicates “arithmetic left shift instruction”, and is expressed by an instruction code of “50”. “S
“T” indicates a “store instruction” and is represented by an instruction code of “11”.

[0147]

[Table 1] LD RGS1, 100 LD RGS2, 101 ADD RGS1, RGS2 LEA RGS2, 001 SLA RGS1, RGS2 ST RGS1, 102

Initial operation

In the computer 10 according to the present invention, each “address” of the program holding device 14 is
The program shown in Table 2 held on a magnetic disk (not shown) is automatically given and held, and the respective addresses of the data holding device 16 are held on a magnetic disk (not shown). The unprocessed data is automatically given and held.

[0150]

[Table 2]

In the computer 10 according to the present invention, a reset signal RESET is generated from a reset signal source (not shown) when the power is turned on (or the reset button of the input / output device 17 is pressed).

Along with this, the control device 13 clears the count content of the counter CNT ₆ of the program counter 613 and sends the program counter 613 to the program holding device 14.
Indicates an address "0".

[0153] In the construction pointer 413, the flip-flop FF ₄₀ is "1", the output signal (i.e. build command signal) Construction command signal CPQ ₀ of CPQ ₀ ~CPQ ₃ is active
(That is, “1”) and the construction command signals CPQ _{1 to} CPQ
Q ₃ is deactivated (ie, “0”) (see Table 3).
Incidentally, the construction pointer 413, a required arithmetic circuit to the processing circuit 211A of the processing block 11A by constructing the command signal CPQ ₀
(In this case, a load instruction processing circuit).

[0154] Similarly, the processing pointer 513, the flip-flop FF ₅₀ is "1", the output signal (i.e. processing instruction signal) processing instruction signal PPQ ₀ of PPQ ₀ ~PPQ ₃ is active (i.e. "1" ) And the processing command signals PPQ ₁ to
PPQ ₃ is deactivated (ie, "0") (see Table 3)
. That is, the processing pointer 513 indicates the processing command signal PPQ ₀
Indicates that the processing circuit 211A of the processing block 11A should perform required arithmetic processing (execution of a load instruction in this case).

In the control device 13, a control signal generation circuit
Constructed flag signal generation circuit CENDF _{3A to} CE in 313A to 313D
The contents of the NDF _3D are cleared to “0”, and the contents of the processed flag signal generation circuits PENDF _{3A to} PENDF _3D are “1”.
Is set to That is, the control signal generation circuits 313A to 31
The constructed flag signals CENDF _{0 to} CENDF _{3 in} 3D are all inactive
(That is, “0”), and the processing blocks 11A to 11A
This indicates that the required arithmetic circuit has not been constructed in 11D (see Table 3). Also, control signal generation circuits 313A to 313D
The processed flag signals PENDF _{0 to} PENDF ₃ in the middle are all active (that is, “1”), and the processing blocks 11A to 11D
(Table 3)
See).

[0156]

[Table 3]

Construction of processing circuit 211A--Load instruction processing circuit

In the control signal generating circuit 313A of the control device 13,
Since the processed flag signal PENDF ₀ and the construction command signal CPQ ₀ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 3, the AND circuit AND _3A1
Becomes active (ie, "1") and the processing block
The start of the construction operation of the appropriate arithmetic circuit (here, the load instruction processing circuit) in 11A is instructed (see FIG. 16).

In the control signal generation circuit 313A of the control device 13,
Since the count content of the shift register circuit SR _3A is cleared by a reset signal RESET, the first to third output Q ₁ to Q ₃ are set to "0", and first to third inverting output Q ₁ ^* ＱQ ₃ ^* are set to “1”.

The shift register SR _3A receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3A1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3A becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

The shift register SR _3A receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3A1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. This is accompanied, the shift register SR _3A outputs "0" from the first inverted output terminal Q ₁ ^*, and outputs "0" from the second inverting output terminal Q ₂ ^*. When "1" second from the output terminal Q ₂ of the shift register SR _3A is output, as described later, the shift signal SFTC ₀ is active, which is the output of the AND circuit the AND _3A3 (i.e. "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. Accordingly, the construction command signal CPQ ₀ is inactive
(That is, “0”), and the data _provided from the AND circuit AND _3A1 to the data input terminal A of the shift register SR _3A is set to “0”.

The shift register SR _3A receives the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3A1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3A
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3A2 is connected to the shift register SR _3A
Is _ANDed between the first output and the second inverted output of the shift register _SR3A , when the first output of the shift register SR3A becomes "1", "1" is output. Therefore, the write signal WT ₀ and the increment signal INCP ₀ output from the control signal generation circuit 313A are both active (ie, “1”) when the first output of the shift register SR _3A becomes “1”. )).

The AND circuit AND _3A3 is provided with a shift register SR _3A
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3A becomes "1", and outputs "1". For this reason, the shift signal SFTC ₀ output from the control signal generation circuit 313A is output when the second output of the shift register SR _3A becomes “1”.
Active (ie, "1").

As described above, the count value "0" of the program counter 613 is used as the address signal PC in the program holding device.
Since it is given to 14 of the address inputs AD, the program holding unit 14, "0" and the output data held in the address (i.e. the load instruction) from the data output terminal DATA as instructions INST _0, the instruction register 113A~ 113D (Table 2,
11A, 11B and 22).

[0166] Instruction register 113A, this time, since the write signal WT ₀ is given from the control signal generator circuit 313A to the write signal input terminal, upon its rise, instruction INST ₀ given from the program hold unit 14 Is taken in and held. Incidentally, the instruction registers 113B to 113D receive the write signal from the control signal generation circuits 313B to 313D at the write signal input terminal.
WT ₁ ~WT ₃ is not given (i.e. the write signal WT ₁
~ WT ₃ is inactive), so that the instruction INST ₀ given from the program holding device 14 is not taken in.

[0167] Instruction decoder 213A decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₀ given from the instruction register 113A to an address input terminal AD of the conversion table circuit TBL _3A, decrypts The result is transmitted from the data output terminal DATA of the conversion table circuit TBL _3A to the circuit selection signal SC _0.
(See FIG. 12). The circuit selection signal SC ₀ is
As shown in Table 4, it is "0" and the switch control device
It is given to the connection information selection circuit 212A of 12A (see FIG. 7).
.

[0168]

[Table 4]

[0169] In the switch control unit 12A, when the circuit selection signal SC ₀ from the instruction decoder 213A of the control unit 13 is given, the contents of the circuit selection signal SC ₀ (i.e. circuit number)
The switch connection information corresponding to "0" is selected and given to the processing block 11A (see FIG. 7). As a result, a load instruction processing circuit (shown as “211A”) is constructed as the processing circuit 211A in the processing block 11A (FIGS. 3A and 3B).
And FIG. 23).

The instruction decoder 213A converts the information (operand 1) held in the 21st to 24th bits of the instruction INST ₀ given from the instruction register 113A into the input data selection signal SIA ₀ and the output data selection signal. signal
Output as SO ₀ (see FIG. 12). The input data selection signal SIA ₀ and the output data selection signal SO ₀ are provided to the input data selection circuit 111A and the output data selection circuit 311A of the processing block 11A, respectively, and are used as described later.

The instruction decoder 213A outputs the information (operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 113A as it is, as an input data selection signal SIB ₀ ( (See FIG. 12). Input data selection signal SIB ₀ is applied to input data selection circuit 111A of the processing block 11A, is used as described below.

The instruction decoder 213A converts the information (that is, operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 113A into an OR circuit.
OR _3A to decode and decode result to index modification signal
It is output as IXS ₀ and given to the load instruction processing circuit 211A of the processing block 11A (see FIG. 12). The index modification signal IXS ₀ is inactive because all of the 17th to 20th bits of the instruction INST ₀ are “0” as apparent from Table 2.
(That is, "0"), indicating that no index modification has been made.

[0173] Instruction decoder 213A is the first bit to the information held in the first 16-bit instruction INST ₀ given from the instruction register 113A (i.e. operand 3), it is output as the address signal AD _0, processing block 11A
To the load instruction processing circuit 211A (see FIG. 12). Address signal AD ₀ indicates the address of the data holding device 16.

The load instruction processing circuit 21 is added to the processing block 11A.
After 1A is constructed, the control signal generation circuit 313A, the output of the AND circuit the AND _3A3 (i.e. shift signal SFTC ₀₎ is provided to construct flag signal generating circuit CENDF _3A as a clock signal, and already processed as a clear signal This is supplied to the flag signal generation circuit PENDF _3A (see FIG. 16). For this reason,
The constructed flag signal generation circuit CENDF _3A is a shift register
When the second output of SR _3A becomes "1", a high-level signal applied to data input terminal D (ie, "1")
Is stored, and the constructed flag signal CENDF ₀ is made active (that is, “1”) as shown in Table 5. The processed flag signal generation circuit PENDF _3A is provided with a shift register SR
When the second output of _3A becomes "1", its content is cleared, the processed flag signal PENDF ₀ and inactive as shown in Table 5 (i.e. "0"). Incidentally, between the generation timing of the output of the control signal generating circuit output 313A of AND circuit the AND _3A2 (i.e. the write signal WT ₀ and increment signal INCP ₀₎ generation timing of the AND circuit the AND _3A3 (i.e. shift signal SFTC ₀₎ Is the time required to hold the instruction INST _{0 in} the instruction register 113A, the time required to decode the instruction INST ₀ in the instruction decoder 213A, and the processing block 11A
Is determined in consideration of the time required for switching the changeover switches SWNG _{A1 to} SWNG _{Am when} constructing the load instruction processing circuit 211A.

[0175]

[Table 5]

In the construction pointer 413, the control signal generation circuit
Shift signal SFTC given from the AND circuit AND _3A3 of 313A
Counter according to ₀ (that is, flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11B (that is, the construction command signal CPQ ₁ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₂ , and CPQ ₃ become “0”.
(See Table 5 and FIG. 20).

Since the constructed flag signal CENDF ₀ becomes active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₀ is active (ie, “1”), the control signal generating circuit 313A of the aND circuit the aND _3A4 is a process start signal STRT ₀ for instructing processing start of the load instruction processing circuit 211A of the processing blocks 11A and active (i.e. "1") (see FIG. 16). When the processing start signal STRT ₀ is given to the load instruction processing circuit 211A of the processing block 11A, the load instruction processing circuit 211A of the processing block 11A is
A load instruction is executed as described later (see FIG. 23).

Load instruction processing circuit 21 of processing block 11A
When the processing in 1A (that is, execution of the load instruction) is completed, the load instruction processing circuit 211A of the processing block 11A
The processing end signal END ₀ is made active (that is, “1”) as described later (see FIG. 23). This is accompanied, in the process pointer 513, the counter (i.e. the flip-flop FF ₅₀ ~FF ₅₃₎ Since data is moved, a signal indicating a processing block 11B (i.e. processing command signal) PPQ ₁ is "1", The other processing command signals PPQ ₀ , PPQ ₂ and PPQ ₃ become “0” (see FIG. 21). Also, a control signal generation circuit
In the 313A, the output of the OR circuit OR _3A1 becomes high level to clear the held content of the constructed flag signal generating circuit CENDF _3A , and thus the constructed flag signal CENDF ₀ is inactive as shown in Table 6 (that is, “0” )). Furthermore, the control signal generation circuit 313A, the high-level signal source to the processing flag signal generating circuit PENDF _3A by processing end signal END ₀ high level given from the load instruction processing circuit 211A (not shown) "1" Table 6 shows that the processed flag signal PENDF ₀
Becomes active (ie, “1”) as shown in FIG.

[0179]

[Table 6]

[0180] The program counter 613, when the increment signal INCP ₀ given from the control signal generator circuit 313A becomes active (i.e. "1"), the count value "1" is increased by the program held as the address signal PC Device 14
(See FIG. 22).

Construction of processing circuit 211B--Load instruction processing circuit

In control signal generation circuit 313B of control device 13,
Since the processed flag signal PENDF ₁ and the construction command signal CPQ ₁ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 6, the AND circuit AND _3B1
Becomes active (ie, "1") and the processing block
The start of the construction operation of an appropriate arithmetic circuit (here, a load instruction processing circuit) in 11B is instructed (see FIG. 17).

In control signal generation circuit 313B of control device 13,
Since the count content of the shift register SR _3B has been cleared by the reset signal RESET, the first to third outputs Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

Shift register SR_3BIs the clock signal CLOC
At the rise of K, AND circuit AN is connected to data input terminal A.
D_3B1Data "1" given by
Therefore, the first output terminal Q₁ Outputs "1". to this
Accompanying the shift register SR _3BIs the first inverted output terminal Q
₁ ^*Outputs "0".

The shift register SR _3B receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3B1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3B outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* . When "1" second from the output terminal Q ₂ of the shift register SR _3B is output, as described later, the shift signal SFTC ₁ is active, which is the output of the AND circuit the AND _3B3 (ie "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. Accordingly, the construction command signal CPQ ₁ is inactive.
(That is, “0”), and the data _supplied from the AND circuit AND _3B1 to the data input terminal A of the shift register SR _3B is set to “0”.

The shift register SR _3B receives the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3B1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3B
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3B2 is connected to the shift register SR _3B
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3B becomes "1", and outputs "1". Therefore, the write signal WT ₁ and the increment signal INCP ₁ output from the control signal generation circuit 313B are both active (ie, “1”) when the first output of the shift register SR _3B becomes “1”. )).

The AND circuit AND _3B3 is connected to the shift register SR _3B
And the third inverted output of the shift register SR _3B , the second output of the shift register SR _3B outputs “1” when the second output of the shift register SR _3B becomes “1”. Therefore, the shift signal SFTC ₁ which is output from the control signal generator circuit 313B, when the second output of the shift register SR _3B becomes "1",
Active (ie, "1").

As described above, the count value "1" of the program counter 613 is used as the address signal PC in the program holding device.
Since it is given to 14 of the address inputs AD, the program holding unit 14, "1" and the output data held in the address (i.e. the load instruction) from the data output terminal DATA as instructions INST _1, instruction register 113A~ 113D (Table 2,
11A, 11B and 22).

[0190] Instruction register 113B, the time, since the write signal WT ₁ is supplied from the control signal generator circuit 313B to the write signal input terminal, upon its rise, the instruction given from the program hold unit 14 INST ₁ Is stored inside. Incidentally, the instruction registers 113A, 113C, 113D do not receive the write signals WT ₀ , WT ₂ , WT ₃ from the control signal generation circuits 313A, 313C, 313D at the write signal input terminals (that is, the write signal WT ₀ , WT ₂ and WT ₃ are inactive), so that the instruction INST ₁ given from the program holding device 14 is not taken in.

[0191] Instruction decoder 213B decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₁ given from the instruction register 113B to the address inputs AD conversion table circuit TBL _3B, decryption The result is sent from the data output terminal DATA of the conversion table circuit TBL _3B to the circuit selection signal SC _1.
(See FIG. 13). The circuit selection signal SC ₁ is
As shown in Table 4, it is "0" and the switch control device
It is given to the connection information selection circuit 212B of 12B (see FIG. 8).
.

[0192] In the switch control device 12B, when the circuit selection signal SC ₁ from the instruction decoder 213B of the controller 13 is given, the contents (i.e., circuit number) the circuit selection signal SC ₁
The switch connection information corresponding to "0" is selected and given to the processing block 11B (see FIG. 8). Thus, a load instruction processing circuit (shown as “211B”) is constructed as a processing circuit 211B in the processing block 11B (FIGS. 4A and 4B).
And FIG. 23).

[0193] Instruction decoder 213B is the information held in the first 21 bits to 24 bits of instruction INST ₁ given from the instruction register 113B (i.e. operand 1), as it is, the input data selection signal SIA ₁ and the output data selection circuit
Output as SO ₁ (see FIG. 13). Input data selection signal SIA ₁ and the output data selection circuit SO _1, respectively, are given in the input data selection circuit 111B and the output data selection circuit 311B of the processing block 11B, is used as described below.

[0194] Instruction decoder 213B is the information held in the 17th bit to the 20th bit of the instruction INST ₁ given from the instruction register 113B (i.e. operand 2) directly outputs an input data selection signal SIB ₁ ( (See FIG. 13). Input data selection signal SIB ₁ is applied to input data selection circuit 111B of the processing block 11B, is used as described below.

The instruction decoder 213B converts the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₁ given from the instruction register 113B into an OR circuit.
OR _3B to decode and decode result to index modification signal
IXS ₁ is output to the load instruction processing circuit 211B of the processing block 11B (see FIG. 13). Index modification signal IXS _1, since all of the 17 bits to the 20 bits of instruction INST ₁ is as evident in Table 2 "0", inactive
(That is, "0"), indicating that no index modification has been made.

[0196] Instruction decoder 213B includes a first bit to information held in the 16-bit instruction INST ₁ given from the instruction register 113B (i.e. operand 3), it is output as the address signal AD _1, processing block 11B
To the load instruction processing circuit 211B (see FIG. 13). The address signal AD ₁ indicates the address of the data holding device 16.

The load instruction processing circuit 21 is added to the processing block 11B.
After 1B is constructed, in the control signal generation circuit 313B, the output of the AND circuit AND _3B3 (that is, the shift signal SFTC ₁ ) is supplied to the constructed flag signal generation circuit CENDF _3B as a clock signal and processed as a clear signal. This is supplied to a flag signal generation circuit PENDF _3B (see FIG. 17). For this reason,
The constructed flag signal generation circuit CENDF _3B is a shift register
When the second output of SR _3B becomes “1”, a high-level signal applied to data input terminal D (ie, “1”)
Is taken and held, and the constructed flag signal CENDF ₁ is made active (that is, “1”) as shown in Table 7. The processed flag signal generation circuit PENDF _3B
When the second output of the _3B becomes "1", its content is cleared, the processed flag signal PENDF ₁ and inactive as shown in Table 7 (that is, "0"). Incidentally, between the occurrence time of the output of the generator when and AND circuit the AND _3B3 of the output of the AND circuit the AND _3B2 of the control signal generator circuit 313B (i.e. write signal WT ₁ and increment signal INCP ₁₎ (i.e. the shift signal SFTC ₁₎ the time difference, the instruction register time required for holding the instruction INST ₁ for 113B, the time required to decode the instruction INST ₁ in the instruction decoder 213B, processing block 11B
Is determined in consideration of the time required for switching the changeover switches SWNG _{B1 to} SWNG _{Bm when} the load instruction processing circuit 211B is constructed.

[0198]

[Table 7]

In the construction pointer 413, a control signal generation circuit
Shift signal SFTC given from AND circuit AND _{3B3 of} 313B
₁ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11C (that is, the construction command signal CPQ ₂ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₁ and CPQ ₃ become “0”.
(See Table 7 and FIG. 20).

Since the constructed flag signal CENDF ₀ becomes active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₁ is active (ie, “1”), the control signal generation circuit 313B of the aND circuit the aND _3B4 is a process start signal STRT ₁ for instructing processing start of the load instruction processing circuit 211B of the processing block 11B and active (i.e. "1") (see FIG. 17). When the processing start signal STRT ₁ is given to the load instruction processing circuit 211B of the processing block 11B, the load instruction processing circuit 211B of the processing block 11B
A load instruction is executed as described later (see FIG. 23).

Load instruction processing circuit 21 of processing block 11B
When the processing in 1B (that is, execution of the load instruction) is completed, the load instruction processing circuit 211B of the processing block 11B
The processing end signal END ₁ is made active (that is, “1”) as described later (see FIG. 23). This is accompanied, in the process pointer 513, the counter (i.e. the flip-flop FF ₅₀ ~FF ₅₃₎ Since data is moved, a signal indicating a processing block 11C (i.e. processing instruction signal) PPQ ₂ is Table 8
As shown in FIG. 7, the signal becomes “1”, and the other processing command signals PPQ ₀ , P
PQ ₁ and PPQ ₃ become “0” (see FIG. 21). Further, in the control signal generation circuit 313B, the output of the OR circuit OR _3B1 becomes high level to clear the held content of the constructed flag signal generation circuit CENDF _3B , so that the constructed flag signal CENDF ₁ is as shown in Table 8. It becomes inactive (that is, “0”). Furthermore, the control signal generating circuit 313B, a high level signal source to the processing flag signal generating circuit PENDF _3B by the high level of the processing end signal END ₁ supplied from the load instruction processing circuit 211B (not shown) "1" The processed flag signal PE
NDF ₁ is active (ie, "1") as shown in Table 8.

[0202]

[Table 8]

[0203] The program counter 613, when the increment signal INCP ₁ given from the control signal generator circuit 313B becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 14 (see FIG. 22).

Construction of processing circuit 211C ... addition instruction processing circuit

In the control signal generation circuit 313C of the control device 13,
Since the processed flag signal PENDF ₂ and the construction command signal CPQ ₂ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 8, the AND circuit AND _3C1
Becomes active (ie, "1") and the processing block
The start of the construction operation of an appropriate arithmetic circuit (here, an addition instruction processing circuit) in 11C is instructed (see FIG. 18).

In the control signal generation circuit 313C of the control device 13,
Since the count content of the shift register SR _3C is cleared by a reset signal RESET, the first to third output Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

The shift register SR _3C receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3C1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3C has the first inverted output terminal Q
Outputs "0" from ₁ ^* .

The shift register SR _3C receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3C1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3C outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* . When "1" second from the output terminal Q ₂ of the shift register SR _3C is output, as described later, the shift signal SFTC ₂ is active, which is the output of the AND circuit the AND _3C3 (i.e. "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. Accordingly, the construction command signal CPQ ₂ becomes inactive.
(That is, “0”), and the data _provided from the AND circuit AND _3C1 to the data input terminal A of the shift register SR _3C is set to “0”.

[0209] The shift register SR _3C is, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3C1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3C
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3C2 is connected to the shift register SR _3C
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3C becomes "1", and outputs "1". Therefore, the write signal WT ₂ and the increment signal INCP ₂ output from the control signal generation circuit 313C are both active (ie, “1”) when the first output of the shift register SR _3C becomes “1”. )).

The AND circuit AND _3C3 is provided with a shift register SR _3C
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3C becomes "1", and outputs "1". Therefore, the shift signal SFTC ₂ which is output from the control signal generating circuit 313C, when the second output of the shift register SR _3C becomes "1",
Active (ie, "1").

As described above, the count value “2” of the program counter 613 is used as the address signal PC as the program holding device.
Since it is given to 14 of the address inputs AD, the program holding unit 14, "2" and the output data held in the address (ie, addition instruction) from the data output terminal DATA as the instruction INST _2, instruction register 113A~ 113D (see Table 2, FIGS. 11A, 11B and 22).

[0213] Instruction register 113C is, at this time, since the write signal WT ₂ is supplied from the control signal generator circuit 313C to the write signal input terminal, upon its rise, the instruction given from the program hold unit 14 INST ₂ Is taken in and held. By the way, the instruction registers 113A, 113B, 113D are
Write signal input to the control signal generation circuit 313A, 313B, are not given the write signal WT _0, WT _1, WT ₃ from 313D (that is, the write signal WT _0, WT _1, WT ₃ is inactive Therefore, the instruction INST ₂ given from the program holding device 14 is not taken in.

[0214] Instruction decoder 213C decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₂ given from the instruction register 113C to the address input AD of the conversion table circuit TBL _3C, decryption The result is converted from the data output terminal DATA of the conversion table circuit TBL _3C to the circuit selection signal SC _2.
(See FIG. 14). The circuit selection signal SC ₂ is
As shown in Table 4, "3" indicates that the switch control device
Provided to connection information selection circuit 212C of 12C (see FIG. 9)
.

[0215] In the switch control device 12C, when the circuit selection signal SC ₂ from the instruction decoder 213C of control device 13 is provided, the contents (i.e., circuit number) the circuit selection signal SC ₂
The switch connection information corresponding to "3" is selected and given to the processing block 11C (see FIG. 9). As a result, in the processing block 11C, an addition instruction processing circuit (shown as "211C") is constructed as the processing circuit 211C (see FIGS. 5A, 5B and 24).

The instruction decoder 213C receives the information (that is, the operand 1) held in the 21st to 24th bits of the instruction INST ₂ given from the instruction register 113C, without changing the input data selection signal SIA ₂ and the output data selection signal. signal
Output as SO ₂ (see FIG. 14). Input data selection signal SIA ₂ and the output data selection signal SO _2, respectively, are given in the input data selection circuit 111C and the output data selection circuit 311C of the processing block 11C, is used as described below.

[0217] Instruction decoder 213C is the information held in the 17th bit to the 20th bit of the instruction INST ₂ given from the instruction register 113C (i.e. operand 2) directly outputs an input data selection signal SIB ₂ ( (See FIG. 14). Input data selection signal SIB ₂ is applied to input data selection circuit 111C of the processing block 11C, is used as described below.

The instruction decoder 213C applies the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₂ given from the instruction register 113C to an OR circuit.
OR _3C to decode and decode result to index modification signal
It is output as IXS ₂ and given to the addition instruction processing circuit 211C of the processing block 11C (see FIG. 14). Index modification signal
IXS ₂ are the as apparent "1" to at least Tsugahyo 2 of the 17 bits to the 20 bits of instruction INST _2, it indicates that the next active (i.e. "1"), the index modification has been made But the addition instruction processing circuit
The 211C does not use this.

[0219] Instruction decoder 213C is the information held in the first bit to the 16th bit of the instruction INST ₂ given from the instruction register 113C (i.e. operand 3), it is output as the address signal AD _2, the processing block 11C
To the addition instruction processing circuit 211C (see FIG. 14). However, the address signal AD _2, since not required by the add instruction processing circuit 211C of the processing block 11C, not be utilized (see FIG. 24).

The addition instruction processing circuit 211C is added to the processing block 11C.
Is generated, the control signal generation circuit 313C outputs the output of the AND circuit AND _3C3 (that is, the shift signal SFTC ₂ ) to the constructed flag signal generation circuit CENDF _3C as a clock signal, and outputs the processed flag as a clear signal. The signal is supplied to a signal generation circuit PENDF _3C (see FIG. 18). For this reason, the constructed flag signal generation circuit CENDF _3C uses the shift register SR
_When the second output of _3C becomes "1", the data input terminal D
Captures and holds the high-level signal provided to
As the construction flag signal CENDF ₂ shown in Table 9, active (i.e. "1"). When the second output of the shift register SR _3C becomes “1”, the contents of the processed flag signal generation circuit PENDF _3C are cleared, and the processed flag signal PENDF ₂ is turned off as shown in Table 9. Active (ie, “0”). Incidentally, the control signal generation timing of the output (i.e. the write signal WT ₂ and increment signal INCP ₂₎ generation circuit 313C of the AND circuit the AND _3C2 AND circuit the AND _3C3
The time difference between the output of the instruction (i.e., the shift signal SFTC ₂ ) and the time at which the instruction INST ₂ is held in the instruction register 113 C, the time required to decode the instruction INST ₂ in the instruction decoder 213 C, and the addition in the processing block 11 C Changeover switches SWNG _{C1 to} SWNG _{Cm when} constructing the instruction processing circuit 211C
Is determined in consideration of the time required for the switching.

[0221]

[Table 9]

In the construction pointer 413, the control signal generation circuit
Shift signal SFTC given from AND circuit AND _{3C3 of} 313C
₂ according to the counter (i.e., flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11D (that is, the construction command signal CPQ ₃ ) becomes “1”, and the other construction command signals CPQ _{0 to} CPQ ₂ become “0” (Table 9).
And FIG. 20).

Since the constructed flag signal CENDF ₂ becomes active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₂ is active (ie, “1”), the control signal generating circuit 313C of the aND circuit the aND _3C4 is a process start signal STRT ₂ for instructing processing start of the addition instruction processing circuit 211C of the processing block 11C and active (i.e. "1") (see FIG. 18). When the processing start signal STRT ₂ is supplied to the addition instruction processing circuit 211C of the processing block 11C, add instruction processing circuit 211C of the processing block 11C is, as described later, executes the add instruction (see Figure 24).

Addition instruction processing circuit 211C of processing block 11C
When the process (i.e. execution of the addition instruction) is completed in, add instruction processing circuit 211C of the processing block 11C is a processing end signal END ₂ and later as the active (i.e., "1") (see FIG. 24). Along with this, the processing pointer 51
3, the counter (i.e., flip-flops FF _{50 to} FF
Since data of ₅₃₎ is moved, a signal indicating a processing block 11D (i.e. processing instruction signal) PPQ ₃ as is shown in Table 10 becomes "1", other processing command signal PPQ ₀ ~PPQ ₂ is "0" (See FIG. 21). Also, a control signal generation circuit
In the 313C, the output of the OR circuit OR _3C1 becomes high level to clear the contents held in the constructed flag signal generation circuit CENDF _3C1 , and the constructed flag signal CENDF ₂ is inactive as shown in Table 10 (that is, "0"). )). Furthermore, the control signal generating circuit 313C, the high-level signal source to the processing flag signal generating circuit PENDF _3C by the high level of the processing end signal END ₂ given from the add instruction processing circuit 211C (not shown) from the "1" The processed flag signal PENDF ₂
It becomes active (ie, "1") as shown in FIG.

[0225]

[Table 10]

[0226] The program counter 613, when the increment signal INCP ₂ given from the control signal generator circuit 313C becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 14 (see FIG. 22).

Construction of processing circuit 211D: Load effective address
Instruction processing circuit

In control signal generation circuit 313D of control device 13,
Since the processed flag signal PENDF ₃ and the construction command signal CPQ ₃ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 10, the AND circuit AND
The output of _3D1 becomes active (that is, "1"), and commands the start of the construction operation of the appropriate arithmetic circuit (here, the load effective address instruction processing circuit) in the processing block 11D.
(See FIG. 19).

In control signal generation circuit 313D of control device 13,
Since the count content of the shift register SR _3D is cleared by a reset signal RESET, the first to third output Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

The shift register SR _3D receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3D1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3D becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

The shift register SR _3D receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3D1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Accordingly, the shift register SR _3D outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* . When "1" second from the output terminal Q ₂ of the shift register SR _3D is output, as described later, the shift signal SFTC ₃ which is the output of the AND circuit the AND _3D3 is active (i.e. "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. _Accompanying this, the data given from the AND circuit AND _3D1 to the data input terminal A of the shift register SR _3D is set to “0”.

The shift register SR _3D receives the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3D1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3D
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3D2 is connected to the shift register SR _3D
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3D becomes "1", and outputs "1". Therefore, the write signal WT ₃ and the increment signal INCP ₃ output from the control signal generation circuit 313D are both active (ie, “1”) when the first output of the shift register SR _3D becomes “1”. )).

The AND circuit AND _3D3 is connected to the shift register SR _3D
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3D becomes "1", and outputs "1". Therefore, the shift signal SFTC ₃ which is output from the control signal generating circuit 313D when the second output of the shift register SR _3D becomes "1",
Active (ie, "1").

As described above, the count value “3” of the program counter 613 is used as the address signal PC in the program holding device.
Since it is given to 14 of the address inputs AD, the program holding unit 14, "3" and the output data held in the address (i.e. the load effective address instruction) from the data output terminal DATA as instructions INST _3, an instruction register 113A to 113D (see Table 2, FIGS. 11A, 11B and 22).

[0236] Instruction register 113D, the time, since the write signal WT ₃ is given from the control signal generating circuit 313D to the write signal input terminal, upon its rise, instruction INST ₃ given from the program hold unit 14 Is taken in and held. By the way, the instruction registers 113A to 113C receive the write signal from the control signal generation circuits 313A to 313C at the write signal input terminal.
WT _{0 to} WT ₂ are not given (that is, write signal WT ₀
~ WT ₂ is inactive), so that the instruction INST ₃ given from the program holding device 14 is not taken in.

[0237] Instruction decoder 213D decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₃ given from the instruction register 113D to the conversion table circuit TBL _3D the address inputs AD, decryption The result is sent to the circuit selection signal SC ₃ from the data output terminal DATA of the conversion table circuit TBL _3D.
(See FIG. 15). The circuit selection signal SC ₃ is
As shown in Table 4, "2" indicates that the switch control device 12
D is provided to the connection information selection circuit 212D (see FIG. 10).
.

[0238] In the switch control device 12D, when the circuit selection signal SC ₃ from the instruction decoder 213D of the control unit 13 is given, the contents of the circuit selection signal SC ₃ (i.e. circuit number)
The switch connection information corresponding to "2" is selected and given to the processing block 11D (see FIG. 10). As a result, a load effective address instruction processing circuit (shown as “211D”) is constructed as the processing circuit 211D in the processing block 11D.
(See FIGS. 6A, 6B and 25).

The instruction decoder 213D converts the information (ie, operand 1) held in the 21st to 24th bits of the instruction INST ₃ given from the instruction register 113D into the input data selection signal SIA ₃ and the output data selection signal. signal
Output as SO ₃ (see FIG. 15). The input data selection signal SIA ₃ and the output data selection signal SO ₃ are provided to the input data selection circuit 111D and the output data selection circuit 311D of the processing block 11D, respectively, and are used as described later.

[0240] Instruction decoder 213D is the first 17 bits to information held in the 20-bit instruction INST ₃ given from the instruction register 113D (i.e. operand 2) directly outputs an input data selection signal SIB ₃ ( (See FIG. 15). Input data selection signal SIB ₃ is applied to input data selection circuit 111D processing block 11D, are utilized as described below.

The instruction decoder 213D converts the information (that is, operand 2) held in the 17th to 20th bits of the instruction INST ₃ given from the instruction register 113D into an OR circuit.
OR Decodes to _3D and decodes the result to index modification signal
IXS ₃ is output to the load effective address instruction processing circuit 211D of the processing block 11D (see FIG. 15). Index modification signal IXS _3, all of the 17 bits to the 20 bits of the instruction INST ₃ since a as clear "0" in Table 2, the non-active (i.e. "0"), and has not been indexed modified It is shown that.

[0242] Instruction decoder 213D is the first bit to the information held in the first 16-bit instruction INST ₃ given from the instruction register 113D (i.e. operand 3), it is output as the address signal AD _3, processing blocks 11D
To the load effective address instruction processing circuit 211D (see FIG. 1).
5). Address signal AD ₃ indicates the address of the data holding device 16.

After the load effective address instruction processing circuit 211D is constructed in the processing block 11D, the control signal generating circuit 31
In 3D, the output of AND circuit AND _3D3 (i.e., the shift signal
SFTC ₃ ) is supplied to the constructed flag signal generating circuit CENDF _3D as a clock signal, and is supplied to the processed flag signal generating circuit PENDF _3D as a clear signal (see FIG. 19).
. For this reason, the constructed flag signal generation circuit CENDF _3D
When the second output of the shift register SR _3D becomes “1”, a high-level signal applied to the data input terminal D
(Ie, “1”) is captured and held, and the constructed flag signal CENDF ₃ is activated (ie, “1”) as shown in Table 11. The processed flag signal generation circuit PEND
When the second output of the shift register SR _3D becomes “1”, the contents of F _3D are cleared and the processed flag signal PE
NDF ₃ is inactive as shown in Table 11 (ie "0")
And By the way, the AND circuit of the control signal generation circuit 313D
Timing of generation of output of AND _3D2 (that is, write signal WT ₃ and increment signal INCP ₃ ) and output of AND circuit AND _3D3
The time difference between the occurrence of the shift signal SFTC ₃ and the time required to hold the instruction INST _{3 in} the instruction register 113 D, the time required to decode the instruction INST ₃ in the instruction decoder 213 D, and the load effective address in the processing block 11 D Switch SWNG _{D1 when} constructing the instruction processing circuit 211D
〜SWNG _Dm is determined in consideration of the time required for switching.

[0244]

[Table 11]

In the construction pointer 413, the control signal generation circuit
Shift signal SFTC given from AND circuit AND _{3D3 of} 313D
₃ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11A (that is, the construction command signal CPQ ₀ ) becomes “1”, and the other construction command signals CPQ _{1 to} CPQ ₃ become “0” (Table 1).
1 and FIG. 20).

Since the constructed flag signal CENDF ₃ is active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₃ is active (ie, “1”), the control signal generating circuit 313D AND circuit AND _3D4 is a load effective address instruction processing circuit 211D of the processing block 11D.
Activates the processing start signal STRT ₃ to instruct the processing start
(That is, “1”) (see FIG. 19). When the process start signal STRT ₃ applied to the load effective address instruction processing circuit 211D of the processing block 11D, the load effective address instruction processing circuit 211D of the processing block. 11D, as described later, executes the load effective address instruction (see FIG. 25 ).

[0247] When the processing in the load effective address instruction processing circuit 211D of the processing block 11D is completed, the load effective address instruction processing circuit 211D of the processing block 11D is a processing end signal END ₃ a as described later active (i.e. "1") (See FIG. 25). Along with this, the processing pointer 51
3, the counter (i.e., flip-flops FF _{50 to} FF
Since data of ₅₃₎ is moved, a signal indicating a processing block 11A (i.e. processing command signal) PPQ ₀ as is shown in Table 12 "1", and the other processes the command signal PPQ ₁ ~PPQ ₃ "0" (See FIG. 21). Also, a control signal generation circuit
In the 313D, the output of the OR circuit OR _3D1 becomes high level to clear the contents held in the constructed flag signal generation circuit CENDF _3D1 , and thus the constructed flag signal CENDF ₃ is inactive as shown in Table 12 (that is, "0 )). Further, the control signal generation circuit 313D includes a load effective address instruction processing circuit 211D.
Since taking a high-level signal source (not shown) from "1" by the processing end signal END ₃ a high level given to the processed flag signal generating circuit PENDF _3D from the processed flag signal PENDF ₃ Table 12 As shown, it is active (ie, "1").

[0248]

[Table 12]

[0249] The program counter 613, when the increment signal INCP ₃ supplied from the control signal generating circuit 313D becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 14 (see FIG. 22).

Construction of processing circuit 211A: arithmetic left shift instruction processing
Circuit

In the control signal generation circuit 313A of the control device 13,
Since the processed flag signal PENDF ₀ and the construction command signal CPQ ₀ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 12, the AND circuit AND
The output of _3A1 becomes active (that is, "1"), and commands the start of the construction operation of the appropriate arithmetic circuit (here, the arithmetic left shift instruction processing circuit) in the processing block 11A (FIG. 16).
See).

In the control signal generation circuit 313A of the control device 13,
The output of the AND circuit AND _3A1 is “0” for a certain period
Since was, counting the contents of the shift register SR _3A is cleared, the first to third output Q ₁ to Q ₃ is accompanied thereto
Is set to “0”, and the first to third inverted outputs Q ₁ ^* to
Q ₃ ^* is set to “1”.

[0253] The shift register SR _3A, the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3A1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3A becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0254] The shift register SR _3A, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3A1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. This is accompanied, the shift register SR _3A outputs "0" from the first inverted output terminal Q ₁ ^*, and outputs "0" from the second inverting output terminal Q ₂ ^*. When "1" second from the output terminal Q ₂ of the shift register SR _3A is output, as described later, the shift signal SFTC ₀ is active, which is the output of the AND circuit the AND _3A3 (i.e. "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. _Along with this, the data _supplied from the AND circuit AND _3A1 to the data input terminal A of the shift register SR _3A is set to “0”.

The shift register SR _3A receives the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3A1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3A
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3A2 is connected to the shift register SR _3A
Is _ANDed between the first output and the second inverted output of the shift register _SR3A , when the first output of the shift register SR3A becomes "1", "1" is output. Therefore, the write signal WT ₀ and the increment signal INCP ₀ output from the control signal generation circuit 313A are both active (ie, “1”) when the first output of the shift register SR _3A becomes “1”. )).

The AND circuit AND _3A3 is provided with a shift register SR _3A
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3A becomes "1", and outputs "1". For this reason, the shift signal SFTC ₀ output from the control signal generation circuit 313A is output when the second output of the shift register SR _3A becomes “1”.
Active (ie, "1").

As described above, the count value “4” of the program counter 613 is used as the address signal PC in the program holding device.
14, the program holding device 14 transfers the data (ie, the arithmetic left shift command) held at the address "4" from the data output terminal DATA to the instruction IN.
Output as ST ₀ and give to instruction registers 113A-113D
(See Table 2, FIG. 11A, FIG. 11B and FIG. 22).

[0259] Instruction register 113A, this time, since the write signal WT ₀ is given from the control signal generator circuit 313A to the write signal input terminal, upon its rise, instruction INST ₀ given from the program hold unit 14 Is taken in and held. Incidentally, the instruction registers 113B to 113D receive the write signal from the control signal generation circuits 313B to 313D at the write signal input terminal.
WT ₁ ~WT ₃ is not given (i.e. the write signal WT ₁
~ WT ₃ is inactive), so that the instruction INST ₀ given from the program holding device 14 is not taken in.

[0260] Instruction decoder 213A decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₀ given from the instruction register 113A to an address input terminal AD of the conversion table circuit TBL _3A, decrypts The result is transmitted from the data output terminal DATA of the conversion table circuit TBL _3A to the circuit selection signal SC _0.
(See FIG. 12). The circuit selection signal SC ₀ is
As shown in Table 4, it is "4" and the switch control device
It is given to the connection information selection circuit 212A of 12A (see FIG. 7).
.

[0261] In the switch control unit 12A, when the circuit selection signal SC ₀ from the instruction decoder 213A of the control unit 13 is given, the contents of the circuit selection signal SC ₀ (i.e. circuit number)
The switch connection information corresponding to "4" is selected and given to the processing block 11A (see FIG. 7). As a result, an arithmetic left shift instruction processing circuit (shown as “211A”) is constructed as the processing circuit 211A in the processing block 11A (FIG. 3A,
3B and FIG. 26).

The instruction decoder 213A converts the information (ie, operand 1) held in the 21st to 24th bits of the instruction INST ₀ given from the instruction register 113A into the input data selection signal SIA ₀ and the output data selection signal. signal
Output as SO ₀ (see FIG. 12). The input data selection signal SIA ₀ and the output data selection signal SO ₀ are given to the input data selection circuit 111A and the output data selection circuit 311A of the processing block 11A, respectively, and are used as described later.

The instruction decoder 213A outputs the information (operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 113A as it is, as the input data selection signal SIB ₀ ( (See FIG. 12). Input data selection signal SIB ₀ is applied to input data selection circuit 111A of the processing block 11A, is used as described below.

The instruction decoder 213A converts the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 113A into an OR circuit.
OR _3A to decode and decode result to index modification signal
It is output as IXS ₀ and given to the arithmetic left shift instruction processing circuit 211A of the processing block 11A (see FIG. 12). Index modification signal IXS ₀ are the instruction INST least Tsugahyo 2 As will be apparent to a 17th bit to 20th bit of ₀ "1", and active (i.e. "1"), and the index modification made Indicates that processing block 11A
Since it is not required by the arithmetic left shift instruction processing circuit 211A, it is not used (see FIG. 26).

[0265] Instruction decoder 213A is the first bit to the information held in the first 16-bit instruction INST ₀ given from the instruction register 113A (i.e. operand 3), it is output as the address signal AD _0, processing block 11A
To the arithmetic left shift instruction processing circuit 211A (see FIG. 12). However, the address signal AD _0, because not required by the arithmetic left shift instruction processing circuit 211A of the processing block 11A, is not used.

[0266] The processing after the arithmetic left shift instruction processing circuit 211A is constructed in block 11A, control the signal generating circuit 313A, the output of the AND circuit the AND _3A3 (i.e. shift signal SFTC
₀ ) is a built-in flag signal generation circuit CE as a clock signal.
The signal is supplied to the NDF _3A and to the processed flag signal generating circuit PENDF _3A as a clear signal (see FIG. 16). Therefore, when the second output of the shift register SR _3A becomes "1", the constructed flag signal generating circuit CENDF _3A outputs a high-level signal (that is, "1") given to the data input terminal D. And hold it, and the built flag signal CENDF ₀
Is active (ie, “1”) as shown in Table 13. The processing flag signal generating circuit PENDF _{3 A} includes a shift register when the second output of the SR _3A becomes "1", its content is cleared, the processed flag signal PENDF ₀ Table 13
Inactive as shown in (1) (that is, "0"). By the way, the output of the AND circuit AND _3A2 of the control signal generation circuit 313A
(That is, the write signal WT ₀ and the increment signal INCP
The time difference between the occurrence time of the output of the generator when and AND circuit the AND _{3 A3 0)} (i.e. the shift signal SFTC ₀₎ is the time required for holding the instruction INST ₀ for the instruction register 113A, the instruction INST ₀ in the instruction decoder 213A Time required to decode the data, arithmetic left shift instruction processing circuit 211A in processing block 11A
Is determined in consideration of the time required for switching the changeover switches SWNG _{A1 to} SWNG _{Am when} constructing the device.

[0267]

[Table 13]

In the construction pointer 413, the control signal generation circuit
Shift signal SFTC given from the AND circuit AND _3A3 of 313A
Counter according to ₀ (that is, flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11B (that is, the construction command signal CPQ ₁ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₂ , and CPQ ₃ become “0”.
(See Table 13 and FIG. 20).

Since the constructed flag signal CENDF ₀ is active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₀ is active (ie, “1”), the control signal generating circuit 313A of the aND circuit the aND _3A4 is a process start signal STRT ₀ for instructing processing start of the arithmetic left shift instruction processing circuit 211A of the processing blocks 11A and active (i.e. "1") (see FIG. 16). Processing start signal STRT
₀ is the arithmetic left shift instruction processing circuit 211A of the processing block 11A
, The arithmetic left shift instruction processing circuit 211A of the processing block 11A executes the arithmetic left shift instruction as described later (see FIG. 26).

When the processing in the arithmetic left shift instruction processing circuit 211A of the processing block 11A is completed, the processing block 11A
Arithmetic left shift instruction processing circuit 211A of the processing end signal END ₀
Is active (ie, “1”) as described later (FIG. 26).
See). This is accompanied, in the process pointer 513, the data of the counter (i.e., flip-flop FF ₅₀ ~FF ₅₃₎ is moved, a signal indicating a processing block 11B (i.e. processing command signal) PPQ ₁ is shown in Table 14 Like "1"
And the other processing command signals PPQ ₀ , PPQ ₂ , and PPQ ₃ become “0” (see FIG. 21). In the control signal generation circuit 313A,
_Since the output of the OR circuit OR _3A1 becomes high level to clear the held content of the constructed flag signal generation circuit CENDF _3A , the constructed flag signal CENDF ₀ is inactive as shown in Table 14.
(That is, “0”). Further, the control signal generation circuit 313
In A, since a high-level processing end signal END ₀ given from the arithmetic left shift instruction processing circuit 211A receives “1” from a high-level signal source (not shown) to the processed flag signal generation circuit PENDF _3A , Table 1 shows the processed flag signal PENDF ₀
It becomes active (ie, "1") as shown in FIG.

[0271]

[Table 14]

[0272] The program counter 613, when the increment signal INCP ₀ given from the control signal generator circuit 313A becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 14 (see FIG. 22).

Construction of processing circuit 211B: Store instruction processing circuit

In the control signal generation circuit 313B of the control device 13,
Since the processed flag signal PENDF ₁ and the construction command signal CPQ ₁ given from the construction pointer 413 are both active (ie, “1”) as shown in Table 14, the AND circuit AND
The output of _3B1 becomes active (that is, "1") and instructs the start of the construction operation of the appropriate arithmetic circuit (here, the store instruction processing circuit) in the processing block 11B (see FIG. 17).
.

In control signal generation circuit 313B of control device 13,
The output of the AND circuit AND _3B1 is "0" for a certain period
Since was, counting the contents of the shift register SR _3B is cleared, the first to third output Q ₁ to Q ₃ is accompanied thereto
Is set to “0”, and the first to third inverted outputs Q ₁ ^* to
Q ₃ ^* is set to “1”.

The shift register SR _3B receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3B1 therein, outputs "1" from the first output terminal Q _1. Accordingly, the shift register SR _3B has the first inverted output terminal Q
Outputs "0" from ₁ ^* .

The shift register SR _3B receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3B1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3B outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* . When "1" second from the output terminal Q ₂ of the shift register SR _3B is output, as described later, the shift signal SFTC ₁ is active, which is the output of the AND circuit the AND _3B3 (ie "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. _Along with this, the data _supplied from the AND circuit AND _3B1 to the data input terminal A of the shift register SR _3B is set to “0”.

The shift register SR _3B receives the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3B1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3B
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3B2 is connected to the shift register SR _3B
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3B becomes "1", and outputs "1". Therefore, the write signal WT ₁ and the increment signal INCP ₁ output from the control signal generation circuit 313B are both active (ie, “1”) when the first output of the shift register SR _3B becomes “1”. )).

The AND circuit AND _3B3 is connected to the shift register SR _3B
And the third inverted output of the shift register SR _3B , the second output of the shift register SR _3B outputs “1” when the second output of the shift register SR _3B becomes “1”. Therefore, the shift signal SFTC ₁ which is output from the control signal generator circuit 313B, when the second output of the shift register SR _3B becomes "1",
Active (ie, "1").

As described above, the count value "5" of the program counter 613 is used as the address signal PC in the program holding device.
Since it is given to 14 of the address inputs AD, the program holding unit 14, "5" and the output data held in the address (i.e. store instruction) from the data output terminal DATA as instructions INST _1, instruction register 113A~ 113D (Table 2,
11A, 11B and 22).

[0282] Instruction register 113B, the time, since the write signal WT ₁ is supplied from the control signal generator circuit 313B to the write signal input terminal, upon its rise, the instruction given from the program hold unit 14 INST ₁ Is taken in and held. By the way, the instruction registers 113A, 113C, 113D are
Write signals WT ₀ , WT ₂ , WT ₃ are not applied to the write signal input terminals from control signal generation circuits 113 A, 113 C, 313 D (that is, write signals WT ₀ , WT ₂ , WT ₃ are inactive) Therefore, the instruction INST ₁ given from the program holding device 14 is not taken in.

[0283] Instruction decoder 213B decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₁ given from the instruction register 113B to the address inputs AD conversion table circuit TBL _3B, decryption The result is sent from the data output terminal DATA of the conversion table circuit TBL _3B to the circuit selection signal SC _1.
(See FIG. 13). The circuit selection signal SC ₁ is
As shown in Table 4, it is "1" and the switch control device
It is given to the connection information selection circuit 212B of 12B (see FIG. 8).
.

[0284] In the switch control device 12B, when the circuit selection signal SC ₁ from the instruction decoder 213B of the controller 13 is given, the contents (i.e., circuit number) the circuit selection signal SC ₁
The connection information corresponding to “1” is selected, and the processing block 11B
(See FIG. 8). This allows processing blocks
11B has a store instruction processing circuit as a processing circuit 211B.
(Shown as "211B") (see FIGS. 4A, 4B and 27).

[0285] Instruction decoder 213B is the information held in the first 21 bits to 24 bits of instruction INST ₁ given from the instruction register 113B (i.e. operand 1), as it is, the input data selection signal SIA ₁ and the output data selection signal
Output as SO ₁ (see FIG. 13). Input data selection signal SIA ₁ and output data selection signal SO _1, respectively, are given in the input data selection circuit 111B and the output data selection circuit 311B of the processing block 11B, is used as described below.

[0286] Instruction decoder 213B is the information held in the 17th bit to the 20th bit of the instruction INST ₁ given from the instruction register 113B (i.e. operand 2) directly outputs an input data selection signal SIB ₁ ( (See FIG. 13). Input data selection signal SIB ₁ is applied to input data selection circuit 111B of the processing block 11B, is used as described below.

The instruction decoder 213B converts the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₁ given from the instruction register 113B into an OR circuit.
OR _3B to decode and decode result to index modification signal
It is output as IXS ₁ and given to the store instruction processing circuit 211B of the processing block 11B (see FIG. 13). Index modification signal IXS _1, since all of the 17 bits to the 20 bits of instruction INST ₁ is as evident in Table 2 "0", inactive
(That is, "0"), indicating that no index modification has been made.

[0288] Instruction decoder 213B includes a first bit to information held in the 16-bit instruction INST ₁ given from the instruction register 113B (i.e. operand 3), it is output as the address signal AD _1, processing block 11B
To the store instruction processing circuit 211B (see FIG. 13). The address signal AD ₁ indicates the address of the data holding device 16.

Store instruction processing circuit 21 is added to processing block 11B.
After 1B is constructed, in the control signal generation circuit 313B, the output of the AND circuit AND _3B3 (that is, the shift signal SFTC ₁ ) is supplied to the constructed flag signal generation circuit CENDF _3B as a clock signal and processed as a clear signal. This is supplied to a flag signal generation circuit PENDF _3B (see FIG. 17). For this reason,
The constructed flag signal generation circuit CENDF _3B is a shift register
When the second output of SR _3B becomes “1”, a high-level signal applied to data input terminal D (ie, “1”)
The stored flag signal CENDF ₁ is stored in Table 15
As shown in (1). Also,
The processed flag signal generation circuit PENDF _3B is a shift register
When the second output of the SR _3B becomes "1", its content is cleared, the processed flag signal PENDF ₁ and inactive as shown in Table 15 (that is, "0"). Incidentally, the control signal generating circuit output 313B of the AND circuit the AND _3B2 output generation timing (i.e. write signal WT ₁ and increment signal INCP ₁₎ and an AND circuit the AND _3B3 (ie shift signal SFTC
The time difference between the occurrence time of _1), the time required for holding the instruction INST ₁ for the instruction register 113B, the instruction decoder 213B
Time required to decode instruction INST ₁ in, processing block 1
It is determined in consideration of the time required for switching the changeover switches SWNG _{B1 to} SWNG _{Bm when} constructing the store instruction processing circuit 211B in 1B.

[0290]

[Table 15]

In the construction pointer 413, a control signal generation circuit
Shift signal SFTC given from AND circuit AND _{3B3 of} 313B
₁ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 11C (that is, the construction command signal CPQ ₂ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₁ and CPQ ₃ become “0”.
(See Table 15 and FIG. 20).

Since the constructed flag signal CENDF ₁ becomes active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₁ is active (ie, “1”), the control signal generating circuit 313B of the aND circuit the aND _3B4 is a process start signal STRT ₁ for instructing the start of processing the store instruction processing circuit 211B of the processing block 11B and active (i.e. "1") (see FIG. 17). When the processing start signal STRT ₁ is given to the store instruction processing circuit 211B of the processing block 11B, the store instruction processing circuit 211B of the processing block 11B
A store instruction is executed as described later (see FIG. 27).

Store instruction processing circuit 21 of processing block 11B
When the processing in 1B (that is, execution of the store instruction) is completed, the store instruction processing circuit 211B of the processing block 11B
The processing end signal END ₁ is made active (that is, “1”) as described later (see FIG. 27). This is accompanied, in the process pointer 513, the counter (i.e. the flip-flop FF ₅₀ ~FF ₅₃₎ Since data is moved, a signal indicating a processing block 11C (i.e. processing instruction signal) PPQ ₂ is Table 1
It becomes "1" as shown in FIG.
Q ₀ , PPQ ₁ and PPQ ₃ become “0” (see FIG. 21). The control in the signal generating circuit 313B, the output of the OR circuit OR _3B1 becomes the high level to clear the contents held in construction flag signal generating circuit CENDF _3B, constructed flag signal CENDF ₁ is Table 1
As shown in FIG. 6, it becomes inactive (that is, "0"). Further, in the control signal generation circuit 313B, the store instruction processing circuit 21
Processed by the processing end signal END ₁ a high level supplied from 1B flag signal generating circuit PENDF high signal source to _3B since capture "1" (not shown), processed flag signal PENDF ₁ is Table 16 Becomes active (ie, “1”) as shown in FIG.

[0294]

[Table 16]

[0295] The program counter 613, when the increment signal INCP ₁ given from the control signal generator circuit 313B becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 14 (see FIG. 22).

Processing in processing circuit 211A: Load instruction
Run

Load instruction processing circuit 21 of processing block 11A
When 1A is constructed, as apparent from Table 5, the processing command signal PPQ ₀ given from the processing pointer 513 becomes active.
(I.e., "1"), and since the constructed flag signal CENDF ₀ is active (i.e., "1"), the output of the AND circuit AND _3A4 of the control signal generation circuit 313A, that is, the processing start signal STRT ₀ is It becomes active (that is, "1") and is supplied to the processing start signal input terminal STRT _A of the load instruction processing circuit 211A of the processing block 11A (see FIGS. 16, 21 and 23). By the way, the processed flag signal PENDF ₀ is shown in Table 5.
As apparent from FIG. 7, the output of the AND circuit AND _3A1 of the control signal generation circuit 313A becomes inactive (ie, “0”), and the construction pointer
The construction command signal CPQ ₀ given from 413 is temporarily active.
Even if it becomes (1), the construction of the arithmetic circuit in the processing block 11A is not restarted. In other words, the construction of a new arithmetic circuit in the processing block 11A is prevented until the desired arithmetic processing (that is, the load instruction processing) is completed in the load instruction processing circuit 211A of the processing block 11A.

Load instruction processing circuit 21 of processing block 11A
At 1A, the processing start signal STRT ₀ given to the processing start signal input end STRT _A is applied to the load input end of the down counter DCNT _A.
This is given to the LD (see FIG. 23).

The down counter DCNT _A is connected to the load input terminal LD.
When the processing start signal STRT ₀ is supplied to the data input terminal D, the “constant” supplied to the data input terminal D is fetched inside to start the subtraction operation.

[0300] Instruction decoder 213A of the controller 13, by decoding an instruction INST ₀ given from the instruction register 113A, after outputted a circuit selection signal SC _0, inputs the input data selection signal SIA _0, SIB ₀ data It is given to the selection circuit 111A, and an output data selection signal SO applied ₀ to the output data selection circuit 311A, and an address signal AD ₀ and index modification signal IXS ₀ load instruction processing circuit 211A of the address signal input terminal
AD _A and an index modification signal input terminal IXS _A.

[0301] In the load instruction processing circuit 211A, an address signal AD ₀ is, is given to the data input terminal B of the adder ADD _A, from the input data selecting circuit 111A through the data input terminal D _ABIN the data input A The data is added to the given input data S _ABIN and output from the output terminal F.

[0302] Selector circuits SELT _A, the address signal without index modification signal IXS ₀ is response to be non-active (i.e. "0"), selects the output of the adder ADD _A
AD ₀ is selected, and is output from the address signal output terminal AD _AOUT to the data bus 15 as the address signal AD _ABS . Incidentally, the content of the address signal AD _ABS is "100" as apparent from Tables 1 and 2.

[0303] In the load instruction processing circuit 211A, a bus control signal generation circuit BCNTL _A is, generates a read signal READ _ABS, is output toward the data bus 15 from the bus control signal output terminal BCNT _AOUT.

[0304] data holding device 16, when via the data bus 15 the address signals AD _ABS and read signal READ _ABS given raw data DAT _ABS held in the corresponding "100" address to the address signal AD _ABS (That is, S _ABS ) and outputs it to the data bus 15.

Data bus for load instruction processing circuit 211A
15 unprocessed data DAT _ABS supplied from the data holding unit 16 via the (ie S _ABS) are applied to data input and output terminals D _A, data output via the data transfer circuit DTRF _A D
Output data S from _AOUT to output data selection circuit 311A
Output as _A.

The output data S _A output from the load instruction processing circuit 211A is given to the data input terminals of the selector circuits SELECT _{A1 to} SELT _A3 of the output data selection circuit 311A (see FIG. 3). Selector circuit SELT of output data selection circuit 311A
_At the other data input terminals of _{A1 to} SELECT _A3, the contents held by the register circuits RGS _{D1 to} RGS _D3 of the holding circuit 411D are input data S _D1.
It is given as ~S _D3.

In output data selection circuit 311A, control device 13
Output data selection signal given from instruction decoder 213A of
SO ₀ is decoded by the decoder DEC _A , and the decoding result is selected by the selection signal SO _A1
SOSO _A3 are given to the selection signal input terminals of the selector circuits SELECT _A1 SELSEL _A3 . Here, as is clear from Tables 1 and 2, the selection signal SO _A1 is active (ie, “1”),
The selection signals SO _A2 and SO _A3 are inactive (that is, “0”).

Since the selection signal SO _A1 is active (ie, “1”), the selector circuit SELT _A1 selects the output data S _A and outputs the output data S _{A1 to} the register circuit RGS _A1 of the holding circuit 411A. I do. Four

Since the selection signal SO _A2 is inactive (that is, “0”), the selector circuit SELECT _A2 selects the input data S _D2 and sends it as the output data S _{A2 to} the register circuit RGS _A2 of the holding circuit 411A. Output.

Since the selection signal SO _A3 is inactive (that is, “0”), the selector circuit SELECT _A3 selects the input data S _D3 and sends it as the output data S _{A3 to} the register circuit RGS _A3 of the holding circuit 411A. Output.

[0311] down counter DCNT _A, when the count content becomes "0", the write signal output terminal WT _A from the output terminal Q
A control signal generating circuit 313A and the processing pointer 513 of the write signal WT ₀ output is directed to the output data selection circuit 311A, and the processing end signal output terminal END via the _A processing end signal END ₀ the controller 13 via the Output to Incidentally, the subtraction operation time of the down counter DCNT _A is determined by a “constant” given to the data input terminal D, and consideration is given to ensuring a necessary time for processing the load instruction.

The register circuits RGS _{A1 to} RGS of the holding circuit 411A
In _A3, held output data S _A1 to S _A3 in response to the write signal WT ₀ provided from the load instruction processing circuit 211A, the input data S _A1 from the output terminal Q toward the load instruction processing circuit 211B to S _A3 Output as

[0313] In processing pointer 513 of the control unit 13, when the processing end signal END ₀ from the load instruction processing circuit 211A is provided, the output of the OR circuit OR ₅ becomes high level, the output "1" of the flip-flop FF ₅₀ flip It shifted to flop FF _51, and takes in the "0" to the flip-flop FF _50.
Therefore, the processing command signals PPQ _{0 to} PPQ ₃ are “0”, “1”, “0”, and “0”, respectively, as shown in Table 6.

In the control signal generation circuit 313A of the control device 13,
When the processing end signal END ₀ is given from the load instruction processing circuit 211A, the output of the OR circuit OR _3A1 becomes high level, and the held content of the constructed flag signal generation circuit CENDF _3A is cleared.
As shown in Table 6, the constructed flag signal CENDF ₀ output from the output terminal Q is inactive (that is, “0”). This is accompanied, the output or process start signal STRT ₀ of the AND circuit the AND _3A4, a non-active (i.e. "0").

In the control signal generation circuit 313A of the control device 13,
When a processing end signal END ₀ is given from the load instruction processing circuit 211A, “1” is taken into the processed flag signal generation circuit PENDF _3A , and the processed flag signal PENDF ₀ output from the output terminal Q is displayed. As shown in FIG. 6, it is active (that is, “1”). _Along with this, AND circuit AND _3A1
Indicates that the construction command signal CPQ ₀ is newly active (that is, “1”).
Then, the construction operation of a new arithmetic circuit is started in the same manner as described above.

In other words, the control signal generation circuit 313A of the control device 13 sends the processing end signal from the load instruction processing circuit 211A.
Until END ₀ is given, processed flag signal generation circuit PEND
"1" is not to be taken in F _3A, is processed flag signal PENDF ₀ being output from the output terminal Q is kept non-active as shown in Table 5 (i.e. "0").
Accordingly, the output of the AND circuit AND _3A1 becomes inactive.
(That is, “0”), and even if the construction command signal CPQ ₀ given from the construction pointer 413 becomes active (ie, “1”), the construction of the arithmetic circuit in the processing block 11A is stopped. I won't restart.

Processing in processing circuit 211B: Load instruction
Run

Load instruction processing circuit 21 of processing block 11B
When 1B is constructed, the processing command signal PPQ ₁ given from the processing pointer 513 becomes active, as is apparent from Table 7.
(I.e. "1") In addition to being so constructed flag signal CENDF ₁ is active (i.e. "1"), output or process start signal STRT ₁ of the AND circuit the AND _3B4 of the control signal generating circuit 313B includes active (i.e. "1"), and given to the process start signal input terminal STRT _B of the load instruction processing circuit 211B of the processing block 11B (see FIGS. 17, 21 and 23). By the way, the processed flag signal PENDF ₁ is shown in Table 7.
As is evident, the output of the AND circuit AND _3B1 of the control signal generation circuit 313B becomes inactive (ie, “0”) and the construction pointer
The construction command signal CPQ ₁ given from 413 is temporarily active.
Even if it becomes (1), the construction of the arithmetic circuit in the processing block 11B is not restarted. In other words, the construction of a new arithmetic circuit in the processing block 11B is prevented until the desired arithmetic processing (that is, the load instruction processing) is completed in the load instruction processing circuit 211B of the processing block 11B.

Load instruction processing circuit 21 of processing block 11B
In 1B, the processing start signal STRT ₁ given to the processing start signal input end STRT _B is applied to the load input end of the down counter DCNT _B.
This is given to the LD (see FIG. 23).

The down counter DCNT _B has a load input terminal LD.
When the processing start signal STRT ₁ is given, starts a subtraction operation captures "constants" are given to the data input terminal D to the inside.

[0321] Instruction decoder 213B of the controller 13, by decoding an instruction INST ₁ given from the instruction register 113B, after outputted a circuit selection signal SC _1, inputs the input data selection signal SIA _1, SIB ₁ data given to the selection circuit 111B, and an output data selection signal SO ₁ applied to the output data selection circuit 311B, and the address signal AD ₁ and index modification signals IXS ₁ load instruction processing circuit 211B of the address signal input terminal
They are respectively given to AD _B and index modification signal input IXS _B.

[0322] In the load instruction processing circuit 211B, address signals AD ₁ is, the adder ADD is given to the data input terminal B of _B, from the input data selecting circuit 111B through the data input terminal D _BBIN the data input A It is added to the given input data S _BBIN and output from the output terminal F.

[0323] Selector circuits SELT _B, the address signal without index modification signal IXS ₁ is according to a non-active (i.e. "0"), selects the output of the adder ADD _B
AD ₁ is selected and output from the address signal output terminal AD _BOUT to the data bus 15 as the address signal AD _BBS . Incidentally, the content of the address signal AD _BBS is "101" as apparent from Tables 1 and 2.

In the load instruction processing circuit 211B, the bus control signal generation circuit BCNTL _B generates a read signal READ _BBS and outputs it from the bus control signal output terminal BCNT _BOUT to the data bus 15.

[0325] data holding device 16, when via the data bus 15 the address signals AD _BBS and read signal READ _BBS given raw data DAT _BBS held in the corresponding "101" address to the address signal AD _BBS (That is, S _BBS ) and outputs it to the data bus 15.

Data bus for load instruction processing circuit 211B
15 raw data DAT _BBS provided from the data holding unit 16 via (i.e. S _BBS) is applied to data input and output terminals D _B, data output via the data transfer circuit DTRF _B D
Output data S from _BOUT to output data selection circuit 311B
Output as _B.

[0327] output data S _B is output from the load instruction processing circuit 211B, is given to the data input terminal of the selector circuit SELT _B1 ~SELT _B3 of the output data selection circuit 311B (see FIG. 4). Selector circuit SELT of output data selection circuit 311B
The other data input terminals of _{B1 to} SELECT _B3 receive the contents held by the register circuits RGS _{A1 to} REG _A3 of the holding circuit 411A as input data S _A1.
ＳS _A3 .

In output data selection circuit 311B, control device 13
Output data selection signal given from instruction decoder 213B of
SO ₁ is decoded by the decoder DEC _B , and the decoding result is selected by the selection signal SO _B1
SOSO _B3 are provided to the selection signal input terminals of the selector circuits SELECT _B1 SELSELT _B3 . Here, as is clear from Tables 1 and 2, the selection signal SO _B2 is active (ie, “1”).
Therefore, the selection signals SO _B1 and SO _B3 are inactive (ie, “0”).

Since the selection signal SO _B1 is inactive (that is, “0”), the selector circuit SELECT _B1 selects the output data S _A1 and sends it as the output data S _{B1 to} the register circuit RGS _B1 of the holding circuit 411B. Output.

[0330] The selector circuit SELT _B2, since the selection signal SO _B2 is active (i.e. "1"), input select data S _B, toward the register circuit RGS _B2 of the holding circuit 411B as the output data S _B2 output I do.

Since the selection signal SO _B3 is inactive (that is, “0”), the selector circuit SELECT _B3 selects the input data S _A3 and outputs it as output data S _{B3 to} the register circuit RGS _B3 of the holding circuit 411B. Output.

[0332] Down counter DCNT _B when the count content becomes "0", the write signal output terminal WT _B from the output terminal Q
A control signal generating circuit 313B and the processing pointer 513 of the write signal WT ₁ outputs directed to the output data selection circuit 311B to and process end signal output terminal END _B through the processing end signal END ₁ control unit 13 via the Output to Incidentally, the subtraction operation time of the down counter DCNT _B is determined by a “constant” given to the data input terminal D, and consideration is given to securing a time required for processing the load instruction.

Register circuits RGS _{B1 to} RGS of holding circuit 411B
In _B3, held output data S _B1 to S _B3 in response to the write signal WT ₁ given from the load instruction processing circuit 211B, the input data S from the output terminal Q toward the add instruction processing circuit 211C
It is output as _B1 ~S _B3.

[0334] In processing pointer 513 of the control unit 13, when the processing end signal END ₁ from the load instruction processing circuit 211B is supplied, the output of the OR circuit OR ₅ becomes high level, the output "0" of the flip-flop FF ₅₀ flip shifted to flop FF _51, and shifts the output "1" of the flip-flop FF ₅₁ to the flip-flop FF _52, and the flip-flop FF ₅₀
To "0". Therefore, the processing command signals PPQ _{0 to} PPQ
Q ₃ is, as shown in Table 8, each "0", "0",
They are "1" and "0".

In the control signal generation circuit 313B of the control device 13,
When the processing end signal END ₁ is given from the load instruction processing circuit 211B, the output of the OR circuit OR _3B1 becomes high level, and the contents held by the constructed flag signal generation circuit CENDF _3B are cleared.
Construction flag signal CENDF ₁ which is outputted from the output terminal Q and the non-active as shown in Table 8 (i.e. "0").
This is accompanied, output or process start signal STRT ₁ of the AND circuit the AND _3B4 becomes the non-active (i.e. "0").

In the control signal generation circuit 313B of the control device 13,
When a processing end signal END ₁ is given from the load instruction processing circuit 211B, “1” is taken into the processed flag signal generation circuit PENDF _3B , and the processed flag signal PENDF ₁ output from the output terminal Q is shown in Table 8. Active (ie, "1") as shown. Along with this, AND circuit AND
_3B1 is, that the build command signal CPQ ₁ becomes newly active (i.e. "1") the town, to start building operation of the new operation circuit in the same manner as described above.

In other words, in the control signal generation circuit 313B of the control device 13, the processing completion signal is sent from the load instruction processing circuit 211B.
Until END ₁ is given, processed flag signal generation circuit PEND
"1" is not to be taken in F _3B, the output end processing is output from the Q flag signal PENDF ₁ is maintained in a state of non-active as shown in Table 7 (that is, "0").
Accordingly, the output of the AND circuit AND _3B1 becomes inactive.
(Ie, “0”), and even if the construction command signal CPQ ₁ given from the construction pointer 413 becomes active (ie, “1”), the construction of the arithmetic circuit in the processing block 11B is stopped. I won't restart.

Processing in processing circuit 211C : execution of addition instruction
line

Addition instruction processing circuit 211C of processing block 11C
Is constructed, as is apparent from Table 9, the processing command signal PPQ ₂ given from the processing pointer 513 is active (ie, “1”), and the constructed flag signal CE
Since the NDF ₂ is active (ie, “1”), the output of the AND circuit AND _3C4 of the control signal generation circuit 313C, that is, the processing start signal STRT ₂ becomes active (ie, “1”), and the addition instruction processing of the processing block 11C is performed. It is given to the processing start signal input terminal STRT _C circuit 211C (see FIGS. 18, 21 and 24). Incidentally, since the processed flag signal PENDF ₂ is inactive (that is, “0”) as apparent from Table 9, the output of the AND circuit AND _3C1 of the control signal generation circuit 313C is inactive (that is, “0”). ) And the construction pointer 41
Even if the construction command signal CPQ ₂ given from 3 becomes active (ie, “1”), the construction of the arithmetic circuit in the processing block 11C is not restarted. In other words, the desired arithmetic processing is performed by the load instruction processing circuit 211C of the processing block 11C.
Until the end of the load instruction processing, a new arithmetic circuit is prevented from being built in the processing block 11C.

Addition instruction processing circuit 211C of processing block 11C
Then, the processing start signal STRT ₂ given to the processing start signal input terminal STRT _C is changed to the load input terminal LD of the down counter DCNT _C.
(See FIG. 24).

The down counter DCNT _C has a load input terminal LD.
When the processing start signal STRT ₂ is supplied to the input terminal, the “constant” supplied to the data input terminal D is taken in and the subtraction operation is started.

[0342] Instruction decoder 213C of control device 13, by decoding an instruction INST ₂ given from the instruction register 113C, after outputted a circuit selection signal SC _2, inputs the input data selection signal SIA _2, SIB ₂ data It is given to the selection circuit 111C, and has given the output data selection signal SO ₂ to the output data selection circuit 311C.

[0343] In addition the instruction processing circuit 211C, the adder ADD _C of the data input A through the data input terminal D _{CA IN} given input data S _CAIN from the input data selection circuit 111C, and the data to the data input terminal B The input data S _CBIN is given from the input data selection circuit 111C via the input terminal D _CBIN, and after being added to each other, from the output terminal F to the data output terminal D _CBIN.
Output data S to output data selection circuit 311C via _COUT
Output as _C.

The output data S _C output from the addition instruction processing circuit 211C is output to the selector circuit of the output data selection circuit 311C.
This is given to the data input terminals of SELT _{C1 to} SELT _C3 (Fig. 5
See). Selector circuit SELECT _C1 of output data selection circuit 311C
To the other data input terminals of ~ SELT _C3 , the held contents of the register circuits RGS _B1 ~ REG _B3 of the holding circuit 411B are input data S _B1 ~
Given as _SB3 .

In output data selection circuit 311C, control device 13
Output data selection signal given from the instruction decoder 213C of
SO ₂ is decoded by the decoder DEC _C , and the decoding result is selected by the selection signal SO _C1
Giving the selection signal input terminal of the selector circuit SELT _C1 ~SELT _C3 as to SO _C3 city. Here, as is evident in Table 1 and Table 2, the selection signal SO _C1 active (i.e. "1")
Therefore, the selection signals _SOC2 and _SOC3 are inactive (that is, "0").

[0346] The selector circuit SELT _C1, since the selection signal SO _C1 is active (i.e. "1"), the output select data S _C, toward the holding circuit 411C of the register circuit RGS _C1 as the output data S _C1 output I do.

[0347] The selector circuit SELT _C2 is chosen because the signal SO _C2 is non-active (i.e. "0"), selects the input data S _B2, towards the holding circuit register circuit 411C RGS _C2 as output data S _C2 Output.

[0348] The selector circuit SELT _C3 is chosen because the signal SO _C3 is non-active (i.e. "0"), the input select data S _C3, towards the register circuit RGS _C3 of the holding circuits 411C as output data S _C3 Output.

[0349] Down counter DCNT _C when the counted content becomes "0", the write signal output terminal WT _C from an output terminal Q
And outputs the write signal WT ₂ to the output data selection circuit 311C through the control signal generator 313 and the processing end signal END ₂ to the control signal generating circuit 313C and the processing pointer 513 of the controller 13 through the processing end signal output terminal END _C. Output to Incidentally, the subtraction operation time of the down counter DCNT _C is determined by a “constant” given to the data input terminal D, and consideration is given to securing a time required for processing the addition instruction.

Register circuits RGS _{C1 to} RGS of holding circuit 411C
In _C3, the addition instruction processing circuit is output data S _C1 to S _C3 in response to the write signal WT ₂ given retention from 211C, the input data S _C1 ~ towards the load effective address instruction processing circuit 211D from the output terminal Q and outputs it as the S _C3.

[0351] In processing pointer 513 of the control unit 13, when the processing end signal END ₂ provided from the addition instruction processing circuit 211C, the output of the OR circuit OR ₅ becomes high level, the output "0" of the flip-flop FF ₅₀ flip shifted to flop FF _51, and shifts the output "0" of the flip-flop FF ₅₁ to the flip-flop FF _52, and the flip-flop FF ₅₂
Shifting the output "1" to the flip-flop FF _53, and takes in the "0" to the flip-flop FF _50. For this reason,
The processing command signals PPQ _{0 to} PPQ ₃ are “0”, “0”, “0”, and “1”, respectively, as shown in Table 10.

In the control signal generation circuit 313C of the control device 13,
When the processing end signal END ₂ is given from the addition instruction processing circuit 211C, the output of the OR circuit OR _3C1 becomes high level, the held content of the constructed flag signal generation circuit CENDF _3C is cleared, and the output is output from the output terminal Q. construction flag signal CENDF ₂ and non-active as shown in Table 10 (that is, "0").
This is accompanied, output or process start signal STRT ₂ of the AND circuit the AND _3C4 becomes a non-active (i.e. "0").

In the control signal generation circuit 313C of the control device 13,
When the processing end signal END ₂ is given from the addition instruction processing circuit 211C, “1” is taken into the processed flag signal generation circuit PENDF _3C , and the processed flag signal PENDF ₂ output from the output terminal Q is shown in Table 10. Active (ie, "1") as shown. Along with this, AND circuit AND
_3C1 is that the build command signal CPQ ₂ becomes newly active (i.e. "1") the town, to start building operation of the new operation circuit in the same manner as described above.

In other words, the control signal generation circuit 313C of the control device 13 sends the processing end signal from the load instruction processing circuit 211C.
Until END ₂ is given, processed flag signal generation circuit PEND
"1" is not to be taken in F _3C, is processed flag signal PENDF ₂ being output from the output terminal Q is kept non-active as shown in Table 9 (i.e. "0").
Accordingly, the output of the AND circuit AND _3C1 becomes inactive.
(Ie, “0”), and even if the construction command signal CPQ ₂ given from the construction pointer 413 becomes active (ie, “1”), the construction of the arithmetic circuit in the processing block 11A is continued. I won't restart.

Processing in Processing Circuit 211D: Load Effective A
Execution of dress instruction

When the load effective address instruction processing circuit 211D of the processing block 11D is constructed, the processing instruction signal PPQ ₃ given from the processing pointer 513 is active (ie, “1”), as is apparent from Table 11. In addition, since the constructed flag signal CENDF ₃ is active (ie, “1”), the output of the AND circuit AND _3D4 of the control signal generation circuit 313D, that is, the processing start signal STRT ₃ becomes active (ie, “1”). , given to the process start signal input terminal STRT _D of the load effective address instruction processing circuit 211D of the processing block 11D (see FIG. 19, FIGS. 21 and 25). Incidentally, since the processed flag signal PENDF ₃ is inactive (that is, “0”) as apparent from Table 11, the output of the AND circuit AND _3D1 of the control signal generation circuit 313D is inactive (ie, “0”). Thus, even if the construction command signal CPQ ₃ given from the construction pointer 413 becomes active (that is, “1”), the construction of the arithmetic circuit in the processing block 11D is not restarted. Until the desired arithmetic processing (that is, load instruction processing) is completed in the load effective address instruction processing circuit 211D, the processing block
Prevents new arithmetic circuits from being built in 11D.

[0357] At processing block 11D of the load effective address instruction processing circuit 211D, the process start signal STRT ₃ given to the processing start signal input terminal STRT _D, it is given to the load input LD of the down counter DCNT _D (FIG. 25).

The down counter DCNT _D is a load input terminal LD.
When the process start signal STRT ₃ given, starts a subtraction operation captures "constants" are given to the data input terminal D to the inside.

[0359] Instruction decoder 213D of the control unit 13, by decoding an instruction INST ₃ given from the instruction register 113D, after outputted a circuit selection signal SC _3, inputs the input data selection signal SIA _3, SIB ₃ data given to the selection circuit 111D, and the output data selection signal SO gives ₃ to the output data selection circuit 311D, and the address signal AD ₃ and index modification signal address signal input terminal AD _D and index of IXS ₃ load effective address instruction processing circuit 211D Modification signal input IX
Give to _SD respectively.

[0360] In the load effective address instruction processing circuit 211D, an address signal AD _3, the data input terminal of the adder ADD _D B
To the data input terminal A and the data input terminal D
_The data is added to the input data S _DBIN given from the input data selection circuit 111D via _DBIN, and output from the output terminal F.

[0361] The selector circuit SELT _D, the address signal without the index modification signal IXS ₃ according to a non-active (i.e. "0"), selects the output of the adder ADD _D
Select AD _3, the data output terminal D as the output data S _D
The data is output from _DOUT to the output data selection circuit 311D. Incidentally, the address signal AD ₃ are as evident in Table 1 and Table 2 "1".

Output data _SD output from load effective address instruction processing circuit 211D is output data selection circuit 311D.
Are given to the data input terminal of the selector circuit SELT _D1 ~SELT _D3 (FIG. 6A, see Fig. 6B). Output data selection circuit
The contents held by the register circuits RGS _{C1 to} REG _C3 of the holding circuit 411C are given as input data S _{C1 to} S _{C3 to} the other data input terminals of the selector circuits SELECT _{D1 to} SELT _D3 of 311D.

In output data selection circuit 311D, control device 13
Output data selection signal given from the instruction decoder 213D of
SO ₃ is decoded by the decoder DEC _D , and the decoding result is selected by the selection signal SO _D1
Giving the selection signal input terminal of the selector circuit SELT _D1 ~SELT _D3 as to SO _D3 city. Here, as is clear from Tables 1 and 2, the selection signal _SOD1 is active (that is, "1").
_Therefore , the selection signals _SOD2 and _SOD3 are inactive (that is, "0").

[0364] The selector circuit SELT _D1, since the selection signal SO _D1 is active (i.e. "1"), the output select data S _D, toward the register circuit RGS _D1 of the holding circuit 411D as output data S _D1 output I do.

[0365] The selector circuit SELT _D2 is chosen because the signal SO _D2 is non-active (i.e. "0"), selects the input data S _C2, toward the register circuit RGS _D2 of the holding circuit 411D as output data S _D2 Output.

[0366] The selector circuit SELT _D3, since the selection signal SO _D3 is non-active (i.e. "0"), the input select data S _C3, towards the register circuit RGS _D3 of the holding circuit 411D as output data S _D3 Output.

When the count value becomes "0", the down counter DCNT _D switches from the output terminal Q to the write signal output terminal WT _D
And outputs the write signal WT ₃ to the output data selection circuit 311D via the control signal generator 313D and the processing end signal END ₃ via the processing end signal output terminal END _D to the control signal generating circuit 313D and the processing pointer 513 of the controller 13. Output to Incidentally, the subtraction operation time of the down counter DCNT _D is determined by a “constant” given to the data input terminal D, and consideration is given to securing a time required for processing the load effective address instruction.

Register circuits RGS _{D1 to} RGS of holding circuit 411D
_{At D3} , the output data S _{D1 to} S _D3 are held in accordance with the write signal WT ₃ given from the load effective address instruction processing circuit 211D, and the arithmetic terminal shift instruction processing circuit 211A is output from the output terminal Q.
Are output as input data S _{D1 to} S _D3 .

At the processing pointer 513 of the control device 13, the processing end signal END _{3 is} output from the load effective address instruction processing circuit 211D.
When given, the output of the OR circuit OR ₅ becomes high level, and shifts the output "0" of the flip-flop FF ₅₀ to the flip-flop FF _51, and the output "0" of the flip-flop FF ₅₁ to the flip-flop FF ₅₂ shift, and shifts the output "0" of the flip-flop FF ₅₂ to the flip-flop FF _53, and shifts the output "1" of the flip-flop FF ₅₃ to the flip-flop FF _50. Therefore, the processing command signals PPQ _{0 to} PPQ ₃ are “1”, “0”, “0”, and “0”, respectively, as shown in Table 12.

In the control signal generation circuit 313D of the control device 13,
Processing end signal from load effective address instruction processing circuit 211D
When END ₃ is given, the output of the OR circuit OR _3D1 becomes high level, the contents held in the constructed flag signal generation circuit CENDF _3D are cleared, and the constructed flag signal CENDF ₃ outputted from the output terminal Q is displayed in Table 12. Is inactive (ie, “0”) as shown in FIG. This is accompanied, the output or process start signal STRT ₃ AND circuit the AND _3D4, an inactive (i.e. "0").

In the control signal generation circuit 313D of the control device 13,
Processing end signal from load effective address instruction processing circuit 211D
When END ₃ is given, the processed flag signal generation circuit PENDF
“1” is taken into _3D, and the processed flag signal PENDF ₃ output from the output terminal Q is activated as shown in Table 12.
(That is, “1”). _Along with this, the AND circuit AND _{3D1 waits} for the construction command signal CPQ _{3 to} become newly active (ie, “1”), and starts the construction operation of a new arithmetic circuit in the same manner as described above.

In other words, in the control signal generation circuit 313D of the control device 13, “1” is taken into the processed flag signal generation circuit PENDF _3D until the processing end signal END ₃ is given from the load effective address instruction processing circuit 211D. Without being
Is processed flag signal PENDF ₃ being output from the output terminal Q is kept non-active as shown in Table 11 (that is, "0"). Accordingly, the output of the AND circuit AND _3D1 is maintained in an inactive (ie, “0”) state, and the construction command signal given from the construction pointer 413 is output.
Even if CPQ ₃ becomes active (that is, “1”), the construction of the arithmetic circuit in the processing block 11D is not restarted.

Processing in processing circuit 211A: arithmetic left shift
Execution of instruction

When the arithmetic left shift instruction processing circuit 211A of the processing block 11A is constructed, as is apparent from Table 13,
Processing command signal PPQ ₀ given from processing pointer 513
Is active (ie, “1”) and the constructed flag signal CENDF ₀ is active (ie, “1”),
Control signal output or process start signal STRT ₀ generation circuit 313A of the AND circuit the AND _3A4 is active (i.e., "1"), and the arithmetic left shift instruction processing circuit 211A of the processing blocks 11A
It is given to the process start signal input terminal STRT _A (see FIGS. 16, 21 and 26). By the way, the processed flag signal
Since PENDF ₀ is inactive (that is, “0”) as apparent from Table 13, the output of the AND circuit AND _3A1 of the control signal generation circuit 313A becomes inactive (that is, “0”), and the construction pointer 413 Even if the construction command signal CPQ ₀ given by the processor becomes active (ie, “1”), the construction of the arithmetic circuit in the processing block 11A is not restarted. In other words, the construction of a new arithmetic circuit in the processing block 11A is prevented until the required arithmetic processing (ie, arithmetic left shift instruction processing) is completed in the arithmetic left shift instruction processing circuit 211A of the processing block 11A.

In the arithmetic left shift instruction processing circuit 211A of the processing block 11A, the processing start signal STRT _{0 applied} to the processing start signal input terminal STRT _A is applied to the load input terminal LD of the shift register SR _A. 26).

[0376] The shift register SR _A, when the processing start signal STRT ₀ provided to the load input LD, a data input terminal D
Input data selection circuit 111A via data input terminal D _AAIN
The first to fifteenth bits of the input data S _AAIN given from the internal memory are taken in.

[0377] Instruction decoder 213A of the controller 13, by decoding an instruction INST ₀ given from the instruction register 113A, after outputted a circuit selection signal SC _0, inputs the input data selection signal SIA _0, SIB ₀ data It is given to the selection circuit 111A, and has given the output data selection signal SO ₀ to the output data selection circuit 311A.

In the arithmetic left shift instruction processing circuit 211A, the data input terminal D _{AAIN is connected} to the data input terminal D of the shift register SR _A.
From the input data selection circuit 111A through the input data S _AAIN
And the data input terminal D is connected to the shift input terminal SFT.
Input data S from input data selection circuit 111A via _ABIN
ABIN is provided, and the first to fifteenth bits of the input data S _{AAIN fetched} from the data input terminal D are _shifted in accordance with the input data S _{ABIN supplied} to the shift input terminal SFT, Output and input data S
The 16th bit of _AAIN is added, and output from the data output terminal D _AOUT to the output data selection circuit 311A as output data S _A.

The output data S _A output from the arithmetic left shift instruction processing circuit 211A is given to the data input terminals of the selector circuits SELECT _{A1 to} SELECT _A3 of the output data selection circuit 311A (see FIG. 3). The other data input terminals of the selector circuits SELT _{A1 to} SELT _A3 of the output data selection circuit 311A are connected to the holding circuit 41.
The contents held in the 1D register circuits RGS _{D1 to} REG _D3 are given as input data S _{D1 to} S _D3 .

In the output data selection circuit 311A, the control device 13
Output data selection signal given from instruction decoder 213A of
SO ₀ is decoded by the decoder DEC _A , and the decoding result is selected by the selection signal SO _A1
SOSO _A3 are given to the selection signal input terminals of the selector circuits SELECT _A1 SELSEL _A3 . Here, as is clear from Tables 1 and 2, the selection signal SO _A1 is active (ie, “1”).
And the selection signals SO _A2 and SO _A3 are inactive (ie, “0”).

Since the selection signal SO _A1 is active (ie, “1”), the selector circuit SELECT _A1 selects the output data S _A and outputs the output data S _{A1 to} the register circuit RGS _A1 of the holding circuit 411A. I do.

Since the selection signal SO _A2 is inactive (that is, “0”), the selector circuit SELECT _A2 selects the input data S _D2 and sends it as the output data S _{A2 to} the register circuit RGS _A2 of the holding circuit 411A. Output.

Since the selection signal SO _A3 is inactive (that is, “0”), the selector circuit SELECT _A3 selects the input data S _D3 and outputs it as output data S _{A3 to} the register circuit RGS _A3 of the holding circuit 411A. Output.

[0384] The shift register SR _A, after having sent an output from the output terminal F, the output data selection circuit a write signal WT ₀ from processing end signal output terminal END through write signal output terminal WT _A
311A, and outputs a processing end signal END ₀ via the processing end signal output terminal END _A to the control signal generation circuit 31 of the controller 13.
Output to 3A and processing pointer 513.

Register circuits RGS _{A1 to} RGS of holding circuit 411A
_{At A3} , the output data S _{A1 to} S _A3 are held in response to the write signal WT ₀ given from the arithmetic left shift instruction processing circuit 211A, and the input data S _A1 to S _A1 to S ₃ are output from the output terminal Q to the store instruction processing circuit 211B. and outputs it as the S _A3.

[0386] In processing pointer 513 of the control unit 13, when the processing end signal END ₀ provided from the arithmetic left shift instruction processing circuit 211A, the output of the OR circuit OR ₅ goes high, the output of the flip-flop FF ₅₀ "1" The flip-flop FF ₅₁
It shifted to, and take in the "0" to the flip-flop FF _50. Therefore, as shown in Table 14, the processing command signals PPQ _{0 to} PPQ ₃ are “0”, “1”, “0”,
It becomes “0”.

In the control signal generation circuit 313A of the control device 13,
When the processing end signal END ₀ is given from the arithmetic left shift instruction processing circuit 211A, the output of the OR circuit OR _3A1 becomes high level, the held content of the constructed flag signal generation circuit CENDF _3A is cleared, and the output is output from the output terminal Q. Built flag signal
CENDF ₀ is inactive (that is, “0”) as shown in Table 14. This is accompanied, the output or process start signal STRT ₀ of the AND circuit the AND _3A4, a non-active (i.e. "0").

The control signal generation circuit 313A of the control device 13
When a processing end signal END ₀ is given from the arithmetic left shift instruction processing circuit 211A, “1” is taken into the processed flag signal generation circuit PENDF _3A , and the processed flag signal PENDF ₀ output from the output terminal Q is displayed. As shown in FIG. 14, it is active (that is, "1"). Along with this, AND circuit AND _3
A1 is that the build command signal CPQ ₀ becomes newly active (i.e. "1") the town, to start building operation of the new operation circuit in the same manner as described above.

[0389] In other words, the control signal generating circuit 313A of the controller 13, the arithmetic left shift instruction processing circuit 211A until the process end signal END ₀ given, the processed flag signal generating circuit PENDF _3A "1" is taken The processed flag signal PENDF ₀ output from the output terminal Q is
As shown in (1), it is maintained in an inactive state (ie, "0"). Accordingly, the output of the AND circuit AND _3A1 is
Even if the construction command signal CPQ ₀ given from the construction pointer 413 becomes active (ie, “1”), the processing block
Does not restart the construction of the arithmetic circuit in 11A.

Processing in processing circuit 211B: Store instruction
Run

Store instruction processing circuit 21 of processing block 11B
When 1B is constructed, the processing command signal PPQ ₁ given from the processing pointer 513 becomes active as is apparent from Table 15.
(I.e. "1") In addition to being so constructed flag signal CENDF ₁ is active (i.e. "1"), output or process start signal STRT ₁ of the AND circuit the AND _3B4 of the control signal generating circuit 313B includes active (i.e. "1"), and (see FIGS. 21 and and 17 27) applied to the process start signal input terminal STRT _B store instruction processing circuit 211B of the processing block 11B.

[0392] Store instruction processing circuit 21 of processing block 11B
In 1B, the processing start signal STRT ₁ given to the processing start signal input end STRT _B is applied to the load input end of the down counter DCNT _B.
This is given to the LD (see FIG. 27).

The down counter DCNT _B is connected to the load input terminal LD.
When the processing start signal STRT ₁ is given, starts a subtraction operation captures "constants" are given to the data input terminal D to the inside.

The instruction decoder 213B of the control device 13
Instruction INST given from the register 113B ₁ To decrypt
Circuit selection signal SC₁ Output, and then select the input data.
Select signal SIA₁, SIB₁ To the input data selection circuit 111B,
Address signal AD₁ And index modification signal IXS₁To
Address signal input terminal AD of store instruction processing circuit 211B_B And
IXS_BTo each
You.

[0395] In the store instruction processing circuit 211B, the input data S _BAIN the relative data input D _BAIN are given from the input data selection circuit 111B is already processed data via the data transfer circuit DTRF _B from the data output terminal D _B The data is output to the data bus 15 as DAT _BBS ^* (that is, S _BBS ^* ).

[0396] In the store instruction processing circuit 211B, address signals AD ₁ is, the adder ADD is given to the data input terminal B of _B, from the input data selecting circuit 111B through the data input terminal D _BBIN the data input A The input data S _BBIN is added to the given input data and output from the output terminal F.

[0397] Selector circuits SELT _B, the address signal without index modification signal IXS ₁ is according to a non-active (i.e. "0"), selects the output of the adder ADD _B
AD ₁ is selected and output from the address signal output terminal AD _BOUT to the data bus 15 as the address signal AD _BBS . Incidentally, the address signal AD _BBS is "102" as apparent from Tables 1 and 2.

[0398] In the store instruction processing circuit 211B, a bus control signal generation circuit BCNTL _B is, generates a write signal WT _{BB S,} is output toward the data bus 15 from the bus control signal output terminal BCNT _BOUT.

When the address signal AD _BBS and the write signal WT _BBS are applied via the data bus 15, the data holding device 16 stores the processed data DAT _BBS ^* (at address 102) corresponding to the address signal AD _BBS. That is, S _BBS ^* ) is written and held.

[0400] down counter DCNT _B, when the count content becomes "0", the processing end signal output terminal from the output terminal Q
Output is directed to the control signal generating circuit 313B and the processing pointer 513 of the processing end signal END ₂ the control device 13 via the END _B.
Incidentally, the subtraction operation time of the down counter DCNT _B is determined by a "constant" given to the data input terminal D, and consideration is given to securing a time required for processing the store instruction.

[0401] In processing pointer 513 of the control unit 13, the store instruction processing circuit 211B from the processing end signal END ₂ is supplied, the output of the OR circuit OR ₅ becomes high level, the output "0" of the flip-flop FF ₅₀ flip shifted to flop FF _51, and shifts the output "1" of the flip-flop FF ₅₁ to the flip-flop FF _52, and the flip-flop FF ₅₀
To "0". Therefore, the processing command signals PPQ _{0 to} PPQ
As shown in Table 16, Q ₃ is “0”,
They are "0", "1", and "0".

[0402] In the control signal generation circuit 313B of the control device 13,
When the processing end signal END ₂ is given from the store instruction processing circuit 211B, the output of the OR circuit OR _3B1 becomes high level, and the held content of the constructed flag signal generation circuit CENDF _3B is cleared.
Construction flag signal CENDF ₂ being output from the output terminal Q and the non-active as shown in Table 16 (that is, "0"). This is accompanied, output or process start signal STRT ₂ of the AND circuit the AND _3B4 becomes the non-active (i.e. "0").

In the control signal generation circuit 313B of the control device 13,
When the processing end signal END ₁ is given from the store instruction processing circuit 211B, “1” is taken into the processed flag signal generation circuit PENDF _3B , and the processed flag signal PENDF ₁ output from the output terminal Q is shown in Table 16. Active (ie, "1") as shown. Along with this, AND circuit AND
_3B1 is, that the build command signal CPQ ₁ becomes newly active (i.e. "1") the town, to start building operation of the new operation circuit in the same manner as described above.

As described above, the computer of the first embodiment
According to the data processing blocks 11A, 11B, 11C, 1
Computer space with four 1D processing blocks
In this case, for example, during a certain time Δt (n), the block 11A
And the block 11D independently of the logic
Rewriting is performed, and in block 11B, the time Δt
The logic already written at the rising timing Δt (n−1)
The addition operation is performed based on the
Already written at the preceding timing Δt (n−1)
A subtraction operation is performed based on the logic. And this Δ
At the next timing Δt (n + 1) after t (n),
Prior to the logic already written in Δt (n),
Block 11A and block 11D are
By performing the above processing, block 11B and block 11C
Will be executed at the next timing Δt (n + 2).
Operation that can be rewritten to logic, respectively.
U ... each processing block connected in an annular shape
Is rewritten and the circle is changed while changing the arithmetic circuit itself.
It moves in a ring (in an orbit). Such a configuration
And the movement of command words and data
Routes can be separated from each other and waiting for job execution
Speed up processing by eliminating waste of processing time such as time
Can be achieved. However, for example,
FPL with program arrays arranged in a matrix
A (field programmable logic array)
In such a case, a finite number of arrays are arranged vertically and horizontally
The number of arrays is at least
Number of required processing steps or processing sequences
Is always necessary and must be processed for all of those arrays.
It is practically impossible to rewrite logical logic at once
So, for example, scan selective writing for each array
It is necessary to perform
It takes time to process
It was difficult or impossible to achieve the improvement in the world.

(Configuration of the Second Embodiment)

Also, referring to FIGS. 29 to 54,
Regarding a second embodiment of the computer according to the present invention,
The configuration will be described in detail. Here, for the purpose of simplifying the description, the case where the program shown in Table 17 is executed
A description will be given mainly of a case where a load instruction, a load instruction, an addition instruction, an arithmetic left shift instruction and a store instruction are sequentially executed, but the present invention is not limited thereto.

[0407] Overall configuration (see Fig. 29)

Reference numeral 20 denotes a computer according to the present invention, and an appropriate number (here, “four”) of processing blocks 21 A
A processing device for executing the program while sequentially constructing (selecting) the arithmetic circuits required for executing the program in the processing blocks 21A to 21D.
Has 21,

[0409] The computer 20 according to the present invention also includes:
First to fourth input / output terminals (specifically, the instruction decoder 22
Second to sixth output terminals of 3A to 223D and control signal generation circuit
323A to 323D, second to fourth output terminals and third input terminals, and first to fourth input terminals of the processing pointer 523) are input / output terminals (specifically, input data) of the processing blocks 21A to 21D. (The first and second input terminals of the selection circuits 121A to 121D and the first to third input terminals and the third output terminals of the processing circuits 221A to 221D).
A control unit 23 for sequentially constructing (selecting) necessary arithmetic circuits in 21D as described later and monitoring the arithmetic processing in the processing blocks 21A to 21D, and an input terminal of the control unit 23 (specifically, an instruction The output terminals are connected to the first input terminals of the registers 123A to 123D, and the input terminal (specifically, the address input terminal) is connected to the fifth output terminal (specifically, the program counter 623) of the controller 23. Output terminal), and holds a program for controlling the control device 23 (and, consequently, a program for the arithmetic processing in the processing blocks 21A to 21D of the processing device 21), and in accordance with a request from the control device 23, And a program holding device 24 for outputting the data toward 23.

[0410] The computer 20 according to the present invention further comprises:
Input / output terminals of processing blocks 21A to 21D of processing device 21 (specifically, address signal output terminals AD _AOUT of processing circuits 221A to 221D)
To AD _DOUT, and transferring the raw data to the processing blocks 21A ～21D of bus control signals output BCNT _AOUT ~BCNT _DOUT and data input and output terminals D _A to D _D) process is connected to the apparatus 21 Processing blocks 21A to 21D of the processing device 21
A data bus 25 for receiving processed data from the data bus 25, an input / output terminal connected to the data bus 25, a data holding device 26 for holding unprocessed data and processed data, and a data bus 25. The data input / output terminals are connected to each other, and the unprocessed data held in the data holding device 26 is received in advance from an external device (not shown) via the data bus 25, and is then sent to the data holding device 26 via the data bus 25. An input / output device 27 is provided for receiving processed data provided and held in the data holding device 26 via the data bus 25 and then sending the processed data to an external device (not shown). Incidentally, the input / output device 27 is a reset for generating a reset signal used in the control device 23 (specifically, the control signal generation circuits 323A to 323D, the construction pointer 423, the processing pointer 523, and the program counter 623). A signal source (not shown) is built in and generates a reset signal when power is turned on and when a reset button is pressed.

[0411]Configuration of Processing Unit 21 (see FIGS. 29 to 37B)
See)

[0412] For convenience of explanation, the processing device 21 is
It is assumed that the processing block is composed of one processing block 21A to 21D, but the present invention is not limited to this, and includes all processing blocks composed of a plurality of processing blocks.

The processing blocks 21A to 21D include, for example, arithmetic circuits (here, a load instruction processing circuit, a store instruction processing circuit, a load effective address instruction processing circuit, an addition instruction processing circuit, and an arithmetic left shift circuit) required to execute a program. Instruction processing circuit) to build the appropriate number (for example,
10000 gate circuits (for example, an appropriate number of exclusive OR circuits, an appropriate number of AND circuits, an appropriate number of OR circuits, and an appropriate number of NAND circuits) are appropriately connected through an appropriate number of changeover switches. (For example, in a matrix) by a field programmable gate array FPGA or the like. The field programmable gate array FPGA includes, for example, two exclusive OR circuits EXOR ₁ and EXOR ₂ and two AND circuits AND ₁ and AND
₂ and 2 OR circuits OR ₁ , OR ₂ and 3 NAND circuits NAND ₁
~ NAND ₃ and 20 crosspoint switches CSW ₁₁ ~ CS
W ₁₄ ; ・ ・ ・; CSW _{51 to} CSW ₅₄ and 22 disconnection switch SW ₁₁₁₂
It may be created by arranging them in a matrix through SW ₄₄₅₄ (see FIGS. 2A and 2B). Incidentally, the cross-point switch _{CSW 11 ~CSW 14; ···; CSW} 51 ~CSW 54 and disconnect switch SW ₁₁₁₂ to SW ₄₄₅₄ is constituted by arranging the switch appropriately.

Processing block 21A (FIGS. 30A, 30B,
(See FIGS. 34A and 34B)

The processing block 21A of the processing device 21
The second input terminal is the second input terminal of the instruction decoder 223A of the controller 23.
The input data S _D1 to S _D1 ... Applied to the third to fifth input terminals according to the input data selection signals SIA ₀ and SIB ₀ supplied from the instruction decoder 223A of the control device 23 and connected to the third output terminal. S _D3 from selecting a desired input data the data output terminal D _AAOUT, D _ABOUT input data from the S _AAIN, and the input data selecting circuit 121A for outputting as S _ABIN, the data input D _AAIN the input data selecting circuit 121A Data output terminal D
Instruction decoder coupled to _AAOUT and data input D _ABIN is connected to the data output terminal D _ABOUT input data selection circuit 121A and the circuit selection signal input terminal SC _A control device 23 223A
And a processing start signal input terminal STRT
Connected to a second and the address signal input terminal AD _A to the output terminal is connected to a sixth output of the instruction decoder 223A of the control unit 23 and the index modification signal input terminal of the control signal generation circuit 323A of _A controller 23 IXS _A is the instruction decoder of controller 23
223A is connected to the fifth output terminal and is a processing end signal output terminal.
END _A is connected to the third input terminal of the control signal generating circuit 323A of the control device 23 and the first input terminal of the processing pointer 523, and the address signal output terminal AD _AOUT is connected to the data bus 25 and the bus control signal output terminal. end BCNT _AOUT the selected control device the desired operation circuit according to the circuit selection signal SC ₀ provided from the data bus 25 connected to and data output terminals D _a are controlled device connected to the data bus 25 23 The input data S _AAIN , S _{ABIN supplied} from the input data selection circuit 121A or the _unprocessed data _supplied from the data bus 25 according to the processing start signal STRT ₀ , address signal AD ₀ , and index modification signal IXS ₀ provided from ₂₃ . processing circuit for outputting data S _ABS as appropriate to the process to the first output terminal (i.e. data output D _AOUT) or the output from the data output terminal D _a data S _a or already processed data S _ABS ^* 221A , First to third input terminal connected to the first output of the processing circuit 221A (i.e. data output terminal D _{AO UT)} of and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 421D (that is, the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ), and the seventh input terminal is connected to the instruction decoder 223A of the controller 23. A control device connected to the fourth output end;
Output data S _A and the register circuit RG fourth to hold circuit 421D to the input terminal of the sixth processing circuit 221A in response to the output data selection signal SO ₀ given from 23 of the instruction decoder 223A
Input data S _D1 to S _D1 given from S _{D1 to} RGS _D3 , respectively.
An output data selection circuit 321A for selecting desired data from S _D3 and outputting it as output data S _{A1 to} S _A3 from first to third data output terminals, and writing to a second output terminal of processing circuit 221A Signal input terminals (that is, register circuits RGS _{A1 to} RG
A write signal input terminal WT of S _A3 is connected to each of the first to third data output terminals of the output data selection circuit 321A.
The data input terminals D) of the RGS _{A1 to} RGS _A3 are connected to each other, and the output data S _{A1 to} S _A3 given from the output data selection circuit 321A are written into the write signal WT given from the processing circuit 221A.
A holding circuit 421A for holding the register circuits RGS _{A1 to} RGS _A3 according to ₀ is included.

In the input data selection circuit 121A, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 421D (that is, the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ). connected and controlled input control unit 23 and the second register circuit of the holding circuit 421D according to the input data selection signal SIA ₀ provided from the instruction decoder 223A outputs connected to and control the end 23 of the instruction decoder 223A of RGS _D1 input given from ～RGS _D3 data S _D1 to S _D3
And a selector circuit SEL _A1 for selecting one of them and outputting it from the data output terminal D _AAOUT, and a first to third data output terminal of the holding circuit 421D for the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{D1 to} RGS _D3 ) and the control input terminal is connected to the third output terminal of the instruction decoder 223A of the control device 23. register circuits holding circuit 421D according to the input data selection signal SIB ₀ given RGS _D1 ~
A selector circuit SEL _A2 for selecting one of the input data S _{D1 to} S _D3 given from RGS _{D 3} and outputting it from the data output terminal D _ABOUT is included.

The processing circuit 221A first sets the data input terminal D
_BIN is input data selection circuit via data input terminal D _ABIN
121A is connected to the data output terminal D _ABOUT , and the processing start signal input terminal STRT is connected to the second output terminal of the control signal generation circuit 323A of the control device 23 via the processing start signal input terminal STRT _A , and The signal input terminal AD is the address signal input terminal
The signal IXS is connected to the fourth output terminal of the instruction decoder 223A of the control device 23 via the AD _A , and is connected to the index modification signal input terminal IXS.
Is controlled by the control device 23 via the index modification signal input terminal IXS _A.
And the data output terminal D _OUT is connected to the first to third data input terminals of the output data selection circuit 321A via the selection switch SW _A11 and the data output terminal D _AOUT. That is, the selector circuits SELT _{A1 to} SE
Is connected to the LT first data input of _A3), and the processing end signal output terminal END the write signal input terminal of the holding circuit 421A via the selection switch SW _{A1 2} and the write signal output terminal WT _A (i.e. register (Write signal input terminals WT of circuits RGS _{A1 to} RGS _A3 )
And the processing end signal output terminal END is connected to the first input terminal of the control signal generator 323A of the control device 23 and the first terminal of the processing pointer 523 via the selection switch SW _A12 and the processing end signal output terminal END _A. The input terminal, the address signal output terminal AD _OUT is connected to the data bus 25 via the address signal output terminal AD _AOUT and the selection switch SW _A13 , and the bus control signal output terminal BCNT _OUT is connected to the bus control signal output terminal BC
Data bus 25 via NT _AOUT and select switch SW _A14
And the data input / output terminal D is connected to the data input / output terminal D
_A and the selection switch SW is connected to the data bus 25 via the _A15, the control unit 23 of the instruction decoder address signal supplied from 223A AD ₀ and index modification signals IX
S ₀ and the processing start signal STRT ₀ provided from the control signal generation circuit 323A of the control device 23 and the input data selection circuit 121
Data bus 2 according to input data S _ABIN given from A
5 the required raw data S _ABS from the data holding device 26 via
Load instruction processing circuit 221A for reading and capturing data ₁
Is included.

The processing circuit 221A also has a data input terminal D
_AIN is input data selection circuit via data input terminal D _AAIN
121A is connected to the data output terminal D _AAOUT , the data input terminal D _BIN is connected to the data output terminal D _{AB OUT} of the input data selection circuit 121A via the data input terminal D _ABIN , and the processing start signal input terminal STRT is connected command of the control signal generating circuit is connected to the second output terminal of 323A, and an address signal input terminal AD address signal input terminal AD through the _a controller 23 of the control device 23 via a processing start signal input STRT _a is connected to the fourth output of the decoder 223A, and the index modifying signal input IXS is connected to a fifth output of the instruction decoder 223A of the control unit 23 via the index modification signal input IXS _a,
And processing end signal output terminal END the write signal input terminal of the holding circuit 421A via the selection switch SW _A22 and the write signal output terminal WT _A (i.e. the write signal input terminal WT register circuits RGS _{A 1} ~RGS _A3) And processing end signal output terminal END
Is connected to the first input terminal of the control signal generator 323A of the control device 23 and the first input terminal of the processing pointer 523 via the selection switch SW _A22 and the processing end signal output terminal END _A ,
And the address signal output terminal AD _OUT is the address signal output terminal AD
_AOUT is connected to the data bus 25 via the selection switch SW _A23 and the bus control signal output terminal BCNT _OUT is connected to the data bus 25 via the bus control signal output terminal BCNT _AOUT and the selection switch SW _A24 , and data input / output is performed. end D is connected to the data bus 25 through the data input and output terminals D _a and the selection switch SW _A25, command of the control unit 23 decoder 22
Address signal AD ₀ and index modification signal IXS ₀ given from 3A and control signal generating circuit 32 of control device 23
Start process given from 3A signal STRT ₀ and the input data selecting circuit 121A inputs data given from S _AAIN, S _ABIN
A store instruction processing circuit 221A ₂ for allowing held by sending the already processed data S _ABS ^* in the data holding unit 26 via the data bus 25 in response to, and inclusions.

The processing circuit 221A further includes a data input terminal D
_BIN is input data selection circuit via data input terminal D _ABIN
121A is connected to the data output terminal D _ABOUT , and the processing start signal input terminal STRT is connected to the second output terminal of the control signal generation circuit 323A of the control device 23 via the processing start signal input terminal STRT _A , and The signal input terminal AD is the address signal input terminal
The signal IXS is connected to the fourth output terminal of the instruction decoder 223A of the control device 23 via the AD _A , and is connected to the index modification signal input terminal IXS.
Is controlled by the control device 23 via the index modification signal input terminal IXS _A.
And the data output terminal D _OUT is connected to the first to third data input terminals of the output data selection circuit 321A via the selection switch SW _A31 and the data output terminal D _AOUT. That is, the selector circuits SELECT _A1 to
Is connected to the SELT first data input of _A3), and the processing end signal output terminal END selection switch SW _A32 and the write signal input terminal of the holding circuit 421A via a write signal output terminal WT _A (i.e. register circuit RGS _{A1 to} RGS _A3 write signal input W
T), and the processing end signal output terminal END is connected to the first input terminal of the control signal generator 323A of the control device 23 and the processing pointer 523 via the selection switch SW _A32 and the processing end signal output terminal END _A. 1 and an address signal AD ₀ and an index modification signal IXS ₀ provided from an instruction decoder 223A of the control device 23, and a processing start signal STRT ₀ provided from a control signal generation circuit 323A of the control device 23. And a load effective address instruction processing circuit 221A ₃ for _obtaining and outputting a load effective address according to the input data S _ABIN given from the input data selection circuit 121A.
Is included.

The processing circuit 221A additionally has a data input terminal D
_AIN Is the data input terminal D_AAINInput data selection circuit via
121A data output terminal D_AAOUT Connected to
Power end D_BIN Is the data input terminal D_ABINInput data selection via
Output terminal D of selector circuit 121A _ABOUT Connected to the
Processing start signal input terminal STRT_A Through
And the second output terminal of the control signal generation circuit 323A of the controller 23.
And the data output terminal D_OUT Is the selection switch SW
_A41 And data output terminal D_AOUTOutput data selection via
The first to third data inputs of circuit 321A (ie,
Lector circuit SELT_A1~ SELT_A3First data input terminal)
And the processing end signal output terminal END is set to the selection switch SW.
_A42 And write signal output terminal WT_A Via the holding circuit 421A
Write signal input terminal (that is, register circuit RGS_A1 ~ RGS_A3 
To the write signal input terminal WT), and output the processing end signal.
Force end END is selection switch SW_A42 And processing end signal output
End END_AOf the control signal generator 323A of the controller 23 via the
1 and the first input of the processing pointer 523.
From the control signal generation circuit 323A of the control device 23.
Given processing start signal STRT₀ Input data selection according to
Input data S given from circuit 121A_AAIN, S_ABINEach other
Addition instruction processing circuit 221A for adding and outputting_Four 
Is included.

The processing circuit 221A also has a data input terminal D
_AIN Is the data input terminal D_AAINInput data selection circuit via
121A data output terminal D_AAOUT Connected to
Power end D_BIN Is the data input terminal D_ABINInput data selection via
Output terminal D of selector circuit 121A_{AB OUT} Connected to the
Processing start signal input terminal STRT_A Through
And the second output terminal of the control signal generation circuit 323A of the controller 23.
And the data output terminal D_OUT Is the selection switch SW
_A51 And data output terminal D_AOUTOutput data selection via
The first to third data inputs of circuit 321A (ie,
Lector circuit SELT_A1~ SELT_A3First data input terminal)
And the processing end signal output terminal END is set to the selection switch SW.
_A52 And write signal output terminal WT_A Via the holding circuit 421A
Write signal input terminal (that is, register circuit RGS_A1 ~ RGS_A3 
To the write signal input terminal WT), and output the processing end signal.
Force end END is selection switch SW_A52 And processing end signal output
End END_AOf the control signal generator 323A of the controller 23 via the
1 and the first input of the processing pointer 523.
From the control signal generation circuit 323A of the control device 23.
Given processing start signal STRT₀ And input data selection times
Input data S given from the path 121A_ABINInput data according to
Input data S given from the data selection circuit 121A. _AAINThe left
Arithmetic left shift instruction processing circuit 22 for shifting and outputting
1A_Five Is included.

[0422] processing circuit 221A, taken together, an instruction of the control unit 23 input via the circuit selection signal input terminal SC _A decoder 22
3A are connected to the first output terminal, and the first to fifth output terminals are respectively provided with selection switches SW _{A11 to} SW _A15 ; SW _{A22 to} SW
_{A25; SW A31 ~SW A32; SW} A41 ~SW A42; SW A51 ~SW A52 are connected to, select the decrypted decoding result of the circuit selection signal SC ₀ provided from the instruction decoder 223A of the control unit 23 signals SC
Selection switches SW _{A11 to} SW _A15 as _{A1 to} SC _A5 ; SW
_{A22 to} SW _A25 ; SW _{A31 to} SW _A32 ; SW _{A41 to} SW _A42 ; SW _{A51 to} SW
Given to _A52 , load instruction processing circuit 221A ₁ , store instruction processing circuit 221A ₂ , load effective address instruction processing circuit 221A ₃ , addition instruction processing circuit 221A _4, and arithmetic left shift instruction processing circuit 221A
Decoder DECD _A for selecting any one of ₅
Have a wrap.

[0423] Output data selection circuit 321A includes a decode the output data selection signal SO ₀ supplied from the fourth connection to which instruction decoder 223A to the output terminal of the instruction decoder 223A of input control unit 23 decodes the result _A decoder DEC _A for outputting as selection signals SO _{A1 to} SO _A3 , a first data input terminal connected to the data output terminal D _AOUT of the processing circuit 221A, and a second data input terminal connected to the first data input terminal of the holding circuit 421D. the data output (i.e. the data output terminal Q of the register circuit RGS _D1) the selection signal SO _A1 that is connected to and controlled input to is given from the decoder DEC _a is connected to the first output of the decoder DEC _a When active (ie, “1”), the output data S _A given from the processing circuit 221A is selected and output as output data S _A1 , and the selection signal SO _A1 given from the decoder DEC _A is inactive (ie, “0”). ”) When the holding circuit 421D The selector circuit SELT _A1 for selecting and outputting the input data S _D1 supplied from the register circuit RGS _D1 as output data S _A1
When the first data input terminal connected to the data output terminal D _AOUT processing circuit 221A and the second data input terminal holding circuit 42
1D second data output terminal (ie, register circuit RGS _D2
Process when the selection signal SO _A2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _A is connected to the second output terminal of the decoder DEC _A of the active (i.e., "1") The output data S _A given from the circuit 221A is selected and output as output data S _A2 , and when the selection signal SO _A2 given from the decoder DEC _A is inactive (that is, “0”), the register circuit of the holding circuit 421D is selected. A selector circuit SELECT _A2 for selecting the input data S _D2 given from RGS _D2 and outputting it as output data S _A2 ; a first data input terminal connected to the data output terminal D _AOUT of the processing circuit 221A; 2
Is the third data output terminal of the holding circuit 421D.
(I.e. register circuit RGS _D3 data output terminal Q of) is connected to and the third is connected to an output end decoder DEC selection signal given from the _A SO control input end decoder DEC _{A
When A3} is active (ie, "1"), it selects the output data S _A given from the processing circuit 221A, outputs it as output data S _A3 , and selects the selection signal SO _A3 given from the decoder DEC _A
Is inactive (ie, “0”), a selector circuit SE for selecting the input data S _D3 given from the register circuit RGS _D3 of the holding circuit 421D and outputting it as output data S _A3.
LT _A3 .

The processing block 21B (FIG. 31A, FIG. 31B,
(See FIGS. 35A and 35B)

The processing block 21B of the processing device 21
The second input terminal is the second input terminal of the instruction decoder 223B of the controller 23.
The input data S _A1 ... Applied to the third to fifth input terminals in accordance with the input data selection signals SIA ₁ and SIB ₁ supplied from the instruction decoder 223B of the control device 23 and connected to the third output terminal. An input data selection circuit 121B for selecting desired input data from S _A3 and outputting it as input data S _BAIN and S _BBIN from data output terminals D _BAOUT and D _BBOUT , and a data input terminal D _BAIN for input data selection circuit 121B Data output terminal D
Instruction decoder coupled to _BAOUT and data input D _BBIN is connected to the data output terminal D _BBOUT the input data selecting circuit 121B and the circuit selection signal input terminal SC _B control unit 23 223B
And a processing start signal input terminal STRT
The second is connected to the output end and the address signal input terminal AD _B is connected to a sixth output of the instruction decoder 223B of the controller 23 and the index modification signal input terminal of the control signal generating circuit 323B and _B controller 23 IXS _B is the instruction decoder of controller 23
A processing end signal output terminal connected to the fifth output terminal of the 223B
END _B is connected to the third input terminal of the control signal generation circuit 323B of the control device 23 and the first input terminal of the processing pointer 523, and the address signal output terminal AD _BOUT is connected to the data bus 25 and the bus control signal output. end BCNT _BOUT the selected control device the desired operation circuit according to the circuit selection signal SC ₁ given from the data connected to the bus 25 and the data input and output terminals D _B data bus 25 connected to it and the controller 23 23, the input data S _BAIN and S _BBIN provided from the input data selection circuit 121B or the _unprocessed data provided from the data bus 25 in accordance with the processing start signal STRT ₁ , address signal AD ₁ and index modification signal IXS ₁ provided from the data bus 25. processing circuit for outputting data S _BBS as appropriate to the process to the first output terminal (i.e. data output D _BOUT) or the output data S from the data input terminal D _{B B} or already processed data S _BBS ^* 221B , First to third input terminal connected to the first output of the processing circuit 221B (i.e. data output terminal D _{BO UT)} of and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 421A (that is, the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ), and the seventh input terminal is connected to the instruction decoder 223B of the controller 23. A control device connected to the fourth output end;
Output data S _B and the fourth to sixth register circuit RG holding circuit 421A to the input terminal of the processing circuit 221B in response to the output data selection signal SO ₁ given from 23 of the instruction decoder 223B
S _A1 ~RGS _A3 input data S _A1 ~ given each from
An output data selection circuit 321B for selecting desired data from S _A3 and outputting it from the first to third data output terminals as output data S _{B1 to} S _B3 , and writing to a second output terminal of processing circuit 221B Signal input end (that is, register circuits RGS _{B1 to} RG
Write signal input of S _B3 WT) is first to third data input to the first to third data output of each connected and the output data selection circuit 321B (i.e. register circuit
The data input terminals D) of RGS _{B1 to} RGS _B3 are connected to each other, and the output data S _{B1 to} S _B3 given from the output data selection circuit 321B are written into the write signal WT given from the processing circuit 221B.
And a holding circuit 421B for holding the register circuits RGS _{B1 to} RGS _B3 in accordance with ₁ .

In the input data selection circuit 121B, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 421A (that is, the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ). connected and controlled input control unit 23 and the second register circuit of the holding circuit 421A according to the input data selection signal SIA ₁ given from the instruction decoder 223B of connected and the controller 23 to the output terminal of the instruction decoder 223B of RGS _A1 input data given from ~RGS _A3 S _A1 ~S _A3
And a selector circuit SEL _B1 for selecting one of them and outputting the selected data from the data output terminal D _BAOUT, and a first to third data output terminal of the holding circuit 421A as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{A1 to} RGS _A3 ) and the control input terminal is connected to the third output terminal of the instruction decoder 223B of the control device 23. register circuits holding circuit 421A according to the given input data selection signal SIB ₁ RGS _A1 ~
And a selector circuit SEL _B2 for choosing one of RGS _{A 3} input data given from the S _A1 to S _A3 output from the data output terminal D _BBOUT, are inclusions.

[0427] The processing circuit 221B first selects the data input terminal D
_BIN is input data selection circuit via data input terminal _DBBIN
It is connected to 121B of the data output terminal D _BBOUT, and process start signal input terminal STRT is connected to the second output terminal of the control signal generating circuit 323B of the control device 23 via a processing start signal input terminal STRT _B, and the address The signal input terminal AD is the address signal input terminal
It is connected to the fourth output of the instruction decoder 223B of the controller 23 through the AD _B, and index qualification signal input IXS
Is connected to the control device 23 via the index modification signal input terminal IXS _B.
Instruction is connected to the fifth output terminal of the decoder 223B, and the data output terminal D _OUT is the first to third data input via the selection switch SW _B11 and a data output terminal D _BOUT output data selection circuit 321B ( That is, the selector circuits SELT _B1 to
Is connected to the SELT first data input of _B3), and the processing end signal output terminal END the write signal input of the hold circuit 421B via the selector switch SW _B12 and the write signal output terminal WT _B (i.e. register circuit RGS _{B1 to} RGS _B3 write signal input terminals W
It is connected to T), and the processing end signal output terminal END selection switch SW _B12 and processing end signal output terminal END first input terminal and the processing pointer 523 of the control signal generator 323B of the control device 23 through the _B It is connected to one input terminal, and an address signal output terminal AD _OUT is connected via an address signal output terminal AD _{BO UT} and the selection switch SW _B13 to the data bus 25, and bus control signals output BCNT _OUT bus control signals via an output terminal BCNT _BOUT and the selection switch SW _B14 are connected to the data bus 25, and data input terminal D via the data input and output terminals D _B and the selection switch SW _B15 data bus
Are connected to 25, the control unit 23 of the instruction processing start signal STRT ₁ and the input data given from the control signal generating circuit 323B of the address signal supplied from the decoder 223B AD ₁ and index modification signal IXS ₁ and the control unit 23 the load instruction processing circuit 221B ₁ for fetching from the data holding unit 26 via the data bus 25 in response to given from the selection circuit 121B input data S _BBIN reads the necessary raw data S _BBS, are inclusions .

The processing circuit 221B also has a data input terminal D
_AIN is input data selection circuit via data input terminal _DBAIN
Is connected to 121B of the data output terminal D _BAOUT, and the data input D _BIN is connected to the data output terminal D _{BB OUT} of the input data selecting circuit 121B through the data input terminal D _BBIN, and process start signal input terminal STRT is The processing start signal input terminal STRT _B is connected to the second output terminal of the control signal generation circuit 323B of the control device 23, and the address signal input terminal AD is connected to the command of the control device 23 via the address signal input terminal AD _B. is connected to the fourth output of the decoder 223B, and the index modifying signal input IXS is connected to a fifth output of the instruction decoder 223B of the controller 23 via the index modification signal input IXS _B,
And processing end signal output terminal END the write signal input of the hold circuit 421B via the selector switch SW _B22 and the write signal output terminal WT _B (i.e. the write signal input terminal WT register circuits RGS _{B 1} ~RGS _B3) And processing end signal output terminal END
Is connected to the first input of the first input terminal and the processing pointer 523 of the control signal generator 323B of the selection switch SW _B22 and processing end signal output terminal END _B controller via the 23,
And the address signal output terminal AD _OUT is the address signal output terminal AD
_BOUT is connected to the data bus 25 via the selection switch SW _B23 and the bus control signal output terminal BCNT _OUT is connected to the data bus 25 via the bus control signal output terminal BCNT _BOUT and the selection switch SW _B24 , and data input / output is performed. end D is connected to the data bus 25 through the data input and output terminals D _B and the selection switch SW _B25, command of the control unit 23 decoder 22
Address signal AD ₁ and index modification signal IXS ₁ given from 3B and control signal generating circuit 32 of control device 23
The processed data S _BBS ^* is sent to the data holding device 26 via the data bus 25 in accordance with the processing start signal STRT ₁ given from 3B and the input data S _BAIN and S _BBIN given from the input data selection circuit 121B. a store instruction processing circuit 221B ₂ for allowing the holding, and inclusions.

The processing circuit 221B further includes a data input terminal D
_BIN is input data selection circuit via data input terminal _DBBIN
It is connected to 121B of the data output terminal D _BBOUT, and process start signal input terminal STRT is connected to the second output terminal of the control signal generating circuit 323B of the control device 23 via a processing start signal input terminal STRT _B, and the address The signal input terminal AD is the address signal input terminal
It is connected to the fourth output of the instruction decoder 223B of the controller 23 through the AD _B, and index qualification signal input IXS
Is connected to the control device 23 via the index modification signal input terminal IXS _B.
Instruction is connected to the fifth output terminal of the decoder 223B, and the data output terminal D _OUT is the first to third data input via the selection switch SW _B31 and a data output terminal D _BOUT output data selection circuit 321B ( That is, the selector circuits SELT _B1 to
Is connected to the SELT first data input of _B3), and the processing end signal output terminal END the write signal input of the hold circuit 421B via the selector switch SW _B32 and the write signal output terminal WT _B (i.e. register circuit RGS _{B1 to} RGS _B3 write signal input terminals W
It is connected to T), and the processing end signal output terminal END selection switch SW _B32 and processing end signal output terminal END first input terminal and the processing pointer 523 of the control signal generator 323B of the control device 23 through the _B is connected to one input terminal, the control unit address signal AD ₁ given from the instruction decoder 223B of 23 and index modification signal IXS ₁ and the control device control signal generating circuit processing start signal given from 323A STRT ₁ 23 And a load effective address instruction processing circuit 221B ₃ for _obtaining and outputting a load effective address according to the input data _SBBIN given from the input data selection circuit 121B.
Is included.

The processing circuit 221B additionally has a data input terminal D
_AIN Is the data input terminal D_BAINInput data selection circuit via
Data output terminal D of 121B_BAOUT Connected to
Power end D_BIN Is the data input terminal D_BBINInput data selection via
Data output terminal D of selector circuit 121B_BBOUT Connected to the
Processing start signal input terminal STRT_B Through
And the second output terminal of the control signal generation circuit 323B of the control device 23
And the data output terminal D_OUT Is the selection switch SW
_B41 And data output terminal D_BOUTOutput data selection via
The first to third data inputs of circuit 321B (ie,
Lector circuit SELT _B1~ SELT_B3First data input terminal)
And the processing end signal output terminal END is set to the selection switch SW.
_B42 And write signal output terminal WT_B Of the holding circuit 421B via
Write signal input terminal (that is, register circuit RGS_B1 ~ RGS_B3 
To the write signal input terminal WT), and output the processing end signal.
Force end END is selection switch SW_B42 And processing end signal output
End END_BThe control signal generator 323B of the controller 23 via the
1 and the first input of the processing pointer 523.
From the control signal generation circuit 323B of the control device 23.
Given processing start signal STRT₁ Input data selection according to
The input data S given from the circuit 121B_BAIN, S_BBINEach other
Addition instruction processing circuit 221B for adding and outputting_Four 
Is included.

The processing circuit 221B also has a data input terminal D
_AIN is input data selection circuit via data input terminal _DBAIN
Is connected to 121B of the data output terminal D _BAOUT, and the data input D _BIN is connected to the data output terminal D _{BB OUT} of the input data selecting circuit 121B through the data input terminal D _BBIN, and process start signal input terminal STRT is It is connected to the second output terminal of the control signal generation circuit 323B of the control device 23 via the processing start signal input terminal STRT _B , and the data output terminal D _OUT is connected to the selection switch SW.
_B51 and data output through the D _BOUT connected to the first to third data input of the output data selection circuit 321B (or first data input terminal of the selector circuit SELT _B1 ~SELT _B3), and the processing end signal Output terminal END is selection switch SW
_B52 and write signal input terminal of the holding circuit 421B via the write signal output terminal WT _B (i.e. register circuit RGS _B1 ~RGS _B3
Of the control signal generator 323B of the controller 23 via the selection switch _SWB52 and the processing end signal output end END _B. and processing are connected to the first input terminal of the pointer 523, corresponding to the control unit 23 of the control signal generating circuit 323B processes given from the start signal STRT ₁ and the input data selecting circuit input data S _BBIN given from 121B Arithmetic shift left instruction processing circuit 22 for shifting input data S _BAIN given from input data selection circuit 121B to the left and outputting the same.
1B ₅ is included.

[0432] processing circuit 221B, taken together, an instruction of the control unit 23 input via the circuit selection signal input terminal SC _B decoder 22
3B, the first to fifth output terminals are connected to selection switches SW _{B11 to} SW _B15 ; SW _{B22 to} SW, respectively.
_{B25; SW B31 ~SW B32; SW} B41 ~SW B42; SW B51 ~SW B52 are connected to, select the decrypted decoding result of the circuit selection signal SC ₁ given from the instruction decoder 223B of the controller 23 signals SC
Selection switches SW _{B11 to} SW _B15 as _{B1 to} SC _B5 ; SW
_{B22 to} SW _B25 ; SW _{B31 to} SW _B32 ; SW _{B41 to} SW _B42 ; SW _{B51 to} SW
Given to _B52 , load instruction processing circuit 221B ₁ , store instruction processing circuit 221B ₂ , load effective address instruction processing circuit 221B ₃ , addition instruction processing circuit 221B ₄ and arithmetic left shift instruction processing circuit 221B
Decoder DECD _B for selecting any one of ₅
Have a wrap.

[0433] Output data selection circuit 321B is a decodes the output data selection signal SO ₁ given from the connected and instruction decoder 223B to the fourth output of the instruction decoder 223B of input control unit 23 decodes the result selection signal SO _B1 to SO and a decoder DEC _B for outputting as _B3, first the first data input terminal connected to the data output terminal D _BOUT processing circuit 221B and a second data input terminal holding circuit 421A the data output (i.e. the data output terminal Q of the register circuit RGS _A1) selection signal SO _B1 that is connected to and controlled input to is given from the decoder DEC _B is connected to the first output of the decoder DEC _B is active (i.e. "1") processing circuit selects the output data S _B supplied from 221B outputs as output data S _B1 and selection signals SO _B1 provided from the decoder DEC _B is inactive (i.e., when the "0 ”) Holds circuit 421A The selector circuit SELT _B1 for selecting and outputting the input data S _A1 supplied from the register circuit RGS _A1 as output data S _B1
When the first data input terminal connected to the data output terminal D _BOUT processing circuit 221B and a second data input terminal holding circuit 42
1A second data output terminal (ie, register circuit RGS _A2
Process when the selection signal SO _B2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _B is connected to the second output terminal of the decoder DEC _B of the active (i.e., "1") register circuits holding circuits 421A when the output is and the selection signal SO _B2 is inactive given from the decoder DEC _B selects the output data S _B supplied from circuit 221B as the output data S _B2 (i.e. "0") A selector circuit SELECT _B2 for selecting the input data S _A2 given from RGS _A2 and outputting it as output data S _B2 , a first data input terminal connected to the data output terminal D _BOUT of the processing circuit 221B, and 2
Is the third data output terminal of the holding circuit 421A.
(I.e. register circuit RGS _A3 data output terminal Q of) it is connected to and the third is connected to an output end decoder DEC selection signal given from _B SO control input end decoder DEC _B
B3 is active (i.e. "1") when the processing circuit selects the output data S _B supplied from 221B outputs as output data S _B3 and selective given from the decoder DEC _B signal SO _B3
Is inactive (ie, “0”), a selector circuit SE for selecting the input data S _A3 given from the register circuit RGS _A3 of the holding circuit 421A and outputting it as output data S _B3.
LT _B3 .

The processing block 21C (FIGS. 32A and 32B,
(See FIGS. 36A and 36B)

The processing block 21C of the processing device 21
The second input terminal is the second input terminal of the instruction decoder 223C of the controller 23.
The input data S _B1 ... Connected to the third output terminal and supplied to the third to fifth input terminals in accordance with the input data selection signals SIA ₂ and SIB ₂ supplied from the instruction decoder 223C of the control device 23. It desired select input data to the data output terminal D _CAOUT from S _B3, input data S _CAIN from D _CBOUT, input data selection circuit 121C for outputting the S _Cbin, the data input D _CAIN is the input data selection circuit 121C Data output terminal D
Instruction decoder coupled to _CAOUT and data input D _Cbin is connected to the data output terminal D _CBOUT the input data selection circuit 121C and the circuit selection signal input terminal SC _C control unit 23 223C
And a processing start signal input terminal STRT
Connected to a second and the address signal input terminal AD _C to the output terminal is connected to a sixth output of the instruction decoder 223C of control device 23 and the index modification signal input terminal of the control signal generating circuit 323C of _C is the control device 23 IXS _C is the instruction decoder of the controller 23
223C is connected to the fifth output terminal and is a processing end signal output terminal.
END _C is connected to the third input terminal of the control signal generating circuit 323C of the control device 23 and the first input terminal of the processing pointer 523, and the address signal output terminal _ADCOUT is connected to the data bus 25 and the bus control signal output is provided. end BCNT _COUT is connected to the data bus 25 and the data input and output terminals D _C is selected controller a desired operation circuit according to the circuit selection signal SC ₂ given from the connected and the control unit 23 to the data bus 25 23, the input data S _CAIN and S _{CBIN supplied} from the input data selection circuit 121C or the _unprocessed data _supplied from the data bus 25 according to the processing start signal STRT ₂ , address signal AD ₂ , and index modification signal IXS ₂ processing circuit for outputting data S _CBS as appropriate to the process to the first output terminal (i.e. data output D _COUT) or data input and output terminals D _C from the output data S _C or already processed data S _CBS ^* 221C , First to third input terminal connected to the first output of the processing circuit 221C (i.e. data output terminal D _{CO UT)} of and the fourth to sixth
Is connected to the first to third data output terminals of the holding circuit 421B (that is, the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ), and the seventh input terminal is connected to the instruction decoder 223C of the controller 23. A control device connected to the fourth output end;
Output data S _C and the register circuit RG fourth to hold circuit 421B to the input terminal of the sixth processing circuit 221C according to the output data selection signal SO ₂ given from 23 of the instruction decoder 223C
Input data S _B1 to S _B1 given from S _{B1 to} RGS _B3 respectively
An output data selection circuit 321C for selecting desired data from S _B3 and outputting the output data as output data S _{C1 to} S _C3 from the first to third data output terminals and writing to a second output terminal of the processing circuit 221C. Signal input terminal (that is, register circuits RGS _{C1 to} RG
Write signal input terminal WT) is first to third data input to the first to third data output of each connected and the output data selection circuit 321C of S _C3 (i.e. register circuit
The data input terminals D) of the RGS _{C1 to} RGS _C3 are connected to each other, and the output data S _{C1 to} S _C3 given from the output data selection circuit 321C are written into the write signal WT given from the processing circuit 221C.
₂ and a holding circuit 421C for holding the register circuits RGS _{C1 to} RGS _C3 in accordance with ₂ .

In the input data selection circuit 121C, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 421B (that is, the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ). connected and controlled input control unit 23 and the second register circuit of the holding circuit 421B according to the input data selection signal SIA ₂ given from the instruction decoder 223C outputs the connected and the control device to end 23 of the instruction decoder 223C of RGS _B1 input given from ~RGS _B3 data S _B1 ~S _B3
And a selector circuit SEL _C1 for selecting one of them and outputting it from the data output terminal D _CAOUT, and a first to third data output terminal of the holding circuit 421B as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{B1 to} RGS _B3 ), and the control input terminal is connected to the third output terminal of the instruction decoder 223C of the control device 23. register circuits holding circuit 421B according to the given input data selection signal SIB ₂ RGS _B1 ~
A selector circuit SEL _C2 for selecting one of the input data S _{B1 to} S _B3 given from the RGS _{B 3} and outputting it from the data output terminal D _CBOUT is included.

[0437] The processing circuit 221C first selects the data input terminal D
_BIN is input data selection circuit via data input terminal D _CBIN
It is connected to the data output D _CBOUT of 121C, and process start signal input terminal STRT is connected to the second output terminal of the control signal generating circuit 323C of the control device 23 via a processing start signal input STRT _C, and the address The signal input terminal AD is the address signal input terminal
It is connected to the fourth output of the instruction decoder 223C of the control apparatus 23 via the AD _C, and the index modifying signal input IXS
Controller 23 but via the index modification signal input IXS _C
And the data output terminal D _OUT is connected to the first to third data input terminals of the output data selection circuit 321C via the selection switch SW _C11 and the data output terminal D _COUT. That is, the selector circuits SELT _C1 to
Is connected to the SELT first data input of _C3), and the processing end signal output terminal END the write signal input terminal of the holding circuit 421C via the selection switch SW _C12 and the write signal output terminal WT _C (i.e. register circuit RGS _{C1 to} RGS _C3 write signal input W
Is connected to T), and the processing end signal output terminal END selection switch SW _C12 and processing end signal output terminal END control via the _C controller 23 signal generator first input terminal and the processing pointer 523 323C It is connected to one input terminal, and an address signal output terminal AD _OUT is connected via an address signal output terminal AD _{CO UT} and the selection switch SW _C13 to the data bus 25, and bus control signals output BCNT _OUT bus control signals It is connected via an output terminal BCNT _COUT and the selection switch SW _C14 to the data bus 25, and data input terminal D via the data input and output terminals D _C and selection switch SW _C15 data bus
Are connected to 25, the control unit 23 of the instruction processing start signal STRT ₂ and the input data given from the control signal generating circuit 323C of the address signal supplied from the decoder 223C AD ₂ and index modification signals IXS ₂ and a control device 23 the load instruction processing circuit 221C ₁ for fetching from the data holding unit 26 via the data bus 25 in response to given from the selection circuit 121C input data S _Cbin reads the necessary raw data S _CBS, have inclusions .

The processing circuit 221C also has a data input terminal D
_CIN is input data selection circuit via data input terminal D _CAIN
The data output terminal D _CAOUT of the 121C is connected to the data output terminal D _BIN of the input data selection circuit 121C via the data input terminal D _CBIN , and the processing start signal input terminal STRT is connected to the data output terminal D _{CB OUT} of the input data selection circuit 121C. command of the control signal generating circuit is connected to the second output terminal of 323C, and the address signal input terminal AD address signal input terminal AD through the _C controller 23 of the control device 23 via a processing start signal input STRT _C It is connected to the fourth output of the decoder 223C, and the index modifying signal input IXS is connected to a fifth output of the instruction decoder 223C of the control apparatus 23 via the index modification signal input IXS _C,
And processing end signal output terminal END the write signal input terminal of the holding circuit 421C via the selection switch SW _A22 and the write signal output terminal WT _C (i.e. the write signal input terminal WT register circuits RGS _{C 1} ~RGS _C3) And processing end signal output terminal END
Is connected to the first input terminal of the control signal generator 323C of the control device 23 and the first input terminal of the processing pointer 523 via the selection switch SW _C22 and the processing end signal output terminal END _C ,
And the address signal output terminal AD _OUT is the address signal output terminal AD
_The bus control signal output terminal BCNT _OUT is connected to the data bus 25 via the bus control signal output terminal BCNT _COUT and the selection switch SW _C24 , and is connected to the data bus 25 via _COUT and the selection switch SW _C23. output terminal D is connected to the data bus 25 through the data input and output terminals D _C and selection switch SW _{C2 5,} the instruction decoder of the controller 23
Address signal AD ₂ and index modification signal IXS ₂ given from 223C and control signal generation circuit of control device 23
Processing start signal STRT ₂ and the input data selecting circuit input data S _CAIN given from 121C provided from 323C, S
A store instruction processing circuit 221C ₂ for allowing held by sending the already processed data S _CBS ^* in the data holding unit 26 via the data bus 25 in response to _Cbin, are inclusions.

The processing circuit 221C further includes a data input terminal D
_BIN is input data selection circuit via data input terminal D _CBIN
It is connected to the data output D _CBOUT of 121C, and process start signal input terminal STRT is connected to the second output terminal of the control signal generating circuit 323C of the control device 23 via a processing start signal input STRT _C, and the address The signal input terminal AD is the address signal input terminal
It is connected to the fourth output of the instruction decoder 223C of the control apparatus 23 via the AD _C, and the index modifying signal input IXS
Controller 23 but via the index modification signal input IXS _C
And the data output terminal D _OUT is connected to the first to third data input terminals of the output data selection circuit 321C via the selection switch SW _C31 and the data output terminal D _COUT. That is, the selector circuits SELT _C1 to
Is connected to the SELT first data input of _C3), and the processing end signal output terminal END the write signal input terminal of the holding circuit 421C via the selection switch SW _C32 and the write signal output terminal WT _C (i.e. register circuit RGS _{C1 to} RGS _C3 write signal input W
T), and the processing end signal output terminal END is connected to the first input terminal of the control signal generator 323C of the controller 23 and the processing pointer 523 of the processing pointer 523 via the selection switch SW _C32 and the processing end signal output terminal END _C. is connected to one input terminal, the control unit address signal AD ₂ given from the instruction decoder 223C of 23 and index modification signals IXS ₂ and a control unit 23 of the control signal generating circuit processing start signal given from 323C STRT ₂ And a load effective address instruction processing circuit 221C ₃ for _obtaining and outputting a load effective address according to the input data S _CBIN given from the input data selection circuit 121C.
Is included.

The processing circuit 221C additionally has a data input terminal D
_AIN is input data selection circuit via data input terminal D _CAIN
The data output terminal D _CAOUT of the 121C is connected to the data input terminal D _BIN of the input data selection circuit 121C via the data input terminal D _CBIN , and the processing start signal input terminal STRT is connected to the data output terminal D _CBOUT of the input data selection circuit 121C. The start signal input terminal STRT _C is connected to the second output terminal of the control signal generation circuit 323C of the control device 23, and the data output terminal D _OUT is connected to the selection switch SW.
_C41 and a data output terminal D _COUT are connected to the first to third data input terminals of the output data selection circuit 321C (that is, the first data input terminals of the selector circuits SELT _{C1 to} SELT _C3 ), and a processing end signal. Output terminal END is selection switch SW
_C42 and the write signal input terminal of the holding circuit 421C through the write signal output terminal WT _C (i.e. register circuit RGS _C1 ~RGS _C3
And the processing end signal output terminal END is connected to the first input terminal of the control signal generator 323C of the control device 23 via the selection switch SW _C42 and the processing end signal output terminal END _C. and is connected to the first input terminal of the processing pointer 523, the control unit 23 input data S _CAIN of control signal generating circuit in response to the processing start signal STRT ₂ given from 323C provided from the input data selection circuit 121C of , add instruction processing circuit for adding and outputting S _Cbin mutually 221C ₄
Is included.

The processing circuit 221C also has a data input terminal D
_AIN is input data selection circuit via data input terminal D _CAIN
The data output terminal D _CAOUT of the 121C is connected to the data output terminal D _BIN of the input data selection circuit 121C via the data input terminal D _CBIN , and the processing start signal input terminal STRT is connected to the data output terminal D _{CB OUT} of the input data selection circuit 121C. It is connected to the second output terminal of the control signal generation circuit 323C of the control device 23 via the processing start signal input terminal STRT _C , and the data output terminal D _OUT is connected to the selection switch SW.
_C51 and the data output terminal D _COUT are connected to the first to third data input terminals of the output data selection circuit 321C (that is, the first data input terminals of the selector circuits SELT _{C1 to} SELT _C3 ) and a processing end signal. Output terminal END is selection switch SW
_C52 and the write signal input terminal of the holding circuit 421C through the write signal output terminal WT _C (i.e. register circuit RGS _C1 ~RGS _C3
And the processing end signal output terminal END is connected to the first input terminal of the control signal generator 323C of the control device 23 via the selection switch SW _C52 and the processing end signal output terminal END _C. and processing are connected to the first input terminal of the pointer 523, corresponding to the control unit 23 of the control signal generating circuit 323C treatment given from the start signal STRT ₂ and the input data selecting circuit input data S _Cbin given from 121C arithmetic left for outputting input data S _{C AIN} supplied from the input data selection circuit 121C and left shift Te shift instruction processing circuit 22
1C ₅ is included.

[0442] processing circuit 221C, taken together, an instruction of the control unit 23 input via the circuit selection signal input terminal SC _C decoder 22
3C, and the first to fifth output terminals are respectively connected to selection switches SW _{C11 to} SW _C15 ; SW _{C22 to} SW
_{C25; SW C31 ~SW C32; SW} C41 ~SW C42; SW C51 ~SW C52 are connected to, select the decrypted decoding result of the circuit selection signal SC ₂ given from the instruction decoder 223C of the control apparatus 23 signals SC
Selection switches SW _{C11 to} SW _C15 as _{C1 to} SC _C5 ; SW
_{C22 to} SW _C25 ; SW _{C31 to} SW _C32 ; SW _{C41 to} SW _C42 ; SW _{C51 to} SW
Load instruction processing circuit 221C ₁ applied to the _C52, the store instruction processing circuit 221C _2, the load effective address instruction processing circuit 221C _3, add instruction processing circuit 221C ₄ and the arithmetic left shift instruction processing circuit 221C
Decoder DECD _C for selecting any one of ₅
Have a wrap.

[0443] Output data selection circuit 321C is the fourth decodes the output data selection signal SO ₂ provided from the connected and instruction decoder 223C decodes the result to the output terminal of the instruction decoder 223C of input control unit 23 a decoder DEC _C for outputting a selection signal SO _C1 ~SO _C3, first the first data input terminal connected to the data output terminal D _COUT processing circuit 221C and the second data input terminal holding circuit 421B the data output (i.e. register circuit RGS _B1 data output terminal Q) of the selection signal SO _C1 that is connected to and controlled input to is given from the decoder DEC _C is connected to the first output of the decoder DEC _C is active (i.e. "1") processing circuits given output data S _C to select from 221C outputs as output data S _C1 and the selection signal SO _C1 is inactive given from the decoder DEC _C (that is, when "0 )) When the holding circuit 421B The selector circuit SELT _C1 to select the input data S _B1 supplied from the register circuit RGS _B1 and outputs it as output data S _C1
When the first data input terminal connected to the data output terminal D _COUT processing circuit 221C and the second data input terminal holding circuit 42
1B second data output terminal (ie, register circuit RGS _B2
Process when the selection signal SO _C2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _C is connected to the second output terminal of the decoder DEC _C of the active (i.e., "1") register circuits holding circuits 421B when the outputs and selectively signal SO _C2 is inactive given from the decoder DEC _C selects the output data S _C given from the circuit 221C as output data S _C2 (i.e. "0") A selector circuit SELECT _C2 for selecting the input data S _B2 given from RGS _B2 and outputting it as output data S _C2 ; a first data input terminal connected to the data output terminal D _COUT of the processing circuit 221C; 2
Is the third data output terminal of the holding circuit 421B.
(I.e. register circuit RGS _B3 data output terminal Q of) it is connected to and the third is connected to an output end decoder DEC _C selection signal given from SO control input end decoder DEC _C
C3 selection signal SO _C3 supplied from output as active (i.e. "1") output data S _C3 selects the output data S _C supplied from the processing circuit 221C when and decoder DEC _C
Is inactive (ie, “0”), the selector circuit SE for selecting the input data S _B3 given from the register circuit RGS _B3 of the holding circuit 421B and outputting it as output data S _C3.
LT _C3 .

Processing block 21D (FIGS. 33A, 33B,
(See FIGS. 37A and 37B)

The processing block 21D of the processing device 21 includes the first
The second input terminal is the second input terminal of the instruction decoder 223D of the controller 23.
The input data S _C1 ... Connected to the third output terminal and supplied to the _third to fifth input terminals according to the input data selection signals SIA ₃ and SIB ₃ supplied from the instruction decoder 223D of the control device 23. An input data selection circuit 121D for selecting desired input data from S _C3 and outputting it from the data output terminals D _DAOUT and D _{DBOUT as} input data S _DAIN and S _DBIN , and a data input terminal D _DAIN for the input data selection circuit 121D Data output terminal D
Instruction decoder coupled to the _DAOUT and data input D _DBIN is connected to the data output terminal D _DBOUT the input data selecting circuit 121D and the circuit selection signal input terminal SC _D the control device 23 223D
And a processing start signal input terminal STRT
_D is connected to a sixth output of the instruction decoder 223D of the control signal generator is connected to the second output terminal of the circuit 323D and the address signal input terminal AD _D control unit 23 of the control device 23 and the index modification signal input terminal IXS _D is the instruction decoder of controller 23
A processing end signal output terminal connected to the fifth output terminal of the 223D
END _D is connected to the third input terminal of the control signal generating circuit 323D of the control device 23 and the first input terminal of the processing pointer 523, and the address signal output terminal _ADDOUT is connected to the data bus 25 and the bus control signal output. end BCNT _DOUT is connected to the data bus 25 and the data input and output terminals D _D is selected controller a desired operation circuit according to the circuit selection signal SC ₃ supplied from the control unit 23 is connected to the data bus 25 23, the input data S _DAIN and S _{DBIN supplied} from the input data selection circuit 121D or the _unprocessed data _supplied from the data bus 25 in accordance with the processing start signal STRT ₃ , the address signal AD ₃ , and the index modification signal IXS ₃ processing circuit for outputting data S _DBS as appropriate to the process to the first output terminal (i.e. data output D _DOUT) or the output from the data output terminal D _D data S _D or already processed data S _DBS ^* 221D , First to third first, second and third input the first output terminal (i.e. data output D _DOUT) connected to and input of the fourth to sixth processing circuit 221D of the holding circuit 421C of the data Output end
(Ie, the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ) and the seventh input terminal thereof is connected to the fourth output terminal of the instruction decoder 223D of the control device 23.
Output data selection signal given from the instruction decoder 223D of
Output data S _D and the fourth processing circuit 221D according to SO ₃
And a register circuit RGS of the holding circuit 421C at the sixth input terminal.
_C1 input given from each of ~RGS _C3 data S _C1 ~
An output data selection circuit 321D for selecting desired data from S _C3 and outputting it from the first to third data output terminals as output data S _{D1 to} S _D3 , and writing to a second output terminal of processing circuit 221D Signal input terminal (that is, register circuits RGS _{D1 to} RG
Write signal input terminal WT) is first to third data input to the first to third output terminals of each connected and the output data selection circuit 321D of S _D3 (i.e. register circuit RGS _D1
To RGS _D3 are connected to each other, and the output data S _D1 given from the output data selection circuit 321D is connected.
A holding circuit 421D for holding the register circuit RGS _D1 ~RGS _D3 in response to the write signal WT ₃ that received to S _D3 from the processing circuit 221D, are inclusions.

In the input data selection circuit 121D, the first to third data input terminals are respectively connected to the first to third data output terminals of the holding circuit 421C (that is, the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ). connected and controlled input control unit 23 and the second register circuit of the holding circuit 421C according to the input data selection signal SIA ₃ given from the instruction decoder 223D of the output connected to and control the end 23 of the instruction decoder 223D of RGS _C1 input given from ~RGS _C3 data S _C1 ~S _C3
And a selector circuit SEL _D1 for selecting one of them and outputting the data from the data output terminal D _DAOUT, and a first to third data output terminal of the holding circuit 421C as the first to third data input terminals.
(I.e., the data output terminals Q of the register circuits RGS _{C1 to} RGS _C3 ) and the control input terminal is connected to the third output terminal of the instruction decoder 223D of the control device 23. register circuit RGS _C1 of the holding circuit 421C according to the given input data selection signal SIB ₃ ~
A selector circuit SEL _D2 for selecting one of the input data S _{C1 to} S _C3 given from the RGS _{C 3} and outputting it from the data output terminal D _DBOUT is included.

[0447] The processing circuit 221D first selects the data input terminal D
_BIN is input data selection circuit via data input terminal D _DBIN
The processing start signal input terminal STRT is connected to the second output terminal of the control signal generation circuit 323D of the control device 23 via the processing start signal input terminal STRT _D , and is connected to the data output terminal D _DBOUT of the control device 121D. The signal input terminal AD is the address signal input terminal
It is connected to the fourth output terminal of the instruction decoder 223D of the control device 23 via the AD _D , and the index modification signal input terminal IXS
Controller 23 but via the index modification signal input terminal IXS _D
And the data output terminal D _OUT is connected to the fifth output terminal of the output data selection circuit 321D via the selection switch SW _D11 and the data output terminal D _DOUT. That is, the selector circuits SELECT _D1 to
Is connected to the SELT first data input of _D3), and the processing end signal output terminal END the write signal input terminal of the holding circuit 421D via the selector switch SW _D12 and the write signal output terminal WT _D (i.e. register circuit RGS _{D1 to} RGS _D3 write signal input terminal W
Is connected to T), and the processing end signal output terminal END selection switch SW _D12 and processing end signal output terminal END control of the control unit 23 via the _D signal generator first input terminal and the processing pointer 523 323D It is connected to one input terminal, and an address signal output terminal AD _OUT is connected via an address signal output terminal AD _{DO UT} and the selection switch SW _D13 to the data bus 25, and bus control signals output BCNT _OUT bus control signals The output terminal BCNT is connected to the data bus 25 via the _DOUT and the selection switch SW _D14 , and the data input / output terminal D is connected to the data bus 25 via the data input / output terminal _DD and the selection switch SW _D15.
, And an address signal AD ₃ and an index modification signal IXS ₃ provided from an instruction decoder 223D of the control device 23, and a processing start signal STRT ₃ and an input data selection provided from a control signal generation circuit 323D of the control device 23. A load instruction processing circuit for reading and taking in required unprocessed data S _DBS from the data holding device 26 via the data bus 25 in accordance with the input data S _DBIN given from the circuit 121D.
The 221D _1, are inclusions.

The processing circuit 221D also has a data input terminal D
_DIN Is the data input terminal D_DAINInput data selection circuit via
121D data output terminal D_DAOUT Connected to
Power end D _BIN Is the data input terminal D_DBINInput data selection via
Data output terminal D of selection circuit 121D_{DB OUT} Connected to the
Processing start signal input terminal STRT_D Through
And the second output terminal of the control signal generation circuit 323D of the control device 23
And the address signal input terminal AD is the address signal
Input terminal AD_D Of the instruction decoder 223D of the control device 23 via the
4 and connected to the output of index 4
Terminal IXS is the index modification signal input terminal IXS_DControl via
Connected to the fifth output of the instruction decoder 223D of the device 23,
And the processing end signal output terminal END is selected switch SW_D22 And
And write signal output terminal WT_D Write signal of the holding circuit 421D via
Input terminal (that is, the register circuit RGS_{D 1} ~ RGS_D3 Write signal
Signal input terminal WT) and the processing end signal output terminal END
Is the selection switch SW_D22 And processing end signal output terminal END_DTo
A first input of a control signal generator 323D of the controller 23 via
End and a first input end of the processing pointer 523,
And address signal output terminal AD_OUT Is the address signal output end AD
_DOUTAnd selection switch SW_D23 To data bus 25 via
Connected and bus control signal output terminal BCNT_OUT Is bus control
Signal output terminal BCNT_DOUTAnd selection switch SW_D24 Through
Connected to the data bus 25 and the data input / output terminal D
Data input / output terminal D_D And selection switch SW_{D2 Five} Through the day
Connected to the tabus 25 and the instruction decoder of the controller 23.
Address signal AD given from 223D_Three And index
Qualifier signal IXS_ThreeAnd control signal generation circuit of control device 23
Processing start signal STRT given from 323D_Three And input data
Input data S given from the data selection circuit 121D._DAIN, S
_DBINTo the data holding device 26 via the data bus 25 according to the
Processing data S_DBS ^*Store for sending and retaining
Instruction processing circuit 221D_Two Is included.

The processing circuit 221D further includes a data input terminal D
_BIN is input data selection circuit via data input terminal D _DBIN
The processing start signal input terminal STRT is connected to the second output terminal of the control signal generation circuit 323D of the control device 23 via the processing start signal input terminal STRT _D , and is connected to the data output terminal D _DBOUT of the control device 121D. The signal input terminal AD is the address signal input terminal
It is connected to the fourth output terminal of the instruction decoder 223D of the control device 23 via the AD _D , and the index modification signal input terminal IXS
Controller 23 but via the index modification signal input terminal IXS _D
And the data output terminal D _OUT is connected to the first to third data input terminals of the output data selection circuit 321D through the selection switch SW _D31 and the data output terminal D _DOUT. That is, the selector circuits SELECT _D1 to
Is connected to the SELT first data input of _D3), and the processing end signal output terminal END the write signal input terminal of the holding circuit 421D via the selector switch SW _D32 and the write signal output terminal WT _D (i.e. register circuit RGS _{D1 to} RGS _D3 write signal input terminal W
Is connected to T), and the processing end signal output terminal END selection switch SW _D32 and processing end signal output terminal END control of the control unit 23 via the _D signal generator first input terminal and the processing pointer 523 323D is connected to one input terminal, the control unit address signal AD ₃ given from the instruction decoder 223D of 23 and index modification signals IXS ₃ and a control unit 23 control signal generation circuit processing start signal given from 323D STRT ₃ of And a load effective address instruction processing circuit 221D ₃ for _obtaining and outputting a load effective address in accordance with the input data S _DBIN given from the input data selection circuit 121D.
Is included.

The processing circuit 221D additionally has a data input terminal D
_AIN is input data selection circuit via data input terminal D _DAIN
It is connected to the data output D _DAOUT of 121D, and the data input terminal D _BIN is connected to the data output terminal D _DBOUT the input data selecting circuit 121D via the data input terminal D _DBIN, and process start signal input STRT processing The start signal input terminal STRT _D is connected to the second output terminal of the control signal generation circuit 323D of the control device 23, and the data output terminal D _OUT is connected to the selection switch SW.
_D41 and a data output terminal D _DOUT are connected to the first to third data input terminals of the output data selection circuit 321D (that is, the first data input terminals of the selector circuits SELT _{D1 to} SELT _D3 ), and a processing end signal. Output terminal END is selection switch SW
_D42 and the write signal input terminal of the holding circuit 421D via the write signal output terminal WT _D (i.e. register circuit RGS _D1 ~RGS _D3
Of the control signal generator 323D of the controller 23 via the selection switch _SWD42 and the processing end signal output terminal END _D. and is connected to the first input terminal of the processing pointer 523, control unit 23 of the control signal generating circuit 323D inputs data given from the input data selection circuit 121D according to the process start signal STRT ₃ given from S _DAIN , add instruction processing circuit for adding and outputting S _DBIN mutually 221D ₄
Is included.

The processing circuit 221D has a data input terminal D
_AIN is input data selection circuit via data input terminal D _DAIN
121D is connected to the data output terminal D _DAOUT , the data input terminal D _BIN is connected to the data output terminal D _{DB OUT} of the input data selection circuit 121D via the data input terminal D _DBIN , and the processing start signal input terminal STRT is connected It is connected to the second output terminal of the control signal generation circuit 323D of the control device 23 via the processing start signal input terminal STRT _D , and the data output terminal D _OUT is connected to the selection switch SW.
_D51 and the data output terminal D _DOUT are connected to the first to third data input terminals of the output data selection circuit 321D (that is, the first data input terminals of the selector circuits SELT _{D1 to} SELT _D3 ), and the processing end signal Output terminal END is select switch SW
_D52 and the write signal input terminal of the holding circuit 421D via the write signal output terminal WT _D (i.e. register circuit RGS _D1 ~RGS _D3
Is connected to the write signal input terminal WT), and the processing end signal output terminal END first input terminal of the control signal generator 323D of the selection switch SW _D52 and processing end signal output terminal END via the _D control unit 23 and processing are connected to the first input terminal of the pointer 523, corresponding to the control unit 23 of the control signal generating circuit 323D treatment given from the start signal STRT ₃ and the input data selecting circuit input data S _DBIN given from 121D Arithmetic shift left instruction processing circuit 22 for shifting the input data S _DAIN given from the input data selection circuit 121D to the left and outputting the shifted data.
1D ₅ is included.

[0452] processing circuit 221D, taken together, an instruction of the control unit 23 input via the circuit selection signal input terminal SC _D decoder 22
It is connected to the first output terminal of the 3D, and the first to fifth output terminals respectively selecting switch SW _D11 ~SW _D15; SW _D22 ~SW
_{D25; SW D31 ~SW D32; SW} D41 ~SW D42; SW D51 ~SW D52 is connected to, select the decrypted decoding result of the circuit selection signal SC ₃ given from the instruction decoder 223D of the control unit 23 signals SC
Select switches SW _{D11 to} SW _D15 as _{D1 to} SC _D5 ; SW
_{D22 to} SW _D25 ; SW _{D31 to} SW _D32 ; SW _{D41 to} SW _D42 ; SW _{D51 to} SW
Given to _D52 , load instruction processing circuit 221D ₁ , store instruction processing circuit 221D ₂ , load effective address instruction processing circuit 221D ₃ , addition instruction processing circuit 221D ₄ and arithmetic left shift instruction processing circuit 221D
Decoder DECD _D for selecting any one of ₅
Have a wrap.

[0453] Output data selection circuit 321D is a fourth output data selection signal SO ₃ provided from the connected and instruction decoder 223D decodes the decoded results to the output terminal of the instruction decoder 223D of the input end control unit 23 selection signal SO _D1 and decoder DEC _D for outputting as to SO _D3, first the first data input terminal connected to the data output terminal D _DOUT processing circuit 221D and a second data input terminal holding circuit 421C the data output (i.e. register circuit RGS data output terminal Q of the _C1) selection signal SO _D1 that is connected to and controlled input to is given from the decoder DEC _D is connected to the first output of the decoder DEC _D is active (i.e. "1") processing circuit selects the output data S _D supplied from 221D outputs as output data S _D1 and selection signals SO _D1 supplied from the decoder DEC _D is inactive (i.e., when the "0 ”) Hold circuit 421C The selector circuit SELT _D1 for outputting the register circuits RGS input data S _C1 applied from _C1 as selects and outputs data S _D1
The first data input terminal is connected to the data output terminal _DOUT of the processing circuit 221D and the second data input terminal is connected to the holding circuit 42.
1C second data output terminal (ie, register circuit RGS _C2
Process when the selection signal SO _D2 that is connected to and controlled input to the data output terminal Q) is given from the decoder DEC _D is connected to the second output terminal of the decoder DEC _D of the active (i.e., "1") register circuits holding circuits 421C when the output is and the selection signal SO _D2 is inactive given from the decoder DEC _D selects the output data S _D provided from the circuit 221D as output data S _D2 (i.e. "0") A selector circuit SELT _D2 for selecting the input data S _C2 given from RGS _C2 and outputting it as output data S _D2 , a first data input terminal connected to the data output terminal D _DOUT of the processing circuit 221D, and the third data output (i.e. the data output terminal Q of the register circuit RGS _C3) is connected to and the control input of the second data input terminal holding circuit 421C is connected to the third output terminal of the decoder DEC _D Given from the cage decoder DEC _D Selected signal
When SO _D3 is active (ie, “1”), it selects the output data S _D given from the processing circuit 221D, outputs it as output data S _D3 , and selects the selection signal SO given from the decoder DEC _{D
When D3} is inactive (ie, "0"), a selector circuit for selecting the input data S _C3 given from the register circuit RGS _C3 of the holding circuit 421C and outputting it as output data S _D3
SELT _D3 .

[0454]Configuration of control device 23 (see FIGS. 38A to 49)
See)

The control device 23 has a data input terminal connected to the data output terminal DATA of the program holding device 24, and the instructions INST _{0 to} IN given from the program holding device 24.
Instruction registers 123A to 123D for holding ST ₃ respectively
The data input terminals are connected to the data output terminals of the instruction registers 123A to 123D, respectively.
The instructions INST _{0 to} INST ₃ held in the memory are decoded, and various decoding signals (that is, address signals AD _{0 to} AD ₃ , index modification signals IXS _{0 to} IXS ₃ , circuit selection signals SC _{0 to} SC ₃ , input data selection) signal _{SIA 0 ~SIA 3; SIB 0 ~SIB} 3, the output data selection signal SO ₀ to SO ₃₎ an instruction decoder for generating 223A
223D and a first output terminal (that is, a write signal output terminal) is connected to a write signal input terminal of each of the instruction registers 123A to 123D, and the first input terminal is connected to a processing circuit 221A to a processing block 21A to 21D. 221D of the processing end signal output terminal eND _a ~END _D process end signals provided from the processing circuit 221A~221D each connected to and processing blocks 21A ～21D the eND ₀ ~END various control signals in accordance with the ₃ ( That is, the write signals WT _{0 to} W
T ₃ , processing start signals STRT _{0 to} STRT ₃ , increment signal INC
P _{0 to} INCP ₃ and shift signal SFTC _{0 to} SFTC ₃ ), and control signal generation circuits 323A to 323D for generating and outputting from the first to fourth output terminals, respectively.
The first to fourth input terminals are respectively connected to the fourth output terminal of the 323D, and the first to fourth output terminals are connected to the second input terminals of the control signal generation circuits 323A to 323D, respectively. block 21A ～21D processing circuit 221A~221D desired control signal generating circuit constructed (here selection) generates a building instruction signal CPQ ₀ ~CPQ ₃ for instructing the operation circuit in 323A
Construction pointer 423 for providing the ～323D, processing block 21A ～21D processing circuit to process end signal output terminal END _A ~END first to fourth input terminals to the _D of 221A~221D is by and first not connected The fourth output terminal is a control signal generation circuit 32.
Processing block 21A when the third processing from the processing circuit 221A~221D each connected to and processing blocks 21A ～21D to an input end signal END ₀ ~END ₃ of 3A~323D given to 21
D generates processing command signals PPQ _{0 to} PPQ ₃ for instructing the processing in the processing circuits 221A to 221D to generate control signal generation circuits 323A to 323.
A processing pointer 523 for giving to 3D, and first to fourth input terminals connected to third output terminals of the control signal generation circuits 323A to 323D, respectively, and an output terminal is connected to the program holding circuit 24.
INST _{0 to} INST
₃ and a program counter 623 for generating an address signal PC for notifying the end of reading and requesting the reading of the next instruction and for giving the same to the program holding device 24.

The instruction registers 123A to 123D store a plurality of bits (for example, 32 bits) given from the program holding device 24.
INST _{0 to} INST ₃ may be provided, and a well-known register may be employed as desired.

[0457] Instruction decoder 223A is output to the processing circuit 221A of the processing block 21A from the sixth output terminal as it is as the address signal AD ₀ the first bit to the 16th bit of the instruction INST ₀ given from the instruction register 123A And the instruction IN
The 17th to 20th bits of ST ₀ are processed by the OR circuit OR _3A to generate an index modification signal IXS ₀ , which is then output from the fifth output terminal to the processing circuit 221A of the processing block 21A, and the instruction INST ₀ the 17th bit to the 20th bit as the input data selection signal SIB ₀ towards the input data selection circuit 121A of the processing block 21A from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₀ output data selection circuit as input data selection signal SIA ₀ as a second output towards the input data selection circuit 121A of the processing block 21A from the output end and the processing from the fourth output terminal as an output data selection signal SO ₀ blocks 21A and output to the 321A, the first output to generate a circuit selection signal SC ₀ from the data output terminal dATA giving the address inputs AD of the 25th bit to 32nd bit conversion table circuit TBL _3A instruction INST ₀ Processing circuitry included in the processing block 21A of the processing apparatus 21 from
Towards the circuit selection signal input terminal SC _A of 221A has a structure of outputting.

The instruction decoder 223B outputs the _first to sixteenth bits of the instruction INST ₁ given from the instruction register 123B as it is as an address signal AD1 from the sixth output terminal to the processing circuit 221B of the processing block 21B. And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₁ in OR circuit OR _3B outputs toward the fifth output After generating an index modified signal IXS ₁ to the processing circuit 221B of the processing block 21B, the instruction INST ₁ the output toward the input data selection circuit 121B of the 17th bit to the third output terminal from the processing block 21B the first 20 bits directly as input data selection signal SIB _1, the first 21 bits to 24 bits of instruction INST ₁ output data selection circuit as input data selection signal SIA ₁ as a second output towards the input data selection circuit 121B of the processing block 21B from the output end and the output data selection signal SO ₁ as a fourth output from the processing block 21A and output to the 321B, a first output to generate a circuit selection signal SC ₁ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₁ to the address input AD of the conversion table circuit TBL _3B Processing circuitry included in the processing block 21B of the processing apparatus 21 from
Towards the circuit selection signal input terminal SC _B of 221B has a structure of outputting.

[0459] Instruction decoder 223C is output to the sixth output terminal of the first bit to the 16th bit of the instruction INST ₂ given from the instruction register 123C as it address signal AD ₂ to the processing circuit 221C of the processing block 21C And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₂ in OR circuit OR _3C outputs toward the fifth output After generating an index modified signal IXS ₂ to the processing circuit 221C of the processing block 21C, the instruction INST ₂ the 17th bit to the 20th bit as the input data selection signal SIB ₂ towards the input data selection circuit 121C of the processing block 21C from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₂ output data selection circuit as the input data selection signal SIA ₂ as a second input data selecting circuit towards 121C outputs processing block 21C from the output end and the processing from the fourth output terminal as an output data selection signal SO ₂ blocks 21C and output to the 321C, a first output to generate a circuit selection signal SC ₂ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₂ to an address input terminal AD of the conversion table circuit TBL _3C Processing circuitry included in the processing block 21C of the processing unit 21 from
Towards the circuit selection signal input terminal SC _C of 221C has a structure of outputting.

[0460] Instruction decoder 223D is outputted to the sixth output terminal of the first bit to the 16th bit of the instruction INST ₃ given from the instruction register 123D as it is as the address signal AD ₃ to the processing circuit 221D processing block 21D And the instruction IN
Processing the 17th bit to the 20th bit of the ST ₃ in OR circuit OR _3D output toward the fifth output After generating an index modified signal IXS ₃ to the processing circuit 221D of the processing block 21D, the instruction INST ₃ the 17th bit to the 20th bit as the input data selection signal SIB ₃ toward the input data selection circuit 121D processing block 21D from the third output terminal and the output of the first 21 bits to 24 bits of instruction INST ₃ output data selection circuit as the input data selection signal SIA ₃ as a second input data selecting circuit towards 121D and output of the processing block 21D from an output end and a fourth processing from the output terminal block 21D as an output data selection signal SO ₃ and output to the 321D, a first output to generate a circuit selection signal SC ₃ from the data output terminal dATA giving 25th bit to 32nd bit of the instruction INST ₃ in the conversion table circuit TBL _3D the address inputs AD Processing circuitry included in the processing block 21D of the processing apparatus 21 from
Towards the circuit selection signal input terminal SC _D of 221D has a configuration of outputting.

The control signal generating circuit 323A has an AND circuit AND _3A1 having one input terminal connected to the first output terminal of the construction pointer 423, a data input terminal A connected to the output terminal of the AND circuit AND _3A1 , and A shift register SR _3A having a clock input CK connected to a clock signal source (not shown) and a clear input connected to a reset signal source (not shown);
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3A of the shift register SR _3A Write signal WT ₀ and increment signal
AND circuit the AND _3A2 for providing instructions to output the INCP ₀ from the output terminal registers 123A and respectively to the program counter 623, a second output Q ₂ and the third inverting output terminal of the shift register SR _3A Q ₃ ^* in the aND circuit for providing the second output and the third inverting output is outputted from the output terminal of the shift signal SFTC ₀ which becomes high level when both the high-level construction pointer 423 of the shift register SR _3A is connected _3A3 and one input terminal is a third output terminal of the processing circuit 221A of the processing block 21A (that is, the processing end signal output terminal EN
D _A ) and the other input terminal is connected to the reset signal source, and the processing end signal END ₀ or the reset signal RESET given from the processing circuit 221A of the processing block 21A is at a high level (that is, “1”). when the OR circuit OR _3A1 for delivering high-level output signal from the output terminal, without a clock input terminal CK is connected to the output terminal of the aND circuit the aND _3A3 and the data input D is high level signal source (not ) And the clear input terminal CLR is connected to the output terminal of the OR circuit OR _3A1 , and the constructed flag signal generating circuit CENDF _3A for outputting the constructed flag signal CENDF ₀ from the output terminal Q;
The clock input CK is connected to the third output of the processing circuit 221A of the processing block 21A (that is, the processing end signal output END _A ) and the data input is connected to a high level signal source (not shown); Clear input terminal CLR is AND circuit AND
_3A3 is connected to the output terminal, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the AND circuit AND _3A1.
And a processed flag signal generating circuit PENDF _3A for generating a processed flag signal PENDF ₀ from an output terminal Q and an output terminal Q of a constructed flag signal generating circuit CENDF _3A . An input terminal is connected and the other input terminal is connected to the first output terminal of the processing pointer 513, and the processing start signal STRT which becomes high when the constructed flag signal CENDF ₀ and the processing command signal PPQ ₀ are high. _An AND circuit AND _3A4 for outputting ₀ from the output terminal to give to the processing circuit 221A of the processing block 21A is included.

The control signal generation circuit 323B has an AND circuit AND _3B1 having one input terminal connected to the second output terminal of the construction pointer 423, a data input terminal A connected to the output terminal of the AND circuit AND _3B1 , and A shift register SR _3B having a clock input CK connected to a clock signal source (not shown) and a clear input connected to a reset signal source (not shown);
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3B of the shift register SR _3B Write signal WT ₁ and increment signal
AND circuit the AND _3B2 for providing instructions to output the INCP ₁ from the output end register 123B and the program counter 623, respectively, the second output terminal Q ₂ and the third inverting output terminal of the shift register SR _3B Q ₃ ^* in the aND circuit for providing the second output and the third inverting output is outputted from the output terminal of the shift signal SFTC ₁ together a high-level high when building the pointer 423 of the shift register SR _3B is connected _3B3 and one input terminal is a third output terminal of the processing circuit 221B of the processing block 21B (that is, the processing end signal output terminal EN
D _B) connected to and the other input terminal is given from the processing circuit 221B of the processing block 21B is connected to a reset signal source processing end signal END ₁ or a reset signal RESET is high (i.e. "1") An OR circuit OR _3B1 for transmitting a high-level output signal from the output terminal, a clock input terminal CK is connected to an output terminal of the AND circuit AND _3B3 , and a data input terminal D is connected to a high-level signal source (not shown). connected and clear input terminal and a built flag signal generating circuit CENDF _3B for outputting the constructed flag signal CENDF ₁ from the output terminal Q is connected to an output terminal of the OR circuit OR _3B1 in), the clock input CK Is the third of the processing circuit 221B of the processing block 21B.
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3B3 output (i.e. processing end signal output terminal END _B) is connected to and the data input terminal to a high level signal source (not shown) of Further, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the other input terminal of the AND circuit AND _{3 B1.}
Processed flag signal generation circuit PEND for generating PENDF ₁
F _3B and the output terminal Q of the constructed flag signal generation circuit CENDF _3B
Is connected to one input terminal and the other input terminal is connected to the second output terminal of the processing pointer 523, and becomes a high level when the constructed flag signal CENDF ₁ and the processing command signal PPQ ₁ are at a high level. an aND circuit the aND _3B4 for providing to the processing circuit 221B outputs to the processing block 21B from the output end of the start signal STRT _1, are inclusions.

The control signal generating circuit 323C has an AND circuit AND _3C1 having one input terminal connected to the third output terminal of the construction pointer 423, a data input terminal A connected to the output terminal of the AND circuit AND _3C1 , and a shift register SR _3C clock input CK is a clock signal source connected to a (not shown) and the clear input connected to a reset signal source (not shown),
First output Q ₁ and the first output and the second inverting output are both high-level high-level when the second inversion output terminal Q ₂ ^* is connected to the shift register SR _3C of the shift register SR _3C Write signal WT ₂ and increment signal
AND circuit the AND _3C2 for providing respectively the INCP ₂ into the instruction register 123C and the program counter 623 and outputs from an output terminal, a second output Q ₂ and the third inverting output terminal of the shift register SR _3C Q ₃ ^* in the aND circuit for providing the second output and the third inverting output outputs a shift signal SFTC ₂ together a high-level high-level when the output terminal building pointer 423 of the shift register SR _3C is connected _3C3 and one input terminal is a third output terminal of the processing circuit 221C of the processing block 21C (that is, the processing end signal output terminal EN
D _C ) and the other input terminal is connected to the reset signal source, and the processing end signal END ₂ or the reset signal RESET given from the processing circuit 221C of the processing block 21C is at a high level (that is, “1”). An OR circuit OR _3C1 for transmitting a high-level output signal from the output terminal, a clock input terminal CK is connected to an output terminal of the AND circuit AND _3C3 , and a data input terminal D is a high-level signal source (not shown). ) And the clear input terminal is connected to the output terminal of the OR circuit OR _3C1 , and the constructed flag signal generating circuit CENDF _3C for outputting the constructed flag signal CENDF ₂ from the output terminal Q, and the clock input terminal CK Is the third of the processing circuit 221C of the processing block 21C.
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3C3 output (i.e. processing end signal output terminal END _C) is connected to and the data input terminal to a high level signal source (not shown) of Further, the preset input terminal PR is connected to the reset signal source, and the output terminal Q is connected to the other input terminal of the AND circuit AND _{3 C1.}
Processed flag signal generation circuit PEND for generating PENDF ₂
And F _3C, constructed flag signal generating circuit CENDF _3C one input terminal is connected and the other third of the connected and constructed flag signal to an output terminal of the input end processing pointer 523 to the output terminal of CENDF ₂ and processing instruction signal PPQ ₂ is an aND circuit the aND _3C4 for providing the processing circuit 221C outputs the processing block 21C from the output end of the process start signal STRT ₂ serving as a high-level high-level when, and inclusions.

The control signal generation circuit 323D has an AND circuit AND _3D1 having one input terminal connected to the fourth output terminal of the construction pointer 423, a data input terminal A connected to the output terminal of the AND circuit AND _3D1 , and a shift register SR _3D clock input CK is a clock signal source connected to a (not shown) and the clear input connected to a reset signal source (not shown),
First output Q ₁ and the second inverting output terminal Q ₂ ^* in the connected and the first shift register SR _3D output and the second inverting output are both high-level high-level when the shift register SR _3D Write signal WT ₃ and increment signal
AND circuit AND that outputs INCP ₃ from the output terminal and supplies it to the instruction register 123D and the program counter 623, respectively.
_3D2 and the second output terminal Q ₂ and the third inverted output terminal Q ₃ ^* of the shift register SR _3D and the shift register
An AND circuit AN for outputting a shift signal SFTC ₃ which becomes a high level when both the second output and the third inverted output of the SR _3D are at a high level from the output terminal and supplies it to the construction pointer 423
_D3D3 and one input terminal is a processing circuit 22 of a processing block 21D.
Third output terminal of 1D (ie, processing end signal output terminal END _D )
And the other input terminal is connected to the reset signal source. When the processing end signal END ₃ or the reset signal RESET given from the processing circuit 221D of the processing block 21D is at a high level (that is, “1”), the output terminal is Circuit OR _3D1 for transmitting a high-level output signal from the OR, a clock input terminal CK is connected to an output terminal of an AND circuit AND _3D3 , and a data input terminal D is connected to a high-level signal source (not shown). And the clear input terminal CLR is connected to the output terminal of the OR circuit OR _3D1 , and the constructed flag signal generating circuit CENDF _3D for outputting the constructed flag signal CENDF ₃ from the output terminal Q and the clock input terminal CK are processed. Third of processing circuit 221D of block 21D
Connected and the clear input terminal CLR is connected to the output terminal of the AND circuit the AND _3D3 output (i.e. processing end signal output terminal END _D) is connected to and the data input terminal to a high level signal source (not shown) of The preset input terminal PR is connected to the reset signal source, the output terminal Q is connected to the other input terminal of the AND circuit AND _3D1 , and the processed flag signal is output from the output terminal Q.
Processed flag signal generation circuit PEND for generating PENDF ₃
F _3D and the output terminal Q of the constructed flag signal generation circuit CENDF _3D
Is connected to the fourth output terminal of the processing pointer 523, and has a high level when the constructed flag signal CENDF ₃ and the processing command signal PPQ ₃ are at a high level. an aND circuit the aND _3D4 for providing to the processing circuit 221D outputs the processing block 21D from the output end of the start signal STRT _3, are inclusions.

[0465] Construction pointer 423, a fourth output end (i.e. the AND circuit the AND _3A3 output end of ~AND _3D3) connected to it has control of the first to fourth input terminals respectively control signal generating circuit 323A~323D an oR circuit oR ₄ for outputting a high level signal when any one of the signal generating circuit shift signal given from 323A~323D SFTC ₀ ~SFTC ₃ became high, the clock input terminal CK is oR circuit The output terminal of OR ₄ and the preset input terminal PR are connected to a reset signal source (not shown).
A flip-flop FF ₄₀ for outputting the constructed command signal CPQ ₀ to command to build a desired operation circuit to the processing circuit 221A of the A, and clears the clock input terminal CK is connected to the output terminal of the OR circuit OR ₄ input CLR is connected to the reset signal source and the output terminal of the input terminal D flip-flop FF ₄₀ Q
And a flip-flop FF ₄₁ for outputting a construction command signal CPQ ₁ from the output terminal Q to the processing circuit 221B of the processing block 21B to instruct a desired arithmetic circuit.
When the clock input terminal CK is OR circuit connected to the output terminal of the OR ₄ and the clear input terminal CLR is connected to the reset signal source and the connected and an output terminal Q to the output terminal Q of the input terminal D flip-flop FF ₄₁ To processing block 221C of processing block 21C
Desired flip-flop FF ₄₂ for outputting the constructed command signal CPQ ₂ for commanding to construct an arithmetic circuit, a clock input terminal CK is connected to the output terminal of the OR circuit OR ₄ and the clear input terminal CLR is reset processing circuit of the signal source connected to and input terminal D flip-flop FF ₄₂ output end is connected to the Q and the output terminal Q flip-flop processed from a connected and an output terminal Q to the input terminal D of the FF ₄₀ block 21D 221D Command CP for instructing the user to construct a desired arithmetic circuit
A flip-flop FF ₄₃ for outputting a Q _3, are inclusions.

The processing pointer 523 has a first to fourth input terminals each of which corresponds to the processing circuit 221A of the processing blocks 21A to 21D.
To 221D (ie, the processing end signal output terminal EN
_{D A} ~END D) any one of the processing end signal END ₀ ~END ₃ given from the connected and processing circuitry 221A~221D to but OR circuit for outputting a high level signal when a high level OR ₅ and the clock input terminal CK are connected to the output terminal of the OR circuit OR ₅ and the preset input terminal PR is connected to the reset signal source (not shown). From the output terminal Q to the processing circuit 221A of the processing block 21A. A flip-flop FF ₅₀ for outputting a processing command signal PPQ ₀ for instructing execution of a desired arithmetic processing in the constructed arithmetic circuit, and a clock input terminal CK.
Is connected to the output terminal of the OR circuit OR ₅ and the clear input terminal CL
R performs a desired operation processing by the arithmetic circuit is connected to the reset signal source and the input terminal D is constructed from the output terminal Q is connected to an output terminal Q of the flip-flop FF ₅₀ to the processing circuit 221B of the processing block 21B Processing command signal
A flip-flop FF ₅₁ for outputting the PPQ _1, a clock input terminal CK is connected to the output terminal of the OR circuit OR ₅ and clear input terminal CLR is connected to the reset signal source and the input terminal D
And outputs the processed command signals PPQ ₂ to command but to perform desired processing by the arithmetic circuit constructed from a connected and an output terminal Q to the output terminal Q to the processing circuit 221C of the processing block 21C of the flip-flop FF ₅₁ Flip-flops for FF ₅₂
If, connected and an output terminal Q to the output terminal Q of the clock input CK is connected to the output terminal of the OR circuit OR ₅ and clear input terminal CLR is connected to the reset signal source and the input terminal D flip-flop FF ₅₂ is processing circuit of the processing block 21D from a connected and an output terminal Q to the input terminal D of the flip-flop FF ₅₀
A flip-flop FF ₅₃ for outputting a processing instruction signal PPQ ₃ for commanding to perform a desired operation processing by the arithmetic circuit constructed 221D, are inclusions.

The program counter 623 has its first to fourth input terminals connected to the third output terminals of the control signal generation circuits 323A to 323D (ie, the output terminals of the AND circuits AND _{3A2 to} AND _3D2 ). an oR circuit oR ₆ for outputting a high level signal when any one of the signal generating circuit increment signal supplied from 323A~323D INCP ₀ ~INCP ₃ became high, the clock input terminal CK is oR circuit
The output terminal of OR ₆ and the clear input terminal CLR are connected to a reset signal source (not shown), and the first to sixteenth output terminals Q _{0 to} Q ₁₅ are connected to the address input terminal AD of the program holding circuit 24. Are connected and the output signals PC _{0 to} PC ₁₅ are used as the address signals PC as the address input terminals AD of the program holding circuit 24.
And a counter CNT ₆ for supplying the counter CNT.

Detailed Configuration of Processing Circuits 221A-221D Load
Instruction processing circuit (see Fig. 50)

In the load instruction processing circuit 221 _X1 , the load input terminal LD is connected to the processing start signal input terminal STRT, the data input terminal D is connected to a constant generation source (not shown), and the output terminal Q is processed. The control signal generating circuit 323X of the control device 23 sends a processing start signal ST
Counting contents starts a subtraction operation captures constants applied to data input terminal D depending on the RT _i is given is "0"
, A down counter DCNT for outputting a processing end signal _SENDXi from the output terminal Q via the processing end signal output terminal END (X = A to D; i = 0 to 3;
The same applies hereinafter).

[0470] load instruction processing circuit 221 _X1 is also a data input terminal D _BIN is connected to the data input terminal B data input terminal A is to connected and the address signal input terminal AD to the data input terminal D _BIN ( That is, the input data S _{XB IN supplied} to the data input terminal A) and the address signal input terminal AD
(I.e. data input B) and the adder ADD to output the address signal AD _i given to adding to the output terminal F to each other, the first input terminal the address signal input terminal AD
And the second input is connected to the output F of the adder ADD and the output is the address signal output.
Is connected to AD _OUT and the adder when the index modification signals IXS _i given from the instruction decoder 223X of the switching signal input terminal index modification signal input IXS connected to it and the controller 23 is active (i.e. "1") The output of ADD is output as the address signal AD _{XBS from the} address signal output terminal AD _OUT to the data bus 25 via the address signal output terminal AD _XOUT , and the index modification signal IXS _i provided from the instruction decoder 223X of the control device 23. as the address signal AD _XBS but the address signal AD _i given from the instruction decoder 223X of the controller 13 when the non-active (i.e. "0")
And a selector circuit SELT for outputting from the address signal output terminal AD _OUT to the data bus 25 via the address signal output terminal AD _XOUT .

[0471] load instruction processing circuit 221 _X1 is further bus control signal output terminal BCNT _OUT bus control signals output from the bus control signal output terminal BCNT _OUT output terminal are connected to
Read signal READ _XBS to data bus 25 via BCNT _XOUT
A bus control signal generation circuit BCNTL for outputting the data output terminal D _OUT to the connected data output terminal D to the data bus 25 is connected from the data bus 25 through the data input terminal D _X The unprocessed data DAT _XBS (ie, S _XBS ) given to the data input / output terminal D is used as it is as the output data S _X1 from the data output terminal D _OUT to the output data selection circuit.
Data transfer circuit DTRF for outputting to 321X,
Have a wrap.

Detailed Configuration of Processing Circuits 221A-221D--Store
Instruction processing circuit (see Fig. 51)

In store instruction processing circuit 221 _X2 , load input terminal LD is connected to processing start signal input terminal STRT, data input terminal D is connected to a constant generation source (not shown), and output terminal Q is processed. The constant which is connected to the signal output terminal END and which is given to the data input terminal D when the processing start signal STRT _i is given from the control unit 23 to the processing start signal input terminal STRT (therefore, the load input terminal LD). To start the subtraction operation, and when the counted content becomes "0", the processing end signal S _ENDXi from the output terminal Q via the processing end signal output terminal END.
Has a down counter DCNT for outputting
(X = A to D; i = 0 to 3; the same applies hereinafter).

[0474] store instruction processing circuit 221 _X2 also data input D _BIN is connected to the data input terminal B data input terminal A is to connected and the address signal input terminal AD to the data input terminal D _BIN ( That is, the input data S _{XB IN applied} to the data input terminal A) and the address signal input terminal AD
(I.e. data input B) and the adder ADD to output the address signal AD _i given to adding to the output terminal F to each other, the first input terminal the address signal input terminal AD
And the second input is connected to the output F of the adder ADD and the output is the address signal output.
AD _OUT connected to and switching signal input terminal index modification signal input IXS connected to the index given from which the control unit 23 modified signal IXS _i is the output of the adder ADD when active (i.e. "1") Address signal AD _XBS
Control when the address signal output terminal AD _OUT address signal output terminal toward the data bus 25 via an AD _XOUT outputs and controller index modification signal IXS _i given from 23 non-active (i.e. "0") as The address signal AD _{i supplied} from the device 23 is directly used as the address signal AD _{XBS from the} address signal output terminal AD _OUT to the address signal output terminal AD.
_And a selector circuit SELT for outputting to the data bus 25 via _XOUT .

Store instruction processing circuit 221_X2 The bus
Control signal output terminal BCNT_OUT Output terminal is connected to
Bus control signal output terminal BCNT_OUT From the bus control signal output terminal
BCNT _XOUTWrite signal WT to the data bus 25 via_XBS To
Bus control signal generation circuit BCNTL for output and data
Data input to data input / output terminal D connected to bus 25
Edge D_AIN Is connected and the data input terminal D_AIN Given to
Input data S_XAINThe processed data DAT as it is
_XBS ^*(Ie S_XBS ^*) From the data input / output terminal D
Data input / output terminal D_X Output to data bus 25 via
And a data transfer circuit DTRF for storing the data.

Detailed Configuration of Processing Circuits 221A-221D--Load
Effective address instruction processing circuit (see FIG. 52)

Load effective address instruction processing circuit 221 _X3
Has a load input terminal LD connected to a processing start signal input terminal STRT, a data input terminal D connected to a constant generation source (not shown), and an output terminal Q connected to a processing end signal output terminal END. When the processing start signal STRT _i is supplied from the control device 23 to the processing start signal input terminal STRT (and, consequently, the load input terminal LD), the constant given to the data input terminal D is fetched and the subtraction operation is started. A down counter DCNT for outputting the processing end signal _SENDXi from the output terminal Q via the processing end signal output terminal END when it becomes "0"
(X = A to D; i = 0 to 3; the same applies hereinafter).

Load effective address instruction processing circuit 221 _X3
The data input terminal A is connected to the data input terminal D _BIN and the data input terminal B is connected to the address signal input terminal AD, and is applied to the data input terminal D _BIN (that is, the data input terminal A). An adder ADD for adding the input data S _XBIN and the address signal AD _{i supplied} to the address signal input terminal AD (that is, the data input terminal B) to each other, and outputting the result from the output terminal F; The input terminal is connected to the address signal input terminal AD, the second input terminal is connected to the output terminal F of the adder ADD, the output terminal is connected to the data output terminal _DOUT , and the switching signal input terminal is connected. Connected to the index modification signal input terminal IXS
Index modification signal given from IXS _i is active (i.e. "1") output data S _X3 the output of the adder ADD when
From the data output terminal D _OUT via the data output terminal D _XOUT and outputted to the output data selection circuit 311X and the index modifying signal IXS _i supplied from the control unit 23 is inactive as
(I.e. "0") the data output terminal D of the address signal AD _i given from the controller 23 as output data S _X3 when
The selector circuit SELT for outputting toward the output data selection circuit 321X through the data output terminal D _XOUT from _OUT, are inclusions.

Detailed Configuration of Processing Circuits 221A-221D--Addition Order
Command processing circuit (see Fig. 53)

In addition instruction processing circuit 221 _X4 , load input terminal LD is connected to processing start signal input terminal STRT, data input terminal D is connected to a constant generation source (not shown), and output terminal Q is processed. The constant which is connected to the signal output terminal END and which is given to the data input terminal D when the processing start signal STRT _i is given from the control unit 23 to the processing start signal input terminal STRT (therefore, the load input terminal LD). , A down counter DCNT for outputting a processing end signal _SENDX4 from the output terminal Q via the processing end signal output terminal END when the count content becomes "0".

In addition instruction processing circuit 221 _X4 , data input terminals D _AIN and D _BIN are connected to data input terminals A and B, respectively, and output terminal F is connected to data output terminal D _OUT. Data input terminals D _AIN , D from circuit 121X
_BIN (that is, data input terminals A and B) and the input data S _XAIN and S _XBIN given _thereto are added to each other, and the addition result is output to the output terminal F
Adder AD for outputting to the output data selection circuit 321X via the data output terminal D _OUT as output data S _X4
D.

Detailed configuration of processing circuits 221A to 221D: arithmetic left
Shift instruction processing circuit (see FIG. 54)

[0483] Arithmetic left shift instruction processing circuit 221 _X5 is load input terminal LD to processing start signal input STRT is connected and the data input terminal D _AIN to a data input terminal D connected and shifted to the data input terminal D _BIN The signal input terminal SFT is connected, the processing end signal output terminal END is connected to the processing end signal output terminal ED, and the data output terminal D _OUT is connected to the output terminal F and the data input terminal D _AIN. When the start signal STRT _i is _supplied , the first to fifteenth bits of the input data S _{XAIN supplied} to the data input terminal D _AIN are fetched and held therein, and then the data input terminal D _BIN
Is shifted to the left in accordance with the input data S _XBIN provided to the data input terminal D _AIN and output as output data S _X5 by adding the 16th bit of the input data S _XAIN provided to the data input terminal D _AIN. In addition, a shift register SR for outputting the processing end signal _SENDX5 from the processing end signal output terminal ED via the processing end signal output terminal END after the output of the output data S _X5 is included.

(Operation of the Second Embodiment)

Further, referring to FIGS. 28 to 54,
Regarding a second embodiment of the computer according to the present invention,
The operation will be described in detail. Here, the instructions INST _{0 to} IN
ST ₃ is the data holding device 2 in the 1st to 16th bits.
The information of the holding position (that is, address) of the unprocessed data or the processed data in 6 is held as operand 3, and the processing block 21A is stored in the 17th to 20th bits.
Register circuit RG of holding devices 421A to 421D included in
S _{A1 to} RGS _A3 ; ・ ・ ・; Operand 2 is the number of RGS _{D1 to} RGS _D3
It retained as the register circuit of the 21-bit to 24-bit processing block 21A ～21D holding device included in _{421A~421D RGS A1 ~RGS A3; ···;} RGS D1 ~RGS D 3 of the number operand 1 It is assumed that the instruction codes of Table 20 are held in the 25th to 32nd bits (FIG. 28)
See).

[0486] Although only the case where the program shown in Table 17 is executed will be described here, the present invention is not intended to be limited to this. The program shown in Table 17 is assumed to be stored in advance on a magnetic disk (not shown), but takes the form shown in Table 18 if it is displayed in hexadecimal. Incidentally, “LD” indicates a “load instruction” and is expressed by an instruction code of “10”. “AD
“D” indicates an “addition instruction” and is represented by an instruction code of “20.” “LEA” indicates a “load effective address instruction” and is represented by an instruction code of “12.” “SLA” indicates “arithmetic left shift instruction” and is expressed by an instruction code of “50”.
“ST” indicates a “store instruction” and is represented by an instruction code of “11”.

[0487]

Table 17 LD RGS1, 100 LD RGS2, 101 ADD RGS1, RGS2 LEA RGS2, 001 SLA RGS1, RGS2 ST RGS1, 102

[0488] Initial operation

In the computer 20 according to the present invention, each "address" of the program holding device 24 is
The program shown in Table 18 held on a magnetic disk (not shown) is automatically given and held, and is held on a magnetic disk (not shown) for each "address" of the data holding device 26. The unprocessed data is automatically given and held.

[0490]

[Table 18]

In the computer 20 according to the present invention, a reset signal RESET is generated from a reset signal source (not shown) when the power is turned on (or the reset button of the input / output device 27 is pressed).

[0492] It is accompanied, in the control device 23, the count content of the counter CNT ₆ of the program counter 623 is cleared, the program holding unit from the program counter 623 24
Indicates an address "0".

[0493] In the construction pointer 423, the flip-flop FF ₄₀ is "1", the output signal (i.e. build command signal) Construction command signal CPQ ₀ of CPQ ₀ ~CPQ ₃ is active
(That is, “1”) and the construction command signals CPQ _{1 to} CPQ
Q ₃ is deactivated (ie, “0”) (see Table 19)
. By the way, the construction pointer 423 indicates the construction command signal CPQ ₀
Therefore, a required arithmetic circuit (here, a load instruction processing circuit) should be constructed in the processing circuit 221A of the processing block 21A, that is, a required arithmetic circuit (here, the load instruction processing circuit) in the processing circuit 221A of the processing block 21A. Is to be selected.

[0494] Similarly, the processing pointer 523, the flip-flop FF ₅₀ is "1", the output signal (i.e. processing instruction signal) processing instruction signal PPQ ₀ of PPQ ₀ ~PPQ ₃ is active (i.e. "1" ) And the processing command signals PPQ ₁ to
PPQ ₃ is deactivated (ie, "0") (see Table 19). That is, the processing pointer 523 is the processing command signal PP
Q ₀ indicates that the processing circuit 221A of the processing block 21A should perform required arithmetic processing (here, execution of a load instruction).

In the control device 23, a control signal generation circuit
Constructed flag signal generation circuit CENDF _{3A to} CE in 323A to 323D
The contents of the NDF _3D are cleared to “0”, and the contents of the processed flag signal generation circuits PENDF _{3A to} PENDF _3D are “1”.
Is set to That is, the control signal generation circuits 323A to 323A
The constructed flag signals CENDF _{0 to} CENDF _{3 in} 3D are all inactive
(That is, “0”), and the processing blocks 21A to 21A to
21D indicates that the required arithmetic circuit has not been constructed (selected here) (see Table 19). The processed flag signals PENDF _{0 to} PEND in the control signal generation circuits 323A to 323D
F ₃ are all being an active (i.e. "1"), required processing in the processing blocks 21A ～21D (i.e. build operation;
Here, a selection operation can be performed (see Table 19).

[0496]

[Table 19]

Construction of processing circuit 221A--Load instruction processing circuit
Selection of 221A ₁

In the control signal generation circuit 323A of the control device 23,
Since the processed flag signal PENDF ₀ and the construction command signal CPQ ₀ given from the construction pointer 423 are both active (ie, “1”) as shown in Table 19, the AND circuit AND
The output of _3A1 becomes active (that is, "1"), and instructs the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the load instruction processing circuit) in the processing block 21A (see FIG. 43).

In the control signal generation circuit 323A of the control device 23,
Since the count content of the shift register circuit SR _3A is cleared by a reset signal RESET, the first to third output Q ₁ to Q ₃ are set to "0", and first to third inverting output Q ₁ ^* ＱQ ₃ ^* are set to “1”.

[0500] The shift register SR _3A, the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3A1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3A becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0501] The shift register SR _3A, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3A1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. This is accompanied, the shift register SR _3A outputs "0" from the first inverted output terminal Q ₁ ^*, and outputs "0" from the second inverting output terminal Q ₂ ^*.

[0502] The shift register SR _3A, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "1" that are given from the AND circuit the AND _3A1 to the data input A to the inside, and outputs "1" from the first output terminal Q _1, and the second output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3A
Inverting output terminal Q ₁ ^* from "0" outputs, and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3A2 is connected to the shift register SR _3A
Is _ANDed between the first output and the second inverted output of the shift register _SR3A , when the first output of the shift register SR3A becomes "1", "1" is output. Therefore, the write signal WT ₀ and the increment signal INCP ₀ output from the control signal generation circuit 323A are both active (ie, “1”) when the first output of the shift register SR _3A becomes “1”. )).

The AND circuit AND _3A3 is provided with a shift register SR _3A
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3A becomes "1", and outputs "1". Therefore, the shift signal SFTC ₀ which is output from the control signal generator circuit 323A, when the second output of the shift register SR _3A becomes "1",
Active (ie, "1").

[0505] As described above, the count value "0" of the program counter 623 is used as the address signal PC as the program holding device.
24, the program holding device 24 outputs the data (that is, the load command) held at the address “0” from the data output terminal DATA as the command INST ₀ , and outputs the command register 123A to the command register 123A. Give to 123D (Table 1
8, see FIGS. 38 and 49).

[0506] Instruction register 123A, this time, since the write signal WT ₀ is given from the control signal generator circuit 323A to the write signal input terminal, upon its rise, instruction INST ₀ given from the program hold unit 24 Is taken in and held. By the way, the instruction registers 123B to 123D receive the write signal from the control signal generation circuits 323B to 323D at the write signal input terminal.
WT ₁ ~WT ₃ is not given (i.e. the write signal WT ₁
~ WT ₃ is inactive), so that the instruction INST ₀ given from the program holding device 24 is not taken in.

[0507] Instruction decoder 223A decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₀ given from the instruction register 123A to an address input terminal AD of the conversion table circuit TBL _3A, decrypts The result is sent from the data output terminal DATA of the conversion table circuit TBL _3A to the circuit selection signal SC _0.
(See FIG. 39). The circuit selection signal SC ₀ is
As shown in Table 20, it is "0" and the processing block 21
A of FIG. 34A and FIG.
B).

[0508]

[Table 20]

[0509] In the processing circuit 221A of the processing block 21A, when the circuit selection signal SC ₀ from the instruction decoder 223A of the control unit 23 is given, the decoder DECD the contents of the circuit selection signal SC ₀ (i.e. circuit number) "0" It decodes the _a, and active only selection signal SC _A1 of the selection signals SC _A1 to SC _A5 (i.e. "1") (see FIGS. 34A and 34B).
Thus, in the processing circuit 221A of the processing block 21A, the selection switches SW _{A11 to} SW _A15 are turned on, and the load instruction processing circuit 221A ₁ is constructed (that is, selected) (see FIGS. 30A, 30B and 50).

[0510] The instruction decoder 223A receives the information (ie, operand 1) held in the 21st to 24th bits of the instruction INST ₀ given from the instruction register 123A as it is, by inputting the input data selection signal SIA ₀ and the output data selection signal. signal
Output as SO ₀ (see FIG. 39). The input data selection signal SIA ₀ and the output data selection signal SO ₀ are provided to the input data selection circuit 121A and the output data selection circuit 321A of the processing block 21A, respectively, and are used as described later.

[0511] The instruction decoder 223A outputs the information (operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 123A as it is, as the input data selection signal SIB ₀ ( (See FIG. 39). Input data selection signal SIB ₀ is applied to input data selection circuit 121A of the processing block 21A, is used as described below.

[0512] The instruction decoder 223A converts the information (that is, operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 123A into an OR circuit.
OR _3A to decode and decode result to index modification signal
It is output as IXS ₀ and given to the load instruction processing circuit 221A ₁ of the processing block 21A (see FIG. 39). The index modification signal IXS ₀ is inactive (ie, “0”) because all of the 17th to 20th bits of the instruction INST ₀ are “0” as is apparent from Table 18, and the index modification is not performed. It is shown that.

[0513] The instruction decoder 223A outputs the information (ie, operand 3) held in the 1st to 16th bits of the instruction INST ₀ given from the instruction register 123A as it is, as an address signal AD ₀ , and the processing block 21A
Give the the load instruction processing circuit 221A ₁ (see FIG. 39).
Address signal AD ₀ indicates the address of the data holding device 26.

The load instruction processing circuit 22 is added to the processing block 21A.
After 1A ₁ is constructed, the control signal generation circuit 323A, the output of the AND circuit the AND _3A3 (i.e. shift signal SFTC ₀₎ is,
Flag signal generation circuit CENDF _3A constructed as clock signal
, And to the processed flag signal generation circuit PENDF _3A as a clear signal (see FIG. 43). Therefore, when the second output of the shift register SR _3A becomes "1", the constructed flag signal generating circuit CENDF _3A outputs a high-level signal (that is, "1") given to the data input terminal D. And hold it, and the built flag signal CENDF ₀
Is active (ie, “1”) as shown in Table 21. When the second output of the shift register SR _3A becomes “1”, the contents of the processed flag signal generation circuit PENDF _3A are cleared, and the processed flag signal PENDF ₀ is displayed in Table 21.
Is inactive (ie, “0”) as shown in FIG. By the way, the output of the AND circuit AND _3A2 of the control signal generation circuit 323A
(That is, the write signal WT ₀ and the increment signal INCP
The time difference between the occurrence time of the output of the generator when and AND circuit the AND _{3A3 0)} (i.e. the shift signal SFTC ₀₎ is the time required for holding the instruction INST ₀ for instruction register 123A, the instruction INST ₀ in the instruction decoder 223A the time required for decryption, is determined by considering the time required for introduction of the selection switch SW _A11 to SW _A15 upon the construction of the load instruction processing circuit 221A ₁ in processing block 21A.

[0515]

[Table 21]

At the construction pointer 423, the control signal generation circuit
Shift signal SFTC given from the AND circuit AND _3A3 of 323A
Counter according to ₀ (that is, flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21B (that is, the construction command signal CPQ ₁ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₂ , and CPQ ₃ become “0”.
(See Table 21 and FIG. 47).

Since the constructed flag signal CENDF ₀ is active (ie, “1”) and the output of the processing pointer 523 (ie, processing command signal) PPQ ₀ is active (ie, “1”), the control signal generating circuit 323A of the aND circuit the aND _3A4 is a process start signal STRT ₀ for instructing processing start of the load instruction processing circuit 221A ₁ processing block 21A and active (i.e. "1") (see FIG. 43). When the processing start signal STRT ₀ is given to the load instruction processing circuit 221A ₁ of the processing block 21A, the load instruction processing circuit 221A _{1 of the} processing block 21A
Executes a load instruction as described later (see FIG. 50).

The load instruction processing circuit 22 of the processing block 21A
When the processing in 1A ₁ (i.e. execution of a load instruction) is completed, the load instruction processing circuit processing block 21A 221A _{1
Activates the} processing end signal S _ENDA1 output from the processing end signal output terminal END (that is, “1”) as described later.
And then, treated as a processing end signal END ₀ through the holding circuit 421A provided in, and the selection switch SW _A12 and processing end signal output terminal END _A as a write signal WT ₀ via the selection switch SW _A12 and the write signal output terminal WT _A A pointer 523 and a control signal generation circuit 323A (FIGS. 30A, 30B, and 34).
A, FIG. 34B and FIG. 50). This is accompanied, in the process pointer 523, the data of the counter (i.e., flip-flop FF ₅₀ ~FF ₅₃₎ is moved, a signal indicating a processing block 21B (i.e. processing command signal) PPQ ₁ is shown in Table 22 Becomes "1" and the other processing command signal PP
Q ₀ , PPQ ₂ and PPQ ₃ become “0” (see FIG. 48). The control in the signal generating circuit 323A, since clearing the output contents held high level is to construct flag signal generating circuit CENDF _3A of the OR circuit OR _3A1, constructed flag signal CENDF ₀ tables 2
As shown in FIG. 2, it becomes inactive (that is, "0"). Further, in the control signal generation circuit 323A, the load instruction processing circuit 22
Since taking "1" from the high-level signal source (not shown) to the processed flag signal generating circuit PENDF _3A by processing end signal END ₀ high level, the processed flag signal PENDF ₀ Table given from 1A ₁ It becomes active (ie, "1") as shown in FIG.

[0519]

[Table 22]

[0520] The program counter 623, when the increment signal INCP ₀ given from the control signal generator circuit 323A becomes active (i.e. "1"), the count value "1" is increased by the program held as the address signal PC Device 24
(See FIG. 49).

Construction of processing circuit 221B ... Load instruction processing circuit
Choice of 221B ₁

In the control signal generation circuit 323B of the control device 23,
Since the processed flag signal PENDF ₁ and the construction command signal CPQ ₁ given from the construction pointer 423 are both active (that is, “1”) as described above as shown in Table 22, the output of the AND circuit AND _3B1 is active ( That is, it becomes "1"), and instructs the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the load instruction processing circuit) in the processing block 21B (see FIG. 44).

[0523] In the control signal generation circuit 323B of the control device 23,
Since the count content of the shift register SR _3B has been cleared by the reset signal RESET, the first to third outputs Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

[0524] The shift register SR _3B, the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3B1 therein, outputs "1" from the first output terminal Q _1. Accordingly, the shift register SR _3B has the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0525] The shift register SR _3B, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3B1 to the data input A to the inside uptake, and outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3B outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* .

[0526] The shift register SR _3B, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "1" that are given from the AND circuit the AND _3B1 to the data input A to the inside, and outputs "1" from the first output terminal Q _1, and the second output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3B
Inverting output terminal Q ₁ ^* from "0" outputs, and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3B2 is connected to the shift register SR _3B
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3B becomes "1", and outputs "1". Therefore, the control signal generator circuit 323B write signal WT ₁ and increment signal is outputted from the INCP _1, when the first output of the shift register SR _3B becomes "1", both active (i.e., "1 )).

The AND circuit AND _3B3 is connected to the shift register SR _3B
And the third inverted output of the shift register SR _3B , the second output of the shift register SR _3B outputs “1” when the second output of the shift register SR _3B becomes “1”. Therefore, the shift signal SFTC ₁ which is output from the control signal generator circuit 323B, when the second output of the shift register SR _3B becomes "1",
Active (ie, "1").

As described above, the count value “1” of the program counter 623 is used as the address signal PC as the program holding device.
Since given to 24 of the address inputs AD, the program holding unit 24 is "1" and the output data held in the address (i.e. the load instruction) from the data output terminal DATA as instructions INST _1, instruction register 123A~ Give to 123D (Table 1
8, see FIGS. 38A, 38B and 49).

[0530] Instruction register 123B, the time, since the write signal WT ₁ is supplied from the control signal generator circuit 323B to the write signal input terminal, upon its rise, the instruction given from the program hold unit 24 INST ₁ Is stored inside. Incidentally, the instruction registers 123A, 123C, and 123D do not receive the write signals WT ₀ , WT ₂ , and WT ₃ from the control signal generation circuits 323A, 323C, and 323D at the write signal input terminals (that is, the write signal WT ₀ , WT ₂ and WT ₃ are inactive), so that the instruction INST ₁ given from the program holding device 24 is not fetched inside.

[0531] Instruction decoder 223B decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₁ given from the instruction register 123B to the address inputs AD conversion table circuit TBL _3B, decryption The result is sent from the data output terminal DATA of the conversion table circuit TBL _3B to the circuit selection signal SC _1.
(See FIG. 40). The circuit selection signal SC ₁ is
As shown in Table 20, it is "0" and the processing block 21
B of FIG. 35A and FIG.
B).

[0532] In the processing circuit 221B of the processing block 21B, when the circuit selection signal SC ₁ from the instruction decoder 223B of the controller 23 is given, the decoder DECD the contents of the circuit selection signal SC ₁ (or circuit ID) "0" analyzed with a _B, and active only selection signal SC _B1 of the selection signals SC _B1 to SC _B5 (i.e. "1") (see FIGS. 35A and 35B).
Thus, the processing circuit 221B of the processing block 21B, the selection switch SW _B11 to SW _B15 is turned on, the load instruction processing circuit 221B ₁ is constructed (ie selected) (FIG. 31A,
31B, 35A, 35B and 50).

The instruction decoder 223B receives the information (ie, operand 1) held in the 21st to 24th bits of the instruction INST ₁ given from the instruction register 123B as it is, without changing the input data selection signal SIA ₁ and the output data selection signal. circuit
Output as SO ₁ (see FIG. 40). Input data selection signal SIA ₁ and the output data selection circuit SO _1, respectively, are given in the input data selection circuit 121B and the output data selection circuit 321B of the processing block 21B, is used as described below.

[0534] Instruction decoder 223B is the information held in the 17th bit to the 20th bit of the instruction INST ₁ given from the instruction register 123B (i.e. operand 2) directly outputs an input data selection signal SIB ₁ ( See FIG. 40). Input data selection signal SIB ₁ is applied to input data selection circuit 121B of the processing block 21B, is used as described below.

The instruction decoder 223B converts the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₁ given from the instruction register 123B into an OR circuit.
OR _3B to decode and decode result to index modification signal
Output as IXS _1, giving a load instruction processing circuit 221B ₁ of the processing block 21B (see FIG. 40). Index modification signal IXS _1, all of the 17 bits to the 20 bits of instruction INST ₁ is because it is as clear "0" in Table 18, the non-active (i.e. "0"), and has not been indexed modified It is shown that.

[0536] Instruction decoder 223B is the information held in the first bit to the 16th bit of the instruction INST ₁ given from the instruction register 123B (i.e. operand 3), it is output as the address signal AD _1, processing block 21B
Give the the load instruction processing circuit 221B ₁ (see FIG. 40).
Address signal AD ₁ indicates the address of the data holding device 26.

[0537] The load instruction processing circuit 22 is added to the processing block 21B.
After 1B ₁ is constructed, in the control signal generation circuit 323B, the output of the AND circuit AND _3B3 (that is, the shift signal SFTC ₁ )
Flag signal generator CENDF _3B constructed as clock signal
, And to the processed flag signal generation circuit PENDF _3B as a clear signal (see FIG. 44). Therefore, when the second output of the shift register SR _3B becomes “1”, the constructed flag signal generation circuit CENDF _3B outputs a high-level signal (ie, “1”) given to the data input terminal D. Captures and holds the built flag signal CENDF ₁
Is active (ie, “1”) as shown in Table 23. When the second output of the shift register SR _3B becomes “1”, the contents of the processed flag signal generation circuit PENDF _3B are cleared, and the processed flag signal PENDF ₁ is displayed in Table 23.
Is inactive (ie, “0”) as shown in FIG. By the way, the output of the AND circuit AND _3B2 of the control signal generation circuit 323B
(That is, the write signal WT ₁ and the increment signal INCP
The time difference between the occurrence time of the output of the generator when and AND circuit the AND _3B3 (ie shift signal SFTC _{1) 1),} the time required for holding the instruction INST ₁ for the instruction register 123B, the instruction INST ₁ in the instruction decoder 223B the time required for decryption, is determined by considering the time required for introduction of the selection switch SW _B11 to SW _B15 upon the construction of the load instruction processing circuit 221B ₁ in the processing block 21B.

[0538]

[Table 23]

The construction pointer 423 has a control signal generation circuit
Shift signal SFTC given from AND circuit _{3B3 of} 323B
₁ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21C (that is, the construction command signal CPQ ₂ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₁ , and CPQ ₃ become “0”.
(See Table 23 and FIG. 47).

Since the constructed flag signal CENDF ₀ is active (ie, “1”) and the output of the processing pointer 523 (ie, processing command signal) PPQ ₁ is active (ie, “1”), the control signal generating circuit 323B of the aND circuit the aND _3B4 is a process start signal STRT ₁ for instructing processing start of the load instruction processing circuit 221B ₁ of the processing block 21B and active (i.e. "1") (see FIG. 44). When the processing start signal STRT ₁ is given to the load instruction processing circuit 221B ₁ of the processing block 21B, the load instruction processing circuit 221B _{1 of the} processing block 21B is provided.
Executes a load instruction as described later (see FIG. 50).

The load instruction processing circuit 22 of the processing block 21B
When the processing in 1B ₁ (i.e. execution of a load instruction) is completed, the load instruction processing circuit processing block 21B 221B _{1
Activates the} processing end signal S _ENDB1 output from the processing end signal output terminal END (that is, “1”) as described later.
And then, supplied to the retaining circuit 421B as the write signal WT ₁ via the selection switch SW _B12 and the write signal output terminal WT _B, and the selection switch SW _B12 and processing end signal output terminal END _B treated as a processing end signal END ₁ through It is given to the pointer 523 and the control signal generation circuit 323B (FIGS. 31A, 31B and 35).
A, see FIG. 35B and FIG. 50). This is accompanied, in the process pointer 523, the data of the counter (i.e., flip-flop FF ₅₀ ~FF ₅₃₎ is moved, a signal indicating a processing block 21C (i.e. processing instruction signal) PPQ ₂ is shown in Table 24 Becomes "1" and the other processing command signal PP
Q ₀ , PPQ ₁ and PPQ ₃ become “0” (see FIG. 48). The control in the signal generating circuit 323B, so clears the held contents of the output of already constructed a high-level flag signal generating circuit CENDF _3B of the OR circuit OR _3B1, constructs flag signal CENDF ₁ is Table 2
As shown in FIG. 4, it becomes inactive (that is, "0"). Further, in the control signal generation circuit 323B, the load instruction processing circuit 22
Since taking "1" from the high-level signal source (not shown) to the processed flag signal generating circuit PENDF _3B by processing end signal END ₁ a high level, is processed flag signal PENDF ₁ table given from 1B ₁ As shown in FIG. 24, it becomes active (ie, “1”).

[0542]

[Table 24]

[0543] The program counter 623, when the increment signal INCP ₁ given from the control signal generator circuit 323B becomes as described above active (i.e. "1"), the count value by "1" increases, the address signal PC To the address input terminal AD of the program holding device 24 (see FIG. 49).

Construction of processing circuit 221C ... addition instruction processing circuit 22
Choice of 1C ₄

[0545] In the control signal generation circuit 323C of the control device 23,
Since the processed flag signal PENDF ₂ and the construction command signal CPQ ₂ given from the construction pointer 423 are both active (ie, “1”) as shown in Table 24, the AND circuit AND
The output of _3C1 becomes active (that is, "1"), and instructs the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the addition instruction processing circuit) in the processing block 21C (see FIG. 45).

[0546] In the control signal generation circuit 323C of the controller 23,
Since the count content of the shift register SR _3C is cleared by a reset signal RESET, the first to third output Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

The shift register SR _3C receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3C1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3C has the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0548] The shift register SR _3C is, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3C1 to the data input A to the inside uptake, and outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3C outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* .

[0549] The shift register SR _3C is, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "1" that are given from the AND circuit the AND _3C1 to the data input A to the inside, and outputs "1" from the first output terminal Q _1, and the second output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3C
Inverting output terminal Q ₁ ^* from "0" outputs, and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3C2 is connected to the shift register SR _3C
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3C becomes "1", and outputs "1". Therefore, the write signal WT ₂ and the increment signal INCP ₂ output from the control signal generation circuit 323C are both active (ie, “1”) when the first output of the shift register SR _3C becomes “1”. )).

The AND circuit AND _3C3 is connected to the shift register SR _3C
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3C becomes "1", and outputs "1". Therefore, the shift signal SFTC ₂ which is output from the control signal generating circuit 323C, when the second output of the shift register SR _3C becomes "1",
Active (ie, "1").

As described above, the count value “2” of the program counter 623 is used as the address signal PC as the program holding device.
Since given to 24 of the address inputs AD, the program holding unit 24 is "2" and the output data held in the address (ie, addition instruction) from the data output terminal DATA as the instruction INST _2, instruction register 123A~ To 123D (Table 18,
38A, 38B and 49).

[0553] Instruction register 123C is, at this time, since the write signal WT ₂ is supplied from the control signal generator circuit 323C to the write signal input terminal, upon its rise, the instruction given from the program hold unit 24 INST ₂ Is taken in and held. By the way, the instruction registers 123A, 123B, 123D are
No write signals WT ₀ , WT ₁ , WT ₃ are applied to the write signal input terminals from the control signal generation circuits 323 A, 323 B, 323 D (that is, the write signals WT ₀ , WT ₁ , WT ₃ are inactive) Therefore, the instruction INST ₂ given from the program holding device 24 is not fetched inside.

[0554] Instruction decoder 223C decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₂ given from the instruction register 123C to the address input AD of the conversion table circuit TBL _3C, decryption The result is converted from the data output terminal DATA of the conversion table circuit TBL _3C to the circuit selection signal SC _2.
(See FIG. 41). The circuit selection signal SC ₂ is
As shown in Table 20, it is "3" and the processing block 21
36A (FIG. 36A and FIG. 36).
B).

[0555] In the processing circuit 221C of the processing block 21C, when the circuit selection signal SC ₂ from the instruction decoder 223C of control device 23 is given, the decoder DECD the contents of the circuit selection signal SC ₂ (i.e. circuit number) "3" analyzed with a _C, and active only selection signal SC _C4 of the selection signals SC _C1 to SC _C5 (i.e. "1") (see FIGS. 36A and 36B).
Thus, the processing circuit 221C of the processing block 21C, the selection switch SW _C41, SW _{C4 2} is turned on, the addition instruction processing circuit
221C ₄ is constructed (ie, selected) (FIG. 32A, FIG. 3).
2B and FIG. 53).

[0556] Instruction decoder 223C is the information held in the first 21 bits to 24 bits of instruction INST ₂ given from the instruction register 123C (i.e. operand 1), as it is, the input data selection signal SIA ₂ and the output data selection signal
Output as SO ₂ (see FIG. 41). Input data selection signal SIA ₂ and the output data selection signal SO _2, respectively, are given in the input data selection circuit 121C and the output data selection circuit 321C of the processing block 21C, is used as described below.

The instruction decoder 223C outputs the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₂ given from the instruction register 123C as it is, as the input data selection signal SIB ₂ ( See FIG. 41). Input data selection signal SIB ₂ is applied to input data selection circuit 121C of the processing block 21C, is used as described below.

The instruction decoder 223C outputs the information (ie, operand 2) held in the 17th to 20th bits of the instruction INST ₂ given from the instruction register 123C to an OR circuit.
OR _3C to decode and decode result to index modification signal
Output as IXS _2, giving the add instruction processing circuit 221C ₄ processing block 21C (see FIG. 41). Index modification signal IXS ₂ are the instructions clear as to at least Tsugahyo 18 of the 17 bits to the 20 bits of INST ₂ "1", and active (i.e. "1"), and the index modification made shows that but not using it in the add instruction processing circuit 221C _4.

[0559] Instruction decoder 223C is the information held in the first bit to the 16th bit of the instruction INST ₂ given from the instruction register 123C (i.e. operand 3), it is output as the address signal AD _2, the processing block 21C
It gives the add instruction processing circuit 221C ₄ (see FIG. 41). However, the address signal AD _2, since not required by the add instruction processing circuit 221C ₄ processing block 21C, not be utilized (see FIG. 53).

The addition instruction processing circuit 221C is added to the processing block 21C.
After the circuit ₄ is constructed, in the control signal generation circuit 323C, the output of the AND circuit AND _3C3 (that is, the shift signal SFTC ₂ ) is supplied to the constructed flag signal generation circuit CENDF _3C as a clock signal and processed as a clear signal. This is supplied to a flag signal generation circuit PENDF _3C (see FIG. 45). For this reason,
The built flag signal generation circuit CENDF _3C is a shift register
When the second output of the SR _3C becomes “1”, the high-level signal given to the data input terminal D is taken in and held, and the constructed flag signal CENDF ₂ is activated as shown in Table 25 ( That is, “1”). When the second output of the shift register SR _3C becomes “1”, the contents of the processed flag signal generation circuit PENDF _3C are cleared, and the processed flag signal PENDF ₂ is turned off as shown in Table 25. Active (ie, “0”). By the way, the control signal generation circuit 323C
The output of the AND circuit the AND _3C2 (i.e. the write signal WT ₂ and increment signal INCP ₂₎ generation timing of the AND circuit AN
The time difference between the occurrence time of the output (i.e. the shift signal SFTC ₂₎ of the D _3C3, the time required for holding the instruction INST ₂ for the instruction register 123C, the instruction in the instruction decoder 223C INST
_2, the time required for decoding, and the selection switches SW _C41 , SW _C in the construction of the addition instruction processing circuit 221C ₄ in the processing block 21C
It is determined in consideration of the time required for selecting _C42 .

[0561]

[Table 25]

The construction pointer 423 has a control signal generation circuit
Shift signal SFTC given from AND circuit _{3C3 of} 323C
₂ according to the counter (i.e., flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21D (that is, the construction command signal CPQ ₃ ) becomes “1”, and the other construction command signals CPQ _{0 to} CPQ ₂ become “0” (see Table 2).
5 and FIG. 47).

Since the constructed flag signal CENDF ₂ is active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₂ is active (ie, “1”), the control signal generating circuit 323C of the aND circuit the aND _3C4 is a process start signal STRT ₂ for instructing processing start of the addition instruction processing circuit 221C ₄ processing block 21C and active (i.e. "1") (see FIG. 45). When the processing start signal STRT ₂ is given to the addition instruction processing circuit 221C ₄ of the processing block 21C, the addition instruction processing circuit 221C ₄ of the processing block 21C
As will be described later, an addition instruction is executed (see FIG. 53).

[0564] Addition instruction processing circuit 221C of processing block 21C
When the process (i.e. execution of the addition instruction) is completed in _4, the add instruction processing circuit 221C ₄ processing block 21C is, as described below the processing end signal S _ENDC4 being output from the processing end signal output terminal END active (i.e. " 1 ")
Selection switch SW _C42 and the write signal output terminal WT _C supplied to the holding circuit 421C as a write signal WT ₂ through, and selection switches SW _C42 and processing end signal output terminal END processing _C as a processing end signal END ₂ via the pointer 523 32A, FIG. 32B, FIG. 36A, FIG.
6B and FIG. 53). Accordingly, the processing pointer 513 sets the counter (that is, the flip-flop FF ₅₀
To FF ₅₃ ), the processing block 21D
(Ie, the processing command signal) PPQ ₃ becomes “1” as shown in Table 26, and the other processing command signals PPQ _{0 to} PPQ ₂
Becomes "0" (see FIG. 48). Further, in the control signal generation circuit 323C, the output of the OR circuit OR _3C1 becomes high level to clear the held content of the constructed flag signal generation circuit CENDF _3C1 , so that the constructed flag signal CENDF ₂ is set as shown in Table 26. It becomes inactive (that is, “0”). Furthermore, the control signal generating circuit 323C, the high-level signal source to the processing flag signal generating circuit PENDF _3C by addition instruction processing circuit processing end signal END ₂ high-level given from 221C ₄ (not shown)
, The processed flag signal PENDF ₂ becomes active (ie, “1”) as shown in Table 26.

[0265]

[Table 26]

[0266] The program counter 623, when the increment signal INCP ₂ given from the control signal generator circuit 323C becomes as described above active (i.e. "1"), the count value "1" is incremented by the address signal PC To the address input terminal AD of the program holding device 24 (see FIG. 49).

Construction of processing circuit 221D: Load effective address
Selection of instruction processing circuit 221D ₃

In the control signal generation circuit 323D of the control device 23,
Since the processed flag signal PENDF ₃ and the construction command signal CPQ ₃ given from the construction pointer 423 are both active (ie, “1”) as shown in Table 26, the AND circuit AND
The output of _3D1 becomes active (that is, "1"), and commands the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the load effective address instruction processing circuit) in the processing block 21D (see FIG. 46). .

In the control signal generation circuit 323D of the control device 23,
Since the count content of the shift register SR _3D is cleared by a reset signal RESET, the first to third output Q
_{1 to} Q ₃ are set to “0”, and the first to third inverted outputs Q ₁ ^{* to} Q ₃ ^* are set to “1”.

[0570] The shift register SR _3D is, the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3D1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3D becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0571] The shift register SR _3D is, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3D1 to the data input A to the inside uptake, and outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Accordingly, the shift register SR _3D outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* .

[0572] The shift register SR _3D is, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "1" that are given from the AND circuit the AND _3D1 to the data input A to the inside, and outputs "1" from the first output terminal Q _1, and the second output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3D
Inverting output terminal Q ₁ ^* from "0" outputs, and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3D2 is provided with a shift register SR _3D
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3D becomes "1", and outputs "1". Therefore, the write signal WT ₃ and the increment signal INCP ₃ output from the control signal generation circuit 323D are both active (ie, “1”) when the first output of the shift register SR _3D becomes “1”. )).

[0574] The AND circuit AND _3D3 is a shift register SR _3D
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3D becomes "1", and outputs "1". Therefore, the shift signal SFTC ₃ which is output from the control signal generating circuit 323D when the second output of the shift register SR _3D becomes "1",
Active (ie, "1").

[0575] The count value "3" of the program counter 623 is used as the address signal PC as described above as the program holding device.
24, the program holding device 24 outputs the data held at the address “3” (that is, the load effective address command) from the data output terminal DATA as the command INST ₃ , (See Table 18, FIG. 38A, FIG. 38B and FIG. 49)
.

At this time, since the write signal WT ₃ is supplied from the control signal generation circuit 323 D to the write signal input terminal of the instruction register 123 D, the instruction INST ₃ supplied from the program holding device 24 at the time of its rise. Is taken in and held. By the way, the instruction registers 123A to 123C receive the write signal from the control signal generation circuits 323A to 323C at the write signal input terminal.
WT _{0 to} WT ₂ are not given (that is, write signal WT ₀
~ WT ₂ is inactive), so that the instruction INST ₃ given from the program holding device 24 is not taken in.

[0577] Instruction decoder 223D decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₃ given from the instruction register 123D to the conversion table circuit TBL _3D the address inputs AD, decryption The result is sent to the circuit selection signal SC ₃ from the data output terminal DATA of the conversion table circuit TBL _3D.
(See FIG. 42). The circuit selection signal SC ₃ is
As shown in Table 20, the value is "2" and the processing block 21D
37A and FIG. 37B.
See).

[0578] In the processing circuit 221D of the processing block 21D, when the circuit selection signal SC ₃ from the instruction decoder 223D of the control device 23 is given, the decoder DECD the contents of the circuit selection signal SC ₃ (i.e. circuit number) "2" decodes the _D, and the active only selection signal SC _D3 of the selection signals SC _D1 to SC _D5 (i.e. "1") (see FIGS. 37A and 37B).
Thus, the processing circuit 221D of the processing block 21D, the selection switch SW _D31, SW _{D3 2} is turned on, the load effective address instruction processing circuit 221D ₃ is constructed (ie selected)
(See FIG. 33A, FIG. 33B and FIG. 52).

The instruction decoder 223D receives the information (that is, operand 1) held in the 21st to 24th bits of the instruction INST ₃ given from the instruction register 123D, without changing the input data selection signal SIA ₃ and the output data selection signal. signal
Output as SO ₃ (see FIG. 42). The input data selection signal SIA ₃ and the output data selection signal SO ₃ are provided to the input data selection circuit 121D and the output data selection circuit 321D of the processing block 21D, respectively, and are used as described later.

[0580] Instruction decoder 223D is the first 17 bits to information held in the 20-bit instruction INST ₃ given from the instruction register 123D (i.e. operand 2) directly outputs an input data selection signal SIB ₃ ( See FIG. 42). Input data selection signal SIB ₃ is applied to input data selection circuit 121D processing block 21D, are utilized as described below.

The instruction decoder 223D outputs the information (that is, operand 2) held in the 17th to 20th bits of the instruction INST ₃ given from the instruction register 123D to an OR circuit.
OR Decodes to _3D and decodes the result to index modification signal
Output as IXS _3, applied to the load effective address instruction processing circuit 221D ₃ of the processing block 21D (see FIG. 42). The index modification signal IXS ₃ is inactive (ie, “0”) because all of the 17th to 20th bits of the instruction INST ₃ are “0” as is apparent from Table 18, and the index modification is not performed. It is shown that.

[0582] Instruction decoder 223D is the first bit to the information held in the first 16-bit instruction INST ₃ given from the instruction register 123D (i.e. operand 3), it is output as the address signal AD _3, processing blocks 21D
Gives the load effective address instruction processing circuit 221D ₃ (see FIG. 42). Address signal AD ₃ indicates the address of the data holding device 26.

[0583] After the process block 21D load effective address instruction processing circuit 221D ₃ was constructed, the control signal generating circuit
In the 323D, the output of the AND circuit AND _3D3 (that is, the shift signal SFTC ₃ ) is provided as a clock signal to the constructed flag signal generating circuit CENDF _3D , and is provided as a clear signal to the processed flag signal generating circuit PENDF _3D (FIG. 46). Therefore, the constructed flag signal generation circuit CENDF _3D
Is a high-level signal applied to the data input terminal D when the second output of the shift register SR _3D becomes “1”.
(Ie, “1”) is captured and held, and the constructed flag signal CENDF ₃ is activated (ie, “1”) as shown in Table 27. The processed flag signal generation circuit PEND
When the second output of the shift register SR _3D becomes “1”, the contents of F _3D are cleared and the processed flag signal PE
NDF ₃ is inactive as shown in Table 27 (ie, "0")
And By the way, the AND circuit of the control signal generation circuit 323D
Timing of output of AND _3D2 (that is, write signal WT ₃ and increment signal INCP ₃ ) and output of AND circuit AND _3D3
The time difference between the occurrence of the shift signal SFTC ₃ and the time required to hold the instruction INST _{3 in} the instruction register 123 D, the time required to decode the instruction INST ₃ in the instruction decoder 223 D, and the load effective address in the processing block 21 D Selection switch SW when constructing instruction processing circuit 221D ₃
It is determined in consideration of the time required for switching _{D31 to} SW _D32 .

[0584]

[Table 27]

The construction pointer 423 has a control signal generation circuit
Shift signal SFTC given from AND circuit AND _{3D3 of} 323D
₃ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21A (that is, the construction command signal CPQ ₀ ) becomes “1”, and the other construction command signals CPQ _{1 to} CPQ ₃ become “0” (Table 2).
7 and FIG. 47).

Since the constructed flag signal CENDF ₃ is active (ie, “1”) and the output of the processing pointer 513 (ie, processing command signal) PPQ ₃ is active (ie, “1”), the control signal generating circuit 323D The AND circuit AND _3D4 of the load effective address instruction processing circuit _221D of the processing block 21D
₃ processes a processing start signal STRT ₃ for commanding the start and active (i.e. "1") (see FIG. 46). When the processing start signal STRT ₃ is supplied to the load effective address instruction processing circuit 221D ₃ processing blocks 21D, the load effective address instruction processing circuit 221D ₃ of the processing block. 21D, as described later, executes the load effective address instruction (FIG. (See 52)
.

[0587] When the processing in the load effective address instruction processing circuit 221D ₃ of the processing block 21D is completed, the load effective address instruction processing circuit 221D ₃ of the processing block 21D,
The processing end signal output processing end signal S _ENDD3 being output from the END and as described later active (i.e. "1"), held as the write signal WT ₃ via the selection switch SW _D32 and the write signal output terminal WT _D applied to the circuit 421D, and the selection switch SW _D32 and processing end signal output terminal eND given to the processing pointer 523 and a control signal generating circuit 323D as a processing end signal eND ₃ through _D (FIG. 33A, FIG. 33B, FIG. 37A,
37B and FIG. 52). Along with this, the processing pointer 523 sets the counter (that is, the flip-flop).
Since the data of the FF ₅₀ ~FF ₅₃₎ is moved, the processing block
Signal indicating 21A (i.e. processing command signal) PPQ ₀ tables 28
And as "1" shown in the other processes command signals PPQ ₁ ~
PPQ ₃ becomes “0” (see FIG. 48). Further, in the control signal generation circuit 323D, the output of the OR circuit OR _3D1 becomes high level to clear the held content of the constructed flag signal generation circuit CENDF _3D1 , so that the constructed flag signal CENDF ₃ is as shown in Table 28. It becomes inactive (that is, “0”). Furthermore, the control signal generating circuit 323D, from the load effective address instruction processing circuit 221D ₃ high level supplied from the processing end signal END ₃ by processed flag signal generating circuit PENDF high signal sources in _3D (not shown) since capture "1", the process flag signal PENDF ₃ becomes active as shown in Table 28 (that is, "1").

[0588]

[Table 28]

[0589] The program counter 623, when the increment signal INCP ₃ supplied from the control signal generating circuit 323D becomes as described above active (i.e. "1"), the count value by "1" increases, the address signal PC To the address input terminal AD of the program holding device 24 (see FIG. 49).

Construction of processing circuit 221A: arithmetic left shift instruction processing
Selection of logic circuit 221A ₅

In the control signal generation circuit 323A of the control device 23,
Since the processed flag signal PENDF ₀ and the construction command signal CPQ ₀ given from the construction pointer 423 are both active (ie, “1”) as shown in Table 28, the AND circuit AND
The output of _3A1 becomes active (that is, "1"), and commands the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the arithmetic left shift instruction processing circuit) in the processing block 21A (see FIG. 43). .

In the control signal generation circuit 323A of the control device 23,
The output of the AND circuit AND _3A1 is “0” for a certain period
Since was, counting the contents of the shift register SR _3A is cleared, the first to third output Q ₁ ~ les ₃ is accompanied thereto
Is set to “0”, and the first to third inverted outputs Q ₁ ^* to
Q ₃ ^* is set to “1”.

[0593] The shift register SR _3A, the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3A1 therein, outputs "1" from the first output terminal Q _1. Along with this, the shift register SR _3A becomes the first inverted output terminal Q
Outputs "0" from ₁ ^* .

[0594] The shift register SR _3A, the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3A1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. This is accompanied, the shift register SR _3A outputs "0" from the first inverted output terminal Q ₁ ^*, and outputs "0" from the second inverting output terminal Q ₂ ^*. When "1" second from the output terminal Q ₂ of the shift register SR _3A is output, as described later, the shift signal SFTC ₀ is active, which is the output of the AND circuit the AND _3A3 (i.e. "1"), and the building pointer 423 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. _Along with this, the data _supplied from the AND circuit AND _3A1 to the data input terminal A of the shift register SR _3A is set to “0”.

[0595] The shift register SR _3A, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3A1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3A
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3A2 is connected to the shift register SR _3A
Is _ANDed between the first output and the second inverted output of the shift register _SR3A , when the first output of the shift register SR3A becomes "1", "1" is output. Therefore, the write signal WT ₀ and the increment signal INCP ₀ output from the control signal generation circuit 323A are both active (ie, “1”) when the first output of the shift register SR _3A becomes “1”. )).

The AND circuit AND _3A3 is connected to the shift register SR _3A
Since the second output of the taking the logical product between the third inverting output, when the second output of the shift register SR _3A becomes "1", and outputs "1". Therefore, the shift signal SFTC ₀ which is output from the control signal generator circuit 323A, when the second output of the shift register SR _3A becomes "1",
Active (ie, "1").

As described above, the count value “4” of the program counter 623 is used as the address signal PC in the program holding device.
24, the program holding unit 24 transfers the data (ie, the arithmetic left shift instruction) held at the address "4" from the data output terminal DATA to the instruction IN.
Output as ST _0, Table 18 given to the instruction register 123a through 123d, FIG. 38A, see FIGS. 38B and 49).

[0599] Instruction register 123A, this time, since the write signal WT ₀ is given from the control signal generator circuit 323A to the write signal input terminal, instruction INST ₀ that upon rising, given from the program hold unit 24 Is taken in and held. By the way, the instruction registers 123B to 123D receive the write signal from the control signal generation circuits 323B to 323D at the write signal input terminal.
WT ₁ ~WT ₃ is not given (i.e. the write signal WT ₁
~ WT ₃ is inactive), so that the instruction INST ₀ given from the program holding device 24 is not taken in.

[0600] Instruction decoder 223A decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₀ given from the instruction register 123A to an address input terminal AD of the conversion table circuit TBL _3A, decrypts The result is transmitted from the data output terminal DATA of the conversion table circuit TBL _3A to the circuit selection signal SC _0.
(See FIG. 39). The circuit selection signal SC ₀ is
As shown in Table 20, the value is "4" and the processing block 21
A of FIG. 34A and FIG.
B).

[0601] The processing in block 21A of processing circuit 221A, when the circuit selection signal SC ₀ from the instruction decoder 223A of the control unit 23 is given, the decoder DECD the contents of the circuit selection signal SC ₀ (i.e. circuit number) "4" It decodes the _a, and active only selection signal SC _A5 of the selection signals SC _A1 to SC _A5 (i.e. "1") (see FIGS. 34A and 34B).
Thus, processing in block 21A of processing circuit 221A, the selection switch SW _A51, SW _{A5 2} is turned on, constructed arithmetic left shift instruction processing circuit 221A ₅ (i.e. selected) by the (FIG. 30
A, see FIGS. 30B and 54).

The instruction decoder 223A converts the information (operand 1) held in the 21st to 24th bits of the instruction INST ₀ given from the instruction register 123A into the input data selection signal SIA ₀ and the output data selection signal
Output as SO ₀ (see FIG. 39). The input data selection signal SIA ₀ and the output data selection signal SO ₀ are provided to the input data selection circuit 121A and the output data selection circuit 321A of the processing block 21A, respectively, and are used as described later.

The instruction decoder 223A outputs the information (operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 123A as it is, as the input data selection signal SIB ₀ ( See FIG. 39). Input data selection signal SIB ₀ is applied to input data selection circuit 121A of the processing block 21A, is used as described below.

The instruction decoder 223A outputs the information (that is, operand 2) held in the 17th to 20th bits of the instruction INST ₀ given from the instruction register 123A to an OR circuit.
OR _3A to decode and decode result to index modification signal
Output as IXS _0, gives the arithmetic left shift instruction processing circuit 221A ₅ of the processing block 21A (see FIG. 39). The index modification signal IXS ₀ is the 17th to 20th bits of the instruction INST ₀ .
Since at least one of the bits is a "1", as is evident in Table 18, it becomes active (i.e., "1"), indicating that the index modification has been performed, but the arithmetic left shift instruction processing circuit 221A _{5 of} processing block 21A. It is not used because it is not required in (see Fig. 54)
.

[0605] Instruction decoder 223A is the first bit to the information held in the first 16-bit instruction INST ₀ given from the instruction register 123A (i.e. operand 3), it is output as the address signal AD _0, processing block 21A
Gives the arithmetic left shift instruction processing circuit 221A ₅ (see FIG. 39). However, the address signal AD _0, because not required by the arithmetic left shift instruction processing circuit 221A ₅ processing block 21A, it is not used.

[0606] The processing after the arithmetic left shift instruction processing circuit 221A ₅ is constructed in a block 21A, control the signal generating circuit 323A, the output of the AND circuit the AND _3A3 (i.e. shift signal SFTC
₀ ) is a built-in flag signal generation circuit CE as a clock signal.
The signal is supplied to the NDF _3A and to the processed flag signal generation circuit PENDF _3A as a clear signal (see FIG. 43). Therefore, when the second output of the shift register SR _3A becomes "1", the constructed flag signal generating circuit CENDF _3A outputs a high-level signal (that is, "1") given to the data input terminal D. And hold it, and the built flag signal CENDF ₀
Is active (ie, “1”) as shown in Table 29. When the second output of the shift register SR _3A becomes “1”, the content of the processed flag signal generation circuit PENDF _3A is cleared, and the processed flag signal PENDF ₀ is displayed in Table 29.
Inactive as shown in (1) (that is, "0"). By the way, the output of the AND circuit AND _3A2 of the control signal generation circuit 323A
(That is, the write signal WT ₀ and the increment signal INCP
The time difference between the occurrence time of the output of the generator when and AND circuit the AND _{3A3 0)} (i.e. the shift signal SFTC ₀₎ is the time required for holding the instruction INST ₀ for instruction register 123A, the instruction INST ₀ in the instruction decoder 223A Time required for decoding, arithmetic left shift instruction processing circuit 221A in processing block 21A
₅ is determined in consideration of the time required to turn on the selection switches SW _A11 and SW _A52 .

[0607]

[Table 29]

The construction pointer 423 includes a control signal generation circuit
Shift signal SFTC given from the AND circuit AND _3A3 of 323A
Counter according to ₀ (that is, flip-flop FF ₄₀ ~
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21B (that is, the construction command signal CPQ ₁ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₂ , and CPQ ₃ become “0”.
(See Table 29 and FIG. 47).

Since the constructed flag signal CENDF ₀ is active (ie, “1”) and the output of the processing pointer 523 (ie, processing command signal) PPQ ₀ is active (ie, “1”), the control signal generating circuit 323A of the aND circuit the aND _3A4 is a process start signal STRT ₀ for instructing processing start of the arithmetic left shift instruction processing circuit 221A ₅ processing blocks 21A and active (i.e. "1") (see FIG. 43). Processing start signal ST
RT ₀ is the arithmetic left shift instruction processing circuit 22 of the processing block 21A
Given the 1A _5, an arithmetic left shift instruction processing circuit 221A ₅ of the processing block 21A is, as described later, perform arithmetic left shift instruction (see Figure 54).

Arithmetic left shift instruction processing in processing block 21A
Circuit 221A_Five Is completed, the processing block 21
A arithmetic left shift instruction processing circuit 221A_Five Is the processing end signal
Processing end signal S output from output end END_ENDA5 To
Active (ie, “1”) as described below and the selection switch
H SW_A52 And write signal output terminal WT_A Write signal WT via ₀ 
To the holding circuit and select switch SW_A52 and
Processing end signal output terminal END_AProcessing end signal END via₀As
Provided to the processing pointer 523 and the control signal generation circuit 323A
 (FIGS. 30A, 30B, 34A, 34B and FIG. 5)
4). Accordingly, the processing pointer 523 indicates that
Counter (that is, flip-flop FF₅₀~ FF₅₃) Day
The signal indicating the processing block 21B (the signal
(I.e., processing command signal) PPQ₁As shown in Table 30
It becomes “1” and other processing command signal PPQ₀, PPQ_Two, PPQ_ThreeBut
It becomes "0" (see FIG. 48). Also, a control signal generation circuit
In 323A, OR circuit OR_3A1 Output becomes high level.
Built-in flag signal generation circuit CENDF_3A Clear the contents of
Therefore, the constructed flag signal CENDF₀As shown in Table 30
Inactive (ie, “0”). In addition, the control signal
In the raw circuit 323A, the arithmetic left shift instruction processing circuit 221A_Five From
Given high-level processing end signal END₀Processed by
Flag signal generator PENDF_3A High level signal source (shown)
), The processed flag signal PE
NDF₀Are active (ie, “1”) as shown in Table 30
Become.

[0611]

[Table 30]

[0612] The program counter 623, when the increment signal INCP ₀ given from the control signal generator circuit 323A becomes as described above active (i.e. "1"), the count value by "1" increases, the address signal PC To the address input terminal AD of the program holding device 24 (see FIG. 49).

Construction of processing circuit 221B ... Store instruction processing circuit
Choice of 221B ₂

[0614] In the control signal generation circuit 323B of the control device 23,
Since the processed flag signal PENDF ₁ and the construction command signal CPQ ₁ given from the construction pointer 423 are both active (ie, “1”) as shown in Table 30, the AND circuit AND
The output of _3B1 becomes active (that is, "1"), and instructs the start of the construction operation (here, the selection operation) of the appropriate arithmetic circuit (here, the store instruction processing circuit) in the processing block 21B (see FIG. 44).

The control signal generation circuit 323B of the control device 23
The output of the AND circuit AND _3B1 is "0" for a certain period
Since was, counting the contents of the shift register SR _3B is cleared, the first to third output Q ₁ to Q ₃ is accompanied thereto
Is set to “0”, and the first to third inverted outputs Q ₁ ^* to
Q ₃ ^* is set to “1”.

The shift register SR _3B receives the clock signal CLOC
At the rise of K, an AND circuit AN is connected to the data input terminal A.
Since capture data "1" that are given from the D _3B1 therein, outputs "1" from the first output terminal Q _1. Accordingly, the shift register SR _3B has the first inverted output terminal Q
Outputs "0" from ₁ ^* .

The shift register SR _3B receives the clock signal CLOC
Upon the next rising of the K, the first output of the output terminal Q ₁ is shifted to the second output terminal Q _2, and the data "1" that are given from the AND circuit the AND _3B1 to the data input A to the inside since taking, outputs "1" from the first output terminal Q _1, and outputs "1" from the second output terminal Q _2. Along with this, the shift register SR _3B outputs “0” from the first inverted output terminal Q ₁ ^* and outputs “0” from the second inverted output terminal Q ₂ ^* . When "1" second from the output terminal Q ₂ of the shift register SR _3B is output, as described later, the shift signal SFTC ₁ is active, which is the output of the AND circuit the AND _3B3 (ie "1"), and the building pointer 413 counters
(I.e. the flip-flop FF ₄₀ ~FF ₄₃₎ data is moved. _Along with this, the data _supplied from the AND circuit AND _3B1 to the data input terminal A of the shift register SR _3B is set to “0”.

[0618] The shift register SR _3B, the clock signal CLOC
At the next rising of K, the first and second output terminals Q ₁ ,
Output Q ₂ 'the second respectively, shifted to a third output terminal,
And since capture data "0" to the data input terminal A are given from the AND circuit the AND _3B1 therein, from the first output terminal Q ₁ "0" outputs, and the second from the output terminal Q ₂ " 1 "outputs, and the third output terminal Q _3" outputs 1 ". Along with this, the shift register SR _3B
Inverting output terminal Q ₁ ^* from outputs "1", and outputs "0" from the second inverting output terminal Q ₂ ^*, and outputs "0" from the third inverting output terminal Q ₃ ^* of .

The AND circuit AND _3B2 is connected to the shift register SR _3B
Since the first output of the taking the logical product between the second inverted output, when the first output of the shift register SR _3B becomes "1", and outputs "1". Therefore, the control signal generator circuit 323B write signal WT ₁ and increment signal is outputted from the INCP _1, when the first output of the shift register SR _3B becomes "1", both active (i.e., "1 )).

The AND circuit AND _3B3 is connected to the shift register SR _3B
And the third inverted output of the shift register SR _3B , the second output of the shift register SR _3B outputs “1” when the second output of the shift register SR _3B becomes “1”. Therefore, the shift signal SFTC ₁ which is output from the control signal generator circuit 323B, when the second output of the shift register SR _3B becomes "1",
Active (ie, "1").

[0621] As described above, the count value "5" of the program counter 623 is used as the address signal PC as the program holding device.
Since given to 24 of the address inputs AD, the program holding unit 24 is "5" and the output data held in the address (i.e. store instruction) from the data output terminal DATA as instructions INST _1, instruction register 123A~ Give to 123D (Table 1
8, see FIGS. 38A, 38B and 49).

[0622] Instruction register 123B, the time, since the write signal WT ₁ is supplied from the control signal generator circuit 323B to the write signal input terminal, upon its rise, the instruction given from the program hold unit 24 INST ₁ Is taken in and held. By the way, the instruction registers 123A, 123C, 123D are
Write signals WT ₀ , WT ₂ , WT ₃ are not supplied to the write signal input terminals from the control signal generation circuits 323 A, 323 C, 323 D (that is, the write signals WT ₀ , WT ₂ , WT ₃ are inactive) Therefore, the instruction INST ₁ given from the program holding device 24 is not taken in.

[0623] Instruction decoder 223B decodes giving instruction code held in the 25th bit to 32nd bit of the instruction INST ₁ given from the instruction register 123B to the address inputs AD conversion table circuit TBL _3B, decryption The result is sent from the data output terminal DATA of the conversion table circuit TBL _3B to the circuit selection signal SC _1.
(See FIG. 40). The circuit selection signal SC ₁ is
As shown in Table 20, the value is "1" and the processing block 21
B of FIG. 35A and FIG.
B).

[0624] In the processing circuit 221B of the processing block 21B, when the circuit selection signal SC ₁ from the instruction decoder 223B of the controller 23 is given, the decoder DECD the contents of the circuit selection signal SC ₁ (i.e. circuit number) "1" _B , and only the selection signal SC _B2 among the selection signals SC _{B1 to} SC _B5 is made active (that is, “1”) (see FIGS. 35A and 35B).
Thus, the processing circuit 221B of the processing block 21B, the selection switch SW _B22 to SW _B25 is turned on, the store instruction processing circuit 221B ₂ is constructed (ie selected) (FIG. 31A,
FIG. 31B and FIG. 51).

The instruction decoder 223B converts the information (operand 1) held in the 21st to 24th bits of the instruction INST ₁ given from the instruction register 123B into the input data selection signal SIA ₁ and the output data selection signal
Output as SO ₁ (see FIG. 40). Input data selection signal SIA ₁ and output data selection signal SO _1, respectively, are given in the input data selection circuit 121B and the output data selection circuit 321B of the processing block 21B, is used as described below.

[0626] Instruction decoder 223B is the information held in the 17th bit to the 20th bit of the instruction INST ₁ given from the instruction register 123B (i.e. operand 2) directly outputs an input data selection signal SIB ₁ ( See FIG. 40). Input data selection signal SIB ₁ is applied to input data selection circuit 121B of the processing block 21B, is used as described below.

[0627] Instruction decoder 223B includes an instruction register 17 bit instruction INST ₁ given from 123B to information held in the first 20 bits (i.e., operand 2) a OR circuit
OR _3B to decode and decode result to index modification signal
Output as IXS _1, giving the store instruction processing circuit 221B ₂ of the processing block 21B (see FIG. 40). Index modification signal IXS _1, all of the 17 bits to the 20 bits of instruction INST ₁ is because it is as clear "0" in Table 18, the non-active (i.e. "0"), and has not been indexed modified It is shown that.

[0628] Instruction decoder 223B is the information held in the first bit to the 16th bit of the instruction INST ₁ given from the instruction register 123B (i.e. operand 3), it is output as the address signal AD _1, processing block 21B
Give the the store instruction processing circuit 221B ₂ (see FIG. 40).
Address signal AD ₁ indicates the address of the data holding device 26.

The store instruction processing circuit 22 is added to the processing block 21B.
After 1B ₂ is constructed, in the control signal generation circuit 323B, the output of the AND circuit AND _3B3 (that is, the shift signal SFTC ₁ )
Flag signal generator CENDF _3B constructed as clock signal
, And to the processed flag signal generation circuit PENDF _3B as a clear signal (see FIG. 44). Therefore, when the second output of the shift register SR _3B becomes “1”, the constructed flag signal generation circuit CENDF _3B outputs a high-level signal (ie, “1”) given to the data input terminal D. Captures and holds the built flag signal CENDF ₁
Is active (ie, “1”) as shown in Table 31. When the second output of the shift register SR _3B becomes “1”, the contents of the processed flag signal generation circuit PENDF _3B are cleared, and the processed flag signal PENDF ₁
Is inactive (ie, “0”) as shown in FIG. By the way, the output of the AND circuit AND _3B2 of the control signal generation circuit 323B
(That is, the write signal WT ₁ and the increment signal INCP
The time difference between the occurrence time of the output of the generator when and AND circuit the AND _3B3 (ie shift signal SFTC _{1) 1),} the time required for holding the instruction INST ₁ for the instruction register 123B, the instruction INST ₁ in the instruction decoder 223B the time required for decryption, is determined in consideration of the store instruction processing circuit 221B ₂ of the selection switch SW _B22 to SW turned time required for _B25 upon building at processing block 21B.

[0630]

[Table 31]

The construction pointer 423 includes a control signal generation circuit
Shift signal SFTC given from AND circuit _{3B3 of} 323B
₁ depending on the counter (i.e. flip-flop FF ₄₀
Since the data of the FF ₄₃ ) is moved, the signal indicating the processing block 21C (that is, the construction command signal CPQ ₂ ) becomes “1”, and the other construction command signals CPQ ₀ , CPQ ₁ , and CPQ ₃ become “0”.
(See Table 31 and FIG. 47).

Since the constructed flag signal CENDF ₁ is active (ie, “1”) and the output of the processing pointer 523 (ie, processing command signal) PPQ ₁ is active (ie, “1”), the control signal generating circuit 323B of the aND circuit the aND _3B4 is a process start signal STRT ₁ for instructing the start of processing the store instruction processing circuit 221B ₂ of the processing block 21B and active (i.e. "1") (see FIG. 44). When the processing start signal STRT ₁ is given to the store instruction processing circuit 221B ₂ of the processing block 21B, the store instruction processing circuit 221B _{2 of the} processing block 21B
Executes a store instruction as described later (see FIG. 51).

The store instruction processing circuit 22 of the processing block 21B
When the processing in 1B ₂ (i.e. execution of the store instruction) is completed, the store instruction processing of the processing block 21B circuit 221B _{2
Activates the} processing end signal S _ENDB2 output from the processing end signal output terminal END as described later (that is, “1”).
And then, selects applied to hold circuit 421B as the switch SW _B22 and the write signal WT ₁ via the write signal output terminal WT _B, and the process as a process end signal END ₁ via the selection switch SW _B22 and processing end signal output terminal END _B It is given to the pointer 523 and the control signal generation circuit 323B (FIGS. 31A, 31B and 35).
A, see FIG. 35B and FIG. 51). This is accompanied, in the process pointer 523, the data of the counter (i.e., flip-flop FF ₅₀ ~FF ₅₃₎ is moved, a signal indicating a processing block 21C (i.e. processing instruction signal) PPQ ₂ is shown in Table 32 Becomes "1" and the other processing command signal PP
Q ₀ , PPQ ₁ and PPQ ₃ become “0” (see FIG. 48). The control in the signal generating circuit 323B, so clearing the output contents held high level is to construct flag signal generating circuit CENDF _3B of the OR circuit OR _3B1, constructs flag signal CENDF ₁ is Table 3
As shown in FIG. 2, it becomes inactive (that is, "0"). Further, in the control signal generation circuit 323B, the store instruction processing circuit 22
Since taking "1" from the high-level signal source (not shown) to the processed flag signal generating circuit PENDF _3B by processing end signal END ₁ a high level, is processed flag signal PENDF ₁ table given from 1B ₂ As shown in FIG. 32, it becomes active (that is, “1”).

[0634]

[Table 32]

[0635] The program counter 623, when the increment signal INCP ₁ given from the control signal generator circuit 323B becomes as described above active (i.e. "1"), the count value by "1" increases, the address signal PC To the address input terminal AD of the program holding device 24 (see FIG. 49).

Processing in processing circuit 221A: Load instruction
Run

[0637] When the load instruction processing circuit 221A ₁ as a processing circuit 221A of the processing block 21A is selected, as is evident in Table 21, given by the process pointer 523 are processed command signal PPQ ₀ is active (i.e. "1" ) in addition to being so constructed flag signal CENDF ₀ is active (i.e. "1"), output or process start signal STRT ₀ of the aND circuit the aND _3A4 of the control signal generating circuit 323A is active
(I.e. "1"), and applied through the load instruction processing circuit 221A ₁ processing start signal input terminal STRT to processing start signal input terminal STRT _A processing block 21A (FIG. 34
A, FIG. 34B, FIG. 43 and FIG. 50). By the way,
Since the processed flag signal PENDF ₀ is inactive (ie, “0”) as apparent from Table 21, the output of the AND circuit AND _3A1 of the control signal generation circuit 323A becomes inactive (ie, “0”). Even if the construction command signal CPQ ₀ given from the construction pointer 423 becomes active (that is, “1”), the construction operation of the arithmetic circuit in the processing block 21A is performed.
(Here, the selection operation) is not restarted. In other words,
Desired processing with the load instruction processing circuit 221A ₁ processing block 21A (i.e. the load instruction processing) until the ends,
A new arithmetic circuit is prevented from being constructed (selected here) in the processing block 21A.

The load instruction processing circuit 22 of the processing block 21A
In 1A _1, the process start signal STRT ₀ given to the process start signal input STRT, load input of down counter DCNT LD
(See FIG. 50).

[0639] Down counter DCNT is, when the processing start signal STRT ₀ to the load input LD is given, the data input terminal D
And the subtraction operation is started by taking in the "constant" given to.

[0640] Instruction decoder 223A of the control unit 23, by decoding an instruction INST ₀ given from the instruction register 123A, after outputted a circuit selection signal SC _0, inputs the input data selection signal SIA _0, SIB ₀ data given to the selection circuit 121A, and an output data selection signal SO ₀ to give to the output data selection circuit 321A, and an address signal AD ₀ and index modification signal IXS ₀ load instruction processing circuit 221A ₁ of the address signal input terminal AD and index modification signal IXS is provided via an address signal input AD _A and an index modification signal input IXS _A , respectively.

[0641] In the load instruction processing circuit 221A _1, the address signal AD ₀ is, is given to the data input terminal B of the adder ADD, the data input terminal D _ABIN to the data input terminal A, the input data selected via the D _BIN The data is added to the input data S _ABIN given from the circuit 121A and output from the output terminal F.

The selector circuit SELT responds to the fact that the index modification signal IXS ₀ is inactive (that is, “0”).
Address signal AD ₀ without selecting the output of adder ADD
And outputs it from the address signal output terminals AD _OUT and AD _AOUT to the data bus 25 as the address signal AD _ABS .
Incidentally, the content of the address signal AD _ABS is "100" as apparent from Tables 17 and 18.

[0643] In the load instruction processing circuit 221A _1, the bus control signal generation circuit BCNTL is, generates a read signal READ _ABS, bus control signals output BCNT _OUT, to output toward the data bus 25 from the BCNT _AOUT.

[0644] Data holding device 26, when via the data bus 25 the address signals AD _ABS and read signal READ _ABS given raw data DAT _ABS held in the corresponding "100" address to the address signal AD _ABS (That is, S _ABS ) and outputs it to the data bus 25.

[0645] raw data DAT _ABS supplied from the data holding unit 26 to the load instruction processing circuit 221A ₁ via the data bus 25 is provided via the data input and output terminals D _A to the data input and output terminals D, The data is output as output data S _A1 from the data output terminal D _OUT via the data transfer circuit DTRF, and is output as the output data S _A toward the output data selection circuit 321A via the selection switch SW _A11 and the data output terminal D _AOUT .

The output data S _A output from the load instruction processing circuit 221A ₁ is given to the data input terminals of the selector circuits SELECT _{A1 to} SELT _A3 of the output data selection circuit 321A.
(See FIG. 30). The other data input terminals of the selector circuits SELECT _{A1 to} SELT _A3 of the output data selection circuit 321A are connected to the holding circuit 42.
Holding the contents of the register circuit RGS _D1 ~RGS _D3 of 1D are given as input data S _D1 to S _D3.

In output data selection circuit 321A, control device 23
Output data selection signal given from the instruction decoder 223A of
SO ₀ is decoded by the decoder DEC _A , and the decoding result is selected by the selection signal SO _A1
SOSO _A3 are given to the selection signal input terminals of the selector circuits SELECT _A1 SELSEL _A3 . Here, as is clear from Tables 17 and 18, the selection signal SO _A1 is active (that is, “1”).
And the selection signals SO _A2 and SO _A3 are inactive (ie, “0”).

Since the selection signal SO _A1 is active (that is, “1”), the selector circuit SELECT _A1 selects the output data S _A and outputs the output data S _{A1 to} the register circuit RGS _A1 of the holding circuit 421A. I do.

Since the selection signal SO _A2 is inactive (that is, “0”), the selector circuit SELT _A2 selects the input data S _D2 and outputs it as output data S _{A2 to} the register circuit RGS _A2 of the holding circuit 421A. Output.

Since the selection signal SO _A3 is inactive (that is, “0”), the selector circuit SELECT _A3 selects the input data S _D3 and outputs it as output data S _{A3 to} the register circuit RGS _A3 of the holding circuit 421A. Output.

The down counter DCNT has a count of "0"
, The processing end signal _SENDA1 is output from the output terminal Q via the processing end signal output terminal END, and the selection switch SW
As a write signal WT ₀ through _A12 and the write signal output terminal WT _A and outputted to the output data selection circuit 321A, and controls the processing end signal END ₀ via the selection switch SW _A12 and processing end signal output terminal END _A Control signal generation circuit 323A for device 23
And output it to the processing pointer 523. By the way,
The subtraction operation time of the down counter DCNT is the data input terminal D
Is determined by the "constant" given to the load instruction, and the time required for processing the load instruction is taken into consideration.

[0652] Register circuits RGS _{A1 to} RGS of holding circuit 421A
In _A3, the process processing circuit 221A That load instruction processing circuit 221A outputs the data according to the write signal WT ₀ given from ₁ S _A1 to S _A3 of the block 21A is held, the load instruction processing circuit 221B ₁ from the output terminal Q Input data S _{A1 to} S
Output as _A3 .

[0653] In processing pointer 523 of the control unit 23, when the processing circuit 221A That load instruction processing circuit 221A ₁ from the processing end signal END ₀ processing block 21A is provided, the output of the OR circuit OR ₅ is a high level, the flip-flop FF ₅₀
Shifting the output "1" to the flip-flop FF _51, and takes in the "0" to the flip-flop FF _50. For this reason,
The processing command signals PPQ _{0 to} PPQ ₃ are “0”, “1”, “0”, and “0”, respectively, as shown in Table 22.

The control signal generation circuit 323A of the control device 23
When the processing circuit 221A That load instruction processing circuit 221A ₁ from the processing end signal END ₀ processing block 21A is provided, the output of the OR circuit OR _3A1 goes high, clears the contents held in construction flag signal generating circuit CENDF _3A As shown in Table 22, the constructed flag signal CENDF ₀ output from the output terminal Q is inactive (ie, “0”). This is accompanied, the output or process start signal STRT ₀ of the AND circuit the AND _3A4, a non-active (i.e. "0").

[0655] In the control signal generation circuit 323A of the control device 23,
When the processing circuit 221A That load instruction processing circuit 221A ₁ from the processing end signal END ₀ processing block 21A is given, also processing the flag signal generating circuit PENDF _3A "1" is captured and is outputted from the output terminal Q Processed flag signal
PENDF ₀ is active as shown in Table 22 (ie "1")
And This is accompanied, the AND circuit the AND _3A1 waits for the build command signal CPQ ₀ becomes newly active (i.e. "1"), to start building operation of the new operation circuit in the same manner as described above.

[0656] In other words, the control signal generating circuit 323A of the controller 23, the processing circuit 221A That load instruction processing circuit 221A ₁ processing block 21A until the process end signal END ₀ given, processed flag signal generating circuit PENDF "1" is not to be taken in _3A, is processed flag signal PENDF ₀ being output from the output terminal Q is kept non-active as shown in Table 21 (that is, "0"). Accordingly, the output of the AND circuit AND _3A1 is maintained in an inactive state (ie, “0”), and the construction pointer 42
Even if the construction command signal CPQ ₀ given from 3 becomes active (that is, “1”), the construction (selection here) of the arithmetic circuit in the processing block 21A cannot be restarted.

Processing in processing circuit 221B: Load instruction
Run

[0658] When the processing circuit load instruction processing circuit 221B ₁ as 221B processing block 21B is selected, as is evident in Table 23, given by the process pointer 523 are processed command signal PPQ ₁ is active (i.e. "1" ), The output of the AND circuit AND _3B4 of the control signal generation circuit 323B, that is, the processing start signal STRT ₁ is active because the constructed flag signal CENDF ₁ is active (ie, “1”).
(I.e. "1"), and given through the process start signal input terminal STRT _B to process start signal input STRT of the load instruction processing circuit 221B ₁ of the processing block 21B (FIG. 35
A, FIG. 35B, FIG. 44 and FIG. 50). By the way,
Since processed flag signal PENDF ₁ is a non-active as is evident in Table 23 (that is, "0"), the output of the AND circuit the AND _3B1 of the control signal generating circuit 323B are inactive (i.e. "0") and , even if the building instruction signal CPQ ₁ is tentatively active to be given from the construction pointer 423 (i.e. "1"), building operation of the arithmetic circuit in the processing block 21B
(Here, the selection operation) is not restarted. In other words,
Desired processing with the load instruction processing circuit 221B ₁ of the processing block 21B (i.e. load instruction process) until the ends,
A new arithmetic circuit is prevented from being constructed (selected here) in the processing block 21B.

The load instruction processing circuit 22 of the processing block 21B
In 1B _1, the processing start signal STRT ₁ given to the processing start signal input terminal STRT, load input of down counter DCNT LD
(See FIG. 50).

[0660] Down counter DCNT is, when the processing start signal STRT ₁ to the load input LD is given, the data input terminal D
And the subtraction operation is started by taking in the "constant" given to.

[0661] Instruction decoder 223B of the controller 23, by decoding an instruction INST ₁ given from the instruction register 123B, after outputted a circuit selection signal SC _1, inputs the input data selection signal SIA _1, SIB ₁ data It is given to the selection circuit 121B, and an output data selection signal SO give ₁ to the output data selection circuit 321B, and the address signal AD ₁ and index modification signals IXS ₁ load instruction processing circuit 221B ₁ of the address signal input terminal AD and index modification signal Address signal input terminal AD _B and index modification signal input terminal for input terminal IXS
Each is given via IXS _B.

[0662] In the load instruction processing circuit 221B _1, the address signal AD ₁ is, is given to the data input terminal B of the adder ADD, the data input terminal D _BBIN to the data input terminal A, the input data selected via the D _BIN The data is added to the input data S _BBIN given from the circuit 121B and output from the output terminal F.

The selector circuit SELT responds to the fact that the index modification signal IXS ₁ is inactive (that is, “0”).
Address signal AD ₁ without selecting the output of adder ADD
And outputs the address signal AD _{BBS from the} address signal output terminals AD _OUT and AD _BOUT to the data bus 25.
Incidentally, the content of the address signal AD _BBS is "101" as is clear from Tables 17 and 18.

[0664] In the load instruction processing circuit 221B _1, the bus control signal generation circuit BCNTL is, generates a read signal READ _BBS, bus control signals output BCNT _OUT, to output toward the data bus 25 from the BCNT _BOUT.

[0665] Data holding device 26, when via the data bus 25 the address signals AD _BBS and read signal READ _BBS given, the address signal AD _BBS corresponding to "101" untreated held in the address data DAT _BBS (That is, S _BBS ) and outputs it to the data bus 25.

[0666] Load instruction processing circuit 221B ₁ to raw data DAT _BBS provided from the data holding unit 26 via the data bus 25 is provided via the data input and output terminals D _B to the data input and output terminals D, through the data transfer circuit DTRF output from the data output terminal D _OUT as output data S _B1, is output as output data S _B toward the output data selection circuit 321B via the selector switch SW _B11 and a data output terminal D _BOUT .

[0667] load instruction processing circuit 221B outputs data S _B outputted from the ₁ is given to the data input terminal of the selector circuit SELT _B1 ~SELT _B3 of the output data selection circuit 321B
(See FIG. 31). The other data input terminals of the selector circuits SELECT _{B1 to} SELT _B3 of the output data selection circuit 321B are connected to the holding circuit 42.
Holding the contents of the register circuit RGS _A1 ~RGS _A3 of 1A is given as input data S _A1 to S _A3.

In output data selection circuit 321B, control device 23
Output data selection signal given from the instruction decoder 223B of
SO ₁ is decoded by the decoder DEC _B , and the decoding result is selected by the selection signal SO _B1
SOSO _B3 are given to the selection signal input terminals of the selector circuits SELECT _B1 SELSELT _B3 . Here, as apparent from Tables 17 and 18, the selection signal SO _B2 is active (that is, “1”).
Therefore, the selection signals SO _B1 and SO _B3 are inactive (ie, “0”).

Since the selection signal SO _B1 is inactive (ie, “0”), the selector circuit SELECT _B1 selects the output data S _A1 and directs it as the output data S _{B1 to} the register circuit RGS _B1 of the holding circuit 421B. Output.

[0670] The selector circuit SELT _B2, since the selection signal SO _B2 is active (i.e. "1"), input select data S _B, toward the register circuit RGS _B2 of the holding circuit 421B as the output data S _B2 output I do.

Since the selection signal SO _B3 is inactive (ie, “0”), the selector circuit SELECT _B3 selects the input data S _A3 and sends it as output data S _{B3 to} the register circuit RGS _B3 of the holding circuit 421B. Output.

[0672] The content of the down counter DCNT is "0".
, The processing end signal _SENDB1 is output from the output terminal Q via the processing end signal output terminal END, and the selection switch SW
_B12 and toward the output data selection circuit 321B as the write signal WT ₁ via the write signal output terminal WT _B outputs, and control the processing end signal END ₁ via the selection switch SW _B12 and processing end signal output terminal END _B Control signal generation circuit 323B of device 23
And output it to the processing pointer 523. By the way,
The subtraction operation time of the down counter DCNT is the data input terminal D
Is determined by the "constant" given to the load instruction, and the time required for processing the load instruction is taken into consideration.

[0672] Register circuits RGS _{B1 to} RGS of holding circuit 421B
In _B3, held output data S _B1 to S _B3 in response to the write signal WT ₁ given from the load instruction processing circuit 221B _1, the input data S from the output terminal Q toward the add instruction processing circuit 221C
It is output as _B1 ~S _B3.

[0674] In processing pointer 523 of the control unit 23, the processing circuit 221B i.e. load instruction processing circuit 221B ₁ from the processing end signal END ₁ processing block 21B is applied, the output of the OR circuit OR ₅ is a high level, the flip-flop FF ₅₀
Shifting the output of "0" to the flip-flop FF _51, and the flip-flop output "1" of the flip-flop FF ₅₁
It shifted to FF _52, and takes in the "0" to the flip-flop FF _50. Therefore, the processing command signals PPQ _{0 to} PPQ ₃ are as shown in Table 2
As shown in FIG. 4, “0”, “0”, “1”,
It becomes “0”.

The control signal generation circuit 323B of the control device 23
When the processing circuit 221B i.e. load instruction processing circuit 221B ₁ from the processing end signal END ₁ processing block 21B is given, the output of the OR circuit OR _3B1 goes high, clears the contents held in construction flag signal generating circuit CENDF _3B , The constructed flag signal CENDF ₁ output from the output terminal Q is made inactive (that is, “0”) as shown in Table 24. Accordingly, the output of the AND circuit AND _3B4 , that is, the processing start signal
STRT ₁ becomes inactive (ie, “0”).

[0676] In the control signal generation circuit 323B of the control device 23,
When the processing circuit 221B i.e. load instruction processing circuit 221B ₁ from the processing end signal END ₁ processing block 21B is given, processed flag signal generating circuit PENDF _3B "1" is captured, the process being outputted from the output terminal Q Completed flag signal PEND
As the F ₁ shown in Table 24 and active (i.e. "1"). Accordingly, the AND circuit AND _{3B1 waits} for the construction command signal CPQ _{1 to} become newly active (that is, “1”), and performs the construction operation of the new arithmetic circuit (here, the selection operation) in the same manner as described above. To start.

[0677] In other words, the control signal generating circuit 323B of the control device 23, the processing circuit 221B i.e. load instruction processing circuit 221B ₁ of the processing block 21B to the processing end signal END ₁ is given, processed flag signal generating circuit PENDF "1" is not to be taken in _3B, output processing is outputted from the Q flag signal PENDF ₁ is maintained in a state of non-active as shown in Table 23 (that is, "0"). Accordingly, the output of the AND circuit AND _3B1 is maintained in an inactive state (ie, “0”), and the construction pointer 42
Even if the construction command signal CPQ ₁ given from 3 becomes active (that is, “1”), the construction operation (here, the selection operation) of the arithmetic circuit in the processing block 21B is not restarted.

Processing in processing circuit 221C : execution of addition instruction
line

[0679] When the processing block 21C add instruction processing circuit 221C ₄ as the processing circuit 221C is selected, as is evident in Table 25, the processing is given from the processing pointer 523 command signal PPQ ₂ is active (i.e. "1" ), And the constructed flag signal CENDF ₂ is active (ie, “1”).
Therefore, the AND circuit AND _{3 C4} of the control signal generation circuit 323C
, The processing start signal STRT ₂ becomes active (ie, “1”), and the addition instruction processing circuit of the processing block 21C
The processing start signal input terminal STRT of the 221C ₄ is provided via the processing start signal input terminal STRT _C (FIGS. 36A, 36B,
45 and 53). Incidentally, since the processed flag signal PENDF ₂ is inactive (that is, “0”) as apparent from Table 25, the output of the AND circuit AND _3C1 of the control signal generating circuit 323C is inactive (that is, “0”). ), And even if the construction command signal CPQ ₂ given from the construction pointer 423 becomes active (that is, “1”), the construction operation of the arithmetic circuit in the processing block 21C (here, the selection operation) cannot be restarted. In other words, the processing block
The processing block 21 until the desired arithmetic processing (that is, processing of the addition instruction) is completed in the addition instruction processing circuit 221C ₄ of the 21C.
Prevents a new arithmetic circuit from being built (selected here) in C.

[0680] Addition instruction processing circuit 221C of processing block 21C
In _4, the process start signal STRT ₂ given to processing start signal input terminal STRT, it is given to the load input LD of the down counter DCNT (see FIG. 53).

When the processing start signal STRT ₂ is applied to the load input terminal LD, the data input terminal DCNT
And the subtraction operation is started by taking in the "constant" given to.

[0682] Instruction decoder 223C of control device 23, by decoding an instruction INST ₂ given from the instruction register 123C, after outputted a circuit selection signal SC _2, inputs the input data selection signal SIA _2, SIB ₂ data It is given to the selection circuit 121C, and has given the output data selection signal SO ₂ to the output data selection circuit 321C.

In the add instruction processing circuit 221C ₄ , the adder ADD
The input data S _CAIN is _supplied from the input data selection circuit 121C to the data input terminal A via the data input terminals D _CAIN and D _AIN , and the data input terminals D _CBIN and D C are input to the data input terminal B.
Input data S from input data selection circuit 121C via _BIN
CBIN are given, added to each other, output from the output terminal F as output data S _C4 via the data output terminal D _{OUT, and} are selected as the selection switch SW _C41 and the data output terminal D
Via _COUT is output as output data S _C toward the output data selection circuit 321C.

The output data S _C output from the processing circuit 221C of the processing block 21C, that is, the addition instruction processing circuit 221C ₄
Are the selector circuits SELECT _{C1 to} SE of the output data selection circuit 321C.
It is provided to the data input terminal of LT _C3 (see FIG. 32).
Selector circuit of output data selection circuit 321C SELECT _{C1 to} SELECT _C3
The other data input terminal has a register circuit of the holding circuit 421B.
Holding the contents of the RGS _B1 ~RGS _B3 is given as input data S _B1 to S _B3.

In the output data selection circuit 321C, the control device 23
Output data selection signal given from the instruction decoder 223C of
SO ₂ is decoded by the decoder DEC _C , and the decoding result is selected by the selection signal SO _C1
SOSO _C3 are given to the selection signal input terminals of the selector circuits SELECT _{C1 to} SELECT _C3 . Here, as is evident in Table 17 and Table 18, the selection signal SO _C1 active (i.e. "1")
Therefore, the selection signals _SOC2 and _SOC3 are inactive (that is, "0").

[0686] The selector circuit SELT _C1, since the selection signal SO _C1 is active (i.e. "1"), selects the output data S _C, toward the holding circuit 421C of the register circuit RGS _C1 as the output data S _C1 output I do.

[0687] The selector circuit SELT _C2 is chosen because the signal SO _C2 is non-active (i.e. "0"), selects the input data S _B2, towards the holding circuit register circuit 421C RGS _C2 as output data S _C2 Output.

[0688] The selector circuit SELT _C3, since the selection signal SO _C3 is non-active (i.e. "0"), the input select data S _C3, towards the register circuit RGS _C3 of the holding circuits 421C as output data S _C3 Output.

[0689] The content of the down counter DCNT is "0".
, The processing end signal S _ENDC4 is output from the output terminal Q via the processing end signal output terminal END, and the selection switch SW
_C42 and then output to the output data selection circuit 321C as a write signal WT ₂ through the write signal output terminal WT _C, and selectively switches SW _C42 and processing end signal output terminal END control _C as a processing end signal END ₂ via the Control signal generation circuit 323C for device 23
And output it to the processing pointer 523. By the way,
The subtraction operation time of the down counter DCNT is the data input terminal D
Is determined by the “constant” given to the CPU, and the time required for processing the addition instruction is taken into consideration.

[0690] Register circuits RGS _{C1 to} RGS of holding circuit 421C
In _C3, the process processing circuit 221C i.e. add instruction processing circuit 221C ₄ output data S _C1 to S _C3 in response to the write signal WT ₂ given from the block 21C is maintained, the load effective address instruction processing circuit from the output terminal Q and outputs as the input data S _C1 to S _C3 towards 221D _3.

At the processing pointer 523 of the control device 23, the processing circuit 221C of the processing block 21C, that is, the addition instruction processing circuit
When the processing end signal END ₂ is given from the 221C ₄ , the OR circuit
The output of OR ₅ goes high, shifting the output “0” of flip-flop FF ₅₀ to flip-flop FF ₅₁ and changing the output “0” of flip-flop FF ₅₁ to flip-flop FF
₅₂ , and the output “1” of the flip-flop FF ₅₂
It was shifted to the flip-flop FF _53, and takes in the "0" to the flip-flop FF _50. Therefore, the processing command signal
PPQ _{0 to} PPQ ₃ are “0”, “0”, “0”, and “1”, respectively, as shown in Table 26.

[0690] In the control signal generation circuit 323C of the control device 23,
Processing circuit 221C of processing block 21C, ie, addition instruction processing
Circuit 221C_Four From END_TwoIs given, or
Circuit OR_3C1 Becomes high level and the built flag signal
Generation circuit CENDF_3C Is cleared, and the output terminal Q
The constructed flag signal CENDF that is output_TwoIs shown in Table 26.
As inactive (ie, "0"). Accompanying this
What is AND circuit AND_{Three C4}Output, that is, the processing start signal ST
RT_Two Becomes inactive (ie, “0”).

In the control signal generation circuit 323C of the control device 23,
When the processing circuit 221C i.e. add instruction processing circuit 221C processing end signal END ₂ to ₄ of the processing block 21C is given, "1" is fetched into the processed flag signal generating circuit PENDF _3C,
The processed flag signal PENDF ₂ output from the output terminal Q is made active (that is, “1”) as shown in Table 26.
Accordingly, the AND circuit AND _{3C1 outputs} the construction command signal CP
As soon as Q ₂ becomes newly active (ie, “1”), the construction operation of a new arithmetic circuit is started in the same manner as described above.

[0694] In other words, the control signal generating circuit 323C of the control apparatus 23, the processing circuit 221C i.e. add instruction processing circuit 221C ₄ processing block 21C until the processing end signal END ₂ supplied, processed flag signal generating circuit PENDF "1" for _3C
Is not taken in, and the processed flag signal PENDF ₂ output from the output terminal Q is maintained in an inactive state (that is, “0”) as shown in Table 25. Accordingly, the output of the AND circuit AND _{3 C1} is maintained in an inactive state (ie, “0”), and the construction command signal CPQ ₂ given from the construction pointer 423 is temporarily activated (ie, “ Even if it becomes 1 "), the construction operation of the arithmetic circuit in the processing block 21C (here, the selection operation) is not restarted.

Processing in processing circuit 221D: Load effective address
Execution of dress instruction

[0696] When the load effective address instruction processing circuit 221D ₃ as a processing circuit 221D processing block 21D is selected, as is evident in Table 27, given by the process pointer 523 are processed command signal PPQ ₃ is active (i.e. " 1 ”), and since the constructed flag signal CENDF ₃ is active (ie,“ 1 ”), the control signal generation circuit
Output of AND circuit AND _3D4 of _323D , that is, processing start signal ST
RT ₃ becomes active (ie, “1”) and the processing block
To 21D processing start signal input terminal STRT load effective address instruction processing circuit 221D ₃ of given through the process start signal input terminal STRT _D (see FIG. 37A, FIG. 37B, FIGS. 46 and 52). By the way, the processed flag signal PENDF ₃ is shown in Table 2.
7, the output of the AND circuit AND _3D1 of the control signal generation circuit 323D becomes inactive (ie, "0") and the construction pointer
The construction command signal CPQ ₃ given from 423 is temporarily active.
Even if it becomes (i.e., "1"), the construction operation of the arithmetic circuit (the selection operation here) in the processing block 21D cannot be restarted. In other words, until the desired processing in the load effective address instruction processing circuit 221D ₃ of the processing block 21D (i.e. the load instruction processing) is completed, the process block 21D
Prevents a new arithmetic circuit from being constructed (selected here).

[0697] processing block 21D in load effective address instruction processing circuit 221D ₃ of given process start signal input STRT process start signal STRT _3, are given to the load input LD of the down counter DCNT (Figure 52 See).

When the processing start signal STRT ₃ is applied to the load input terminal LD, the data input terminal DCNT
And the subtraction operation is started by taking in the "constant" given to.

[0699] Instruction decoder 223D of the control device 23, by decoding an instruction INST ₃ given from the instruction register 123D, after outputted a circuit selection signal SC _3, inputs the input data selection signal SIA _3, SIB ₃ data given to the selection circuit 121D, and the output data selection signal SO ₃ applied to the output data selection circuit 321D, and the address signal AD ₃ and index modification signal address signal input terminal AD and indexes IXS ₃ load effective address instruction processing circuit 221D ₃ Modification signal input IX
Giving respectively through address signal input terminal AD _D and index modification signal input terminal IXS _D to S.

[0700] In the load effective address instruction processing circuit 221D _3, the address signal AD _3, the adder ADD of the data input terminal B
To the data input terminal A and the data input terminal D
_The data is added to the input data S _DBIN given from the input data selection circuit 121D via _DBIN and D _BIN and output from the output terminal F.

The selector circuit SELT responds to the fact that the index modification signal IXS ₃ is inactive (that is, “0”).
Address signal AD ₃ without selecting the output of adder ADD
Selecting, from the data output terminal D _OUT as output data S _D3, the selection switch SW _{D3 1} and the data output terminal D
Output data selection circuit 32 as output data _SD via _DOUT
Output to 1D. By the way, the address signal AD ₃ is
As is clear from Tables 17 and 18, the value is “1”.

[0702] The output data S _D output from the load effective address instruction processing circuit 221D _3, output data selection circuit 32
It is provided to the data input terminals of the 1D selector circuits SELT _{D1 to} SELT _D3 (see FIGS. 33A and 33B). The other data input terminals of the selector circuits SELECT _{D1 to} SELT _D3 of the output data selection circuit 321D are connected to the register circuits RGS _{C1 to} RGS _C of the holding circuit 421C.
The held contents of GS _C3 are given as input data S _{C1 to} S _C3 .

[0739] In the output data selection circuit 321D, the control device 23
Output data selection signal given from the instruction decoder 223D of
SO ₃ is decoded by the decoder DEC _D , and the decoding result is selected by the selection signal SO _D1
SOSO _D3 are given to the selection signal input terminals of the selector circuits SELECT _D1 SELSELD _D3 . Here, as is clear from Tables 17 and 18, the selection signal _SOD1 is active (that is, "1").
_Therefore , the selection signals _SOD2 and _SOD3 are inactive (that is, "0").

[0704] The selector circuit SELT _D1, since the selection signal SO _D1 is active (i.e. "1"), the output select data S _D, toward the register circuit RGS _D1 of the holding circuit 421D as output data S _D1 output I do.

[0705] The selector circuit SELT _D2 is chosen because the signal SO _D2 is non-active (i.e. "0"), selects the input data S _C2, toward the register circuit RGS _D2 of the holding circuit 421D as output data S _D2 Output.

[0706] The selector circuit SELT _D3, since the selection signal SO _D3 is non-active (i.e. "0"), the input select data S _C3, towards the register circuit RGS _D3 of the holding circuit 421D as output data S _D3 Output.

The down counter DCNT has a count of "0".
When he became, and outputs a processing end signal S _ENDD3 through the processing end signal output terminal END from the output terminal Q, the selection switch SW _D31
And outputs for the output data selection circuit 321D as a write signal WT ₃ via the write signal output terminal WT _D, and control the processing end signal END ₃ via the selection switch SW _D31 and processing end signal output terminal END _D Output to the control signal generating circuit 323D and the processing pointer 523 of the device 23. Incidentally, the subtraction operation time of the down counter DCNT is determined by a "constant" given to the data input terminal D, and consideration is given to securing a time required for processing the load effective address instruction.

[0708] Register circuits RGS _{D1 to} RGS of holding circuit 421D
In _D3, the processing circuit 221D i.e. load effective address instruction processing circuit 221D ₃ in response to the write signal WT ₃ provided from the output data S _D1 to S _D3 processing block 21D is held,
Toward the output end Q to the arithmetic left shift instruction processing circuit 221A ₅ outputs as the input data S _D1 to S _D3.

[0709] In processing pointer 523 of the control unit 23, when the processing end signal END ₃ from the processing circuit 221D i.e. load effective address instruction processing circuit 221D ₃ of the processing block 21D provided, the output of the OR circuit OR ₅ is a high level, shifting the output "0" of the flip-flop FF ₅₀ to the flip-flop FF _51, and shifts the output "0" of the flip-flop FF ₅₁ to the flip-flop FF _52, and the flip-flop FF
Shifting ₅₂ the output "0" of the flip-flop FF _53, and shifts the output "1" of the flip-flop FF ₅₃ to the flip-flop FF _50. For this reason, the processing command signals PPQ ₀ to
As shown in Table 28, PPQ ₃ is “1”,
They are "0", "0", and "0".

[0710] In the control signal generation circuit 323D of the control device 23,
When a processing end signal END ₃ is given from the processing circuit 221D of the processing block 21D, that is, the load effective address instruction processing circuit 221D ₃ , the output of the OR circuit OR _3D1 becomes high level, and the contents held in the constructed flag signal generation circuit CENDF _3D are read. Cleared and constructed flag signal CEND output from output terminal Q
The F ₃ and inactive as shown in Table 28 (that is, "0"). This is accompanied, the output or process start signal STRT ₃ AND circuit the AND _3D4, an inactive (i.e. "0").

[0711] In the control signal generation circuit 323D of the control device 23,
When the processing end signal END ₃ supplied from the processing circuit 221D i.e. load effective address instruction processing circuit 221D ₃ processing blocks 21D, the processed flag signal generating circuit PENDF _3D "1"
Is captured, the processed flag signal PENDF ₃ being output from the output terminal Q and active as shown in Table 28 (that is, "1"). Along with this, AND circuit AND
_3D1 is the time when the construction command signal CPQ ₃ is newly activated (that is, “1”), and the construction operation of a new arithmetic circuit is performed.
(Here, the selection operation) is started in the same manner as described above.

[0712] In other words, the control signal generating circuit 323D of the control device 23, the processing circuit 221D i.e. load effective address instruction processing circuit 221D ₃ of the processing block 21D until the process end signal END ₃ supplied, processed flag signal generator Circuit PE
“1” is not taken into the NDF _3D, and the processed flag signal PENDF ₃ output from the output terminal Q is maintained in an inactive state (ie, “0”) as shown in Table 27. Accordingly, the output of the AND circuit AND _3D1 is maintained in an inactive state (ie, “0”), and the construction command signal CPQ ₃ given from the construction pointer 423 is temporarily activated (ie, “1”). )), Processing block 21D
Does not restart the operation of constructing the operation circuit (selection operation here).

Processing in processing circuit 221A: arithmetic left shift
Execution of instruction

[0714] When the arithmetic left shift instruction processing circuit 221A ₅ as a processing circuit 221A of the processing block 21A is selected, Table 2
As apparent from FIG. 9, in addition to the processing command signal PPQ ₀ given from the processing pointer 523 being active (ie, “1”), the constructed flag signal CENDF ₀ is active (ie, “1”). , output or process start signal STRT ₀ of the aND circuit the aND _3A4 of the control signal generating circuit 323A is active
(I.e. "1"), and applied through an arithmetic left shift instruction processing circuit processing start signal input STRT to processing start signal input terminal STRT _A of 221A ₅ processing blocks 21A (FIG. 34A, FIG. 34B, FIG. 43 And FIG. 54). Incidentally, since the processed flag signal PENDF ₀ is inactive (that is, “0”) as apparent from Table 29, the output of the AND circuit AND _3A1 of the control signal generation circuit 323A is inactive (ie, “0”). ), And the construction command signal CPQ ₀ given from the construction pointer 423 is temporarily activated (ie, “1”).
Does not restart the operation of constructing the arithmetic circuit (the selection operation here) in the processing block 21A. In other words, the arithmetic left shift instruction processing circuit 221A of the processing block 21A
₅ at the required processing (i.e. processing of an arithmetic left shift instruction) to complete before a new operation circuit to process block 21A is prevented from being built (selected here).

[0715] At processing block 21A arithmetic left shift instruction processing circuit 221A ₅ of the processing start signal STRT ₀ given to the process start signal input STRT, are given to the load input terminal LD of the shift register SR (Fig. 54 See).

When the processing start signal STRT ₀ is _{supplied to} the load input terminal LD, the shift register SR is _supplied to the data input terminal D from the input data selection circuit 121A via the data input terminals D _AAIN and D _AIN . The first to fifteenth bits of the input data S _AAIN are taken in.

[0717] Instruction decoder 223A of the control unit 23, by decoding an instruction INST ₀ given from the instruction register 123A, after outputted a circuit selection signal SC _0, inputs the input data selection signal SIA _0, SIB ₀ data It is given to the selection circuit 121A, and has given the output data selection signal SO ₀ to the output data selection circuit 321A.

[0718] Arithmetic left shift instruction processing circuit 221A _5, data input to the data input D of the shift register SR D _AAIN, the input data S _AAIN from the input data selecting circuit 121A via the D _AIN given and shift input Input data selection circuit via data input terminals D _ABIN and D _BIN to terminal SFT
The input data S _ABIN is provided from 121A, and the first to fifteenth bits of the input data S _{AAIN fetched} from the data input terminal D are shifted according to the input data S _{ABIN supplied} to the shift input terminal SFT. , Output from the output terminal F, and add the 16th bit of the input data S _AAIN , output from the data output terminal D _{OUT as} output data S _A5 , and output data through the selection switch SW _A51 and the data output terminal D _AOUT. as output data S _A for the selection circuit 321A.

The output data S _A output from the arithmetic left shift instruction processing circuit 221A _{5 is} applied to the data input terminals of the selector circuits SELECT _{A1 to} SELECT _A3 of the output data selection circuit 321A (see FIGS. 30A and 30B). ). The other data input terminals of the selector circuits SELT _{A1 to} SELT _A3 of the output data selection circuit 321A are connected to the register circuits RGS _{D1 to} RGS _{D 3 of the} holding circuit 421D.
Are given as input data S _{D1 to} S _D3 .

[0720] In the output data selection circuit 321A, the control device 23
Output data selection signal given from the instruction decoder 223A of
SO ₀ is decoded by the decoder DEC _A , and the decoding result is selected by the selection signal SO _A1
SOSO _A3 are given to the selection signal input terminals of the selector circuits SELECT _A1 SELSEL _A3 . Here, Table 17 and Table 18
As is apparent from FIG. 7, the selection signal SO _A1 is active (ie, “1”), and the selection signals SO _A2 , SO _A3 are inactive (ie, “0”).

The selector circuit SELT _A1 selects the output data S _A because the selection signal SO _A1 is active (ie, “1”), and outputs the output data S _{A1 to} the register circuit RGS _A1 of the holding circuit 421A. I do.

[0722] Since the selection signal SO _A2 is inactive (that is, "0"), the selector circuit SELT _A2 selects the input data S _D2 and directs it as output data S _{A2 to} the register circuit RGS _A2 of the holding circuit 421A. Output.

[0723] Since the selection signal SO _A3 is inactive (that is, "0"), the selector circuit SELT _A3 selects the input data S _D3 and sends it as output data S _{A3 to} the register circuit RGS _A3 of the holding circuit 421A. Output.

[0724] The shift register SR is, after sending the output from the output terminal F, and outputs a processing end signal S _ENDA5 from processing end signal output terminal END, via a selection switch SW _A52 and the write signal output terminal WT _A calligraphy outputs for the output data selection circuit 321A as the write signal WT _0, and the control signal generating circuit 323A and the processing pointer 523 of the selected switch SW _A52 and processing end signal output terminal eND via the _a processing end signal eND ₀ as a control device 23 Output to.

[0725] Register circuits RGS _{A1 to} RGS of holding circuit 421A
In _A3, the processing circuit 221A that is, the output data S _A1 to S _A3 in response to the write signal WT ₀ supplied from an arithmetic left shift instruction processing circuit 221A ₅ is held, the processing circuit 221B from the output terminal Q
That Toward store instruction processing circuit 221B ₂ outputs as the input data S _A1 to S _A3.

[0726] In processing pointer 523 of the control unit 23, the processing circuit 221A That arithmetic left shift instruction processing circuit 221A ₅ from processing end signal END ₀ processing block 21A is provided,
The output of the OR circuit OR ₅ becomes high level, shifts the output "1" of the flip-flop FF ₅₀ to the flip-flop FF _51, and takes in the "0" to the flip-flop FF _50. Therefore, the processing command signals PPQ _{0 to} PPQ ₃ are “0”, “1”, “0”, and “0”, respectively, as shown in Table 30.

[0727] In the control signal generation circuit 323A of the control device 23,
When a processing end signal END ₀ is given from the processing circuit 221A of the processing block 21A, that is, the arithmetic left shift instruction processing circuit 221A ₅ , the output of the OR circuit OR _3A1 becomes high level, and the contents held in the constructed flag signal generation circuit CENDF _3A are changed. Table 3 shows that the completed flag signal CENDF ₀ output from the output terminal Q is cleared.
It is inactive (ie, “0”) as shown in FIG. This is accompanied, the output or process start signal STRT ₀ of the AND circuit the AND _3A4, a non-active (i.e. "0").

[0727] In the control signal generation circuit 323A of the control device 23,
When the processing circuit 221A That process end signal END ₀ from the arithmetic left shift instruction processing circuit 221A ₅ of the processing block 21A is provided, processed flag signal generating circuit PENDF _3A to "1" is captured and is outputted from the output terminal Q Processed flag signal
PENDF ₀ is active as shown in Table 30 (ie "1")
And _Along with this, the AND circuit AND _{3A1 waits} for the construction command signal CPQ _{0 to} become newly active (that is, “1”), and for the construction operation of a new arithmetic circuit (here, the selection operation).
Is started in the same manner as described above.

[0729] In other words, the control signal generating circuit in 323A, the processing block 21A of processing circuit 221A That arithmetic left shift instruction processing circuit 221A ₅ from processing end signal END ₀ of the control device 23
Until it is given, the processed flag signal generator PENDF _3A
, And the processed flag signal PENDF ₀ output from the output terminal Q is maintained in an inactive state (ie, “0”) as shown in Table 29. Accordingly, the output of the AND circuit AND _3A1 is maintained in an inactive state (ie, “0”), and the construction pointer
The construction command signal CPQ ₀ given from 423 is temporarily active.
Even if it becomes (1), the operation for constructing the arithmetic circuit (the selecting operation here) in the processing block 21A cannot be restarted.

Processing in processing circuit 221B: Store instruction
Run

[0731] processing when the store instruction processing circuit 221B ₂ as the processing circuit 221B of the block 21B is selected, the processing instruction signal PPQ ₁ have been given from as apparent processing pointer 523 in Table 31 is active (i.e. "1") In addition, the constructed flag signal CENDF ₁ is active (ie, “1”).
Therefore, the AND circuit AND _{3 B4} of the control signal generation circuit 323B
, Ie, the processing start signal STRT ₁ becomes active (ie, “1”), and is supplied to the processing start signal input end STRT of the store instruction processing circuit 221B ₂ of the processing block 21B via the processing start signal input end STRT _B. (FIG. 35A, FIG. 35
B, FIG. 44 and FIG. 51).

[0732] Store instruction processing circuit 22 of processing block 21B
In 1B _2, the processing start signal STRT ₁ given to the processing start signal input terminal STRT, load input of down counter DCNT LD
(See FIG. 51).

[0733] Down counter DCNT is, when the processing start signal STRT ₁ to the load input LD is given, the data input terminal D
And the subtraction operation is started by taking in the "constant" given to.

[0734] Instruction decoder 223B of the controller 23, by decoding an instruction INST ₁ given from the instruction register 123B, after outputted a circuit selection signal SC _1, inputs the input data selection signal SIA _1, SIB ₁ data given to the selection circuit 121B, and the address signal AD ₁ and index modification signals IXS ₁ a store instruction processing circuit 221B ₂ of the address signal input terminal AD and index modification signal input IXS address signal input terminal AD _B and index modification signal input to It has given through respective end IXS _B.

[0735] store instruction processing circuit in 221B _2, the input data S to the data input terminal D _AIN are supplied from the input data selecting circuit 121B through the data input terminal D _{BA IN
BAIN,} are outputted as the data transfer circuit DTRF already processed through the data output terminal D _B from a data output terminal D via the data DAT _BBS ^* (i.e. ^* S _BBS) on the data bus 25.

[0736] In the store instruction processing circuit 221B _2, address signals AD ₁ is, is given to the data input terminal B of the adder ADD, the data input terminal D _BBIN to the data input terminal A, the input data selected via the D _BIN The data is added to the input data S _{BBIN supplied} from the circuit 121B and output from the output terminal F.

[0737] The selector circuit SELT is responsive to the index modification signal IXS ₁ is non-active (i.e. "0"),
Address signal AD ₁ without selecting the output of adder ADD
And outputs the address signal AD _{BBS from the} address signal output terminal AD _OUT to the data bus 25 via the address signal output terminal AD _BOUT . By the way, the address signal AD _{BB S}
Is "102" as is clear from Tables 17 and 18.

[0738] In the store instruction processing circuit 221B _2, the bus control signal generation circuit BCNTL is, to generate a write signal WT _BBS, bus control signals output BCNT _OUT bus control signals output from the BCNT
Output to the data bus 25 via _BOUT .

[0739] When the address signal AD _BBS and the write signal WT _BBS are applied via the data bus 25, the data holding device 26 sets the processed data DAT _BBS ^* (at address "102" corresponding to the address signal AD _BBS ). That is, S _BBS ^* ) is written and held.

The down counter DCNT has a count of "0".
, The processing end signal _SENDA2 is output from the output terminal Q via the processing end signal output terminal END, and the selection switch SW
_A12 and processing end signal output for directing the processing end signal END ₂ through the output terminal END _B to the control signal generating circuit 323B and the processing pointer 523 of the control unit 23. Incidentally, the subtraction operation time of the down counter DCNT is determined by a "constant" given to the data input terminal D, and consideration is given to securing a time required for processing the store instruction.

[0741] In processing pointer 523 of the control unit 23, the processing circuit 221B That store instruction processing circuit 221B ₂ from the processing end signal END ₂ processing block 21B is applied, the output of the OR circuit OR ₅ is a high level, the flip-flop FF ₅₀
Shifting the output of "0" to the flip-flop FF _51, and the flip-flop output "1" of the flip-flop FF ₅₁
It shifted to FF _52, and takes in the "0" to the flip-flop FF _50. Therefore, the processing command signals PPQ _{0 to} PPQ ₃ are as shown in Table 3.
As shown in FIG. 2, “0”, “0”, “1”,
It becomes “0”.

The control signal generation circuit 323B of the control device 23
When a processing end signal END ₂ is given from the processing circuit 221B of the processing block 21B, that is, the store instruction processing circuit 221B ₂ , the output of the OR circuit OR _3B1 becomes high level, and the contents held in the constructed flag signal generation circuit CENDF _3B are cleared. , The constructed flag signal CENDF ₂ output from the output terminal Q is made inactive (ie, “0”) as shown in Table 32. Accordingly, the output of the AND circuit AND _3B4 , that is, the processing start signal
STRT ₂ becomes inactive (ie, “0”).

[0743] In the control signal generation circuit 323B of the control device 23,
When the processing circuit 221B That store instruction processing circuit 221B ₂ from processing end signal END ₁ processing block 21B is given, processed flag signal generating circuit PENDF _3B "1" is captured, the process being outputted from the output terminal Q Completed flag signal PEND
As the F ₁ shown in Table 32 and active (i.e. "1"). Accordingly, the AND circuit AND _{3B1 waits} for the construction command signal CPQ _{1 to} become newly active (that is, “1”), and performs the construction operation of the new arithmetic circuit (here, the selection operation) in the same manner as described above. To start.

[0744] In other words, the control signal generating circuit 323B of the control device 23, the processing circuit 221B That store instruction processing circuit 221B ₂ of the processing block 21B to the processing end signal END ₁ is given, processed flag signal generating circuit PENDF "1" is not to be taken in _3B, output processing is outputted from the Q flag signal PENDF ₁ is maintained in a state of non-active as shown in Table 31 (that is, "0"). Accordingly, the output of the AND circuit AND _3B1 is maintained in an inactive state (ie, “0”), and the construction pointer 42
Even if the construction command signal CPQ ₁ given from 3 becomes active (that is, “1”), the construction operation (here, the selection operation) of the arithmetic circuit in the processing block 21B is not restarted.

(Third Embodiment)

In addition, FIGS. 28 to 33B and FIG.
The configuration and operation of the third embodiment of the computer according to the present invention will be described in detail with reference to FIGS. 8A to 58B.

In the third embodiment, processing blocks 21A to 21D
Except that the processing circuits 221A to 221D are replaced by the processing circuits 231A to 231D, the configuration and operation and effect are the same as those of the second embodiment. That is, in the third embodiment, the load instruction processing circuit 231A ₁ included in the processing circuits 231A to 231D is used.
~231D _1, the store instruction processing circuit 231A ₂ ~231D _2, load effective address instruction processing circuit 231A ₃ ~231D _3, add instruction processing circuit
231A _{4 to} 231D ₄ and arithmetic left shift instruction processing circuit 231A ₅
~231D Each AND circuit the AND _A1 to processing start signal input STRT of _{5 ~AND D1; AND A2 ~AND D2} ; AND A3 ~AND D3; AN
D _{A4 to} AND _D4 ; Output terminals of AND _{A5 to} AND _D5 are connected, and AND circuit AND _{A1 to} AND _A5 ; AND _{B1 to} AND _{B 5} ; AND _{C1 to} AND
_c5 ; Processing start signal input terminals STRT _{A to} STRT _D are connected to one of the input terminals of AND _{D1 to} AND _D5 , and AND circuit AND
_{A1 to} AND _D1 ; AND _{A2 to} AND _D2 ; AND _{A3 to} AND _D3 ; AND _{A4 to} AND
_D4 ; Decoder DECD _A for AND _{A5 to} AND _D5
~DECD first to fifth output terminal is connected and _D, process start signal input terminal STRT _A ~ processing circuit 231A~231D
Control signal generation circuits 323A to 32 of the control device 23 for STRT _D
Processing start from the 3D signal STRT ₀ ~STRT ₃ are given and the circuit selection signal SC ₀ from the instruction decoder 223A~223D processing circuit 231A~231D circuit selection signal input terminal SC _A to SC _D to the controller 23 to SC _{When 3} is given, the load instruction processing circuit 231A
_{1 ~231D 1,} the store instruction processing circuit 231A ₂ ~231D _2, the load effective address instruction processing circuit 231A ₃ ~231D _3, add instruction processing circuit 231A ₄ ~231D ₄ and the arithmetic left shift instruction processing circuit 231A
₅ process start signal input STRT to process start signal ～231D ₅ STRT except ₀ that ～STRT ₃ is given, has the same structure and effects as the second embodiment.

[0748] Therefore, referring to the above description of the second embodiment, it is considered that the other configuration and operation and effect of the third embodiment can be sufficiently understood. Therefore, further detailed description will be omitted.

(Modification)

In the above description, processing blocks 11A to 11D;
21A to 21D processing circuit 211A to 211D; 221A to 221D; 231A to
Although only the case where the 231D is constructed in a desired arithmetic circuit has been described, the present invention is not limited to this. , The case where the output data selection circuit and the holding circuit are simultaneously constructed.

In the above description, the processing blocks 11A to 11D;
21A to 21D output data selection circuit 311A to 311D; 321A to 32
1D and holding circuits 411A to 411D; 421A to 421D are 3
Selector circuits SELT _{A1 to} SELT _A3 ; ・ ・ ・; SELT _{D1 to} SELT _D3
And register circuits RGS _{A1 to} RGS _A3 ; ・ ・ ・; RGS _{D1 to} RGS _D3
However, the present invention is not limited to this, and the present invention also includes a case where the output data selection circuit and the holding circuit of the processing block include a desired number of selector circuits and register circuits. are doing.

In addition, in the above description, the case where a load instruction, a load instruction, an addition instruction, an arithmetic left shift instruction and a store instruction are sequentially executed is mainly described, but the present invention is not limited to this. However, all cases where other desired instructions are sequentially executed are included. That is, the present invention covers all cases where not only a load instruction processing circuit, an addition instruction processing circuit, an arithmetic left shift instruction processing circuit, and a store instruction processing circuit but also other desired arithmetic circuits are constructed as processing circuits of a processing block. ing.

In the above description, the processing blocks 11A to 11D;
Only the case where 21A to 21D are functionally adjacent to each other via holding circuits 411A to 411D; 421A to 421D (that is, register circuits RGS _{A1 to} RGS _A3 ; ...; RGS _{D1 to} RGS _D3 ) is described. However, the present invention is not limited to this, and encompasses all cases where functionally adjacent processing blocks are isolated via other desired means.

(Summary of Examples)

In summary of the above-described embodiment, the computer according to the present invention is as follows.

(1) (a) A plurality of processing blocks (11A to 11D;
21A to 21D), and (b) a plurality of processing blocks (11A to 11D) included in the processing device (11; 21).
An output end connected to an input end of each of (21A to 21D), and a circuit construction means for sequentially constructing a desired arithmetic circuit in a predetermined order for a plurality of processing blocks (11A to 11D; 21A to 21D); ) A plurality of processing blocks (11A-
The output terminals are connected to the input terminals of 11D; 21A to 21D), and a desired operation is sequentially performed on a plurality of processing blocks (11A to 11D; 21A to 21D) in an arithmetic circuit sequentially constructed by the circuit constructing means. A computer comprising:

(2) Each of the plurality of processing blocks (11A to 11D) included in the processing device (11) includes: (a) gate circuits of a type and number sufficient to construct a desired arithmetic circuit
(b) A desired number of changeover switches (SWNG _{A1 to} SWNG _Am ; ..., SWNG _{D1 to} S
(WNG _Dm ). The computer according to item (1), comprising:

(3) The circuit construction means comprises: (a) a program holding device (14) for holding a program; and (b) an input terminal connected to an output terminal of the program holding device (14), and a processing device.
A plurality of instruction decoders (213A) which are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in (11) and decode instructions in a program given from a program holding device (14). 213D) and (c) multiple instruction decoders (213
A to 213D) have an input terminal connected to the output terminal and an output terminal included in a plurality of processing blocks (11A to 11D) included in the processing device (11).
D) Changeover switch (SWNG _{A1 to} SWNG _Am ; ...; SWNG _{D1 to} SW
NG _Dm ) and is assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11), and a desired one of the plurality of processing blocks (11A to 11D) is provided. A plurality of instruction decoders (213A to 213A)
Multiple processing blocks depending on the result of decoding the instruction by D)
(11A to 11D) changeover switches (SWNG _{A1 to} SWNG _Am ; ...; SWN
G _{D1 to} SWNG _Dm )
(12A to 12D). The computer according to item (2), comprising:

(4) The circuit construction means comprises: (a) a program holding device (14) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (14) and an output terminal for processing. A plurality of processing blocks (11A to 11A) included in the device (11)
D) which is connected to the input terminal of D) and is assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11), and is provided from the program holding device (14). Multiple instruction decoders (213A to 21
3D) and (c) a plurality of instruction decoders (213A to 213D) each having an input terminal connected to an output terminal and an output terminal included in a plurality of processing blocks (11A to 11D) included in a processing device (11). Processing switches (SWNG _{A1 to} SWNG _Am ;...; SWNG _{D1 to} SWNG _Dm ) and included in the processing device (11).
(11A to 11D), and the result of decoding of instructions by a plurality of instruction decoders (213A to 213D) so as to sequentially construct a desired arithmetic circuit in a plurality of processing blocks (11A to 11D). A plurality of switch control devices (12A to 12D) for sequentially switching the changeover switches (SWNG _{A1 to} SWNG _Am ; ...; SWNG _{D1 to} SWNG _Dm ) in the plurality of processing blocks (11A to 11D) in accordance with
(d) An input terminal is connected to an output terminal of the plurality of instruction decoders (213A to 213D), and an output terminal is connected to input terminals of a plurality of processing blocks (11A to 11D) included in the processing device (11). And a plurality of processing blocks (11A to 11A) included in the processing device (11).
11D), a plurality of processing blocks (11A to 11D) and a plurality of instruction decoders (213A to 213D).
Control signal generation circuits that provide various control signals to the
(313A to 313D) and (e) a plurality of control signal generation circuits (313A to 313D).
313D), the output terminal of which is connected to the input terminals of a plurality of control signal generation circuits (313A to 313D), and a desired arithmetic circuit in the processing blocks (11A to 11D). The construction command signal is given to the control signal generation circuits (313A to 313D) in response to the completion of the construction of the processing blocks (11A to
11D) a construction pointer (413) for instructing the construction of a new arithmetic circuit, and (f) a plurality of control signal generation circuits (313A to 313A).
An input terminal is connected to an output terminal of the program holding device (313D), and an output terminal is connected to an input terminal of the program holding device (14). The computer according to item (2), further comprising: a program counter (613) for giving an instruction to output a new program.

(5) Multiple switch control devices (12A to 12D)
But each, (a) a plurality of sets of holding circuit which holds the pair of switch connection information respectively _{(112A 1 ~112A n; ···;} 112D 1 ~
112D _n ) and a plurality of connection information holding circuits (112A to 112
D) and (b) a plurality of sets of holding circuits (112A _{1 to} 112A _n ;...; 112D _{1 to} 112D included in the connection information holding circuits (112A to 112D).
_n ), the input terminal is connected to the output terminal, and the output terminal is a switch (SWNG _{A1 to} SWNG) in a plurality of processing blocks (11A to 11D).
_Am ; ......; SWNG _{D1 to} SWNG _Dm ), and the control input terminal is connected to a plurality of instruction decoders (213A to 213D), and the result of decoding of instructions by the plurality of instruction decoders (213A to 213D) Multiple connection information holding circuits (112A to 112D) according to
From one of a plurality of sets of switch connection information respectively given by the switches (SWNG _{A1 to} SWNG _Am ;...; SWNG _{D1 to} SWNG _Dm ) in the plurality of processing blocks (11A to 11D).
A plurality of connection information selection circuits (212A to 212
D). The computer according to the above mode (3) or (4), comprising:

(6) The processing execution means comprises (a) a program holding device (14) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (14), and
A plurality of instruction decoders (213A) which are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in (11) and decode instructions in a program given from a program holding device (14). 213D) and (c) multiple instruction decoders (213
A to 213D) have an input terminal connected to the output terminal and an output terminal included in a plurality of processing blocks (11A to 11D) included in the processing device (11).
D) and a plurality of instruction decoders (213A) so as to execute desired arithmetic processing in the arithmetic circuit constructed by the circuit constructing means for the plurality of processing blocks (11A to 11D).
(3) or (3) characterized by comprising arithmetic control means for controlling a plurality of processing blocks (11A to 11D) in a predetermined order in accordance with the result of decoding the program by 4) Computer according to paragraph.

(7) The arithmetic control means comprises: (a) a plurality of instruction decoders (213A to 213D) having input terminals connected to output terminals thereof and output terminals included in the processing unit (11); Blocks (11A to 11D) are connected to input terminals and are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11), and a plurality of processing blocks (11A to 11D), a plurality of control signal generation circuits (313A to 313D) for giving various control signals to an arithmetic circuit and a plurality of instruction decoders (213A to 213D) sequentially constructed by circuit construction means,
(b) A plurality of processing blocks (11A) included in the processing device (11)
Input terminals are connected to the output terminals of a plurality of control signal generation circuits (313A to 313D), and circuit construction is performed for a plurality of processing blocks (11A to 11D). In response to the completion of a desired operation in the arithmetic circuit sequentially constructed by the means, a processing command signal is given to a plurality of control signal generating circuits (313A to 313D) and a plurality of processing blocks (11A
11D), a processing pointer (513) for instructing execution of a new operation, and (c) a plurality of control signal generation circuits (313A to 313).
D) has an input terminal connected to the output terminal and an output terminal connected to the input terminal of the program holding device (14), and the program holding device is connected to the output terminals of the plurality of control signal generating circuits (313A to 313D). The computer according to item (6), further comprising a program counter (613) for giving a command to (14) that a new program should be output.

(8) A plurality of control signal generation circuits (313A to 31
3D), (a) one input terminal is connected to the output terminal of the construction pointer (413), and when the processed flag signal is active, the construction command signal given from the construction pointer (413) is A first AND circuit (AND _{3A1 to} AND _3D1 ) for instructing the start of the construction operation by making the output active when it becomes active
(B) a data input terminal is connected to an output terminal of the first AND circuit (AND _{3A1 to} AND _3D1 ), a clock input terminal is connected to a clock signal source, and a clear input terminal is connected to a reset signal source. After being cleared in response to the reset signal given from the reset signal source, the output of the first AND circuit (AND _{3A1 to} AND _3D1 ) given to the data input terminal is given to the clock input terminal. A shift register (SR _{3A to} S3S) that takes in and shifts according to the clock signal
R _3D ) and (c) two input terminals are respectively connected to two different output terminals of the shift register (SR _{3A to} SR _3D ), and the output terminal is a write signal input terminal of the instruction register (113A to 113D). And an input terminal of a program counter (613). A second AND circuit (AND) generates a write signal and an increment signal and supplies them to the instruction registers (113A to 113D) and the program counter (613), respectively.
_{3A2 to} AND _3D2 ) and (d) shift register (SR _{3A to} SR _3D )
The two input terminals are connected to the other two different output terminals, respectively, and the output terminal is connected to the input terminal of the construction pointer (413).
Third AND circuit for providing a 3) and (AND _3A3 ~AND _3D3),
(e) Processing blocks (11A to 11D) included in the processing device (11)
One input terminal is connected to the processing end signal output terminal of the first embodiment, and the other input terminal is connected to the reset signal source, and the processing end signals supplied from the processing blocks (11A to 11D) and the reset signal source are supplied. When at least one of the reset signals is active, an OR circuit (OR _{3A1 to} OR _3D1 ) _whose output is active and (f) a clear input to the output terminal of the OR circuit (OR _{3A1 to} OR _3D1 ) end connected, and a clock input terminal connected to an output terminal of the third aND circuit (aND _3A3 ~AND _3D3), and data input is connected to a high-level signal source, an OR circuit (OR _3A1 ~ OR _3D1 ) is activated and cleared, and then the third AND circuit (AND _3A3 ~ AN _3D1
D _3D3 ) becomes active, a built-in flag signal generation circuit (CENDF _{3A to} CENDF) that takes in a high-level signal from a high-level signal source and makes the built-up flag signal output from the output end active. _3D ) and (g) third AND circuit (AND
_{3A3 ~AND 3D3)} clear input to the output end is connected, and a clock input terminal connected to the processing end signal output terminal of the processing unit (11) to the inclusion the treated blocks (11A to 11D), and The preset input is connected to a reset signal source, and the data input is connected to a high level signal source,
The output terminal is connected to the other input terminal of the first AND circuit (AND _{3A1 to} AND _3D1 ), and when a reset signal supplied from a reset signal source becomes active, a high-level signal is taken in. the output of the third aND circuit (aND _3A3 ~AND _3D3) is cleared when the active processing block (11A～11
When the processing end signal given from D) becomes active, it takes in a high-level signal from a high-level signal source, outputs it from the output terminal, and _supplies it to the first AND circuit (AND _{3A1 to} AND _3D1 ). A processed flag signal generation circuit (PENDF _{3A to} PENDF _3D ) that activates the processed flag signal, and (h) a processing pointer
One input terminal is connected to the output terminal of (513), and the other input terminal is a constructed flag signal generation circuit (CENDF _{3A to} CENDF _3D )
The processing command signal and the constructed flag signal generation circuit provided from the processing pointer (513)
(CENDF _{3A to} CENDF _3D ) Outputs a processing start signal when both of the constructed flag signals given are active, and gives the processing start signal to the processing blocks (11A to 11D) included in the processing device (11). The computer _{according to the} above _mode (4) or (7), _{comprising an} AND circuit (AND _{3A4 to} AND _3D4 ).

(9) A plurality of processing blocks (11A to 11D; 21A to 21D) included in the processing device (11; 21) are connected to the output end of the processing execution means, respectively. An input data selection circuit (111A to 11A) which selects and outputs input data given from the processing block according to the output of the processing execution means.
1D; 121A to 121D) and (b) the input data selection circuit (111A to 121D).
111D; 121A to 121D), an input terminal is connected to an output terminal, and an input / output terminal is connected to a data holding device via a data bus (15; 25).
(16; 26), and the control input terminal is connected to the output terminal of the circuit construction means and the output terminal of the processing execution means,
After a desired arithmetic circuit is constructed according to the output of the circuit construction means, an input data selection circuit (111A to 111D; 121A to 121D)
Input data or data holding device given from (16;
26) performs a desired operation on the unprocessed data provided via the data bus (15; 25) in accordance with the output of the processing execution means, and outputs the operation result from the output terminal in accordance with the output of the processing execution means A processing circuit (211A to 211D; 221A) that outputs as data or outputs as processed data from the input / output terminal to the data holding device (16; 26) via the data bus (15; 25).
~ 221D; 321A ~ 321D) and (c) the processing circuit (211A ~ 211D; 2
21A to 221D; 321A to 321D) have one input terminal connected thereto, the other input terminal connected to the output terminal of the preceding processing block, and the control input terminal connected to the output terminal of the processing execution means. An output data selection circuit (311A to 321D) selects and outputs one of the output of the preceding processing block and the output of the processing circuit (211A to 211D; 221A to 221D; 321A to 321D) according to the output of the processing execution means. 311D; 321A to 321D) and (d)
The input terminal is connected to the output terminal of the output data selection circuit (311A to 311D; 321A to 321D), and the write signal input terminal is connected to the processing circuit.
(211A to 211D; 221A to 221D; 321A to 321D), and the output terminal is connected to the input terminal of the subsequent processing block, and the output data selection circuit (311A to 311
1D; 321A to 321D), captures and holds the output data selected by the processing circuit (211A to 211D; 221A to 221D; 321A to 321D) according to the write signal given thereto, and outputs it to the subsequent processing block. Holding circuits (411A-411D; 421A-
421D). The computer according to item (1), comprising:

(10) The processing circuits (211A to 211D) of the plurality of processing blocks (11A to 11D) included in the processing device (11) are respectively (a) sufficient for constructing a desired arithmetic circuit. (B) a desired number of changeover switches (SWNG _A1
... (SWNG _Am ; SWNG _{D1 to} SWNG _Dm ).

(11) The circuit construction means comprises: (a) a program holding device (14) for holding a program; and (b) an input terminal connected to an output terminal of the program holding device (14), and a processing device.
A plurality of instruction decoders (213A) which are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in (11) and decode instructions in a program given from a program holding device (14). 213D) and (c) multiple instruction decoders (213
A to 213D) have an input terminal connected to the output terminal and an output terminal included in a plurality of processing blocks (11A to 11D) included in the processing device (11).
D) processing circuit (211A to 211D) changeover switch (SWNG _A1
~ SWNG _Am ; ・ ・ ・; SWNG _{D1 to} SWNG _Dm ) and are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11). Processing block (11A
To 11D), a plurality of instruction decoders (213A to 213D) to sequentially construct a desired arithmetic circuit in the processing circuits (211A to 211D).
Processing blocks (11A
Switch (SWN) in the processing circuit (211A to 211D)
G _{A1 to} SWNG _Am ; ...; SWNG _{D1 to} SWNG _Dm ), and a plurality of switch control devices (12A to 12D) for sequentially switching the computer. .

(12) The circuit construction means comprises: (a) a program holding device (14) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (14) and an output terminal for processing. A plurality of processing blocks (11A to 11A) included in the device (11)
D) which is connected to the input terminal of D) and is assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11), and is provided from the program holding device (14). Multiple instruction decoders (213A to 21
3D) and (c) a plurality of instruction decoders (213A to 213D) each having an input terminal connected to an output terminal and an output terminal included in a plurality of processing blocks (11A to 11D) included in a processing device (11). Processing switches (SWNG _{A1 to} SWNG _Am ;...; SWNG _{D1 to} SWNG _Dm ) and included in the processing device (11).
(11A to 11D), and the result of decoding of instructions by a plurality of instruction decoders (213A to 213D) so as to sequentially construct a desired arithmetic circuit in a plurality of processing blocks (11A to 11D). A plurality of switch control devices (12A to 12D) for sequentially switching the changeover switches (SWNG _{A1 to} SWNG _Am ; ...; SWNG _{D1 to} SWNG _Dm ) in the plurality of processing blocks (11A to 11D) in accordance with
(d) An input terminal is connected to an output terminal of the plurality of instruction decoders (213A to 213D), and an output terminal is connected to input terminals of a plurality of processing blocks (11A to 11D) included in the processing device (11). And a plurality of processing blocks (11A to 11A) included in the processing device (11).
11D), a plurality of processing blocks (11A to 11D) and a plurality of instruction decoders (213A to 213D).
Control signal generation circuits that provide various control signals to the
(313A to 313D) and (e) a plurality of control signal generation circuits (313A to 313D).
313D), the output terminal of which is connected to the input terminals of a plurality of control signal generation circuits (313A to 313D), and a desired arithmetic circuit in the processing blocks (11A to 11D). The construction command signal is given to the control signal generation circuits (313A to 313D) in response to the completion of the construction of the processing blocks (11A to
11D) a construction pointer (413) for instructing the construction of a new arithmetic circuit, and (f) a plurality of control signal generation circuits (313A to 313A).
The input terminal is connected to the output terminal of the program holding device (313D), and the output terminal is connected to the input terminal of the program holding device (14). (10). The computer according to (10), further comprising: a program counter (613) for giving a command to output a new program.

(13) A plurality of switch control devices (12A to 12D)
Are respectively (a) a plurality of sets of holding circuits (112A _{1 to} 112A _n ;...; 112D each holding one set of switch connection information.
_{1 to} 112D _n ) and a plurality of connection information holding circuits (112A to 112Dn).
And 112D), (b) the connection information holding circuit (112A ~112D) in the inclusions a plurality of sets of holding circuits _{(112A 1 ~112A n; ···;} 112D 1 ~11
The input terminal is connected to the output terminal of 2D _n ), and the output terminal is a changeover switch (SWNG _{A1 to} SWNG _Am ;...; SWNG in the processing circuits (211A to 211D) of the plurality of processing blocks (11A to 11D). _{D1 to} SWNG _Dm )
And the control input is connected to a plurality of instruction decoders (213
A to 213D) and a plurality of instruction decoders (213
A to 213D), one set of a plurality of sets of switch connection information respectively given from the plurality of connection information holding circuits (112A to 112D) is selected in accordance with the result of decoding the instruction by the plurality of processing blocks (11A to 213D). processing circuit 11D) (211A ~211D) changeover switch (SWNG _A1 ~SWNG _{Am in; ···; SWNG D 1 ~SWNG Dm} ) given to each of the plurality of connection information selection circuit (212A ~212D)
Or (11) or
Computer according to paragraph (12).

(14) The processing execution means comprises: (a) a program holding device (14) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (14), and
A plurality of instruction decoders (213A to 213A to 11C) assigned to the processing blocks (11A to 11D) included in (11) on a one-to-one basis to decode a program given from the program holding device (14). 213D) and (c) multiple instruction decoders (213A
213D), the input terminals of which are connected to the output terminals, and the output terminals of which are included in the processing device (11).
And a plurality of instruction decoders (213A to 213A) to execute desired arithmetic processing in the arithmetic circuit constructed by the circuit constructing means in the plurality of processing blocks (11A to 11D).
And (D) a control unit for controlling a plurality of processing blocks (11A to 11D) in a predetermined order in accordance with a result of decoding the program.
Computer according to paragraph (12).

(15) The arithmetic control means comprises: (a) a plurality of instruction decoders (213A to 213D) having input terminals connected to output terminals thereof and output terminals included in the processing unit (11); Blocks (11A to 11D) are connected to input terminals and are assigned one-to-one to a plurality of processing blocks (11A to 11D) included in the processing device (11), and a plurality of processing blocks (11A to 11D) a plurality of control signal generation circuits (313A to 313D) for giving various control signals to the arithmetic circuit and the plurality of instruction decoders (213A to 213D) sequentially constructed by the circuit construction means;
(b) A plurality of processing blocks (11A) included in the processing device (11)
11D), and the output terminal is connected to the input terminals of a plurality of control signal generation circuits (313A to 313D), and a circuit is constructed in a plurality of processing blocks (11A to 11D). Means for processing a plurality of control signal generating circuits in response to completion of a desired operation in an arithmetic circuit sequentially constructed by means
(313A to 313D) and a processing pointer (51) instructing execution of a new operation in a plurality of processing blocks (11A to 11D).
3) and (c) the input terminals are connected to the output terminals of the plurality of control signal generation circuits (313A to 313D), and the output terminals are connected to the input terminals of the program holding device (14). A program counter (613) for giving a command to output a new program to the program holding device (14) in accordance with the output of the signal generation circuits (313A to 313D). Computer according to item 13).

(16) A plurality of control signal generation circuits (313A to 31
3D), (a) one input terminal is connected to the output terminal of the construction pointer (413), and when the processed flag signal is active, the construction command signal given from the construction pointer (413) is A first AND circuit (AND _{3A1 to} AND _3D1 ) for instructing the start of the construction operation by making the output active when it becomes active
(B) a data input terminal is connected to an output terminal of the first AND circuit (AND _{3A1 to} AND _3D1 ), a clock input terminal is connected to a clock signal source, and a clear input terminal is connected to a reset signal source. After being cleared in response to the reset signal given from the reset signal source, the output of the first AND circuit (AND _{3A1 to} AND _3D1 ) given to the data input terminal is given to the clock input terminal. A shift register (SR _{3A to} S3S) that takes in and shifts according to the clock signal
R _3D ) and (c) two input terminals are respectively connected to two different output terminals of the shift register (SR _{3A to} SR _3D ), and the output terminal is a write signal input terminal of the instruction register (113A to 113D). And an input terminal of a program counter (613). A second AND circuit (AND) generates a write signal and an increment signal and supplies them to the instruction registers (113A to 113D) and the program counter (613), respectively.
_{3A2 to} AND _3D2 ) and (d) shift register (SR _{3A to} SR _3D )
The two input terminals are connected to the other two different output terminals, respectively, and the output terminal is connected to the input terminal of the construction pointer (413).
Third AND circuit for providing a 3) and (AND _3A3 ~AND _3D3),
(e) Processing blocks (11A to 11D) included in the processing device (11)
One input terminal is connected to the processing end signal output terminal of the first embodiment, and the other input terminal is connected to the reset signal source, and the processing end signals supplied from the processing blocks (11A to 11D) and the reset signal source are supplied. When at least one of the reset signals is active, an OR circuit (OR _{3A1 to} OR _3D1 ) _whose output is active and (f) a clear input to the output terminal of the OR circuit (OR _{3A1 to} OR _3D1 ) end connected, and a clock input terminal connected to an output terminal of the third aND circuit (aND _3A3 ~AND _3D3), and data input is connected to a high-level signal source, an OR circuit (OR _3A1 ~ OR _3D1 ) is activated and cleared, and then the third AND circuit (AND _3A3 ~ AN _3D1
D _3D3 ) becomes active, a built-in flag signal generation circuit (CENDF _{3A to} CENDF) that takes in a high-level signal from a high-level signal source and makes the built-up flag signal output from the output end active. _3D ) and (g) third AND circuit (AND
_{3A3 ~AND 3D3)} clear input to the output end is connected, and a clock input terminal connected to the processing end signal output terminal of the processing unit (11) to the inclusion the treated blocks (11A to 11D), and The preset input is connected to a reset signal source, and the data input is connected to a high level signal source,
The output terminal is connected to the other input terminal of the first AND circuit (AND _{3A1 to} AND _3D1 ), and when a reset signal supplied from a reset signal source becomes active, a high-level signal is taken in. the output of the third aND circuit (aND _3A3 ~AND _3D3) is cleared when the active processing block (11A～11
When the processing end signal given from D) becomes active, it takes in a high-level signal from a high-level signal source, outputs it from the output terminal, and _supplies it to the first AND circuit (AND _{3A1 to} AND _3D1 ). A processed flag signal generation circuit (PENDF _{3A to} PENDF _3D ) that activates the processed flag signal, and (h) a processing pointer
One input terminal is connected to the output terminal of (513), and the other input terminal is a constructed flag signal generation circuit (CENDF _{3A to} CENDF _3D )
The processing command signal and the constructed flag signal generation circuit provided from the processing pointer (513)
(CENDF _{3A to} CENDF _3D ) Outputs a processing start signal when both of the constructed flag signals supplied from the processing unit are active, and supplies the processing start signal to the processing blocks (11A to 11D) included in the processing device (11). of the aND circuit (aND _3A4 ~AND _3D4) first (12) and characterized by being obtained by inclusion of the term or the (15) computer according to item.

(17) The processing circuits (221A to 221D) of the plurality of processing blocks (21A to 21D) included in the processing device (21) are respectively (a) sufficient for constructing a desired arithmetic circuit. and _{(221D 1 ~221D 5 221A 1 ~221A} 5;; ···), (b) the arithmetic circuit type operation circuit to the output terminal of the _{(221A 1 ~221A 5; 221D 1} ~221D 5; ···) is disposed, the arithmetic circuit _{(221A 1 ~221A 5; ···;} 221D 1 ~
221D ₅ ) to select one of the switches (SW
_{A11 to} SW _A15 , SW _{A22 to} SW _A25 , SW _A31 , SW _A32 , SW _A41 , SW _A42 , S
W _A51 , SW _A52 ; ・ ・ ・; SW _{D11 to} SW _D15 , SW _{D22 to} SW _D25 , SW _D31 , S
The computer according to item (9), comprising: W _D32 , SW _D41 , SW _D42 , SW _D51 , and SW _D52 ).

(18) The circuit construction means comprises: (a) a program holding device (24) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (24) and an output terminal for processing. A plurality of processing blocks (21A to 21A) included in the device (21)
D) is assigned to the plurality of processing blocks (21A to 21D) included in the processing device (21) one-to-one and connected to the input terminal of the processing device (21), and is provided from the program holding device (24). Multiple instruction decoders (223A to 22
3D) and (c) a plurality of processing blocks (21A to 21D) whose input terminals are connected to the output terminals of the instruction decoders (223A to 223D) and whose output terminals are included in the processing device (21). Processing circuit (221
A to 221D; 231A to 231D) selection switches (SW _{A11 to} SW _A1)
5 , SW _{A22 to} SW _A25 , SW _A31 , SW _A32 , SW _A41 , SW _A42 , SW _A51 , SW
_A52 ; ・ ・ ・; SW _{D11 to} SW _D15 , SW _{D22 to} SW _D25 , SW _D31 , SW _D32 , SW
_D41 , SW _D42 , SW _D51 , SW _D52 ) and a processing device (21)
The arithmetic circuits (221A to 221D; 231A to 231D) in the processing circuits (221A to 221D; 231A to 231D) of the plurality of processing blocks (21A to 21D) are assigned on a one-to-one basis. 221
_{A 1 ~221A 5; ···; 221D} 1 ~221D 5; 231A 1 ~231A 5; ···; 231D
_{1 ~231D 5)} by selecting one of the to sequentially build the desired arithmetic circuit, selection switch (SW _A11 to SW in accordance with the decoded result of the instruction by a plurality of instruction decoders (223A ~223D)
_{A15, SW A22 ~SW A2 5,} SW A31, SW A32, SW A41, SW A42, SW A51, SW
_A52 ; ・ ・ ・; SW _{D11 to} SW _D15 , SW _{D22 to} SW _D25 , SW _D31 , SW _D32 , SW
_D41 , SW _D42 , SW _D51 , SW _D52 ) and a plurality of switch closing means (DECD _{A to} DECD _D ), and (d) a plurality of instruction decoders (223A
223D), an input end of which is connected to the output end, and an output end of which is included in the processing device (21).
Are assigned one-to-one to a plurality of processing blocks (21A to 21D) included in the processing device (21) and a plurality of processing blocks (21A to 21D) and a plurality of instructions. Input terminals are connected to output terminals of a plurality of control signal generation circuits (323A to 323D) for supplying various control signals to the decoders (223A to 223D) and (e) a plurality of control signal generation circuits (323A to 323D). , And the output terminal has a plurality of control signal generation circuits (323A to
323D) and connected to the processing block (21A ~
21D), the construction command signal is sent to a plurality of control signal generation circuits (323A to 323) in accordance with the completion of the construction of the desired arithmetic circuit.
D) and a construction pointer (523) for instructing the construction of a new arithmetic circuit in the processing blocks (21A to 21D), and (f) an input terminal at an output terminal of the plurality of control signal generation circuits (323A to 323D). And the output terminal is connected to the input terminal of the program holding device (24), and the control signal generating circuits (323A to 323A) are connected.
A program counter (623) for giving a command to output a new program to the program holding device (24) in response to the output of (D). Computer.

(19) The processing execution means comprises (a) a program holding device (24) for holding a program, and (b) an input terminal connected to an output terminal of the program holding device (24), and
A plurality of instruction decoders (2) assigned one-to-one to a plurality of processing blocks (21A to 21D) included in (21) and decoding a program given from a program holding device (24).
23A to 223D) and (c) a plurality of instruction decoders (223A to 223D).
The input terminal is connected to the output terminal of D), and the output terminal is connected to a plurality of processing blocks (21A to 21D) included in the processing device (21), and a plurality of processing blocks (21A to 21D). A plurality of processing blocks in accordance with the result of decoding the program by the plurality of instruction decoders (223A to 223D) so as to execute a desired arithmetic processing in the arithmetic circuit constructed by the circuit constructing means.
The computer according to item (17) or (18), further comprising: an arithmetic control unit that controls (21A to 21D) in a predetermined order.

(20) The arithmetic control means comprises: (a) a plurality of instruction decoders (223A to 223D) having an input terminal connected to the output terminal thereof and an output terminal embedded in the processing device (21); It is connected to the input end of the block (21A to 21D) and is assigned one-to-one to a plurality of processing blocks (21A to 21D) included in the processing device (21), and a plurality of processing blocks (21A to 21D). 21D) a plurality of control signal generating circuits (323A to 323D) for giving various control signals to the arithmetic circuit and the plurality of instruction decoders (223A to 223D) sequentially constructed by the circuit constructing means;
(b) A plurality of processing blocks (21A) included in the processing device (21)
21D), and the output terminal is connected to the input terminals of a plurality of control signal generation circuits (323A to 323D), and a circuit is constructed in a plurality of processing blocks (21A to 21D). A plurality of control signal generating circuits for processing instruction signals in response to completion of a desired operation in an arithmetic circuit sequentially constructed by means
(323A to 323D) to indicate the execution of a new operation in a plurality of processing blocks (21A to 21D) (52
3) and (c) a plurality of control signal generation circuits (323A to 323D) whose input terminals are connected to the output terminals and whose output terminals are connected to the input terminals of the program holding device (24). A program counter (623) for instructing the program holding device (24) to output a new program in accordance with the output of the signal generation circuits (323A to 323D). The computer of paragraph (18).

[0776] (21) processing execution means, (d) a plurality of processing circuits (231A ～231D) each arithmetic circuits in the processing block _{(21A~21D) (231A 1 ~231A 5} ; ···; 231D 1 ~ The output terminal is connected to the processing start signal input terminal of 231D ₅ ), one input terminal is connected to the output terminals of the switch-on means (DECD _{A to} DECD _D ), and the other input terminal is processed by the arithmetic control means. It is connected to the start signal output terminal, and the selection switches (SW _{A11 to} SW _A15 , SW _{A22 to} SW _A25 , SW _A31 , SW _A32 , SW _{A11 to} SW _A15 by switch closing means (DECD _{A to} DECD _D )
SW _A41 , SW _A42 , SW _A51 , SW _A52 ; ・ ・ ・; SW _D11 to SW _D15 , SW _D22 to
_{SW D25, SW D31, SW D32} , SW D41, SW D42, SW D51, SW arithmetic circuit processing start signal only during introduction of _{D52) (231A 1 ~231A 5;} ···; 231D
AND circuit to be supplied to the _{1 ~231D 5) (AND A1 ~AND} A5; ···; AND
_{D1 to} AND _D5 ). The computer according to the above mode (18) or (19), comprising:

(22) A plurality of control signal generation circuits (323A to 32
3D), (a) one input terminal is connected to the output terminal of the construction pointer (423), and when the processed flag signal is active, the construction command signal given from the construction pointer (423) is transmitted. A first AND circuit (AND _{3A1 to} AND _3D1 ) for instructing the start of the construction operation by making the output active when it becomes active
(B) a data input terminal is connected to an output terminal of the first AND circuit (AND _{3A1 to} AND _3D1 ), a clock input terminal is connected to a clock signal source, and a clear input terminal is connected to a reset signal source. After being cleared in response to the reset signal given from the reset signal source, the output of the first AND circuit (AND _{3A1 to} AND _3D1 ) given to the data input terminal is given to the clock input terminal. A shift register (SR _{3A to} S3S) that takes in and shifts according to the clock signal
R _3D ) and (c) two input terminals are respectively connected to two different output terminals of the shift register (SR _{3A to} SR _3D ), and the output terminal is a write signal input terminal of the instruction register (123A to 123D). And an input terminal of a program counter (623). A second AND circuit (AND) for generating a write signal and an increment signal and supplying them to the instruction registers (123A to 123D) and the program counter (623), respectively.
_{3A2 to} AND _3D2 ) and (d) shift register (SR _{3A to} SR _3D )
The two input terminals are connected to the other two different output terminals, respectively, and the output terminal is connected to the input terminal of the construction pointer (423).
Third AND circuit for providing a 3) and (AND _3A3 ~AND _3D3),
(e) Processing blocks (21A to 21D) included in the processing device (21)
One input terminal is connected to the processing end signal output terminal, and the other input terminal is connected to the reset signal source, and the processing end signal provided from the processing blocks (21A to 21D) and the processing end signal provided from the reset signal source are provided. When at least one of the reset signals is active, an OR circuit (OR _{3A1 to} OR _3D1 ) _whose output is active and (f) a clear input to the output terminal of the OR circuit (OR _{3A1 to} OR _3D1 ) end connected, and a clock input terminal connected to an output terminal of the third aND circuit (aND _3A3 ~AND _3D3), and data input is connected to a high-level signal source, an OR circuit (OR _3A1 ~ OR _3D1 ) becomes active and is cleared, then the third AND circuit (AND _3A3 ~ AN
D _3D3 ) becomes active, a built-in flag signal generation circuit (CENDF _{3A to} CENDF) that takes in a high-level signal from a high-level signal source and makes the built-up flag signal output from the output end active. _3D ) and (g) third AND circuit (AND
_{3A3 ~AND 3D3)} clear input to the output end is connected, and a clock input terminal connected to the processing end signal output terminal of the processing unit (21) to the inclusion a plurality of processing blocks (21A to 21D) And a preset input terminal is connected to a reset signal source, a data input terminal is connected to a high-level signal source, and an output terminal is a first AND circuit (AND _{3A1 to} AND _3D1 ).
The other is connected to the input terminal takes a high-level signal when the reset signal supplied from the reset signal source becomes active, the third AND circuit (AND _3A3 ~AND _3D3)
Is cleared when the output of the
21D), the high-level signal is fetched from the high-level signal source, output from the output terminal, and _supplied to the first AND circuit (AND _{3A1 to} AND _3D1 ). (H) one input terminal is connected to the output terminal of the processing pointer (523), and the other input terminal is connected to the processed flag signal generating circuit (PENDF _{3A to} PENDF _3D ) that activates the processed flag signal. Constructed flag signal generation circuit (CENDF _{3A to} CEND
F _3D ), and the processing command signal given from the processing pointer (523) and the constructed flag signal given from the constructed flag signal generation circuit (CENDF _{3A to} CENDF _3D ) are both active. And a fourth AND circuit (AND _{3A4 to} AND _3D4 ) that outputs a processing start signal at a certain time and supplies the processing block (21A to 21D) included in the processing device (21). The computer according to paragraph (18) or (20), which is characterized by the following.

[0778]

As is apparent from the above description, the computer according to the present invention includes (a) a processing device having a plurality of processing blocks and (b) An output terminal connected to an input terminal of a plurality of processing blocks included in the processing device, and circuit construction means for sequentially constructing a desired arithmetic circuit in the plurality of processing blocks; (c)
An output terminal connected to an input terminal of the plurality of processing blocks included in the processing device, and a processing execution unit configured to sequentially execute a desired operation on an arithmetic circuit sequentially constructed in the plurality of processing blocks; (I) has the effect of separating command and data movement paths from each other, (ii) has the effect of eliminating waste of processing time, and (iii) achieves high-speed processing Has an effect.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of a computer according to the present invention.

FIG. 2A is a block circuit diagram for illustrating a part of the embodiment shown in FIG. 1 in an enlarged manner.

FIG. 2B is a block circuit diagram for illustrating a part of the embodiment shown in FIG. 1 in an enlarged manner.

FIG. 3A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 3B is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 4A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 4B is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 5A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 5B is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 6A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 6B is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 7 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 8 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 9 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 10 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 11A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 11B is a block circuit diagram showing a part of the embodiment shown in FIG. 1 in an enlarged manner.

FIG. 12 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 13 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 14 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 15 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 16 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 17 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 18 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 19 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 20 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 21 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 22 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 23 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 24 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 25 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 26 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 27 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 1;

FIG. 28 is an explanatory diagram showing instruction words included in a program processed in the embodiment shown in FIGS. 1 and 29;

FIG. 29 is a block circuit diagram showing a second embodiment of the computer according to the present invention.

FIG. 30A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 30B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 31A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 31B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 32A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 32B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 33A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 33B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 34A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 34B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 35A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 35B is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 36A is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 36B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 37A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 37B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 38A is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 38B is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 39 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 40 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 41 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 42 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 43 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 44 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 45 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 46 is a block circuit diagram showing a part of the embodiment shown in FIG. 29 in an enlarged manner.

FIG. 47 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 48 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 49 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 50 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 51 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 52 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 53 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 54 is a block circuit diagram showing an enlarged part of the embodiment shown in FIG. 29;

FIG. 55A is a block circuit diagram for illustrating a part of a third embodiment of a computer according to the present invention in an enlarged manner.

FIG. 55B is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner.

FIG. 56A is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner;

FIG. 56B is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner.

FIG. 57A is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner.

FIG. 57B is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner.

FIG. 58A is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner;

FIG. 58B is a block circuit diagram for illustrating a part of a third embodiment of the computer according to the present invention in an enlarged manner.

[Explanation of the symbols] 10 Computer 11 Processing device FPGA Field-programmable gate array CSW _{11 to} CSW ₅₄ Cross-point switch SW _{1121 to} SW ₄₄₅₄ ... Disconnect switch EXOR ₁ , EXOR ₂ ... Exclusive OR circuit OR ₁ , OR ₂ ... OR circuit AND ₁ , AND ₂ ... AND circuit NAND _{1 to} NAND ₃ NAND circuit 11A Processing block 111A ... Input data selection circuit SEL _A1 , SEL _A2 ... Selector circuit 211A .... Processing circuit 311A ······· Output data selection circuit SELT _{A1 to} SELT _A3 ····· Selector circuit DEC _A ········ Decoder 411A ... Holding circuits RGS _{A1 to} RGS _A3 ... Register 11B ... Process block 111B ... ... Input data selection circuit SEL _B1 , SEL _B2 ... Selector circuit 211B Processing circuit 311B Output data selection circuit SELT _{B1 to} SELT _B3 Selector circuit DEC _B ...... Decoder 411B Hold circuit RGS _{B1 to} RGS _B3 Register 11C ..... Processing block 111C ............. input data selecting circuit SEL _C1, SEL _C2 ········ selector circuit 211C · · · · · · · · Processing circuit 311C Output data selection circuit SELT _{C1 to} SELT _C3 Selector circuit DEC _C Decoder 411C Hold circuit RGS _{C1 to} RGS _C3 Register 11D Processing block 111D Input data selection circuit SEL _D1 , SEL _D2 Selector circuit 211D Processing circuit 311D Output data selection circuit SELT _{D1 to} SELT _D3 ... selector circuit DEC _D ·············· Decoder 411D ....................... holding circuit RGS _D1 ~RGS _D3 ····· register 12A ··············· Switch control device 112A Connection information holding circuit 112A _{1 to} 112A _n Holding circuit 212A ... Connection information selection circuit 212A _{1 to} 212A _m ... Selector circuit 12B ... Switch control device 112B Connection information holding circuit 112B _{1 to} 112B _n Holding circuit 212B ... Connection information selection circuit 212B _{1 to} 212B _m ... Selector circuit 12C ... Switch control device 112C Connection information Information holding circuit 112C _{1 to} 112C _n ... Holding circuit 212C ... Connection information selection circuit 212C _{1 to} 212C _m ... Selector circuit 12D Switch control device 112D Connection information holding circuit 112D _{1 to} 112D _n ... Hold circuit 212D ... Connection information selection circuit 212D _{1 to} 212D _m ... Selector circuit 13 Control device 113A to 113D Instruction register 213A to 213D ……… Instruction decoder OR _3A to OR _3D ……… OR circuit TBL _{3A to} TBL _3D …… Conversion table circuit 313A to 313D… ... control signal generating circuit AND _3A1 ~AND _3D1 ······ A De circuit AND _3A2 ~AND _3D2 ······ AND circuit AND _3A3 ~AND _3D3 ······ AND circuit AND _3A4 ~AND _3D4 ······ and circuit OR _3A1 ~OR _3D1 ····・ ・ OR circuit SR _{3A to} SR _3D・ ・ ・ ・ ・ ・ ・ ・ ・ Shift register CENDF _{3A to} CENDF _3D・ ・ ・ Constructed flag signal generator PENDF _{3A to} PENDF _3D・ ・ ・ Processed flag signal generator 413 ........................... Building pointer OR ₄ ... OR circuit FF ₄₀ to FF ₄₃ ... ... flip-flop 513 ....................... processing pointer OR ₅ ················ OR circuit FF ₅₀ ~ FF ₅₃ Flip-flop 613 Program counter OR ₆ ... OR circuit CNT ₆ ····・ ・ ・ Counter ・ ・ ・ ・ ・ ・ ・ ・ ・ Program holding device 15 ・ ・ ・ ・ ・ ・ ・ ・ ・... Data bus 16 ... I / O device 211X ... Load instruction processing circuit ADD _X: Adder BCNTL _X: Bus control signal generator DCNT _X: Down counter DTRF _X: Data transfer circuit SELT _X: ... Selector circuit 211Y · Add instruction processing circuit ADD _Y ···················· adder DCNT _Y ....................... down Counter 211Z ... Load effective address instruction processing circuit ADD _Z ...・ ・ Adder DCNT _Z・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Down counter SELT _Z・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Selector circuit 211W ・··········· Arithmetic left shift instruction processing circuit SR _W Register 211V ... Store instruction processing circuit ADD _V ... Adder BCNTL _X Bus control signal generation circuit DCNT _V: Down counter DTRF _V: Data transfer circuit SELT _V: ... Selector circuit 20 Computer 21 Processing unit 21A Processing block 121A・ ・ ・ Input data selection circuit SEL _A1 , SEL _A2・ ・ ・ ・ ・ ・ ・ ・ Selector circuit 221A ・ ・ ・ ・ ・ ・ ・ Process Circuit 221A ₁ ... Load instruction processing circuit 221A ₂ ... Store instruction processing circuit 221A ₃ ... .......... load effective address instruction processing circuit 221A ₄ ······· ....... add instruction processing circuit 221A ₅ ··············· arithmetic left shift instruction processing circuit SW _A11 ~SW _A15 ······ selection switches SW _A22 ~ SW _A25: Select switch SW _A31 , SW _A32: Select switch SW _A41 , SW _A42: Select switch SW _A51 , SW _A52:・ ・ ・ Select switch DECD _A・ ・ ・ Decoder 321A ・ ・ ・ ・ ・ ・ ・ ・ ・ Output data selection circuit SELT _A1 ~ SELT _A3・ ・ ・ ・ ・ Selector circuit DEC _A・ ・ ・ ・ ・ ・ ・ Decoder 421A ・ ・ ・ ・ ・ ・ ・ ・ ・ Holding circuit RGS _A1 RGS _A3 Register 21B Processing block 121B Input data selection circuit SEL _B1 , SEL _B2 Selector circuit 221B Processing circuit 221B ₁ Load instruction processing circuit 221B ₂・ ・ ・ Store instruction processing circuit 221B ₃・ ・ ・ ・ ・ ・ ・ Load effective address instruction processing circuit 221B ₄・ ・ ・ ・ ・ ・ ・ ・ ・ ・・ ・ ・ ・ ・ Addition instruction processing circuit 221B ₅・ ・ ・ ・ ・ ・ ・ Arithmetic left shift instruction processing circuit SW _{B11 to} SW _B15・ ・ ・ ・ ・ ・ Selection switch SW _{B22 to} SW _B25 ... Selection switches SW _B31 , SW _B32 ... Select switches SW _B41 , SW _B42 ... Select switches SW _B51 , SW _B52 ...・ Selection switch DECD _B・ ・ ・ ・ ・ ・ Decoder 321B ・ ・ ・ ・ ・ ・ ・ ・ ・ Output data selection circuit SELT _B1 ~ SELT _B3 ... ... selector circuit DEC _B ··· ............ decoder 421B ....................... holding circuit RGS _B1 ~RGS _B3 ····· register 21C · · · · Processing block 121C Input data selection circuit SEL _C1 , SEL _C2 ... Selector circuit 221C Processing circuit 221C ₁ Load instruction processing circuit 221C ₂ ... Store instruction processing circuit 221C ₃ ... Load effective address instruction processing circuit 221C ₄・ ・ ・ ・ ・ ・ ・ ・ ・ Addition instruction processing circuit 221C ₅・ ・ ・ ・ ・ ・ ・ ・ ・ Arithmetic left shift instruction processing circuit SW _C11- SW _C15・ ・ ・ ・ ・ ・ Selection switch SW _C22 〜SW _C25・ ・ ・ ・ ・ ・ Selection switch SW _C31 , SW _C32 ... Select switch SW _C41 , SW _C42 ... Select switch SW _C51 , SW _C52 ... Select switch DECD _C ... ............ decoder 321C ....................... output data selection circuit SELT _C1 ~SELT _C3 ····· selector circuit DEC _C · · · · ·・ ・ ・ Decoder 421C ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Holding circuit RGS _{C1 to} RGS _C3・ ・ ・ ・ ・ ・ Register 21D ・ ・ ・ ・ ・ ・ ・Processing block 121D Input data selection circuit SEL _D1 , SEL _D2・ ・ ・ Selector circuit 221D ・ ・ ・ ・ ・ ・ ・ ・ ・ Processing circuit 221D ₁・ ・ ・ ・ ・ ・ Load instruction processing circuit 221D ₂・ ・ ・ ・..... Store instruction processing circuit 221D ₃ ... Load effective address instruction processing circuit 221D ₄ ... Addition instruction processing circuit 221D ₅ ... Arithmetic left shift instruction processing circuit SW _{D11 to} SW _D15 Selection switch SW _{D22 to} SW _D25 Selection switch SW _D31 , SW _D32 .......... Selection switch SW _D41 , SW _D42 ... Select switch SW _D51 , SW _D52 ... Select switch DECD _D・ ・ ・ Decoder 321D ・ ・ ・ ・ ・ ・ ・ ・ ・ Output data selection circuit SELT _D1 ~ SELT _D3・ ・ ・ ・ ・ ・ Selector circuit DEC _D・ ・ ・ ・ ・ ・ ・ ・ ・Decoder 421D Hold circuit RGS _{D1 to} RGS _D3 Register 23 ..... Control equipment 123a through 123d ············ instruction register 223A～223D ············ instruction decoder OR _3A ~ OR _3D ········· OR circuit TBL _{3A to} TBL _3D: Conversion table circuit 323A to 323D: Control signal generation circuit AND _{3A1 to} AND _3D1: AND circuit AND _{3A2 to} AND _3D2 ······ aND circuit aND _3A3 ~AND _3D3 ······ aND circuit aND _3A4 ~AND _3D4 ······ and circuit OR _3A1 ~OR _3D1 ······ OR circuit SR _3A ~ SR _3D・ ・ ・ ・ ・ ・ ・ ・ ・ Shift register CENDF _3A 〜CENDF _3D・ ・ ・ Constructed flag signal generation circuit PENDF _3A 〜PENDF _3D・ ・ ・ Processed flag signal generation circuit 423 ・ ・ ・ ・ ・ ・............ build pointer OR ₄ ················ OR circuit FF ₄₀ ~ FF ₄₃ ········· flip-flop 523 ・ ・ ・ ・............. processing pointer OR ₅ · · · · · · OR circuit FF ₅₀ ~ FF ₅₃ ········· flip 623 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Program counter OR ₆・ ・ ・ ・ ・ ・ ・ ・ OR circuit CNT ₆・ ・ ・ ・ ・ ・... Counter 24 Program holder 25・ ・ ・ ・ ・ ・ Data bus 26 ・ ・ ・ ・ ・ ・ ・ ・ ・ Data holding device 27 ・ ・ ・ ・... _I / O device 221X ₁ ... Load instruction processing circuit ADD ... Adder BCNTL・ ・ ・ ・ ・ ・ ・ Bus control signal generation circuit DCNT ・ ・ ・ ・ ・ ・ ・ ・ ・ Down counter DTRF ・ ・ ・ ・ ・ ・... Data transfer circuit SELT ... Selector circuit 221X ₂ ...・ ・ ・ ・ ・ Store instruction processing circuit ADD ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Adder BCNTL ・ ・ ・ ・ ・ ・ ・・ ・ ・ Bus control signal generation circuit DCNT ・ ・ ・ ・ ・ ・ ・ ・ ・ Down counter DTRF ・ ・ ・ ・ ・ ・ ・ ・ ・..Data transfer circuit SELT ... Selector circuit 221X ₃ ...・ Load effective address instruction processing circuit ADD Adder DCNT Down counter SELT Selector Circuit 221X ₄ Addition instruction processing circuit ADD Adder DCNT ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Down counter 221X ₅・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Arithmetic left Shift instruction processing circuit SR ... Shift register 231A ... ..Processing circuit 231A ₁ ... Load instruction processing circuit 231A ₂ ... store instruction processing circuit 231A ₃ ··················· load effective address life Processing circuit 231A ₄ ··················· add instruction processing circuit 231A ₅ ··················· left arithmetically Shift instruction processing circuit SW _{A11 to} SW _A15 ... Select switch SW _{A22 to} SW _A25 ... Select switch SW _A31 , SW _A32 ... Select Switch SW _A41 , SW _A42 ... Select switch SW _A51 , SW _A52 ... Select switch DECD _A ... ... Decoder AND _{A1 to} AND _A5 ... AND circuit 231B ... Processing circuit 231B ₁ ... .......... Load instruction processing circuit 231B ₂ ... Store instruction processing circuit 231B ₃ ... ..... Load effective address instruction processing Circuit 231B ₄ Addition instruction processing circuit 231B ₅ Arithmetic shift left Instruction processing circuit SW _{B11 to} SW _B15 ... Select switch SW _{B22 to} SW _B25 ... Select switch SW _B31 , SW _B32 ... Select switch SW _B41 , SW _B42 ... Select switch SW _B51 , SW _B52 ... Select switch DECD _B ... ..Decoders AND _{B1 to} AND _B5 ... AND circuit 231C Processing circuit 231C ₁ ... Load instruction processing circuit 231C ₂ ... Store instruction processing circuit 231C ₃ ... ......... Load effective address instruction processing circuit 2 31C ₄ ... Addition instruction processing circuit 231C ₅ ... Arithmetic left shift instruction Processing circuit SW _{C11 to} SW _C15 ... Select switch SW _{C22 to} SW _C25 ... Select switch SW _C31 , SW _C32 ... Select switch SW _C41 , SW _C42 ... Select switch SW _C51 , SW _C52 ... Select switch DECD _C ...・ Decoder AND _{C1 to} AND _C5・ ・ ・ ・ ・ ・ ・ ・ AND circuit 231D ・ ・ ・ ・ ・ ・ Processing circuit 231D ₁・ ・ ・ ・ ・ ・... Load instruction processing circuit 231D ₂ Store instruction processing circuit 231D ₃ ..... Load effective address instruction processing circuit 231D _4.・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Addition instruction processing circuit 231D ₅・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Arithmetic left shift instruction processing circuit SW _{D11 to} SW _D15 ... Select switch SW _{D22 to} SW _D25 ... Select switch SW _D31 , SW _D32 ... Select switch SW _D41 , SW _D42: Select switch SW _D51 , SW _D52: Select switch DECD _D: Decoder AND _{D1 to} AND _D5 ... AND circuit

Continuation of the front page (56) References JP-A-57-132426 (JP, A) JP-A-1-125123 (JP, A) JP-A-58-215813 (JP, A) JP-A-60-179871 (JP) JP-A-63-118987 (JP, A) JP-A-2-30217 (JP, A) JP-A-60-105050 (JP, A) JP-A-2-18687 (JP, A) JP-A 59-176838 (JP, A) JP-A-63-193233 (JP, A) JP-A-55-147737 (JP, A) JP-A-1-116690 (JP, A) JP-A-58-58672 (JP, A) A) JP-A-2-108150 (JP, A) JP-A-1-238219 (JP, A) JP-A-63-208153 (JP, A) JP-A-62-145350 (JP, A) JP-A-61 −45359 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 7/00 H03K 19/173-19/177

Claims (1)

(57) [Claims] 1. A program holding device for holding a program, a processing device having a plurality of processing blocks connected in a ring, and a process included in the program being executed by the processing device. While rewriting the logic to be performed, in parallel with the processing block, the processing device is wrapped so that the processing based on the logic is executed in accordance with the connection order of the processing blocks. A control device for controlling each of the plurality of processing blocks independently, comprising: an arithmetic circuit for each of the plurality of processing blocks to execute arithmetic processing based on the program A number of gate circuits that can be constructed, and provided between the gate circuits and controlled by the control device. A re-programmable logic array comprising a changeover switch for constructing the arithmetic circuit, wherein the control device controls a storage element for controlling the changeover switch , a program counter, a construction counter, and a processing device.
From the program holding device to the program pointer.
The instruction indicated by the ram counter is read out and the program
Means for updating a memory counter , wherein the storage element has a plurality of bits connected in advance for each one of the changeover switches, and always stores the contents of one bit of the plurality of bits in the storage element. to convey to the changeover switch and selector is provided to control the on and off of the change-over switch, the selector is, out of the reading
Processing block indicated by the construction pointer corresponding to the executed instruction.
ON / OFF of all changeover switches provided in the rack
Is controlled in accordance with the read instruction, and
Build the logic of the corresponding processing content in the relevant processing block
The control device further controls the changeover switch in parallel with the control of the changeover switch.
To the processing block indicated by the processing pointer.
Process based on the logic constructed
The means to be executed by the block and the processing block
When the construction of the logic is completed,
Processing block following the processing block in the connection
If the logic is already processed,
The construction pointer updated to indicate processing blocks,
Processing based on the logic in the processing block
Is completed, then the ring connection
The logic of the next processing block following that processing block
If it has been built, indicate the next processing block.
Means for updating the processing pointer as described above .