JP3283736B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device related to a high voltage complementary metal oxide semiconductor (CMOS) electrostatic protection circuit device.

[0002]

2. Description of the Related Art A conventional high withstand voltage electrostatic protection circuit device will be described with reference to FIGS. 5 and 6
FIG. 7 is a diagram for explaining an example of the conventional device (hereinafter, referred to as “conventional high withstand voltage electrostatic protection circuit device I”).
FIG. 8 is a diagram for explaining another example (hereinafter, referred to as “conventional high withstand voltage electrostatic protection circuit device II”).

(Conventional high withstand voltage electrostatic protection circuit device I) A conventional high withstand voltage electrostatic protection circuit device I is shown in a circuit diagram of FIG. 5, which is inserted between "input / output electrode 101 and ground". Nch gate-off transistor type diode 110, Pch gate-off transistor type diode 109 inserted between "I / O electrode 101 and power supply electrode 103", "I / O electrode 101-"
The fixed resistor 111 is inserted between the protected element electrodes 102 ".

In this circuit configuration, by turning off the gate of a transistor having the same withstand voltage as that of the internal element and using it as a protection diode, a diode having a withstand voltage effective for electrostatic protection is formed. ing. In addition, a resistor effective against an overcurrent from the input terminal to the internal protected element is added.

FIG. 6A is a plan view of a conventional high withstand voltage electrostatic protection circuit device I, and FIG.
It is connected to the drain of an Nch transistor formed in an NchTr field 24 surrounded by a drain P ⁺ diffusion layer 4.
On the other hand, the NchTr gate polysilicon 19 and the source are connected to the ground electrode 2.

Further, the input electrode 1 is connected to the opposite N well 21.
Is connected to the drain of a Pch transistor formed in a PchTr field 23 surrounded by a guarding N ⁺ diffusion layer 20. On the other hand, the PchTr gate polysilicon 22 and the source are connected to the power supply electrode 13. Further, the input electrode 1 is connected to an internal protected element via a polysilicon resistor 18.

FIG. 6B is a cross-sectional view taken along the line DD of FIG. 6A. In the conventional high withstand voltage electrostatic protection circuit device I, FIG.
A high breakdown voltage Nch transistor is formed in the P-type substrate 12, and a depletion layer easily extends in the gate oxide film 27 and the source / drain diffusion layers having an oxide film thickness capable of withstanding the high breakdown voltage. An N ^- diffusion layer 25 and an N ^- diffusion layer contact N ⁺ diffusion layer 26 having a high breakdown voltage are provided. In addition, an interlayer film 11 is provided between the polysilicon and the aluminum, and a field oxide film is further provided for isolation between elements.
Has 17. In FIG. 6B, 1 is an input electrode,
2 is a ground electrode, 4 is a guarding P ⁺ diffusion layer, 19 is N
chTr gate polysilicon.

FIG. 6C is a sectional view taken along the line EE of FIG. 6A, in which a high breakdown voltage Pch transistor is formed in the N well 21 in the P-type substrate 12. similar gate and - having a gate oxide film 27, source - scan, the drain diffusion layer, a depletion layer tends extends, P having a high withstand voltage ^- with a diffusion layer contact P ⁺ diffusion layer 9 ^- diffusion layer 8 and P . 1 is an input electrode, 11 is an interlayer film, 13 is a power supply electrode, 17 is a field oxide film, 20 is a guarded N ⁺ diffusion layer, and 22 is a PchTr gate polysilicon.

(Conventional high withstand voltage electrostatic protection circuit device II) Another conventional high withstand voltage electrostatic protection circuit device II is shown in a circuit diagram of FIG. Nch side junction diode 11 inserted between
3, Pch inserted between “I / O electrode 101 and power supply electrode 103”
It comprises a side junction diode 112 and a fixed resistor 111 inserted between the "input / output electrode 101 and the protected element electrode 102".

In this circuit configuration, since a junction different from the junction of the internal transistor can be used, it is possible to use a protection diode having a lower breakdown voltage than the internal circuit transistor breakdown voltage effective for electrostatic protection.

FIG. 8A is a plan view of a conventional high voltage electrostatic protection circuit device II, in which the input electrode 1 is in the high concentration P well 29 and has a guard ring P ^+. It is connected to an N ⁻ diffusion layer contact N ⁺ diffusion layer 26 in an N ⁻ diffusion layer 25 surrounded by the diffusion layer 4. On the other hand, the guarding P ⁺ diffusion layer 4
Is connected to the ground electrode 2.

Further, the input electrode 1 is connected to the opposite N well 21.
A within the high concentration N-well 28 of the inner, moth - Doringu N ⁺ is surrounded by the diffusion layer 20 P ^- is connected to the diffusion layer contact P ⁺ diffusion layer 9 ^- P in the diffusion layer 8. On the other hand, the guarding N ⁺ diffusion layer 20 is connected to the power supply electrode 13. Also, input electrode 1
Is connected to an internal protected element via a polysilicon resistor 18.

FIG. 8B is a cross-sectional view taken along the line FF of FIG. 8A. In the conventional high withstand voltage electrostatic protection circuit device II, FIG.
Using a high concentration P well 29 in the P-type substrate 12, N
^- low withstand voltage than the internal device to be protected by the diffusion layer 25 diodes -
To form Further, an interlayer film 11 is provided between the polysilicon and the aluminum.
And a field oxide film 17 for isolation between elements. 1 is an input electrode, 2 is a ground electrode, and 4 is a garment.
The draining P ⁺ diffusion layer 26 is an N ⁻ diffusion layer contact N ⁺ diffusion layer.

FIG. 8C is a cross-sectional view taken along the line GG of FIG. 8A, in which the N well 21 in the P-type substrate 12 and the high concentration N well 28 further inside are shown. And a diode having a lower withstand voltage than the internal protected element is formed with the P ⁻ diffusion layer 8. Reference numeral 1 denotes an input electrode, 9 denotes a P ^- diffusion layer contact P ⁺ diffusion layer, 11 denotes an interlayer film, 13 denotes a power supply electrode, 17 denotes a field oxide film, and 20 denotes a guarding N ⁺ diffusion layer.

[0015]

The conventional high withstand voltage electrostatic protection circuit device I uses a transistor-type diode (see FIG. 5 "Pch gate-off transistor-type diode 109"). It is necessary to lay out a source and a drain as a diffusion layer, and further a gate polysilicon.

In addition, in order to realize a high breakdown voltage, the diffusion layer must be a low concentration diffusion layer having a large area so that a depletion layer can be extended in the diffusion layer. Series resistance. In order to reduce the series resistance, it is necessary to increase the width of the diode.

On the other hand, the conventional high withstand voltage electrostatic protection circuit device
In II, a junction type diode having a lower withstand voltage than the internal protected element is used (see FIG. 7 "Pch side junction diode 112", "Nch side junction diode").
High-concentration well diffusion layer (see FIG. 8 "high-concentration N-well 28" and "high-concentration P-well 29" described above in order to strengthen the electric field from the junction used for the internal circuit protected element). Become.

Therefore, in order to form the high concentration well diffusion layer only in the protection circuit device portion, there is a disadvantage that at least a step of photolithography and an ion implantation technique must be added. Also, a fixed resistor for protecting the internal transistor against overcurrent (see "fixed resistor 111" in FIG. 7 described above) is required, and since the resistance value is fixed, a circuit configuration in which the input / output section always has a resistor in the series. It has become.

The present invention has been made in view of the above-mentioned problems and disadvantages of the conventional high withstand voltage electrostatic protection circuit devices I and II. In particular, a semiconductor integrated circuit according to a high withstand voltage electrostatic protection circuit device which can reduce the area by using a well resistor having a low resistance and can eliminate an additional step. It is to provide a device.

[0020]

A high voltage protection circuit device according to the present invention uses a punch-through element using a well instead of a protection diode, and uses a resistance for protecting an internal transistor against overcurrent as an input voltage. N-well resistance (N-well variable resistance) whose resistance value fluctuates depending on the resistance, whereby the resistance becomes high when an input such as a high voltage is applied, thereby protecting the internal protected element. It consists of. In addition, the high withstand voltage protection circuit device according to the present invention has a function and effect that an area can be reduced and an additional step can be eliminated by using a low resistance well resistance.

That is, the present invention provides a first conductive type first well formed in a second conductive type substrate and another grounded first conductive type second well near the first well. A second conductivity type diffusion layer grounded to the same power supply as the second well is present in the first well, and a first conductivity type high concentration diffusion layer is present on both sides of the second conductivity type diffusion layer. Then, the first well on the side connected to the input / output terminal of one of the first conductivity type high-concentration diffusion layers faces the second well and is panned.
Wells for causing Chisuru conducts only during the high voltage input to release charge - as well punchthrough devices, other
The first conductive type high concentration diffusion layer is connected to the internal circuit,
The one first conductivity type high concentration diffusion layer and the other first conductivity type
The first well between the high-concentration diffusion layer and the high-concentration diffusion layer is configured to have a resistance variable at the time of inputting an excessive charge to form a well variable resistance element for limiting an excessive input to the internal circuit. A semiconductor integrated circuit device for protecting the internal circuit. (Claim 1).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described with reference to FIG.
More specifically, referring to FIG. 3A, the high-voltage protection circuit device according to the present invention includes an N-type well 5 (second type) formed in a P-type substrate 12 (second conductive type substrate). A first well of one conductivity type) and another N-type well 6 (second well of first conductivity type) grounded in the vicinity thereof;
(First well) in the N-type well 6 P grounded (second well) identical to the power supply ^- diffusion layer 8 (second conductive type diffusion layer) is present, further, the P ^- diffusion layers 8 (Second conductivity type diffusion layer)
N ⁺ diffusion layers 7 that are high concentration diffusion layers of the first conductivity type
a and N ⁺ diffusion layers 16 are present.

Then, the diffusion layer (input / output side N-type well contact N ⁺ diffusion layer 7a) on the side connected to the input / output terminal 1 of one of the first conductivity type high-concentration diffusion layers is connected to the N-type well 6
(The second well), and the other high-concentration diffusion layer of the first conductivity type (the internal N-type well contact N ⁺ diffusion layer 16)
By connecting to an internal circuit, and by adding a punch-through element by a well and a resistor whose input resistance varies depending on an input voltage to the input and output, the internal circuit is protected from electrostatic breakdown.

[0024]

EXAMPLES Next, the present invention will be described specifically with reference to examples according to the present invention. However, the present invention is not limited to the following examples, and the scope of the gist of the present invention described above. Various modifications and changes are possible within.

(Embodiment 1) A first embodiment (Embodiment 1) of the present invention will be described with reference to FIGS. 1 and 2A and 2B.
FIG. 1 is an equivalent circuit diagram according to a first embodiment of the present invention, and FIG. 2 is a configuration of a high withstand voltage protection circuit device according to the first embodiment.
It is a figure explaining (structure), in which (A) is the top view and (B) is the sectional view on the AA line of (A).

FIG. 1 is a circuit diagram of the high-voltage protection circuit device of the first embodiment, which is the same as the N-well-substrate diode 104 inserted between the "input / output electrode 101 and the ground". N-well -N-well punch sul is inserted in parallel with the position - element 106, further P of N in the well which is inserted in parallel to the same point ^- N-well -P formed by ^- diode - de 105 and, " I / O electrode 101-protected element electrode
It comprises an N-well variable resistor 107 inserted between 102 ".

Since the withstand voltage of the N-well / N-well punch-through element 106 can be controlled by the distance between the N-well and N-well, it can be set lower than the withstand voltages of other diodes and the elements to be protected. And the amount of N welds:
1E12-5E13, N-well push-in 1000-1200 degrees, 3-10
In time, it is possible to control the punch-through-withstand voltage of about 10 to 100 V at an N-well interval of 5 to 20 μm.

Next, the high breakdown voltage protection circuit device of the first embodiment is shown in plan view in FIG.
This will be described with reference to FIG. First, a description will be given with reference to FIG.
P Doringu P ⁺ is connected to the input and output side N-type well contact N ⁺ diffusion layer 7a in the diffusion layer N type well resistor 5 formed in 4, whereas, the same N-type well resistor 5 - is moth ^-
An internal N-type well contact N ⁺ diffusion layer 16 formed opposite to the diffusion layer 8 and the P ⁻ diffusion layer contact P ⁺ diffusion layer 9 formed by self-alignment is connected to the protected element electrode 3. Thus, the variable N-well resistance is configured.

Further, the input / output side N in the N-type well resistor 5
Opposite the well contact N ⁺ diffusion layer 7a to form a separate ground-side N-type well 6, further therein, to form a ground-side N-type well contact N ⁺ diffusion layer 7, the above-mentioned P ^- diffusion layer contact P ⁺ Diffusion layer 9 and ground electrode 2 are connected. Thus, an N-well / N-well punch-through element is formed. In FIG. 2A, reference numeral 10 denotes a contact hole.

Next, referring to FIG. 2B showing a cross section taken along the line AA, the ground-side N-type well 6 and the ground-side N-type well contact N ⁺ diffusion layer 7 and the P-type The N-type well resistor 5 on the opposite side in
A well-N-well punch-through element is formed.
The breakdown voltage is determined at the well-N well interval.

In the N-type well resistor 5, the P-type isolation formed by a field oxide film 17 is provided between the input / output side N-type well contact N ⁺ diffusion layer 7 a and the internal N-type well contact N ⁺ diffusion layer 16. ^A diffusion layer 8 is present. When the high voltage is applied to the input electrode 1, it raises the potential of the N-type well resistor 5, P is connected to the ground electrode 2 ^- To a diffusion layer 8 is present deep, the N-type well -P ^- A depletion layer spreads between the diffusion layers 8, the effective area of the N-type well resistor 5 decreases, and the resistance value increases.

At the same time, the depletion layer also spreads at the junction of the N-type well resistor 5 and the P-type substrate 12, connecting to the ground side N-type well 6, and
The structure is such that development occurs and charges flow through this route. In FIG. 2B, reference numeral 3 denotes a protected element electrode;
A drain P ⁺ diffusion layer, 9 is a P ⁻ diffusion layer contact P ⁺ diffusion layer, and 11 is an interlayer film.

(Embodiment 2) Next, a second embodiment of the present invention will be described.
(Embodiment 2) will be described with reference to FIGS. 3 and 4A to 4C. FIG. 3 is an equivalent circuit diagram according to a second embodiment (embodiment 2) of the present invention, and FIG. 4 is a diagram for explaining the configuration (structure) of the high withstand voltage protection circuit device of the second embodiment. (A) is a plan view thereof, (B) is a sectional view taken along line BB of (A), and (C) is a sectional view taken along line CC of (A).

The high voltage protection circuit device of the second embodiment is shown in FIG. 3 in a circuit diagram, which is almost the same as the circuit of the first embodiment shown in FIG. In addition to the circuit configuration, the power electrode side N-well / N-well punch through element 108 inserted between the “input / output electrode 101 and the power electrode 103”
Is different from the first embodiment in that the configuration is added. By inserting the N-well / N-well punch through element 108 on the power electrode side, the input / output electrode 10
Even when a negative value is applied to 1, the internally protected element can be protected by the punch through element 108.
The other configurations and effects are the same as those of the first embodiment, and thus the description thereof is omitted.

Next, FIG. 4 (A) showing a plan view of the high withstand voltage protection circuit device of the second embodiment and FIG.
This will be described with reference to FIGS. 4B and 4C showing a cross section taken along a line B and a cross section taken along the line CC. First, referring to FIG. 4A showing a plan view, the input electrode 1 is connected to the input / output side N-type well contact in the N-type well resistor 5 formed in the guarding P ⁺ diffusion layer 4. While connected to the N ⁺ diffusion layer 7 a, the P ⁻ diffusion layer 8 and the P ⁻ diffusion layer contact P ⁺ diffusion layer 9 formed by self-alignment are sandwiched in the same N-type well resistance 5.
Internal N-type well contact N ⁺ formed on the opposite side
The diffusion layer 16 is connected to the protected element electrode 3. Thus, the variable N-well resistance is configured.

The input / output side N in the N-type well resistor 5
Well contact N ⁺ forms a separate ground-side N-type well 6 on both sides of the diffusion layer 7a, further forms a ground-side N-type well contact N ⁺ diffusion layer 7 therein, the P ^- diffusion layer contact P ⁺ diffusion The layer 9 is connected to the ground electrode 2.
Thus, an N-well / N-well punch-through element is formed.

Further, another power supply side N-type well 14 is formed on the input / output side N-type well contact N ⁺ diffusion layer 7a in the N-type well resistor 5 and further includes a power supply side N-type well 14 therein.
Type well contact N ⁺ diffusion layer 15
Connect to Thus, the power supply side N-well / N-well punch-through element is configured. It should be noted that 10 in FIG.
Is a contact hole.

Next, FIG. 4 shows a cross section taken along the line BB in FIG.
Referring to (B), the ground-side N-type well 6 and the ground-side N-type well contact N ⁺ diffusion layer 7 and P
N-type well resistance 5 on the opposite side in mold substrate 12
Thus, an N-well-N-well punch-through-element is formed,
The breakdown voltage is determined by the N well-N well interval. In FIG. 4B, 2 is a ground electrode, 11 is an interlayer film,
Reference numeral 7 denotes a field oxide film.

FIG. 4 shows a cross section taken along line CC of FIG.
Explaining with reference to (C), in the N-type well resistor 5,
Between the input / output side N-type well contact N ⁺ diffusion layer 7a and the internal side N-type well contact N ⁺ diffusion layer 16, there is a P ^- diffusion layer 8 separated by a field oxide film 17. When a high voltage is applied to the input electrode 1, the potential of the N-type well resistor 5 rises, and the potential of the P-type well connected to the ground electrode 2 increases.
^- To a diffusion layer 8 is present deep, the N-type well -P ^-
A depletion layer spreads between the diffusion layers 8, the effective area of the N-type well resistor 5 decreases, and the resistance value increases.

The N-type well resistor 5, the P-type substrate 12, and the N-type well 14 constitute a power supply side N-well / N-well punch-through element. In FIG. 4C,
Reference numeral 3 denotes a protected element electrode, 9 denotes a P ⁻ diffusion layer contact P ⁺ diffusion layer, 11 denotes an interlayer film, 13 denotes a power supply electrode, and 15 denotes a power supply side N-type well contact N ⁺ diffusion layer.

[0041]

As described above, the present invention is mainly composed of the P ^- diffusion layer used in the N-well and the high-voltage P-channel MOS as compared with the conventional high withstand voltage protection circuit device.
Since there is no additional step and the resistance value of the N-well itself is low (because of the large cross-sectional area), the effect that the size can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram according to a first embodiment (Embodiment 1) of the present invention.

FIG. 2 is a diagram illustrating a configuration (structure) of a high withstand voltage protection circuit device according to a first embodiment (Embodiment 1) of the present invention;
(A) is the top view, (B) is the sectional view on the AA line of (A).

FIG. 3 is an equivalent circuit diagram according to a second embodiment (Embodiment 2) of the present invention.

FIG. 4 is a diagram for explaining the configuration (structure) of a high-withstand-voltage protection circuit device according to a second embodiment (embodiment 2) of the present invention;
(A) is a plan view thereof, (B) is a sectional view taken along line BB of (A), (C)
FIG. 3 is a cross-sectional view taken along line CC of FIG.

FIG. 5 is an equivalent circuit diagram of a conventional high-voltage electrostatic protection circuit device I.

6A and 6B are views for explaining a conventional high-voltage electrostatic protection circuit device I, wherein FIG. 6A is a plan view thereof, and FIG.
FIG. 3 is a sectional view taken along line D-D, and FIG. 4C is a sectional view taken along line EE of FIG.

FIG. 7 is an equivalent circuit diagram of a conventional high withstand voltage electrostatic protection circuit device II.

8A and 8B are diagrams illustrating a conventional high-voltage electrostatic protection circuit device II, in which FIG. 8A is a plan view thereof, and FIG.
FIG. 2 is a cross-sectional view taken along the line F; FIG. 2C is a cross-sectional view taken along the line GG of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input electrode 2 Ground electrode 3 Protected element electrode 4 Guarding P ⁺ diffusion layer 5 N-type well resistance 6 Ground-side N-type well 7 Ground-side N-type well contact N ⁺ Diffusion layer 7a Input / output-side N-type well contact N ⁺ diffusion layer 8 P ^- diffusion layer 9 P ^- diffusion layer contact P ⁺ diffusion layer 10 contact holes - le 11 interlayer film 12 P-type Sabusutore - DOO 13 power electrode 14 the power source side N-type well 15 power supply side N-type well contact N ⁺ Diffusion layer 16 Internal N-type well contact N ⁺ diffusion layer 17 Field oxide film 18 Polysilicon resistance 19 NchTr gate polysilicon 20 Guarding N ⁺ diffusion layer 21 N well 22 PchTr gate polysilicon 23 PchTr filter − Field 24 NchTr field 25 N ⁻ diffusion layer 26 N ⁻ diffusion layer contact N ⁺ diffusion layer 27 gate Oxide film 28 High concentration N well 29 High concentration P well 101 I / O electrode 102 Protected element electrode 103 Power supply electrode 104 N well-substrate diode 105 N well-P ^- diode 106 N well-N well punch through -Element 107 N-well variable resistor 108 Power electrode side N-well-N-well punch-through element 109 Pch gate-off transistor type diode 110 Nch gate-off transistor type diode 111 Fixed resistor 112 Pch side junction diode 113 Nch side junction diode

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-267588 (JP, A) JP-A-58-42269 (JP, A) JP-A-59-107559 (JP, A) JP-A-Heisei 4- 247654 (JP, A) JP-A-60-74464 (JP, A) JP-A-3-242967 (JP, A) JP-A-4-145658 (JP, A)

Claims (3)

(57) [Claims] A first well of a first conductivity type formed in a substrate of a second conductivity type and another second well of a first conductivity type grounded in the vicinity of the first well are provided in the first well. A second conductivity type diffusion layer grounded to the same power supply as the second well, and a first conductivity type high concentration diffusion layer on both sides of the second conductivity type diffusion layer; The first well on the side connected to the input / output terminal of the one conductivity type high concentration diffusion layer faces the second well to cause punch-through.
A well-well punch-through element that conducts only when a high voltage is input to release electric charges is provided, and the other high-concentration diffusion layer of the first conductivity type is connected to an internal circuit to form a high-concentration diffusion layer of the first conductivity type. The first well between the layer and the other first-conductivity-type high-concentration diffusion layer is configured as a well variable resistance element for increasing the resistance when an excessive charge is input and limiting the excessive input to the internal circuit. Thus, the semiconductor integrated circuit device protects the internal circuit from electrostatic breakdown. 2. An N inserted between an input / output electrode and a ground.
Well-substrate diode, N-well-N-well punch-through element inserted in parallel at the same location, and P-well in N-well inserted in parallel at the same location
And a N-well variable resistor inserted between the input / output electrode and the protected element electrode. A semiconductor integrated circuit device according to a high withstand voltage protection circuit device. 3. An N inserted between an input / output electrode and a ground.
Well-substrate diode, N-well-N-well punch-through element inserted in parallel at the same location, and P-well in N-well inserted in parallel at the same location
A circuit is composed of an N-well and a P-diode formed by-, an N-well variable resistor inserted between an input / output electrode and a protected element electrode, and an N-well variable resistor inserted between an input / output electrode and a power supply electrode. A semiconductor integrated circuit device according to a high withstand voltage protection circuit device, wherein a circuit is configured by an N-well punch-through element on a power supply electrode side.