JP3278613B2 - Language processing system and language processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a language processing system and a language processing method.

[0002]

2. Description of the Related Art In a device having a flash function, there are generally two types of self-writing methods.

One is a method in which a ROM section is divided into an object code rewriting section and a flash memory section as shown in FIG. 13, and the object code rewriting section rewrites a flash memory section, and the other is a method shown in FIG. As described above, there are two types of methods for rewriting the entire flash memory unit.

In the latter case, there is an advantage that the flash memory portion can be widely used, but a means for controlling rewriting of the flash memory portion from outside the flash memory is required. As means, the rewrite object code is loaded into an area other than the flash memory where the object code can be placed, and operation control is passed to the object code, and the object code rewrites the flash memory area.

[0005] As described above, an object code in which the address of a segment located at an absolute address (hereinafter referred to as an address at the time of arrangement) and an address at the time when a program operates on a microcomputer (hereinafter referred to as an address at the time of operation) is different. In the case of creation, in the conventional method, the operating address was described for each segment.

FIG. 15 shows a conventional language processing method, FIG. 16 shows the processing of a syntax analysis section, FIG. 17 shows a source program, FIG. 18 shows an RA symbol table (RA means relocatable assembler), FIG. 19 shows an LK symbol table (LK means a linker).

[0007]

However, the above-mentioned prior art has the following problems.

The first problem is that when there are a plurality of segments having different addresses at the time of arrangement and at the time of operation, it is necessary to obtain the segment size.

[0009] The reason for this is that, for the allocation addresses of the second and subsequent segments, the size of the segment to be allocated first must be determined and the user must take care so that the addresses do not overlap.

A second problem is that every time the device to be used is changed, an area other than the ROM where object codes can be placed must be checked.

The reason is that the conventional information file has no address during operation.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a language processing system and a language therefor capable of automating operation address resolution even when there are a plurality of segments having different addresses at the time of arrangement and at the time of operation. It is to provide a processing method.

[0013]

In the language processing system of the present invention, an arrangement time address which is an address of a segment arranged at an absolute address and an operation time address which is an address when a program operates on a microcomputer are provided. A language processing system for determining an operation address of a segment when at least one different segment is provided, wherein the language processing system includes an assembler unit and a linker unit, and the assembler unit includes a lexical analyzer and a segment type flag. The lexical analyzer includes a syntax analyzer with a setting function, a relocatable assembler code generator, and a relocatable assembler symbol table with a segment type.The lexical analyzer sequentially analyzes the language described in the source program for each delimiter in the source program, Whether the character can be used by the assembler A parsing unit having a segment type flag setting function for analyzing whether or not the source program analyzed by the lexical analyzing unit conforms to the assembler format on a line-by-line basis; Means for outputting a segment type flag to a relocatable assembler symbol table with a segment type when a segment having a different time address and arrangement time address is described in the source program. Means for generating an object program from a source program with reference to the attached relocatable assembler symbol table; the linker section includes a combining section, an arrangement section, a symbol value correction section with a segment type flag determination function, a linker code generation section, and a segment type. Attached A linker symbol table, wherein the combining unit has means for combining segments of the same segment type in the object program output by the assembler unit into one, and means for creating a linker symbol table with segment type, The arranging unit has means for arranging the individual segments combined into one in the memory by the combining unit, and the symbol value correcting unit with a segment type flag determination function is configured to calculate the segment from the address of the segment arranged in the memory by the arranging unit Means for correcting the symbol value in the linker symbol table with segment type and correcting the object program, and reading the segment type flag from the linker symbol table with segment type and when the operating address differs from the allocation address in the segment Is the information file Means for reading an address during operation from the controller and correcting the symbol value, and correcting the object program. The linker code generating section has means for generating a load module program from the object program having the corrected symbol value.

The syntax analysis unit with a segment type flag setting function sequentially analyzes the source program in line as to whether the source program conforms to the assembler format.
When a placement pseudo instruction appears, the means for processing the placement pseudo instruction and whether the placement pseudo instruction is a segment in which the address at the time of placement and the address at the time of operation are different are determined, and the address at the time of placement and the address at the time of operation differ. In the case of a segment, means for outputting a segment type flag to a relocatable assembler symbol table with segment type by a segment type flag setting process may be provided.

In the language processing system according to the present invention, at least one segment in which an arrangement time address which is an address of a segment arranged at an absolute address and an operation time address which is an address when a program operates on a microcomputer is different. A language processing system for determining an operation address of a segment when there is one, wherein the language processing system comprises:
The assembler section includes a lexical analysis section, a syntax analysis section, a relocatable assembler code generation section, and a relocatable assembler symbol table. Means for sequentially analyzing each delimiter in the program to determine whether or not the character can be used by the assembler; the parsing unit converts the source program analyzed by the lexical analysis unit into assemblers for each line And a means for generating a relocatable assembler symbol table. The relocatable assembler code generator generates an object program from a source program by referring to the relocatable assembler symbol table. Having means, The linker section includes a directive program, a directive analysis section, a directive correspondence connection section, an arrangement section, a symbol value correction section with a segment type flag determination function, a linker code generation section, and a linker symbol table with a segment type, and the directive analysis section includes: It has means for analyzing the contents of the directive program, which is a file for specifying the segment type, and the directive corresponding connection unit reads the object program and the analysis contents of the directive analysis unit,
A means for creating a linker symbol table with a segment type, the arranging section having means for arranging individual segments combined into one by a combining section in a memory, and a symbol value correcting section with a segment type flag determination function Means for correcting the symbol value in the linker symbol table with segment type from the address of the segment arranged in the memory by the arranging unit to correct the object program, and reading the segment type flag from the linker symbol table with segment type Means for reading the operating address from the information file and correcting the symbol value when the segment is different from the operating address and the arrangement address, and correcting the object program. The corrected object of And means for generating a load module program from E ECTS program.

In the language processing method of the language processing system according to the present invention, the lexical analysis unit sequentially analyzes the language described in the source program for each delimiter in the source program, and determines whether the character is a character that can be used in an assembler. And the parsing unit with the segment type flag setting function analyzes whether the source program analyzed by the lexical analysis unit conforms to the assembler format on a line-by-line basis. When a segment with a different hour address is described in the source program, the relocatable assembler symbol table with segment type is output to the relocatable assembler symbol table with segment type, and the relocatable assembler symbol table with segment type is referenced by the relocatable assembler code generator And generating an object program from the source program Te, the coupling portion couples the segment of the same segment type in the object program output by the assembler unit into one,
A step of creating a linker symbol table with a segment type, a step of arranging the individual segments combined into one by the combining unit in the memory by the arranging unit, and a arranging unit by the symbol value correcting unit with the segment type flag determination function. Corrects the symbol value in the linker symbol table with segment type from the address of the segment arranged in the memory, corrects the object program, reads the segment type flag from the linker symbol table with segment type, reads the operating address and If the segment has a different address at the time of placement, the operating address is read from the information file, the symbol value is corrected, and the object program is corrected. And a step of generating a load module program from transfected program.

Further, the syntax analyzer with the segment type flag setting function sequentially analyzes whether the source program conforms to the assembler format on a line-by-line basis. Performing instruction processing and determining whether or not the placement pseudo-instruction is a segment where the address at the time of placement and the address at the time of operation are different; if the placement address and the address at the time of operation are different segments, a segment type flag setting process And outputting a segment type flag to a relocatable assembler symbol table with segment type.

In the language processing method of the language processing system according to the present invention, the lexical analysis unit sequentially analyzes the language described in the source program for each delimiter in the source program, and determines whether or not the character can be used in an assembler. Analyzing the source program analyzed by the lexical analysis unit on a line-by-line basis to see if the source program is in assembler format, and generating a relocatable assembler symbol table. A step of generating an object program from the source program by referring to the relocatable assembler symbol table by the assembler code generation unit, and a step of analyzing the contents of the directive program which is a file for specifying the segment type by the directive analysis unit; A step of reading the object program and the analysis contents of the directive analysis unit by the directive correspondence connection unit and creating a linker symbol table with segment type; and a step of placing the individual segments combined by the connection unit into a memory. In the arranging step, the symbol value in the linker symbol table with the segment type is corrected by the symbol value correcting unit with the segment type flag determining function from the address of the segment allocated in the memory by the arranging unit, thereby correcting the object program. The segment type flag is read from the linker symbol table with segment type, and if the operating address differs from the placement address, the operating address is read from the information file to correct the symbol value. It has a step of correcting the E transfected program, the linker code generator, and generating a load module program from the corrected object program symbol values.

The language processing system and the language processing method according to the present invention can automatically resolve the operation address of a segment when the operation address of the segment has at least one segment having a different address at the time of arrangement and operation. The configuration is provided.

The following processing is performed in the assembler unit. The syntax analyzer with a segment type flag setting function outputs a segment type flag to the RA symbol table with segment type when a segment type indicating that the address at the time of operation is different from the address at the time of operation is described in the program. The following processing is performed in the linker section. The joining unit joins segments of the same segment type (hereinafter, similar segments) into one. Also, the symbol information is read from the object program to create an LK symbol table with segment type.

The arranging section arranges each type of segment united by the connecting section. The symbol value correction unit with the segment type flag determination function corrects the symbol value in the segment whose address at the time of arrangement is determined by the arrangement unit. At this time, the symbol value correction unit with segment type flag determination function reads the segment type flag in the LK symbol table with segment type, and checks whether or not the segment address is different from the segment address at the time of operation. In the case of a segment where the address at the time of arrangement and the address at the time of operation are different, the address at the time of operation is read from the information file, and the symbol value is corrected by the address at the time of operation.

This makes it possible to automate the operation address resolution even when there are a plurality of segments where the address at the time of arrangement and the address at the time of operation are different.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of the Present Invention) FIG. 1 is a diagram showing a language processing method according to a first embodiment of the present invention.

Referring to FIG. 1, the present embodiment includes an assembler unit 103 and a linker unit 104. Assembler unit 1
Reference numeral 03 includes a lexical analyzer 110, a syntax analyzer 111 with a segment type flag setting function, an RA code generator 112, and an RA symbol table 113 with a segment type.

The lexical analysis unit 110 stores the source program 10
The language described in 0 is sequentially analyzed for each delimiter in the source program 100, and whether or not the language is a character that can be used by an assembler is analyzed. The syntax analysis unit with segment type flag setting function 111 includes a lexical analysis unit 110
Whether the source program 100 analyzed in accordance with the above is in the assembler format on a line-by-line basis, and if a segment having a different address at the time of operation and at the time of arrangement is described in the source program 100, The segment type flag 1000 (FIG. 2) is output to the symbol table 113.

The segment type-added RA symbol table 113 is a table for registering information on symbols described in the source program 100. The RA symbol table 113 with segment type is
It is referenced from the A code generation unit 112.

The RA code generation unit 112 refers to the contents of the RA symbol table 113 with the segment type from the source program 100 and
1 is generated.

The linker section 104 includes the connecting section 114 and the arrangement section 1
15, a symbol value correction unit 116 with a segment type flag determination function, an LK code generation unit 117, and an LK symbol table with segment type 118.

The combining unit 114 combines similar segments in the object program 101 output by the assembler unit 103 into one, and creates an LK symbol table with segment type 118 on the memory. Arrangement unit 11
5 arranges the individual segments combined into one by the combining unit 114 in the memory.

The symbol value correction unit with segment type flag determination function 116 uses the segment type LK based on the address of the segment arranged in the memory by the arrangement unit 115.
The symbol values in the symbol table 118 are corrected, and the object program is also corrected. Also, the segment type flag (FIG. 11-1100) is read from the LK symbol table with segment type 118, and if the operating address is different from the arrangement address, the operating address is read from the information file 105 to correct the symbol value. Also corrects the object program.

The LK code generator 117 generates the load module program 102 from the object program whose symbol value has been corrected.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIGS.

The lexical analyzer 110 is provided for the source program 10
Input 0 and analyze whether the character can be used by the assembler. Source program 100 after analysis
Is a syntax analyzer 111 with a segment type flag setting function
Supplied to The syntax analysis unit with segment type flag setting function 111 sequentially analyzes whether the source program conforms to the assembler format line by line (steps S200, S201, S204 in FIG. 4).

If a placement pseudo instruction appears, step S
A placement pseudo instruction process S205 is performed by the process of 204. Next, it is determined in step S206 whether or not the placement pseudo-instruction is a segment in which the placement address is different from the operation address. If the placement pseudo instruction is a segment in which the placement address is different from the operation address, a segment type flag setting process (S207) ), The segment type flag 1000 is added to the RA symbol table 113 with segment type.
Is output. The RA code generation unit 112 receives the RA symbol table with segment type 113 as input, and generates the object program 101.

The connection unit 114 is an object program 1
01 is input, analysis is performed for each segment in the object program 101, and similar segments are combined into one segment. The object program 10
1, the symbol information is read out, and an LK symbol table with segment type 118 is created on the memory. The arranging section 115 arranges the combined individual segments.

The symbol value correction unit with segment type flag determination function 116 corrects the symbol value in the LK symbol table with segment type 118 based on the allocated address. The symbol value correction unit 116 with a segment type flag determination function outputs the segment type flag 110 from the LK symbol table 118 with a segment type.
Read 0.

Next, the operation will be described in detail with reference to FIG. It is determined whether or not the segment type flag 1100 indicates that the address at the time of arrangement and the address at the time of operation are different by step S300 in FIG. If the address at the time of arrangement is different from the address at the time of operation, the address at the time of operation is read from the information file 105 (step S30).
2) In step S303, the symbol value is corrected using the operating address. On the other hand, if the address at the time of arrangement and the address at the time of operation are the same, the symbol value is corrected by the address at the time of arrangement at step S301. Finally, the LK code generation unit 117 generates the load module program 102.

Next, the operation of the first embodiment of the present invention will be described using a specific example.

As shown in FIG.
It is assumed that three of 1, 702 are described in the source program 100.

The lexical analyzer 110 shown in FIG. 1 receives the source program 100 and analyzes whether or not the character can be used by an assembler. Since characters that cannot be used in the assembler are not included, the process is passed to the syntax analyzer 111 with a segment type flag setting function. The syntax analysis unit 111 with the segment type flag setting function has three segments 70
The format is analyzed for 0, 701, and 702. now,
It is assumed that the segment 700 is analyzed (steps S200, S201, S204 in FIG. 4). Since the segment 700 has the placement pseudo instruction "cseg", the placement pseudo instruction processing S205 is performed. Further, since "transfer" is a segment type indicating that the address at the time of arrangement and the address at the time of operation are different, the segment type flag 1000 is output to the RA symbol table with segment type 113 (steps S206 and S207 in FIG. 4, FIG. 2B).
1000-1).

Next, it is assumed that the segment 701 is analyzed. Since segment 701 also has "cseg", placement pseudo instruction processing S205 is performed. Since there is no “transfer” in the segment 701, the segment type flag 1000 is not output and the process ends (step S2 in FIG. 2).
06, FIG. 2 (b) 1000-2).

The segment 702 performs the same processing as the segment 700 (steps S206 and S207 in FIG. 4).
Fig. 2 (b) 1000-3). With the above processing, the RA symbol table with segment type 113 becomes as shown in FIG.

Next, the object program 101 including the information of the RA symbol table with segment type 113 is created by the RA code generator 112.

The connection unit 114 is the object program 1
Read 01. Since the object program 101 contains information of the RA symbol table with segment type 113 (FIG. 2B), the LK symbol table with segment type 118 is created based on this information. In addition, since similar segments are combined, in this case, the segment 700 and the segment 702 are combined.
LK symbol table 11 with segment type after combination
8 is as shown in FIG.

Next, the arrangement section 115 arranges each segment in the memory. FIG. 7 shows the memory map. When the arrangement is completed, the symbol value is corrected by the syntax analysis unit with segment type flag determination function 116. Now, it is assumed that the segments 700 and 702 are corrected. At this time, the LK symbol table with segment type 118 is referred to, and the segment type flag 1100 (FIG.
Since 100-1) is active, the operating address is read from the information file 105 and the symbol value is corrected by the operating address of the segment (steps S300, S300).
302, S303). The contents of the information file 105 having the operating address are as shown in the example of the information file (FIG. 8).

Next, when correcting the segment 701, since the segment type flag 1100 is inactive in the LK symbol table with segment type 118, the symbol value is corrected by the address at the time of arrangement of the segment (steps S300 and S301). ).

When the symbol correction is completed, the LK code generator 117 loads the load module program 1
02 is generated.

(Second Embodiment of the Present Invention) In the first embodiment of the present invention, a case where one source program and three segments are used has been described, but the number of source programs and segments is not limited.

As a problem of the first embodiment, it is necessary to newly create the source program 100 or to modify an existing one.

In addition, existing libraries cannot be used.
The problem is raised. A second embodiment is shown as a countermeasure for this.

Referring to FIG. 9, in the present embodiment, a linker 404 has a directive program 403 and a directive analyzer 412.

The assembler unit 402 is equivalent to the conventional assembler unit 103. The directive corresponding connecting unit 405 of the linker unit 404 reads the content analyzed by the directive analyzing unit 412,
And different.

The above is the difference from the embodiment of FIG.

The directive program 403 is a file for designating a segment type. The directive analyzer 412 analyzes the contents of the directive program 403.

The operation of the present embodiment will be described in detail with reference to the drawings.

Since the assembler unit 402 shown in FIG. 9 is equivalent to the conventional assembler unit 103, the lexical analyzer 110 and the RA
Code generation unit 112, placement unit 115, syntax analysis unit 116 with segment type flag determination function, LK code generation unit 117, LK symbol table 11 with segment type
8, the lexical analyzer 110, the RA code generator 112, and the respective units of the embodiment shown in FIG.
The operations are the same as those of the arrangement unit 115, the syntax analysis unit 116 with a segment type flag determination function, the LK code generation unit 117, and the LK symbol table 118 with a segment type, so that the description is omitted.

In the embodiment shown in FIG. 1, the syntax analyzer 111 with a segment type flag setting function analyzes the presence or absence of a segment having an address different from the address at the time of arrangement and the address at the time of operation.
3 output the segment type flag. In the present embodiment, this processing is not performed by the assembler unit 103. Therefore, the description of the source program 100 in FIG. 6 is simplified and becomes the format of the source program 400 shown in FIG. The difference from the source program 100 of FIG. 6 is that the segment type “transfer” indicating that the address at the time of arrangement and the address at the time of operation are different is not necessary in the source program 400 of FIG.

The parsing unit 410 shown in FIG.
0 whether the source program analyzed in the assembler format or not and the RA symbol table 4
11 is performed, which is the same processing as the conventional technique.

The directive correspondence unit 405 reads the object program 401 and the analysis contents of the directive analyzer 412, and generates the LK symbol table with segment type 118.

Next, a specific example will be described.

The case where the source program 400 is input will be described with reference to FIG. As shown in FIG. 10, the source program 400 has three segments 800 and 801 (7
01) and 802 are described. The syntax analysis unit 410 has a segment type “transfer” indicating that the address at the time of placement is different from the address at the time of operation in the above-described specific example.
Since the analysis of r ″ is not performed, the segments 800 and 80
1 (701) and 802 all perform the same processing.
The A-code generation unit generates an object program 401 equivalent to the conventional one.

Next, after reading the old format object program 401, the directive correspondence connection unit 405 calls the directive analysis unit 412.
The directive analysis unit 412 reads and analyzes the directive program 403. Now, assume that the instruction shown in FIG. 11 is described in the directive program 403. The directive analysis unit 412 analyzes this instruction, and sets the placement type to “transfer” for the segments “cseg1” and “cseg3”. Then, it instructs the directive correspondence unit 405 to output the segment type flag 1100 in the corresponding column of the LK symbol table with segment type 118 (steps S500 and S502 in FIG. 12). “Cseg1” refers to the segment 800, and “cseg3” refers to the segment 802.

Directive corresponding connection unit 4 that received the instruction
05 indicates the segments “cseg1” and “cseg1” of the generated segment type-added LK symbol table 118.
The segment type flag is output to the corresponding column of the LK symbol table with segment type 118 corresponding to 3 ″.

The processing after the arrangement unit 115 is the same as in the first embodiment.

In the second embodiment of the present invention, the linker 40
4 has a new effect that the same effect as the embodiment shown in FIG. 1 can be obtained.

[0066]

As described above, the present invention has the following effects.

The first effect is that when there are a plurality of segments having different addresses at the time of operation and addresses at the time of arrangement, it is not necessary to describe the address at the time of operation for each segment. As a result, it is possible to eliminate the troublesomeness of the user when creating a program, and furthermore, it is not necessary to calculate the segment size. This means that calculation errors can be eliminated.

The reason is that the flag is output to the symbol table by means for outputting a flag to the symbol table for a segment having an address different from the address at the time of operation and the address at the time of arrangement, and the flag is read by means for reading the flag output to the thimble table. This is because, after reading, segments are automatically arranged by means for continuously arranging segments having different addresses at the time of operation and at the time of arrangement.

The second effect is that it is not necessary to check the operating address when the device to be developed is changed. As a result, it is possible to eliminate troublesomeness when the user investigates the device.

The reason is that the information file has an operation address and that the address is automatically obtained by means for reading the operation address from the information file.

Further, with the effect of the second embodiment, the trouble of modifying an existing source program can be eliminated.

The reason is that a segment having a different address at the time of operation and an address at the time of arrangement can be specified by the directive program .

[Brief description of the drawings]

FIG. 1 is a diagram showing a language processing method according to a first embodiment of the present invention.

FIG. 2A is a diagram showing an RA symbol table with segment type before processing. (B) A diagram showing an RA symbol table with segment type after processing.

FIG. 3A is a diagram showing an LK symbol table with a segment type before combining. (B) A diagram showing an LK symbol table with segment type after combination.

FIG. 4 is a diagram illustrating processing of a syntax analysis unit with a segment type flag setting function according to the first embodiment of this invention;

FIG. 5 is a diagram illustrating processing of a symbol value correction unit with a segment type flag determination function according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a source program according to the first embodiment of this invention.

FIG. 7 is a diagram showing a memory map according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of an information file.

FIG. 9 is a diagram illustrating a language processing method according to a second embodiment of this invention.

FIG. 10 is a diagram illustrating a source program according to the second embodiment of this invention.

FIG. 11 is a diagram showing instructions described in a directive program.

FIG. 12 is a diagram illustrating processing of a directive analysis unit according to the second embodiment of this invention.

FIG. 13 is a diagram showing a memory map according to a conventional technique.

FIG. 14 is a diagram showing a memory map according to a conventional technique.

FIG. 15 is a diagram showing a conventional language processing method.

FIG. 16 is a diagram showing processing of a syntax analysis unit according to a conventional technique.

FIG. 17 is a diagram showing a source program according to a conventional technique.

FIG. 18 is a chart showing an RA symbol table according to the related art.

FIG. 19 is a table showing an LK symbol table according to the related art.

[Explanation of symbols]

100, 400, 1200 Source program 101 Object program 102 Load module program 103, 402 Assembler unit 104, 404 Linker unit 105 Information file 110 Lexical analysis unit 111 Syntax analysis unit with segment type flag setting function 112 RA code generation unit 113 With segment type RA symbol table 114 Coupling unit 115 Arrangement unit 116 Symbol value correction unit with segment type flag determination function 117 LK code generation unit 118 LK symbol table with segment type 401 Old format object program 403 Directive program 405 Directive correspondence coupling unit 410 Syntax analysis unit 411 RA symbol table 412 Directive analysis unit 600 Memory map 601, 602, 03,604,605,700,7
01 , 702 , 800 , 801, 802, 1401 , 1402 segment 1000, 1100 segment type flag 1203 symbol value correction unit 1204 LK symbol table 1500 RAM 1501 flash memory 1502 ROM

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-241196 (JP, A) JP-A-6-51993 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/06

Claims (6)

(57) [Claims] 1. An arrangement time address which is an address of a segment arranged at an absolute address and an operation time address which is an address when a program operates on a microcomputer,
What is claimed is: 1. A language processing system for determining an operation address of a segment having at least one different segment, said language processing system comprising an assembler unit and a linker unit, wherein said assembler unit comprises a lexical analyzer and a segment type. The lexical analyzer includes a syntax analyzer with a flag setting function, a relocatable assembler code generator, and a relocatable assembler symbol table with a segment type, wherein the lexical analyzer sequentially analyzes a language described in the source program for each delimiter in the source program. Has a means for respectively analyzing whether or not the character can be used in the assembler, the syntax analysis unit with a segment type flag setting function,
Means for analyzing whether or not the source program analyzed by the lexical analysis unit conforms to an assembler format on a line-by-line basis; Means for outputting a segment type flag to the relocatable assembler symbol table with segment type, wherein the relocatable assembler code generation unit refers to the relocatable assembler symbol table with segment type from the source program. Means for generating an object program, wherein the linker section comprises a combining section, an arrangement section, a symbol value correction section with a segment type flag determination function, a linker code generation section, and a linker symbol table with a segment type. The combining unit has means for combining segments of the same segment type in the object program output by the assembler unit into one, and means for creating the linker symbol table with segment type, Means for arranging the individual segments combined into one by the combining unit in a memory, the symbol value correcting unit with a segment type flag determination function having an address of a segment arranged in the memory by the arranging unit. Means for correcting the symbol value in the linker symbol table with segment type, correcting the object program, reading the segment type flag from the linker symbol table with segment type, Address is different Means for reading the address at the time of operation from an information file and correcting the symbol value to correct the object program, wherein the linker code generation unit is configured to execute the object correction with the symbol value corrected. A language processing system having means for generating a load module program from a program. 2. A parsing unit with a segment type flag setting function for sequentially analyzing whether or not the source program conforms to an assembler format line by line, and when a placement pseudo instruction appears, Means for performing a placement pseudo-instruction process; and determining whether or not the placement pseudo-instruction is a segment in which the placement address and the operation address are different. 2. The language processing system according to claim 1, further comprising: means for outputting the segment type flag to the relocatable assembler symbol table with segment type by a segment type flag setting process. 3. A location address, which is an address of a segment located at an absolute address, and an operation address, which is an address when a program operates on a microcomputer,
What is claimed is: 1. A language processing system for determining an operation address of a segment having at least one different segment, said language processing system comprising an assembler unit and a linker unit, wherein said assembler unit comprises a lexical analyzer and a parser. And a relocatable assembler code generator and a relocatable assembler symbol table. Means for analyzing whether or not there is, respectively, the syntax analysis unit, means for analyzing whether the source program analyzed by the lexical analysis unit is in assembler format line by line, and Means for generating a relocatable assembler symbol table, The relocatable assembler code generation unit has means for generating an object program from the source program by referring to the relocatable assembler symbol table. The linker unit includes a directive program, a directive analysis unit, a directive correspondence connection unit, and a placement unit. And a symbol value correction unit with a segment type flag determination function, a linker code generation unit, and a linker symbol table with a segment type, wherein the directive analysis unit analyzes the contents of the directive program which is a file for specifying a segment type. Means for reading the object program and the contents of analysis by the directive analysis unit, and the linker symbol table with segment type. The arrangement unit has means for arranging individual segments combined into one by the combining unit in a memory, and the symbol value correction unit with a segment type flag determination function is Means for correcting the symbol value in the linker symbol table with segment type from the address of the segment allocated in the memory by the allocation unit and correcting the object program; and determining the segment type from the linker symbol table with segment type. Means for reading a flag and, when the operating address and the arrangement address are different segments, reading the operating address from an information file and correcting the symbol value to correct the object program, The linker code generation unit includes: Language processing system having a means for generating a load module program from the corrected said object program symbol values. 4. A step of sequentially analyzing the language described in the source program for each delimiter in the source program by the lexical analysis unit and analyzing whether or not the language is a character usable in an assembler. The segment type flag setting function-equipped syntax analysis unit analyzes whether or not the source program analyzed by the lexical analysis unit conforms to the assembler format on a line-by-line basis. Outputting a segment type flag to the relocatable assembler symbol table with segment type when the segment having a different type is described in the source program; andthe relocatable assembler code generation unit generates the relocatable assembler symbol table with segment type. Generating an object program from the source program with reference to the source program; combining the segments of the same segment type in the object program output by the assembler unit into one by the combining unit; Creating a table; arranging the individual segments combined into one by the combining unit in the memory by the arranging unit; and arranging the segment value by the segment type flag determination function-equipped symbol value correcting unit by the arranging unit. Correcting the symbol value in the segment type-added linker symbol table from the address of the segment arranged in the memory,
The object program is corrected, the segment type flag is read from the linker symbol table with segment type, and when the operating address and the arrangement address are different segments, the operating address is read from the information file. 2. The method according to claim 1, further comprising: correcting the object program by correcting a symbol value; and generating a load module program from the object program having the corrected symbol value by the linker code generator. 3. The language processing method of the language processing system. 5. A step of sequentially analyzing whether or not the source program conforms to the assembler format line by line by the syntax analyzer with the segment type flag setting function, and when an arrangement pseudo instruction appears, Performing a placement pseudo-instruction process; and determining whether the placement pseudo-instruction is a segment in which the placement address and the operation address are different. If the placement address and the operation address are in different segments, Outputting the segment type flag to the relocatable assembler symbol table with segment type by a segment type flag setting process. 6. The lexical analysis unit sequentially analyzes a language described in a source program for each delimiter in the source program, and analyzes whether the language is a character that can be used in an assembler. Analyzing the source program analyzed by the lexical analysis unit in the assembler format on a line basis by the syntax analysis unit to generate the relocatable assembler symbol table; and generating the relocatable assembler code. Generating an object program from the source program by referring to the relocatable assembler symbol table, and analyzing the contents of the directive program, which is a file for specifying a segment type, by the directive analyzer. Reading the object program and the analysis contents of the directive analysis unit by the directive correspondence connection unit to create the linker symbol table with segment type; and the arrangement unit is connected by the connection unit to one. Arranging each segment set in the memory by the symbol value correcting unit with the segment type flag determination function, from the address of the segment arranged in the memory by the arranging unit, the symbol in the linker symbol table with the segment type. After correcting the value,
The object program is corrected, the segment type flag is read from the linker symbol table with segment type, and when the operating address and the arrangement address are different segments, the operating address is read from the information file. 4. The method according to claim 3, further comprising: correcting a symbol value to correct the object program; and generating a load module program from the object program having the corrected symbol value by the linker code generation unit. 5. The language processing method of the language processing system.