JP3276823B2 - Video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit for generating a display video signal having a different synchronizing signal by converting an input video signal on a time axis using a buffer memory such as a field memory or a frame memory. And a circuit for monitoring the passing of addresses between a write address and a read address for a buffer memory.

[0002]

2. Description of the Related Art A case where a video signal from a personal computer or the like is displayed on a normal television receiver or a case where a normal television signal is displayed on a television receiver not operating in synchronization with the television signal. In accordance with the write clock corresponding to the synchronization signal, the input video signal is temporarily written to a buffer memory such as a field memory or a frame memory, and the video signal written according to the read clock corresponding to the synchronization signal of the video signal to be displayed is read. In general, a display video signal is used.

[0003] When the above buffer memory is used,
Since the synchronizing signal frequencies of the input video signal and the display video signal are different, one of the write addresses and the read address always overtakes the other, and in this case, in one screen of the display video, The two fields or frames of the input video are switched, and the image quality is significantly impaired.

Therefore, conventionally, a write address and a read address with respect to a buffer memory are monitored, and it is predicted whether or not one of them overtakes the other. The switching of the display content in was prevented.

[0005]

Normally, a buffer memory such as a field memory or a frame memory has a built-in address counter and determines a write and read address based on an input clock.
For this reason, it is not possible to adopt a configuration in which the address itself is monitored externally in order to predict the overtaking of the address.
Further, in such a configuration, there is a problem that the circuit must be large-scale because the number of bits of the address itself is large.

[0006]

SUMMARY OF THE INVENTION The present invention provides first and second embodiments.
In the video signal processing circuit for alternately writing the input video signal to the buffer memory of, and alternately reading the written video signal to obtain the display video signal, when starting the read operation from the first and second buffer memories, A first address monitoring circuit that determines whether a buffer memory that is performing writing matches a buffer memory that is performing reading, and predicts the occurrence of address overtaking in reading and writing in accordance with the determination result; A detection circuit for detecting a phase difference between a vertical signal of an input video signal and a display video signal and a temporal change amount of the phase difference, a comparison circuit for comparing the phase difference with the temporal change amount, and writing when starting a read operation; A determination circuit for determining whether or not the buffer memory performing the read operation matches the buffer memory attempting to perform the read operation; and A second address monitoring circuit for predicting occurrence of address overtaking in reading and writing in accordance with the results of the comparison circuit and the determination circuit, and a switching circuit for switching between the first and second address monitoring circuits in response to a switching signal And characterized in that:

The present invention also relates to a video signal processing circuit for alternately writing an input video signal to first and second buffer memories and alternately reading the written video signal to obtain a display video signal. When starting a write operation to the second buffer memory, it is determined whether or not the buffer memory that is performing the read operation matches the buffer memory that is to perform the write operation. A first address monitoring circuit for predicting the occurrence of a phase difference, a detection circuit for detecting a phase difference between the input image signal and the vertical signal of the display image signal, and an amount of change with time of the phase difference; A comparison circuit, a buffer memory that performs reading and a buffer memory that performs writing when starting a writing operation A judgment circuit for judging whether they match, a second address monitoring circuit for predicting the occurrence of address overtaking in reading and writing in accordance with the results of the comparison circuit and the judgment circuit, and a second address monitoring circuit in accordance with a switching signal A switching circuit for switching between the first and second address monitoring circuits.

Further, the present invention is characterized in that it further comprises a second detection circuit for detecting that the amount of change with time has become smaller than a predetermined value, and a detection output of the detection circuit is used as the switching signal.

[0009]

FIG. 2 is a block diagram showing an embodiment of the present invention. Reference numerals 1 and 2 denote first and second field memories (M1, M2) each storing an input video signal for one field. ), And write address counters WCTR3 and WCTR4 for designating a write address, respectively.
Read address counters RCTR5 and RCTR6 for designating a read address are provided, and writing and reading are controlled by various signals from a timing control circuit 7.

[0010] The timing control circuit 7 includes an input video clock generator 8 for generating a clock for controlling writing, a display video clock generator 9 for generating a clock for controlling reading, and a clock between the writing address and the reading address. It has an address monitoring circuit 10 for monitoring address overtaking. The input video clock generator 8 receives an input H and an input V, which are a horizontal synchronization signal and a vertical synchronization signal of the input video signal, and outputs a write clock signal WCLK, a write reset signal WRST, a write select signal WE, a write enable signal WE1, and a WE2. Is output.

The write clock signal WCLK corresponds to the bit rate of the input video signal which is digital data in synchronization with the input H, and the write select signal WE
As shown in FIG. 3A, the signal level is inverted every cycle of the input V in synchronization with the input V. The write select signal WE is input to the AND gate 81 as it is, and is inverted by the inverter 82 to be AND gate 83
Is input to

The input video clock generator 8 has a first clock generator 84 therein, and this generator outputs a signal DISP1 indicating a valid display period of the input video signal. As shown in FIG. 3D, this signal DISP1 is a signal which rises after a lapse of a predetermined period t after the inversion of the write select signal WE.
3 is input. Therefore, as shown in FIGS. 3A and 3A, the AND gates 81 and 83 output the write enable signals WE1 and W alternately outputting the H level according to the signal level of the write select signal WE during the same period as the signal DISP1.
E2 is output. Also, the write reset signal WRST
Are also output in synchronization with the rising edge of DISP1, as shown in FIG. 3C, so that the signals WE1, WE2, WRS
T is output after a lapse of a predetermined period t after the inversion of the light select signal WE. When the horizontal synchronization signal cycle of the input video signal is 1H, t is, for example, 20H
The degree is chosen.

The write address counters 3 and 4 in the field memories 1 and 2 are reset by the write reset signal WRST, and increment the write address by counting the write clock WCLK while the signals WE1 and WE2 are at the H level. Therefore, the input video signals are written in the field memories 1 and 2 in order from the lower address to the upper address.
Also, the input video signal is written alternately in field units by the write enable signals WE1 and WE2.

On the other hand, the display video clock generator 9
Generates and outputs a display H and a display V, which are a horizontal synchronizing signal and a vertical synchronizing signal of a display video signal, and further generates a read clock signal RCLK, a read reset signal RRST, a read select signal RE, and read enable signals RE1 and RE2. Is output. The read clock signal RCLK is
It is generated corresponding to the bit rate of the display video signal so as to synchronize with the display H, and the read select signal RE
Is output such that the signal level is inverted every period of the display V in synchronization with the display V as shown in FIG. This read select signal RE is an exclusive OR (EX-EX-) for inputting the output signal MON from the address monitoring circuit 10.
OR) The signal is directly input to the AND gate 91 via the gate 95, and is inverted by the inverter 92 to output the signal A.
The signal is input to the ND gate 93.

The display video clock generator 9 has a second clock generator 94 therein, and this generator outputs a signal DISP2 indicating an effective display period of the display video signal. As shown in FIG. 3, this signal DISP2 rises after a predetermined period t has elapsed after the inversion of the read select signal RE.
3 is input. Therefore, when the signal MON is at the L level, the signal RE passes directly through the EX-OR gate 95 and becomes the signal MRE. From the AND gates 91 and 93, as shown in FIGS. During the same period, read enable signals RE1 and R alternately outputting an H level according to the signal level of read select signal RE
E2 is output. Also, the read reset signal RRST
Are output in synchronization with the rise of DISP2 as shown in FIG.
T is output after a predetermined period t has elapsed after inversion of the read select signal RE.

The read address counters 5 and 6 in the field memories 1 and 2 are reset by the read reset signal RRST, and increment the read address by counting the write clock RCLK while the signals RE1 and RE2 are at the H level. Therefore, reading from the field memories 1 and 2 is performed in order from the lower address to the upper address, and
Reading is performed alternately in field units by the read enable signals RE1 and RE2.

When the address monitoring circuit 10 predicts that an address overtaking will occur in one of the two field memories 1 and 2, the signal MON goes high. When the signal MON goes high, the EX-OR gate 95 inverts the signal RE, so that the signal levels of the signals RE1 and RE2 are inverted. The performed field memory is continuously read again. That is, by changing the read memory, address overtaking on the same field memory is avoided, and deterioration of image quality is prevented.

Next, the address monitoring circuit 10 will be described with reference to FIG. As shown in FIG. 1, the address monitoring circuit 10 includes a first address monitoring circuit 11, a second address monitoring circuit 12, and a switching circuit 13 that switches the outputs MON1 and MON2 of both monitoring circuits according to a mode switching signal MODE. Have been. This mode switching signal M
ODE is a signal input from the outside of a microcomputer or the like, and is a signal determined by what is used as an input video signal source or what kind is used as an output video device. When the synchronizing signal frequency of the display video signal is close, the L level is output. And the switching circuit 1
In 3, the output MON1 of the first address monitoring circuit 11 is output as the signal MON when the signal MODE is at the L level, and the output MON2 of the second address monitoring circuit 12 is output as the signal MON when the signal MODE is at the H level.

Therefore, first, the first address monitoring circuit 11
Will be described. As shown in FIG. 1, the circuit 11 has a very simple configuration, and receives a read select signal RE and a read reset signal RRST.
An ND gate 101 and an output F of the AND gate 101
D flip-flop 102 that inputs RST to a clock terminal and inputs a write enable signal WE to a data terminal
1-bit register. As shown in FIG. 3, the AND gate 101 always outputs the signal WE at H level.
Level read reset signal RRST
From the gate output FRS.
The coincidence between the signals WE and RE is detected by taking in the signal WE into the register 102 at T, and the H level is output when the signals MON1 match and the L level is output when they do not match.

Therefore, as shown in FIG. 3, when the frequencies of the input V and the display V are close and the phase difference is relatively small, the difference between the frequencies of the signals WE and RE and the phase difference are also small. Selection of the field memories 1 and 2 is performed by the signals WE and RE.
The fact that the phase difference is small means that writing and reading are performed on almost the same field memory. Therefore, the writing address and the reading address on the same field memory are different from each other. One may overtake the other. in this case,
In the address monitoring circuit 10, the gate output F shown in FIG.
At the rising edge of RST, the H level WE is
The signal MON1 becomes H level,
Predict that address overtaking will occur. Therefore, the signal RE is inverted and EX-O is output as shown in FIG.
The output signal MRE of the R gate is inverted. This avoids address overtaking.

On the other hand, even if the frequency of the input V is close to the frequency of the display V, as shown in FIG. 4, when the phase difference is large, the phase difference between the signals WE and RE is also large. This is performed on the memory, so that one of the write address and the read address does not overtake the other on the same field memory. In this case, the address monitoring circuit 10 captures the L level WE at the rising edge of the gate output FRST into the register 102, so that the signal MON1 becomes L level and predicts that no address overtaking will occur. Therefore, the read memory is not changed by the signal RE.

By the way, it is assumed that the phase difference gradually widens from the state shown in FIG. 3 and the state becomes as shown in FIG.
In this state, when the gate output FRST rises in the address monitoring circuit 10, the D flip-flop 102 captures the H level immediately before the signal WE drops to the L level. Therefore, the signal MON1 becomes H
Level, the signal RE is inverted accordingly, the signal MRE becomes L level similarly to the signal WE, and writing and reading are performed on the same field memory 2.

However, reading from the field memory 2 is actually started only when the signals RRST and RRST are output.
This is when E2 rises to the H level, and this timing is before the signal WE is inverted to the L level. On the other hand, writing to the field memory 2 is performed by the signal WE.
2 and WRST rise, that is, the signal WE is started after a predetermined period t has elapsed after the inversion, so that there is at least a time difference of t between reading and writing.

Here, since it is assumed that the frequency of the input V is close to the frequency of the display V, the difference between the periods of the two signals does not become smaller than t within one frame.
If there is a time difference of, no address overtaking occurs between writing and reading even in the same field memory.
Therefore, in this case, there is no problem even if the signal MON1 goes high.

Next, it is assumed that the phase difference gradually narrows from the state shown in FIG. 4 to a state shown in FIG. In this state, in the address monitoring circuit 10, the gate output FR
When ST rises, the D flip-flop 102
Captures the L level immediately before rising to the H level as the signal WE. Therefore, the signal MON1 becomes L
Level, the signal RE is not inverted and the signal MRE is the signal W
As in the case of E, the level becomes H level, and writing and reading are performed on the same field memory 1.

However, reading from the field memory 1 is actually started only when the signals RRST and RRST are output.
This is when E1 rises to the H level, and before the signal WE is inverted to the H level. On the other hand, writing to the field memory 1 is performed by the signal WE.
1 and WRST rise, that is, the signal WE is started after a predetermined period t has elapsed after the inversion, so that there is at least a time difference of t between reading and writing.
If the frequency of the input V is close to the frequency of the display V, the difference between the periods of the two signals will not be reduced by t or more within one frame. Therefore, even in the same field memory, no overtaking of the address occurs during writing and reading. Therefore, in this case, there is no problem even if the signal MON1 goes to L level.

The first address monitoring circuit 11 described above works effectively when the synchronizing signal frequencies of the input video signal and the display video signal are close to each other, but the phase difference becomes t in one frame.
If the frequency difference between the two signals is larger as the signal spreads (about 20H) or more, it cannot be predicted correctly.
The second address monitoring circuit 12 shown in FIG. The second address monitoring circuit 12 includes a counter 121 that is reset by the input V and counts the display H, and a register 122 that captures the contents of the counter 121 when the display V falls.
A register 123 that takes in the contents of the register 122 when the display V falls, a register 124 that takes in the contents of the counter 122 when the input V falls,
A, B, L of two registers 122, 123, 124
And an arithmetic circuit 125 for performing an arithmetic operation.

FIG. 8 is a timing chart showing the relationship between the input V and the display V. The counter 121 counts the phase difference (the number of horizontal scanning lines) A from the fall of the input V to the fall of the display V. The value A is sequentially transferred to the register 123. At this time, the following phase difference B is obtained in the register 122. Since the counter 121 finally counts until the next input V is input, the register 124 obtains the number L of horizontal scanning lines in one vertical scanning period of the input V.

Next, the operation contents of the operation circuit 125 are shown in FIG.
This will be described with reference to the flowchart of FIG. Here, FIG.
Examples of the input V and the display V are shown in FIGS. FIG. 11 shows a case where the display V has a lower frequency than the input V, and FIG. 12 shows a case where the display V has a higher frequency than the input V.

Therefore, the arithmetic circuit 125 first sets A,
B and L are fetched and a determination of AB <0 is made (S1).
2). In this determination, it is determined whether or not the delay of the display V with respect to the input V tends to increase. If the determination is Y, the display V is slower than the input V as shown in FIG.
At the timing of the next display V, the phase difference is further enlarged by | AB |. That is, | AB | indicates the amount of change in the phase difference with time, and then the amount of change is compared with | LB | (S13). If the result of this comparison is Y, the relationship between the input V and the display V is switched by the time the next display V occurs. Therefore, when writing and reading are performed on the same memory, an address overtaking occurs.

Therefore, at the time when the signal RRST rises and the reading is started, the signal WE and the signal MRE are compared to determine whether the write memory (W memory) matches the read memory (R memory). Judgment (S
14). This is because the write memory is M1 and the read memory is M2 at the beginning of the hatched portion in FIG.
It corresponds to being. In this case, the read memory M2
During the reading of the data, the write memory becomes M2, and an address overtaking occurs. That is, if they do not match,
Since overtaking occurs before the next display, the signal MON2
And if the value at that time is “0”, “1”
If it is "1", it is set to "0" (S15).

On the other hand, if AB is not negative in S12, as shown in FIG. 12, the display V is earlier than the input V, and the phase difference is A at the next display V timing. −B is smaller. Therefore, it is determined whether the temporal change amount AB of the phase difference is smaller than B (S1).
6). If Y in S16, the relationship between the input V and the display V is switched during the reading of the next field. Therefore, at the time of the rise of the signal RRST, the signal WE
And the signal MRE to determine whether the write memory (W memory) matches the read memory (R memory) (S17). If they match, the read address overtakes the write address by the next display V. Therefore, the process proceeds to S15 where the signal MO
Change the value of N2. This corresponds to that the write memory is M2 and the read memory is M2 at the head of the hatched portion in FIG. In this case, the read address overtakes the write address during the writing of the write memory M2.

If Y in S14 and N in S17, there is no need to change the signal MON2 because address overtaking does not occur in the same memory, which is a problem. If "1" is added to MON2 in S15, and if "Y" in S14 and "N" in S17, wait until three fields have elapsed (S18).
Return to 11. Then, the next A and B are fetched, and the processing for the next field is performed. In S13 and S16, even in the case of N, the write address does not overtake the read address by the timing of the next display V, so that new A and B are fetched at the timing of the next display V, and the processing is repeated.

Here, when it is detected that an address overtaking has occurred, waiting for three fields in S18 is because the operation immediately after the overtaking does not produce a correct value.
Also, it is not practical to convert video signals whose synchronization timing is far apart such that overtaking occurs within three fields. As described above, when the signal MON2 becomes "1", the signal RE is output by the EX-OR gate 95 as described in the first address monitoring circuit.
Is inverted to become an MRE, whereby the read memory is changed.

In FIG. 11, the memories M1 to fn-
Next, if fn-2 is read from the memory M2 after reading 3, the write address of fn to the memory M2 will overtake the read address during that time.
Therefore, by setting MON2 to “1”, the read memory is changed from M2 to M1, and the memory M1 is read twice consecutively to omit the field of fn−2. Thereafter, reading is performed alternately from the memories M2 and M1 until the next overtaking occurs.

In FIG. 12, by setting MON2 to "1", reading of fn-1 from the memory M1 is followed by reading of fn-1 from the memory M1. As a result, the read address overtakes the write address during the writing of fn in the memory M2, and fn-
2 can be prevented from being read. As described above, the second address monitoring circuit 12 can reliably predict address overtaking when the difference between the synchronization signal frequencies of the input video signal and the display video signal is large to some extent. However, the counter 121 in the second address monitoring circuit 12
Since the display H is counted, the synchronizing signal frequency between the input video signal and the display video signal becomes close and the phase difference cannot be detected if the phase difference becomes 1H or less during the horizontal scanning period of the display video signal.

Therefore, in this embodiment, the first and second address monitoring circuits are switched by an external mode signal MODE so that input video signals and display video signals in a wide frequency range can be handled. . Here, as described above, | AB | indicates the amount of change in the phase difference with time, so that a small value means that the synchronizing signal frequencies of the input video signal and the display video signal are close to each other. I do. Therefore, as shown by the dotted lines in FIG.
Is provided, where | A−
B | <C (C: predetermined value) is determined, and a signal MD which becomes H level when Y is obtained and becomes L level when N is output, and this signal is used as a mode switching signal MODE, Switching can be performed automatically. Note that C may be a small value such as 3H or 4H.

The first address monitoring circuit 1 described above
In 1, the overtaking of the address is predicted for each frame, but may be performed for each field. For example, as shown in FIG. 7, an EX-NOR gate 103 that inputs the signals RE and WE, and a D flip-flop 104 that inputs the output of the NOR gate to the data terminal D and inputs the signal RRST to the clock terminal CL, The first address monitoring circuit 11 may be configured.

The first address monitoring circuit 11 predicts address overtaking at the start of the read operation based on the signal RRST. However, in FIGS. 1 and 7, instead of the signals RRST, RE and WE, By using the signals WRST, WE, and RE, respectively, it is possible to predict address overtaking at the start of the write operation with the same configuration. Also in the second address monitoring circuit 12,
Instead of generating the signal MON2 based on the display V,
It is also possible to generate the signal MON2 based on the input V and predict the address overtaking at the start of the write operation. In this case, the EX-OR gate 95 for inputting the signal MON shown in FIG. 2 is removed, the signal RE is used in place of the signal MRE, and the EX-OR gate is provided on the write side so that the signals MON and WE are output. The output and its inverted output are input to AND gates 81 and 83. With this configuration, when an address overtaking is predicted, instead of continuously reading data from the same field memory, writing data can be continuously written to the same memory. Address overtaking can be avoided.

The present invention is naturally applicable to a system using not only a field memory but also a frame memory.

[0041]

According to the present invention, even if the frequency difference between the input video signal and the display video signal is wide, a simple circuit configuration can be used to reliably predict the overtaking of the write and read addresses for the buffer memory. Become. In particular, this is optimal when a buffer memory that internally determines write and read addresses according to an input clock is used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first address monitoring circuit.

FIG. 2 is a block diagram illustrating a video signal processing circuit.

FIG. 3 is a timing chart when it is predicted that an address overtaking will occur.

FIG. 4 is a timing chart when it is predicted that address overtaking will not occur.

FIG. 5 is another timing chart when it is predicted that an address overtaking will occur.

FIG. 6 is another timing chart when it is predicted that address overtaking will not occur.

FIG. 7 is a circuit diagram showing another example of the first address monitoring circuit.

FIG. 8 is an explanatory diagram illustrating a phase difference between an input video signal and a display video signal.

FIG. 9 is a circuit diagram showing a second address monitoring circuit.

FIG. 10 is a flowchart showing processing contents of an arithmetic circuit in the second address monitoring circuit.

FIG. 11 is an explanatory diagram showing a change of a read memory.

FIG. 12 is an explanatory diagram showing another modification of the read memory.

[Explanation of symbols]

 1, 2 field memory 3, 4 write address counter 5, 6 read address counter 7 timing control circuit 8 input video clock generator 9 display video clock generator 10 address monitoring circuit 11 first address monitoring circuit 12 second address monitoring circuit 13 switching circuit 81, 83, 91, 93, 101 AND gate 95, 103 EX-OR gate 102, 104 D flip-flop 121 counter 122, 123, 124 register 125 arithmetic circuit 126 second arithmetic circuit

──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Haruya Ota 2-5-5-Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-64-46375 (JP, A) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 7/01

Claims (3)

(57) [Claims] An image signal processing circuit for alternately writing an input image signal to first and second buffer memories and alternately reading the written image signal to obtain a display image signal, wherein the first and second buffer memories are provided. when starting the read operation from the buffer memory, and determines whether the buffer memory is identical to attempting to buffer memory and reading being written, in the case of coincidence in the same buffer memory
A first address monitoring circuit for predicting the occurrence of an address overtaking in reading and writing, and detecting a generation timing of a vertical signal of the input video signal and the display video signal ;
A detection circuit for detecting a temporal change in the difference between the occurrence timings, and comparing the detected temporal change with a predetermined value;
The input video signal at the next field timing.
Signal and the display video signal are switched.
The next field timing depends on the comparison circuit
Switch the relationship between the input video signal and the display video signal.
When the read operation is started,
Determination circuit for determining whether the buffer memory is identical to attempting to buffer memory and reading is writing, and, second to predict the occurrence of address overtaking the read and write according to the result of determine Teikairo Address monitoring circuit, the input video signal and the display video signal
In response to the switching signal based on the magnitude of the frequency difference
And a switching circuit for switching the second address monitoring circuit. 2. A video signal processing circuit for alternately writing input video signals to first and second buffer memories and alternately reading the written video signals to obtain a display video signal, wherein the first and second buffer memories are provided. When starting a write operation to the buffer memory, it is determined whether or not the buffer memory from which the data is being read matches the buffer memory to which the data is to be written.
A first address monitoring circuit that predicts the occurrence of address overtaking in reading and writing , and a timing of generation of a vertical signal of the input video signal and the display video signal , and further
A detection circuit for detecting a temporal change in the difference between the occurrence timings, and comparing the detected temporal change with a predetermined value;
The input video signal at the next field timing.
Signal and the display video signal are switched.
The next field timing depends on the comparison circuit
Switch the relationship between the input video signal and the display video signal.
When the write operation is started,
Determination circuit for determining whether the buffer memory is identical to attempting to buffer memory and write that performing the read, and, second to predict the occurrence of address overtaking the read and write according to the result of determine Teikairo Address monitoring circuit, the input video signal and the display video signal
In response to the switching signal based on the magnitude of the frequency difference
And a switching circuit for switching the second address monitoring circuit. A second detection circuit for detecting that the amount of change with time has become smaller than a predetermined value, wherein a detection output of the detection circuit is used as the switching signal, and the amount of change with time is predetermined.
If less than the value, the first address monitoring circuit
If the change over time is greater than a predetermined value, the second address monitoring cycle
3. The video signal processing circuit according to claim 1, wherein the circuit is switched to a road .