JP3273926B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, and more particularly, to a digital signal processing device, which comprises an operation means and a non-volatile program storage means for storing a program executed by the operation means. When a plurality of programs are stored in the program storage means,
The present invention relates to a digital signal processing device in which the arithmetic means selects and executes any one of a plurality of programs stored in the program storage means to process a digital signal.

[0002]

2. Description of the Related Art In recent years, as semiconductor technology has improved, relatively large-capacity semiconductor memories have been supplied at a low cost. Therefore, audio signal reproducing devices using semiconductor memories as storage media have been commercialized. It is getting. However, even if a relatively large-capacity semiconductor memory can be used, since the amount of information of audio signals and video signals that change in time series is enormous, high-efficiency encoding processing must be performed when storing these signals. It is mandatory to do. Of course, even when communication is performed using a mobile phone or the Internet, that is, when communication is performed using a relatively narrow band, high-efficiency encoding processing and decoding processing that is paired with the high-efficiency encoding processing are required. For this reason, the demand for Digital Signal Processors (DSPs), which can process audio signals and video signals at high speed with relatively low power consumption, is increasing. The device is equipped with a DSP. For example, in a reproducing apparatus using the above-mentioned semiconductor memory as a storage medium, the above-mentioned DSP is combined, and a coded audio signal or the like stored in the semiconductor memory is subjected to decoding processing by the above-mentioned DSP and reproduced and output, thereby reducing the size of the apparatus. Thus, it is possible to provide a portable device having excellent portability, realizing high performance, vibration resistance, low power consumption, and high speed operation. By the way, in the above-mentioned reproducing apparatus, in order to cope with various encoding methods, the above-mentioned DS is used.
There may be a case where a plurality of decryption programs executed by P are prepared. In this case, it is necessary to select one program from a plurality of stored programs as needed. A technique for selecting one program from a plurality of stored programs and executing the processing is described in, for example, Japanese Patent Application Laid-Open No. 7-306806. In the technology described in the above publication, when an operation key is operated, one of a plurality of programs is selected from a memory pack under the control of a system controller,
For example, the data is supplied to an audio data decompression circuit or a video data decompression circuit, and audio and video are reproduced and output. In order to select one of a plurality of programs, a memory pack includes a read-only memory and a management memory. And an address control circuit. Access management information including a read permission flag and the like corresponding to each program is stored in the management memory. Based on the access management information, the start address of the selected program is read out and read by the address control circuit. The read address is set. One of a plurality of programs stored in the read-only memory is read using the read address.

[0003]

In the technique described in the above publication, even if a plurality of programs have a common part, reading from the read-only memory to a signal processing circuit such as an expansion circuit is performed for each program. Therefore, each time a different program is executed, it is necessary to reread the common portion many times, and the overhead increases. Further, the technology described in the above publication only supports port reading from a memory, and cannot map the address space of a signal processing circuit. For this reason,
It is greatly affected by the physical constraints of the memory. For example, the processing memory provided in the signal processing circuit has a relatively small capacity, so that the program stored in the read-only memory cannot be transferred at one time in many cases. However, since the read-only memory is not mapped to the address space, the signal processing circuit is not used. In order for the circuit to execute a portion that is not stored in the processing memory, it is necessary to access the read-only memory again via the port, and the execution speed is reduced. In addition, the program itself must be created so that the user can operate independently in consideration of the capacity of the processing memory, which increases the burden on the user. Further, an address control circuit or the like is required to select one of a plurality of programs stored in the read-only memory, and the circuit configuration becomes complicated. In order to solve the problems in the prior art, the present invention has improved a digital signal processing device, and a common module among a plurality of programs stored in a program storage means has been previously stored in a nonvolatile second storage. When any one of the plurality of programs is selected to be executed by the arithmetic means, the non-common modules other than the common module among the modules corresponding to the selected program are stored. The common module is copied from the program storage unit to the rewritable volatile first storage unit, and the operation unit transfers the non-common module and the common module from the first storage unit and the second storage unit, respectively. By reading and executing the program, re-reading is possible even when there is a common part between multiple programs. It is an object to provide a digital signal processing apparatus which can suppress to live. Another object is to arrange all the modules of the selected program in the program space so that the non-common module can be used in the first program.
Even if the data cannot be stored in the storage means, it is necessary to suppress the occurrence of rereading, or to reduce the physical constraints on the memory of the program to reduce the burden on the user. Still another object is to simplify a configuration for selecting a plurality of programs.

[0004]

In order to achieve the above object, the invention according to claim 1 comprises an arithmetic unit and a non-volatile program storage unit for storing a program executed by the arithmetic unit. When a plurality of different programs are stored in the program storage means, the arithmetic means selects and executes any one of the plurality of programs stored in the program storage means to execute the digital signal. In the digital signal processing apparatus which processes the above, a rewritable volatile first storage means, and a nonvolatile non-volatile storage of a module common among the plurality of programs in advance among modules constituting each program Read-only second storage means, and any one of the plurality of programs is executed by the arithmetic means. Is selected, all or some of the non-common modules other than the common module among the modules corresponding to the program stored in the program storage means are transferred from the program storage means to the first module. The operation means duplicates the common module and the non-common module.
Via the program memory space of the computing means
The first storage means, the second storage means, and
All of the non-common modules are stored in the first storage means.
If the digital signal processor is not manufactured, the non-common module and the common module are read from the program storage unit and the program is executed to execute the program . The invention according to claim 2, in a digital information processing apparatus according to claim 1, from said program storage means, to replicate the non-common module from the highest its access frequency in said first memory means Things. The invention according to claim 3 is the digital information processing device according to any one of claims 1 or 2, either or both of said first memory means and said second memory means the operation The gist is that it is internally connected to the means. According to a fourth aspect of the present invention, in the digital signal processing device according to any one of the first to third aspects, the plurality of programs are stored in different continuous areas of the program storage means, respectively. The gist is that the arithmetic means selects one of a plurality of programs stored in the program storage means using a selection circuit for selecting the continuous area. According to a fifth aspect of the present invention, in the digital signal processing apparatus according to the fourth aspect , the selection circuit specifies each address of a different continuous area of the program storage means by a predetermined number of bit information. Things. According to a sixth aspect of the present invention, in the digital signal processing apparatus according to any one of the first to fifth aspects, the plurality of programs are programs for reproducing digital audio signals. And

According to the digital signal processing apparatus of any one of claims 1 to 6, a common module among a plurality of programs stored in the program storage means is stored in advance in the nonvolatile second storage means. When it is selected that one of the plurality of programs is to be executed by the arithmetic means, the non-common module other than the common module among the modules corresponding to the selected program is selected. Copying the module from the program storage means to the rewritable volatile first storage means,
The arithmetic unit reads out the non-common module and the common module from the first storage unit and the second storage unit, respectively, and executes the program, so that even when there is a common part between a plurality of programs, The occurrence of rereading can be suppressed. Further, since the common module is stored in the second storage means in advance, overhead transferred from the program storage means can be suppressed, the capacity required for the program storage means can be reduced, and the size of the entire system can be reduced. The scale can be increased. Moreover, the upper SL when all the program storage means of non-common module corresponding to the program in the first storage means is not replicated, the non-common module also program the operation means duplicated not part of the Since it is arranged in the memory space, it is not necessary to re-read the non-replicated part of the non-common module into the first storage means, relax the physical constraints on the memory for the program, and reduce the burden on the user. Can be reduced. Further, according to the digital signal processing device of the second aspect , the non-common module is copied to the volatile first storage means having a high access frequency from a high access frequency. Be faster. Further, according to the digital signal processing device of the third aspect , since one or both of the first storage means and the second storage means are internally connected to the arithmetic means, the circuit is simplified. The size and size are reduced, and it is easy to increase the speed with the bus configuration.
Further, according to the digital signal processing device of the fourth and fifth aspects, the plurality of programs are stored in different continuous areas of the program storage means, respectively, and the arithmetic means selects the continuous area. For example, in order to select one of the plurality of programs stored in the program storage means by using a selection circuit for selecting a plurality of programs, a simple logic circuit or the like representing a predetermined number of bits of information is used. Can be easily selected.

[0006]

Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.
The following embodiment is a specific example of the present invention and does not limit the technical scope of the present invention. First, a digital signal processing device according to an embodiment of the present invention is embodied as, for example, a device for executing a program for decoding pre-encoded and stored audio information, and is a portable small audio information device. It is mounted on a playback device. Here, FIG. 1 is a diagram showing a schematic configuration of a digital signal processing device according to one embodiment of the present invention. FIG.
As shown in FIG. 1, a digital signal processing apparatus according to an embodiment of the present invention includes a multiplier, an accumulator, and the like, and a signal processing element (corresponding to arithmetic means) 100 for executing arithmetic processing such as series arithmetic at high speed. A volatile rewritable memory (corresponding to a first storage unit) 101 and a nonvolatile read-only memory (corresponding to a second storage unit) 102 internally connected to the signal processing element 100; Processing element 10
0, and a program storage memory (corresponding to a program storage means) 103 for storing a program executed by the signal processing element 100. In the present embodiment, the program stored in the program storage memory 103 is a decoding program for reproducing acoustic information. There are various encoding / decoding methods for acoustic information, and a typical one is NTT.
Tw developed by Human Interface Laboratory
inVQ and MPEG Audio used on the Internet
There are ATRAC used for Layer3 and MD. Even if the same method is used, different programs are required if the sampling frequency and compression rate are different. For this reason, in order to realize an audio information reproducing apparatus capable of general-purpose reproduction of data, a decoding program corresponding to the above-mentioned plurality of methods, sampling frequencies, compression rates, and the like is stored in the program storage memory 103. Each must be remembered. However, even though there are various methods, these decoding programs are not completely different from each other, and commonly include a module for time axis-frequency axis conversion and a data table for arithmetic calculation. In. Therefore, in the digital signal processing device according to one embodiment of the present invention, a module common to the above-described programs and the like (hereinafter, referred to as a common module)
Are stored in the read-only memory 102 in advance, and only non-common modules other than the common module are stored in the program storage memory 103. When one of the plurality of programs is selected, the non-common module corresponding to the program is copied to the rewritable memory 101, and the signal processing element 100
Thus, the common module and the non-common module are read from the read-only memory 102 and the rewritable memory 101, respectively, and are executed.

Hereinafter, the digital signal processing device will be described in detail. In the digital signal processing device, the rewritable memory 101 and the read-only memory 102 are integrated on the same chip as the signal processing element 100. As the signal processing element 100, a processor capable of high-speed operation is used to process acoustic information in real time, and its operation clock is, for example, 50 MHz.
about z. In the digital signal processing device, a Harvard architecture having a program bus and a data bus independently is employed for an internal bus, and the signal processing element 100 has, for example, a program memory space and a data memory space of about 64 k words each. .
The program bus and the data bus include an address bus and a data bus, respectively. As the rewritable memory 101 connected to the internal bus, for example, a dual access RAM or a single access RAM having a capacity of about 32 k words (16 bit width) is used. These can operate at twice or the same speed as the signal processing element 100 at high speed. The read-only memory 10 also connected to the internal bus
For example, a mask ROM having a capacity of, for example, about 16 k words (16 bits width) is used as 2. The common module is stored in the read-only memory 102 in advance. The rewritable memory 101 and the read-only memory 102 are respectively arranged, for example, in the program memory space.

The program storage memory 103 includes:
A non-volatile flash memory or the like is used.
It has a capacity of about 12k words (bit width 16). The program storage memory 103 is connected to the signal processing element 100 via an external bus (not shown) via an external bus. For the externally connected program storage memory 103, the same bus (external bus) is used for both the program memory space and the data memory space. The program storage memory 103 includes the above-described TwinVQ or MPEG Audio Layer 3
, ATRAC, etc., non-common modules other than the above-mentioned common module among a plurality of types of programs respectively corresponding to the sampling frequency, the compression rate, etc. are stored. By storing only the non-common modules in the program storage memory 103, the required capacity of the program storage memory 103 can be reduced as compared with the case where all modules are stored. The overhead for transferring from the program storage memory 103 to the rewritable memory 101 can also be suppressed. Here, FIG. 2 schematically shows a connection configuration between the signal processing element and a program storage memory.
As shown in FIG. 2, the signal processing element 100
In addition to a bit width address bus 104, a 3-bit width selector circuit (corresponding to a selection circuit) 105 is provided. The selector circuit 105 is for controlling the upper 3 bits of the 19-bit address including the address bus 104, and can be constituted by a simple logic circuit, for example. By using the selector circuit 105, the signal processing element 100 can store, for example, 64 k words (1
Access can be easily performed for each continuous area (6 bits wide). Here, FIG. 3 shows an example of the program space of the signal processing element and the memory space of the program storage memory. In the program memory space of the signal processing element 100, the rewritable memory 101 can be arranged in an area excluding a reserved area at the head of 0000h to 7FFFh. Further, as shown in FIG. 3, the read only memory 102 is arranged in C000h to FFFFh. As shown in FIG. 3 , the memory space of the program storage memory 103 composed of 512 k words is divided into blocks each having a continuous area of 64 k words, and the top 0000h,..., Of eight blocks (Block 0,. 7
000h is selected under the control of the selector circuit 105. TwinVQ, MPEG Audio Layer3, ATRAC mentioned above
Non-common modules other than the above-mentioned common modules among a plurality of types of programs corresponding to each method, sampling frequency, compression rate, etc. are stored in each block (Block 0,…, Block 7) according to the type. ing. In FIG. 3, each type of non-common module is indicated by oblique lines.

Next, the operation of the digital signal processing device will be described. First, when a user instructs to reproduce the encoded acoustic information stored in the semiconductor memory using, for example, a switch disposed on a housing of an acoustic information reproducing apparatus, a remote control, or the like, or voice recognition or the like, the digital
A microcomputer provided separately from the signal processing device refers to the header information stored in correspondence with the encoded audio information, and determines the encoding method, sampling frequency, compression rate, and the like of the audio information selected by the user. Is determined. Next, the coding method, sampling frequency,
A control signal including information such as a compression rate is output from the microcomputer to the digital signal processing device. In the digital signal processing device, designation information including a selector signal for designating one of the plurality of non-common modules stored in the program storage memory 103 is generated based on the control signal. Then, an address is set by the selector circuit 105 or the like based on the designation information, and the non-common module stored in, for example, Block0 is copied to the rewritable memory 101. At this time, depending on the capacity of the rewritable memory 101, all of the non-common modules may be copied to the rewritable memory 101, or a part of them may be copied. Even when the capacity of the rewritable memory 101 is smaller than that of the non-common module, a portion not stored in the rewritable memory 101 is also arranged in the program memory space of the signal processing element 100. From the perspective of the signal processing element 100, it does not matter which memory the non-common module is physically located in. However, the operation speed of the flash memory used for the program storage memory 103 is about 10 MHz,
Since it is slower than the signal processing element 100 operating at about 0 MHz, when reading from the program storage memory 103 and executing the non-common module, a portion having a relatively low access frequency is stored in the program storage memory 103. It is preferable to copy the portion having a relatively high access frequency to the rewritable memory 101. As described above, a part of the non-common module that has not been copied to the rewritable memory 101 is also arranged in the program memory space. In addition to eliminating the need for re-reading, the physical constraints on the memory for the program can be relaxed and the burden on the user can be reduced. Then, the signal processing element 100 reads the non-common module and the common module from the rewritable memory 101 (including the program storage memory 103 as necessary) and the read-only memory 102 via its own program memory space. Execute. When the audio signal is decoded as described above and the reproduction is completed,
The portion of the rewritable memory 101 used for storing the non-common module is released and prepared for the next decryption.

As described above, according to the digital signal processing device of the present embodiment, a common module among a plurality of programs stored in the program storage memory is stored in the nonvolatile read-only memory in advance. If any one of the plurality of programs is selected to be executed by the signal processing element, a non-common module other than the common module among modules corresponding to the selected program is replaced with the program. By duplicating from the storage memory to the rewritable memory, the signal processing element reads out the non-common module and the common module from the rewritable memory and the read-only memory, respectively, and executes the program, so that the program is shared Re-reading occurs even when there is It is possible to win. In addition, since the common module is stored in the read-only memory in advance, the overhead of transferring from the program storage memory can be suppressed, the capacity required for the program storage memory can be reduced, and the size of the entire system can be reduced. The scale can be increased. In addition, if all of the non-common modules corresponding to the program are not copied from the program storage memory to the rewritable memory, the non-replicated parts of the non-common module are also stored in the program memory of the signal processing element. The arrangement in the space eliminates the need to re-read the non-replicated part of the non-common module into the rewritable memory, and also alleviates the physical constraints on the memory for the program and reduces the burden on the user. Can be.
Further, since the rewritable memory and the read-only memory are internally connected to the signal processing element, the circuit can be simplified and downsized, and the speed can be easily increased by using a bus structure. Further, the plurality of programs are stored in different continuous areas of the program storage memory, respectively, and the signal processing element stores the programs in the program storage memory using a selector circuit for selecting the continuous area. In order to select any one of the plurality of programs, any one of the plurality of programs can be easily selected by, for example, a simple logic circuit.

[0011]

In the above embodiment, the present invention is applied to an audio signal reproducing apparatus for reproducing an audio signal. However, the present invention is not limited to this, and may be applied to an apparatus for processing another digital signal such as a video signal. Is also possible. In the above embodiment, all of the rewritable memory and the read-only memory are mounted on-chip. However, the present invention is not limited to this, and a part of the rewritable memory or the read-only memory is connected to an external bus. An external memory may be used. Such a digital signal processing device is also an example of the digital signal processing device of the present invention. In the above embodiment, the program storage memory 10 is used.
3, only the non-common modules are stored, but if the capacity of the program storage memory 103 is relatively large, the common modules may be stored. Such a digital signal processing device is also an example of the digital signal processing device of the present invention.

[0012]

As described above, according to the digital signal processing apparatus of any one of claims 1 to 6, a common module among a plurality of programs stored in the program storage means is stored in a nonvolatile manner in advance. If any one of the plurality of programs is selected to be executed by the arithmetic means, it is stored in the second storage means, and among the modules corresponding to the selected program, A non-common module other than a common module is copied from the program storage means to a rewritable volatile first storage means, and an arithmetic means reads the non-common module from the first storage means and the second storage means. By reading out the common module and executing the program, the program can be read even if there is a common part between multiple programs. The occurrence of redelivery can be suppressed. Further, since the common module is stored in the second storage means in advance, overhead transferred from the program storage means can be suppressed, the capacity required for the program storage means can be reduced, and the size of the entire system can be reduced. The scale can be increased. Moreover, the upper SL when all the program storage means of non-common module corresponding to the program in the first storage means is not replicated, the non-common module also program the operation means duplicated not part of the Since it is arranged in the memory space, it is not necessary to re-read the non-replicated part of the non-common module into the first storage means, relax the physical constraints on the memory for the program, and reduce the burden on the user. Can be reduced. Further, according to the digital signal processing device of the second aspect , the non-common module is copied to the volatile first storage means having a high access frequency from a high access frequency. Be faster. Further, according to the digital signal processing device of the third aspect , since one or both of the first storage means and the second storage means are internally connected to the arithmetic means, the circuit is simplified. The size and size are reduced, and it is easy to increase the speed with the bus configuration. Further, according to the digital signal processing device of the fourth and fifth aspects, the plurality of programs are stored in different continuous areas of the program storage means, respectively, and the arithmetic means selects the continuous area. For example, in order to select one of the plurality of programs stored in the program storage means by using a selection circuit for selecting a plurality of programs, a simple logic circuit or the like representing a predetermined number of bits of information is used. Can be easily selected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing a connection configuration between a signal processing element and a program storage memory in the digital signal processing device.

FIG. 3 is a diagram showing an example of a memory space of the signal processing element and a program storage memory.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 signal processing element 101 rewritable memory 102 read-only memory 103 program storage memory 105 selector circuit

Continued on the front page (72) Inventor Tetsuya Takahashi 1-5-5 Takatsukadai, Nishi-ku, Kobe City, Hyogo Prefecture Inside Kobe Steel, Ltd. Kobe Research Institute (72) Inventor Yoshiro Nishimoto 1 Takatsukadai, Nishi-ku, Kobe City, Hyogo Prefecture Kobe Steel, Ltd. Kobe Steel, Ltd. Kobe Research Institute (56) References JP-A-9-179740 (JP, A) JP-A-5-2472 (JP, A) JP-A-1-112423 ( JP, A) JP-A-7-271603 (JP, A) JP-A-4-217078 (JP, A) JP-A-5-128280 (JP, A) JP-A-61-165151 (JP, A) JP JP-A 64-59548 (JP, A) JP-A 8-185386 (JP, A) JP-A 8-123728 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9 / 06

Claims (6)

(57) [Claims] An information processing apparatus comprising: an arithmetic means; and a non-volatile program storage means for storing a program executed by the arithmetic means. When a plurality of different programs are stored in the program storage means, In the digital signal processing device in which the arithmetic means selects and executes any one of a plurality of programs stored in the program storage means to process a digital signal, a rewritable volatile first A storage means, and a non-volatile, read-only second storage means which pre-stores a common module among the plurality of programs among modules constituting each program; If any one of them is selected to be executed by the arithmetic means, it is stored in the program storage means. All or some of the non-common modules other than the common module among the modules corresponding to the program are copied from the program storage means to the first storage means, and the calculation means causes the common module and the non- Common mode
The program memory space of the arithmetic means in which the module is arranged
Via the space, the first storage means and the second storage means
Steps and all of the non-common modules are in the first
If it is not copied to the storage means,
A digital signal processing apparatus characterized by reading out the non-common module and the common module from a storage unit and executing the program. Wherein the said program storage means, the digital signal processing apparatus according to claim 1 comprising replicating in said first memory means to the non-common module from the highest its access frequency. 3. The digital signal processing device according to claim 1, wherein one or both of said first storage means and said second storage means are internally connected to said arithmetic means. 4. The plurality of programs are stored in different continuous areas of the program storage means, respectively.
4. The method according to claim 1, wherein said calculating means selects one of a plurality of programs stored in said program storage means using a selection circuit for selecting said continuous area.
4. The digital signal processing device according to any one of 3 . 5. The digital signal processing device according to claim 4 , wherein said selection circuit specifies each address of a different continuous area of said program storage means by a predetermined number of bit information. 6. A digital signal processing apparatus according to any one of claims 1 to 5, which is a program for the plurality of program reproducing digital audio signals.