JP3273080B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device used for a video camera or the like.

[0002]

2. Description of the Related Art Conventional solid-state imaging devices are roughly classified into two types: a MOS (Metal Oxide Semiconductor) type and a CCD (Charge Coupled Device) type. MOS type has a lot of fixed pattern noise,
The CCD type is the mainstream. Since this CCD type solid-state imaging device can be easily miniaturized, an interline system is often used.

FIG. 14 shows a cross-sectional structure of an interline CCD solid-state imaging device. This interline CCD solid-state imaging device is composed of an N-type silicon substrate 1
The well 102, the P ^{- -} P provided on the upper side of the 01 wells 102, photodiode 103, 103 is a photoelectric conversion section provided at a predetermined distance from each other, ... and,
A vertical transfer section 104 provided in the P ^- well 102 between the adjacent photodiodes 103, 103, and a P ⁺ pixel separation region 105 provided to separate the vertical transfer section 104 and the photodiode 103 from each other. Equipped, the above N
An insulating film 106 provided on the silicon substrate 101;
A gate electrode 107 covering the vertical transfer portion 104;
08, a light shielding metal 109 provided on the light shielding metal 108, the insulating film 106 and the light shielding metals 108, 1
09, a color filter 111 disposed above the photodiode 103 in the transparent resin 110, and a color filter 1 on the transparent resin 110.
Micro lens 112 arranged corresponding to 11
And Note that a vertical transfer pulse φV is input to the gate electrode 107. Further, in order to extract excessive charges generated in the photodiode 103, a vertical overflow drain for applying a positive potential V _OFD is provided on the N-type silicon substrate 101 to prevent blooming.

In the above-described CCD type solid-state imaging device of the interline system, one row of photodiodes 1 for performing photoelectric conversion is used.
03, a configuration having one column of vertical transfer units 104 is provided. Then, when the incident light forms an image on the photodiode 103 through the microlens 112 and the color filter 111, the photodiode 1 is changed according to the intensity of the incident light.
An electric charge is induced in 03 and accumulated.

[0005] Then, as shown in the schematic diagrams of FIGS. 15A to 15C, when the format corresponds to a normal TV signal,
As shown in FIG. 15A, the electric charge (indicated by a black circle) accumulated in the photodiodes 103 arranged in a grid pattern is displayed once every 1/60 second in a vertical direction provided in parallel with the photodiodes 103. The data is transferred to the transfer unit 104. The charge of the vertical transfer unit 104 is 1 / f _H cycle (f _H : horizontal synchronization frequency)
Then, the data is sequentially transferred to the horizontal transfer unit 122. In fact, TV
Since the signals are of the interlaced scanning type, after the charges of the odd-numbered rows and the charges of the even-numbered rows of the photodiode 103 are combined (after simultaneous reading of two lines), as shown in FIG. Transfer to And FIG.
(c), the charge transferred to the horizontal transfer unit 122 transfers with IH (1 / f _H) period to the output unit (not shown). At this time, the charge of one pixel is read out by 1/606.
Performed at _fH cycle. In addition, the CC of the above interline system
In the D-type solid-state imaging device, field accumulation is performed in which the signal accumulation period of each pixel is one field period (1/60 second), but there is another frame accumulation in which one frame period (1/30 second) is used. .

The configuration of the transfer drive pulse at this time will be described below.

FIG. 16 shows the above-mentioned interline CCD.
FIG. 2 is an enlarged plan view of the vicinity of an (n, 1) pixel of the solid-state imaging device, and a horizontal transfer unit 127 is provided at one end of a vertical transfer unit 104 corresponding to the photodiodes 103 in one column. The vertical transfer unit 104 and the horizontal transfer unit 12
Forming an electrode 128 of the transfer gate signal TG ₁ is input between the 7. The above photodiode 1
In the region between the rows 03, four electrodes extending in parallel with the horizontal transfer unit 127 are formed.
Vertical drive pulses φV ₂ , φV ₁ , φV ₄ , φV ₃
Is applied. Further, the horizontal transfer unit 127 on the extension line of the vertical transfer unit 104, to form an electrode the horizontal drive pulse H ₁ is input, the horizontal drive pulse H to the right side of the electrode
₁ forms another electrode to which the input is made. Moreover, forming two electrodes horizontal drive pulse H ₂ are inputted in order to the right of the electrodes. That is, two electrodes and the horizontal the horizontal drive pulse H ₁ is input drive pulse H ₂
Are alternately arranged on the horizontal transfer unit 127. Then, the vertical drive pulse φV ₂ , φ
The charges of the vertical transfer unit 104 are vertically transferred to the horizontal transfer unit 127 by V ₁ , φV ₄ , and φV _{3, and} the charges transferred to the horizontal transfer unit 127 are horizontally transferred by horizontal drive pulses H ₁ and H ₂ , It is output to an output unit (not shown).

[0008]

By the way, in the above-described CCD type solid-state imaging device of the interline system, the signal charge of the photodiode 103 becomes small in the high-speed electronic shutter mode, and the ratio of smear charge becomes large.
Smear increases. Further, the dark current of the photodiode 103 increases at a high temperature, the charge accumulation time of the vertical transfer unit 104 increases at a low transfer rate, and the dark current increases. Ratio) worsens.
Further, there is a problem that only one image can be stored in the vertical transfer unit 104, and high-speed continuous imaging cannot be performed. Further, in the case of the interlaced scanning method for frame accumulation, since the information of the charges of the odd-numbered rows and the even-numbered rows of the photodiode 103 is added, there is a problem that the resolution is deteriorated when an object moving at a high speed is imaged.

An object of the present invention is to provide a solid-state imaging device which has good smear characteristics even in a high-speed electronic shutter mode, does not degrade S / N at high temperatures or low transfer rates, and can perform high-speed continuous imaging. is there.

[0010]

According to a first aspect of the present invention, there is provided a solid-state imaging device comprising: a plurality of photoelectric conversion element rows each including a plurality of photoelectric conversion elements; A plurality of sets of vertical transfer units are provided on both sides, each of which is provided in a row, and are coupled to all the photoelectric conversion elements of the corresponding photoelectric conversion element row via a readout gate section. Transfer control means for independently controlling each of the read gate sections provided to transfer the electric charges of the photoelectric conversion element rows to a pair of the vertical transfer sections on both sides of the photoelectric conversion element rows; And a horizontal transfer unit for sequentially transferring charges sequentially output from the plurality of sets of vertical transfer units in the horizontal direction. Further, from each of the above photoelectric conversion element rows,
Charge transfer timing to a pair of vertical transfer units on both sides
Are different on one side and the other
Signal charge and noise are stored in one of the vertical transfer units.
The first charge including the noise charge is transferred to the other vertical transfer unit.
Transfer the second charge composed of the noise charge
The feature is that the charge transfer timing is controlled.
You.

[0011]

According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the horizontal transfer unit includes:
The first charge and the second charge sequentially output from the plurality of sets of vertical transfer units are independently transferred.

According to a third aspect of the present invention, in the solid-state imaging device according to the second aspect, the horizontal transfer unit transfers the first charge output from the one vertical transfer unit.
It has a two-row configuration including a horizontal transfer unit and a second horizontal transfer unit that transfers the second charge output from the other vertical transfer unit.

According to a fourth aspect of the present invention, there is provided a solid-state imaging device comprising: a plurality of photoelectric conversion element rows each including a plurality of photoelectric conversion elements; and a plurality of rows each provided on both sides of each of the photoelectric conversion element rows. The vertical transfer units in one column are respectively coupled to all the photoelectric conversion elements of the corresponding photoelectric conversion element column via the readout gate unit, and the vertical transfer units in the second and subsequent columns are respectively adjacent to the vertical transfer units. A plurality of sets of vertical transfer units coupled via a transfer gate unit, and the readout gate unit and the transfer gate unit are controlled to transfer the charges sequentially output from each photoelectric conversion element column, respectively, to the photoelectric conversion element column. Transfer control means for transferring the signals to the vertical transfer units in the plurality of columns on both sides; and sequentially transferring only the charges sequentially output from the selected vertical transfer unit of the plurality of sets of the vertical transfer units in the horizontal direction. It is characterized in that a flat transfer section. Furthermore, from each photoelectric conversion element row,
The charge transfer timing to the pair of vertical transfer units
By making them different on the other side,
One vertical transfer section contains signal charges and noise charges.
The first charge is transferred and the other vertical transfer
The charge transfer tag is transferred so that a second charge composed of charges is transferred.
It is characterized by controlling the imaging.

[0015]

[0016]

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[0020]

[0021]

[0022]

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[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the solid-state imaging device of the present invention will be described in detail with reference to embodiments.

(First Embodiment) FIG. 1 is a sectional view of a solid-state imaging device according to a first embodiment of the present invention. In this structure, P-type
^A well 2 is provided, a photodiode 3 which is a photoelectric conversion unit, and a vertical transfer unit 4a (hereinafter, referred to as an A register)
And a vertical transfer unit 4b (hereinafter referred to as a B register), a P ⁺ pixel separation region 5 for separating each pixel, an insulating film 6, a gate electrode 7, light-shielding metals 8, 9, a color filter 10, and a micro lens 11. To prevent blooming
A vertical overflow drain for applying a positive potential V _OFD is provided on the substrate in order to extract excess charges generated in the photodiode 3. According to the present invention, one row of photodiodes 3,... Are used as photoelectric conversion elements, and two charge transfer sections of an A register and a B register are used as vertical transfer sections to transfer charges generated in the photodiodes 3,. There is a configuration. Also, a vertical transfer pulse of the vertical transfer unit (also serves as a transfer pulse in this embodiment).
_Are two systems, φ _VA and φ _VB , respectively, A register and B
It is applied to a gate electrode 7 as a transfer means of a register. The vertical transfer pulse preferably has 2 to 4 phases. In the above structure, the color filter is generally used when a color image is to be obtained, and therefore need not be provided when a black and white image is to be obtained.

First, an operation state of the frame accumulation and the interlaced scanning method (simultaneous reading of two lines) will be described.

Once in one frame (two fields), the charges induced and accumulated according to the intensity of the light incident on the photoelectric conversion unit are read into the vertical transfer unit. The odd-numbered rows are transferred to the A-register and the even-numbered rows are simultaneously transferred to the B-register. The information of the A-register is read in the odd-numbered field, and the information of the B-register is read in the even-numbered field. As a result, even if an object moving at a high speed is imaged, a high-resolution image without blur can be obtained.

Next, an embodiment of the present invention in the high-speed electronic shutter mode in the case of field accumulation in the solid-state imaging device having the above structure will be described. Normally, the shutter time in the electronic shutter mode is 1/1500
It is about 0 seconds, and the charge reading pulse width is about 2 μs.

During the vertical blanking period, the charge generated by the photodiode is read into the A register. When the reading is completed, the charge generated by the photodiode is read into the B register, and the A register and the B register are synchronized. The data is vertically transferred, and sequentially transferred to the horizontal transfer unit. The charge transferred from each register (the A register and the B register) to the horizontal transfer unit is composed of the charge read into each register, the smear charge, and the vertical transfer unit dark current. Therefore, when subtraction is performed between the same row of the A register and the B register, information of each pixel in which smear has been canceled can be obtained. As a result, in the high-speed electronic shutter mode, a good image with almost no smear is obtained, and the smear is about 40 dB.
Be improved. In this embodiment, the field accumulation,
In the case of two-line simultaneous reading, simultaneous reading of all pixels in the high-speed electronic shutter mode and non-interlaced scanning are also possible.

Since the information of the optical black portion of the B register in the high-speed electronic shutter mode is information of only the dark current with almost no smear, the information is subtracted between the same row of the A register and the B register of the optical black portion. Thus, the dark current of the effective pixel can be canceled. As a result, it is particularly effective in high-temperature operation where dark current is a problem.

Hereinafter, an embodiment of the present invention will be described in which the oblique spot light is incident on the optical black portion in the solid-state imaging device having the above configuration.

In the optical black part, a dummy A register as a vertical transfer part for the optical black part and B
A register is arranged, the magnitudes of the electric charges of the A register and the B register transferred by the gate electrode as the transfer means for the optical black portion are compared, and from the odd field,
By reading out the charges of the register on the side determined to have a small charge amount from the horizontal transfer unit, an image less affected by the oblique spot light can be obtained in a 1/20 second cycle. 1/20
The second is a time of three fields until the read signal of the third field is completed because one field of a normal TV signal is 1/60 second.

(Second Embodiment) FIG. 2 is a plan view of a solid-state imaging device according to a second embodiment of the present invention, in which two vertical transfer units and one horizontal line transfer unit are used. Reference numeral 21 denotes a plurality of photodiodes as photoelectric conversion elements arranged in a grid pattern, and reference numeral 22 denotes a vertical transfer unit (hereinafter referred to as an A register) provided on one side in parallel with each row of the plurality of photodiodes 21. ) And 23 are vertical transfer units (hereinafter referred to as B registers) provided in line symmetry with the A register with respect to one row of the photodiodes 21, and 24 is connected to one end of the A register and the B register. Horizontal transfer unit. The horizontal transfer unit 24
Are provided with dummy bits 26 which are charge transfer regions. The horizontal transfer section 24 has twice as many charge transfer areas as the sum of the number of pixels in the horizontal direction and the number of dummy bits. On both sides of the area of the A register, the B register and the photodiode 21, an optical black section 25 is provided which is parallel to the A register and the B register and has one end connected to the horizontal transfer section 24. The plurality of photodiodes 21 are (1, 1) to (512,
492), that is, a configuration of 512 columns and 492 rows.

In the solid-state imaging device having the above-described configuration, when the signal accumulation period is the frame accumulation of one field period (1/60 second) and the interlace scanning method is used, the charges of the odd-numbered rows of the photodiode 21 are read into the A register, and The charge of the even-numbered rows of the diode 21 is read into the B register. Then, in the odd field of the TV signal, only the electric charge of the A register is vertically transferred to the horizontal transfer unit 24. In the horizontal transfer unit 24, the transfer to the output unit (not shown) is completed in a 1H cycle. Normally, the reading of one pixel by the horizontal transfer unit 24 is performed at a period of 1/606 f _H (f _H is a horizontal synchronization frequency). In this case, the charge of the horizontal transfer unit 24 is twice the number of pixels in the horizontal direction. Since it has a transfer area,
The readout of one pixel 12f _H period. On the other hand, in the even field of the TV signal, only the charge of the B register is vertically transferred to the horizontal transfer unit 24. Thereafter, the transfer to the output section is completed in a 1H cycle as in the case of the odd field. As described above, in a solid-state imaging device having two vertical transfer units and a single-line horizontal transfer unit, the electric charges of the A register and the B register are output via one horizontal transfer unit 24. Therefore, since the charge information of the odd-numbered rows and the even-numbered rows of the photodiode 21 is not added, even if an object moving at a high speed is imaged, a high-resolution image without blur can be obtained.

Further, in the solid-state imaging device having the above configuration,
In the case where the pixel signal accumulation is the field accumulation and the high-speed electronic shutter mode, a method of canceling noise charges using the A register and the B register will be described below.

FIG. 3 shows the timing of reading the charge of the photodiode 21 into the A register and the B register. First, the electric charge accumulated in the photodiode 21 is extracted to the overflow drain at a period of 1H. For example, the 1H cycle at the time of about 1/15000 second of the electronic shutter is 1H = 1 / fH = 1 / 15.734 KHz. The charge is read from the photodiode 21 into the A register and the B register once every 1/60 second. Since the A register is read immediately before the electric charge is extracted to the overflow drain, E _I × 15000
The signal charge of (E _I : the amount of charge accumulated in one photodiode 21 per second) is read. Then, the electric charge is extracted by the overflow drain, and the electric charge is read from the photodiode 21 to the B register after about 2 μs. This B
The signal charge read into the register has an accumulation period of about 2μ.
Since it is s, it becomes E _I × 1/500000. Also, smear charge and A register, B register
The charge due to the dark current of the register is added to each signal charge. The smear charge and the charge due to the dark current of the A register and the B register are indicated by a dashed line Es. Although the smear charge and the charge due to the dark current of the A and B registers are shown by straight lines for simplicity, the A and B registers, which are the vertical transfer units, depend on the amount of light received during transfer. It rapidly increases at the spot light of the register and the B register. However, the smear charge and the charge due to the dark current of the A and B registers depend on time,
Since the A register and the B register are arranged symmetrically with respect to the photodiodes 21 in one row, if the charges of the A register and the B register are simultaneously transferred to different positions of the horizontal transfer unit, the signal charge and the noise are reduced. The output can be separated into electric charges of the sum of electric charges and noise electric charges. That is, after the charge is transferred from the photodiode 21 to the A register and the B register, the A register and the B register are vertically transferred in synchronization with each other and transferred to the horizontal transfer unit 24. The charges transferred to the horizontal transfer unit 24 are output from the horizontal transfer unit 24 in the order of dummy bits, optical black units, A ₁ , B ₁ , A ₂ , B ₂ ,. Note that the A _1, A _2, ... is the signal charge and the noise charges are vertically transferred from the A register, B _1, B _2, ... is a vertical transfer noise charges from each B register. Since these two noise charges are substantially equal, the noise charges can be canceled by separating the noise charges from the horizontal transfer unit and then subtracting the noise charges from the sum of the signal charges and the noise charges. The B register contains:
In addition to the noise charge, a signal charge of about E _I × 1/500000 is included. Even if the signal charge is canceled, the absolute value of the original signal charge is hardly affected.

As described above, since the noise charge can be removed by using the A register and the B register, a solid-state imaging device having a good smear characteristic and a low S / N with reduced dark noise is realized. be able to.

When noise charges are canceled by using an optical black portion or a dummy portion in addition to the above-described method for canceling the noise charges, the dark current of the photodiode 21 can be corrected, and the operation can be performed during high-temperature operation. Even if the dark noise increases, the dark noise can be removed, so that a solid-state imaging device with a good S / N can be realized.

Further, in imaging at a low transfer rate, even if the charge accumulation time of the A register and the B register becomes long and the charge due to the dark current of the A register and the B register increases, as described above, Noise charge including the charge due to the noise can be canceled. Therefore, even in imaging at a low transfer rate, deterioration of S / N can be prevented.

(Third Embodiment) FIG. 4 is a plan view of a solid-state imaging device according to a third embodiment of the present invention, showing a configuration in which two vertical transfer units and two horizontal transfer units are used.

This solid-state imaging device has another horizontal transfer unit provided in the configuration of the solid-state imaging device of the second embodiment, and the same components are denoted by the same reference numerals. A horizontal transfer unit 27 is provided in parallel with the horizontal transfer unit 24 and on the side opposite to the vertical transfer units 22 and 23 with respect to the horizontal transfer unit 24. Both ends of the horizontal transfer unit 27 have dummy bits 28
Is provided.

In the solid-state imaging device, when the pixel signal accumulation is frame accumulation and the TV signal is of the interlaced scanning type, first, the charges of the odd rows of the photodiode 21 are read into the A register, and the charges of the even rows of the photodiode 21 are read. The charge is read into the B register. Then, in the odd field of the TV signal, only the information of the A register is transferred to the horizontal transfer unit 24, and the transfer to the output unit (not shown) is completed in the horizontal transfer units 24 and 27 in one frame cycle. Reading of one pixel by the horizontal transfer units 24 and 27 is 1/60
Performed in 6f _H period, the transfer clock to 606 f _H level. On the other hand, in the even field of the TV signal, only the information of the B register is transferred to the horizontal transfer unit 27, and thereafter, the transfer to the output unit is completed in one frame cycle as in the case of the odd field. As described above, in a solid-state imaging device having two vertical transfer units and a two-line horizontal transfer unit, the charge of the A register is output through the horizontal transfer unit 24 and the charge of the B register is output through the horizontal transfer unit 27. Output via

When the signal accumulation of the pixel is the field accumulation and the high-speed electronic shutter mode, the charge is transferred from the photodiode 21 to the A register and the B register, and then the A register and the B register are vertically transferred synchronously. ,
The charge from the A register is transferred to the horizontal transfer unit 24, while the charge from the B register is transferred to the horizontal transfer unit 27. The charges transferred to the horizontal transfer unit 24 are horizontally transferred and output in the order of a dummy bit, an optical black unit, A ₁ , A ₂ ,. On the other hand, the electric charge transferred to the horizontal transfer unit 27 includes a dummy bit, an optical black
Horizontally transfer in the order of ₁ , B ₂ ,. Note that the horizontal transfer unit 24 and the horizontal transfer unit 7 output in synchronization. Also, the A _1, A _2, ... is a vertical transferred charges from the A register, B _1, B _2, ... is a vertical transferred charges from the B register.

A method of transferring electric charges from the A register and the B register to the horizontal transfer units 24 and 27 and a method of horizontally transferring the electric charge of the A register and the electric charge of the B register in synchronization will be described below.

FIG. 5 shows the photodiode 21 in the n-th column.
Corresponding A _n registers, B _n registers and horizontal transfer unit 24,
Shows a 27 fragmentary plan view of, on the region between the A _n register and B _n registers and horizontal transfer section 24 extends parallel to the horizontal transfer unit 24, the transfer gate signal TG ₁ is input An electrode 31 is provided. Further, on the area between the horizontal transfer unit 27 and the horizontal transfer unit 24, it is provided electrodes 32 transfer gate signal TG ₂ is input.
The horizontal transfer unit 24 on the extension of the _An register
27 areas A _x, the electrode 33 is formed on A _x, region B _x of the horizontal transfer section 24 and 27 of the extension of the B _n registers, to form an electrode 34 on the B _x. On the other hand, the horizontal transfer units 24 and 2
The electrode 35 in which boron is implanted is formed on the regions A _y , A _y between the regions A _x , A _x and the regions B _x , B _x . Forming a region B _y, electrodes 36 are implanted with boron on B _y between the region _{A x + 1, A x +} 1 and the area B _x, B _x in the horizontal transfer unit 24, 27. Then, enter the horizontal drive pulse H ₁ to the electrode 33 and the electrode 35, and enter the horizontal drive pulse H ₂ in the electrode 34 and the electrode 36, the area A _x, A _x and area A _y, A _y
And with a potential gradient for two-phase driving in and between the regions B _x, B _x and the area B _y, B _y and. Further, the horizontal transfer unit 24 under the transfer gate signal TG ₂ of the electrode 32,
27 areas A _x, is between A _x, to form a channel stopper 30 shown in FIG. 6 (a), this region A _x, separating the A _x. On the other hand, the electrode 3 of the transfer gate signal TG ₂
As shown in FIG. 6 (b), no channel stopper is formed between the areas B _x , B _x of the horizontal transfer sections 24, 27 below
It connects the region B _x area B _x and the horizontal transfer unit 27 of the horizontal transfer unit 24.

Then, as shown in FIGS. 5 and 7, when the transfer gate signal TG ₁ is set to the H level for a predetermined period T ₁ , the charges in the _An register and the _Bn register are transferred to the area of the horizontal transfer section 24. Transfer to A _x and B _x respectively. Next, when the transfer gate signal TG ₁ becomes L level, the transfer gate signal TG ₂ becomes H level, the horizontal drive pulse H _1, H ₂ after a predetermined period to the L level.
When the horizontal drive pulse H _1, H ₂ becomes L level, the horizontal transfer unit the charge area B _x of the horizontal transfer unit 24 27
Transfer to At this time, the charge of the region A _x is for channel stopper 30 under the transfer gate signal TG ₂ of the electrode 32, not transferred to the horizontal transfer unit 27. Next, after the horizontal drive pulses H ₁ and H ₂ are at L level during the period T ₂ , the horizontal drive pulse H ₁ is at H level. When the horizontal drive pulse H ₁ becomes H level during the period T _3,
The electric charge under the electrode 32 of the transfer gate signal TG _{2 in} the area B _x is horizontally transferred to the position of the area A _{x in} the horizontal transfer unit 27. The transfer gate signal TG ₂ during this period T ₃
To the L level, the horizontal transfer unit 24 and the horizontal transfer unit 27 are separated. Then, after the period T ₃ , the clocks of the horizontal drive pulses H ₁ and H ₂ start, and the charges from the _An register in the area A _x of the horizontal transfer unit 24 and the B _{n in} the area A _x of the horizontal transfer unit 27 The charge from the register is
Horizontal transfer to the position of the area A _x-1 is performed in one cycle of the clock.
The horizontal transfer is repeated during the period T _4, and outputs all the charges in the horizontal transfer unit 24, 27.

[0065] In this manner, the A _n registers, because it simultaneously output charge from B _n register and separated by the horizontal transfer unit 24 and 27, it is possible to increase the transfer rate, can cope with high-speed imaging.

(Fourth Embodiment) FIG. 8 is a plan view of a solid-state image pickup device according to a fourth embodiment of the present invention. Reference numeral 51 denotes a plurality of photodiodes as photoelectric conversion elements arranged in a grid pattern. , 52 are four vertical transfer units provided in parallel for each column of the plurality of photodiodes 51, and 53 is a plurality of photodiodes 51.
The four vertical transfer units 54 are provided line-symmetrically with the vertical transfer unit 52 for one column. One end of the vertical transfer unit 52 and one end of the vertical transfer unit 53 is connected via a dummy vertical register 60 as a shift register. The horizontal transfer unit is connected to the horizontal transfer unit. On both sides of the region of the plurality of photodiodes 51, the vertical transfer units 52 and the vertical transfer units 53, optical black units 55 parallel to the vertical transfer units 52 and the vertical transfer units 53 and having one end connected to a horizontal transfer unit 54 are provided. Provided. Also,
Dummy bits 56 are provided at both ends of the horizontal transfer unit 54. The plurality of photodiodes 51 are 49
8 has only two columns of photodiodes 51 in the n-th column and the (n + 1) -th column, and only vertical transfer units 52 and 53 corresponding to the photodiodes 51 in the two columns. ing. The vertical transfer unit 52 is A ₁ column in order from the photodiode 51 side, A ₂ columns, A ₃ rows, constituted by vertical registers A _4-row, vertical transfer unit 53 B ₁ row in order from the photodiode 51 side, B It is composed of vertical registers of ₂ columns, ₃ columns, and ₄ columns. Further, the horizontal transfer section 54 has a charge transfer area twice as large as the sum of the number of pixels in the horizontal direction and the number of dummy bits.

The vertical transfer of the vertical transfer units 52 and 53 is four-phase drive. This is because, in the interlaced scanning method, charges of two pixels in an odd-numbered row and an even-numbered row are added. That is, in the odd field of the TV signal, addition is performed as (n, 1) + (n, 2), (n, 3) + (n, 4),.
In the even field of the TV signal, (n, 1), (n, 2) + (n, 3),
Four-phase driving is used to perform addition as (n, 4) + (n, 5),.

[0068] Figure 9 is an enlarged plan view of the vicinity of the pixel of the solid-state imaging device (n, 1), is formed along the top vertical transfer unit 52 to the A ₁ line to A ₄ columns of the vertical transfer unit 52 Electrodes
The vertical drive pulse _{1AφV 3, 2AφV 3, 3AφV 3} , 4Aφ
The V ₃ to each input, the electrodes formed along the top vertical transfer unit 53 to the B ₁ row .about.B ₄ columns of the vertical transfer unit 53, vertical driving pulses _{1BφV 3, 2BφV 3, 3BφV 3} , 4BφV 3
Are entered. A of the vertical transfer unit 52
_The signal V _G2A is applied to the electrodes formed in the area between the _first row and the _second row.
Type and inputs the signal V _G3A the electrode formed in a region between the _two rows and A ₃ rows A vertical transfer unit 52, the vertical transfer unit 5
The electrode formed in a region between the two A ₃ columns and A ₄ columns are entering signal V _G4A. On the other hand, B _{1 of the} vertical transfer unit 53
Enter the signal V _G2B to electrodes formed in a region between the column and the B ₂ rows, the signal V _G3B the electrode formed in a region between the _two rows and B ₃ rows B of the vertical transfer portion 53 Input and the vertical transfer unit 53
Signal V to the electrode formed in a region between the B ₃ columns and B ₄ columns
_G4B is being entered. Then, the photodiode 5
Four electrodes extending in parallel with the horizontal transfer unit 54 are formed in a region between one row. The four electrodes are provided with vertical drive pulses φV ₂ , φV ₁ , φV ₄ , φV in order from the horizontal transfer unit 54 side.
_You have entered ₃ .

The dummy vertical register 60 includes columns A _{1 to} A ₄ of each vertical transfer section 52 (or vertical transfer section 53).
(The _first column B1 to the _fourth column B4) of the horizontal transfer unit 54 side and four first registers 61 connected to the lowermost end thereof, and one second register 62 connected to the four first registers 61. Have been. Also between the first register 61 lowermost and the four A ₁ row to A ₄ rows of the vertical transfer unit 52 (or the B ₁ row .about.B ₄ columns of the vertical transfer portion 53), and the horizontal transfer unit 54 Four electrodes extending in parallel are formed, and the vertical drive pulses φV ₂ , φV ₁ , φV ₄ ,.
φV ₃ is input. Also, four electrodes extending in parallel with the horizontal transfer unit 54 are formed between the first register 61 and the second register 62, and the four electrodes are sequentially supplied to the four electrodes from the horizontal transfer unit 54 side. ₂ , φV ₁ , φV ₄ ,
φV _D3 is input. In a region between the dummy vertical register 60 and horizontal transfer unit 54 forms an electrode transfer gate signal TG ₁ is input (not shown). The second register 62 on the horizontal transfer unit 54 side
Two electrodes extending in parallel with the horizontal transfer unit 54 are formed thereon, and vertical drive pulses φV ₄ odd and φV _D3 are sequentially input to the two electrodes from the horizontal transfer unit 54 side.

FIG. 10 is a timing chart of the vertical transfer in FIG. 9, and the transfer operation will be described below.

First, at time t ₁ , the vertical drive pulses φV ₁ , φV ₂ , φV ₄ , 1AφV ₃ , 2AφV ₃ , 3AφV ₃ , 4
AφV ₃ and signals V _G2A , V _G3A , and V _G4A are all set to L level. Then, at the next time t ₂ , the vertical drive pulse 1Aφ
_{V 3, 2AφV 3, 3AφV 3} , the 4EifaiV ₃ to H level. Next, the signal V _G2A at time t _3, V _G3A, the V _G4A to H level. The vertical drive pulse 1AφV ₃ is H
Becomes higher voltage level than the level, transfers the vertical drive pulse 1EifaiV ₃ again at a time t ₅ when H level, the charge of the photodiode 51 to the A ₁ line of the vertical transfer unit 52.

Next, at time t ₇ , the vertical drive pulse 1Aφ
When V _{3 is set} to L level and the signal V _G2A is set to L level at time t ₈ , the charge of the column A ₁ of the vertical transfer unit 52 is transferred to the column A ₂ of the vertical transfer unit 52, and the charge of the photodiode 51 is transferred. transferred to the a ₁ line of the vertical transfer unit 52. Then, the vertical drive pulse 1AφV ₃ is set to the H level again. Next,
Similar to the vertical drive pulse 1Eifai ₃ and signal V _2G2, to L level vertical drive pulses 2EifaiV ₃ and signal V _G3A out of phase, then the vertical drive pulses 3EifaiV ₃ and signal V
_G4A is shifted to the L level by shifting the phase. And time t
In _12, it transfers the first charge transfer to A ₁ row of vertical transfer section 52 A ₂ rows, through the A ₃ rows in A ₄ columns.

Next, the vertical drive pulse 4AφV _{3 is set} to L level, and the vertical drive pulse φV ₄ is changed from L level to H level for a predetermined period. When the vertical drive pulse φV ₄ becomes L level again, the vertical drive pulse φV ₁
To the H level. Then, the vertical drive pulse φV ₁
After a predetermined period of time after the signal is set to the H level, the vertical drive pulse φV _{2 is set} to the H level. Then, vertically the vertical drive pulses .phi.V ₂ by the vertical drive pulses .phi.V ₁ after the H level for every predetermined period to the L level, the vertical drive pulses 4EifaiV ₃ after a predetermined time period in the H level, after a predetermined period of time The drive pulse φV _{2 is set} to L level. Then, after a predetermined period, the vertical drive pulse 4AφV _{3 is set} to the L level again, and one vertical transfer is completed. Then, the vertical drive pulse φV ₄ is again changed from the L level to the H level for a predetermined period, and the above operation is repeated in a 1H cycle to output charges to the horizontal transfer unit 54. At this time, the vertical drive pulse 1Aφ
By holding V ₃ , 2AφV ₃ , and 3AφV ₃ at the H level, the electric charges in the A ₁ , A ₂ , and A ₃ columns of the vertical transfer unit 52 are not vertically transferred, and stop at that position.

As described above, A of the vertical transfer section 52
Although _four rows of charges are sequentially vertically transferred to the first register 61 of the dummy vertical register 60, A ₁ column, A ₂ columns, A ₃ columns, because prohibits vertical transfer, the output of the dummy vertical register 60 only the charge of a ₄ rows is outputted to the. That is, the vertical transfer only A ₄ columns of the vertical transfer unit 52, the remaining A ₁
It is to prohibit the vertical transfer of the column ~A ₃ columns. Further, any one of A ₁ row to A ₃ rows of the vertical transfer unit 52 to the vertical transfer, it is also possible to inhibit the vertical transfer of the other columns. Therefore, even if an output of the vertical register of A ₁ row to A ₄ rows of the vertical transfer unit 52 to the dummy vertical register 60,
From the output of the dummy vertical register 60, the vertical transfer unit 52
Output only one column of charges. That is, this solid-state imaging device has a multiplexer that selects and outputs the output of each of the vertical transfer units 52 and 53 corresponding to the photodiodes 51 in one column. Incidentally, B ₁ row of the vertical transfer unit 53, B ₂ rows, B ₃ columns, B ₄ columns is also possible the transfer of charge in the photodiode 51 by the same operation.

Then, the charge output from the dummy vertical register 60 is transferred to the horizontal transfer unit 54 by setting the transfer gate signal TG ₁ shown in FIG. Note that the horizontal transfer unit 54 as a two-phase driving, the clock frequency of the transfer was 1212F _H level.

FIG. 11 shows A _{1 of the} vertical transfer unit 52.
This is an example of a timing that can be used when electric charge exists only in the column (when electric charge exists only in one column of column A). The timing until the time t ₁ ~t ₁₂ is the same as FIG. 10, differs only the timing of the horizontal transfer.

The principle of inhibiting the vertical transfer of the electric charges in the vertical transfer units 52 and 53 will be described below with reference to the potential diagrams of FIGS. 12 (a) to 12 (f), for simplicity of description, the electrodes are vertically driven pulses φV1, φV2, φ
V3 and φV4 are applied to four electrodes.

First, as shown in FIG. 12A, the vertical drive pulse φV _{3 is set} to H level, and the potential well is always deepened. Then, the vertical drive pulses .phi.V charge stored in the region corresponding to the _third electrode, as shown in FIG. 12 (b), when the vertical drive pulse .phi.V ₄ is changed from L level to H level, the vertical drive pulses .phi.V ₃ , φV ₄ . Next, as shown in FIG. 12 (c), the vertical drive pulses .phi.V ₄ and L level, when the vertical drive pulse .phi.V ₁ to H level, charges are collected in the region corresponding to the electrode of the vertical drive pulse .phi.V ₃ again . The next, as shown in FIG. 12 (d), the vertical drive pulses .phi.V ₂ L
When the level is changed from the level to the H level, the vertical drive pulse φV ₁ to
The charge spreads to a region corresponding to the φV ₃ electrode. Next,
As shown in FIG. 12E, when the vertical drive pulse φV1 is changed from H level to L level, the vertical drive pulses φV ₂ , φV
Charges are collected in a region corresponding to the _third electrode. And FIG.
As shown in 2 (f), when the vertical drive pulse .phi.V ₂ to from H level to L level, charges are collected in the region corresponding to the electrode of the vertical drive pulse .phi.V ₃ again. As described above, by always setting the vertical drive pulse φV ₃ to the H level,
Even if the vertical drive pulses φV ₁ , φV ₂ , φV ₄ try to transfer the electric charges in the steps (a) to (f), the transfer can be prohibited.

Further, a method of adding two pixels in the case of the interlaced scanning method will be described with reference to potential diagrams 12 of FIGS. 13 (a) to 13 (c).

First, in FIG. 13 (a), the electric charges n, n + 1, n + 2, n + 3,... Transferred to the vertical transfer units 52, 53 are generated by setting the vertical drive pulses φV ₁ , φV ₃ to H. When the vertical drive pulses φV ₂ and φV ₄ are set to L level, they are separately collected in regions corresponding to the electrodes of the vertical drive pulses φV ₁ and φV ₃ . Then, as shown in FIG. 13B, when the vertical drive pulse φV ₂ is changed from L level to H level, the vertical drive pulse φV ₂
The electric charges in the regions of the vertical drive pulses φV ₁ and φV ₃ adjacent to each other with the region corresponding to the electrode of n + ₃ therebetween are added, and the electric charges n + (n + 1), (n + 2) + (n + 3 ), ... Next, FIG.
As shown in (c), the vertical drive pulses φV ₁ and φV _{2 change} from the H level to the L level, and these added charges collect in a region corresponding to the electrode of each vertical drive pulse φV ₃ ,
The state is equivalent to that of FIG. Transfer of the added charge can be prohibited by always setting the vertical drive pulse φV ₃ to the H level.

As described above, the solid-state imaging device having the above-described configuration is
Vertical drive pulses φV ₁ , φV ₂ , φV which are four-phase drive pulses
_{4, 1AφV 3, 2AφV 3,} 3AφV 3, 4AφV 3, 1BφV
_{3, 2BφV 3, 3BφV 3,} ( not shown) control circuit as a means of controlling the 4BifaiV ₃ and vertical drive pulses .phi.V _D3
And the dummy vertical register 60 constitute a multiplexer. The multiplexer can transfer any one column of the vertical transfer unit 52 and any one column of the vertical transfer unit 53 to the horizontal transfer unit 54. The electric charges of the photodiodes 51 in one column are transferred to the vertical registers in eight columns at different timings, and the horizontal transfer unit 54 is provided for each column by the multiplexer.
, And can output a high-speed continuous electronic shutter image of up to eight frames. Further, the A ₁ line to A ₄ rows of signal charges in the vertical transfer unit 52, _one row .about.B ₄ rows B of the vertical transfer portion 53 as smear charges, etc., when correcting the noise charge, up to 4 frames Capturing of high-speed continuous images is possible.

Further, the provision of the multiplexer makes it possible to simplify the horizontal transfer section and to reduce the transfer rate of vertical transfer and horizontal transfer.

Further, as the metal for the transfer clock of the vertical transfer units 52 and 53, the vertical drive pulses φV ₁ and φV
V ₂ , φV ₄ and vertical drive pulse φV ₃ for a plurality of columns (1Aφ
_{V 3, 2AφV 3, 3AφV 3} , 4AφV 3, 1BφV 3, 2Bφ
V _3, 3BφV _3, 9 strains of 4BifaiV ₃ and .phi.V _D2) is required, a new metal wiring for inhibiting the transfer is not required.

In the first embodiment, it is desirable that the solid-state imaging device has a horizontal transfer section having a charge transfer area of an integral multiple of the number of bits in the horizontal direction and the number of dummy bits.

In the first embodiment, the vertical transfer pulse and the vertical drive pulse φV _A , φV _B are electrically separated from each other, so that a set of the A register and the B register The charges of the photodiode 3 can be transferred at different timings.

In the second and third embodiments, the horizontal transfer unit having the charge transfer area twice as large as the sum of the number of pixels in the horizontal direction and the number of dummy bits is used. Alternatively, a horizontal transfer unit having a charge transfer unit that is an integral multiple of the sum of the number of dummy bits and the number of dummy bits may be used. The horizontal transfer unit may be a one-wire type or a two-wire type so that a charge transfer area twice as large as the sum of the number of pixels in the horizontal direction and the number of dummy bits is convenient for canceling noise charges. Regardless of the above, the number of charge transfer regions of the horizontal transfer unit is important.

The present invention is, of course, not limited to the first, second, third, and fourth embodiments.

[0088]

As described in detail above, claim 1 is as follows.
The solid-state imaging device according to the invention is provided with a plurality of rows of photoelectric conversion elements, each row including a plurality of photoelectric conversion elements, and a row provided on each side of each of the above-described photoelectric conversion element rows. A plurality of sets of vertical transfer units coupled to all the photoelectric conversion elements in a column via a read gate unit, and the read gate units provided on both sides of the photoelectric conversion element columns, respectively, are independently controlled. Transfer control means for transferring the electric charge of each of the photoelectric conversion element rows to a pair of the vertical transfer units on both sides of the photoelectric conversion element row;
And a horizontal transfer section for sequentially transferring charges sequentially output from the plurality of sets of vertical transfer sections in a horizontal direction. Furthermore, the solid-state imaging device according to the first aspect of the present invention.
The pair of the photoelectric conversion element rows are placed on a pair of vertical
The charge transfer timing to the direct transfer
By making each side different,
The direct transfer section includes a first voltage including a signal charge and a noise charge.
The load is transferred, and the other vertical transfer
Charge transfer timing so that the second charge
Is controlled. Claims
2. The solid-state imaging device according to claim 1 , wherein the horizontal transfer unit independently transfers the first charge and the second charge sequentially output from the plurality of sets of vertical transfer units. It is characterized in that it is a configuration that does. The solid-state imaging device according to claim 3 is the solid-state imaging device according to claim 2 , wherein the horizontal transfer unit transfers a first charge output from the one vertical transfer unit; It has a two-row configuration with a second horizontal transfer unit for transferring the second charge output from the other vertical transfer unit. The solid-state imaging device according to claim 4 is provided with a plurality of rows of photoelectric conversion elements each including a plurality of photoelectric conversion elements, and a plurality of rows on both sides of each of the photoelectric conversion element rows, respectively. The vertical transfer units are coupled to all the photoelectric conversion elements of the corresponding photoelectric conversion element column via the readout gate unit, and the vertical transfer units in the second and subsequent columns are respectively connected to the adjacent vertical transfer unit and the transfer gate unit. And a plurality of sets of vertical transfer units coupled through the control unit, and the read gate unit and the transfer gate unit are controlled to transfer the charges sequentially output from each photoelectric conversion element column to a plurality of charges on both sides of the photoelectric conversion element column, respectively. Transfer control means for transferring to each of the column vertical transfer units, and a horizontal transfer unit for sequentially transferring only charges sequentially output from a selected vertical transfer unit of the plurality of sets of vertical transfer units in the horizontal direction. It is characterized in that it comprises. Furthermore, each of the above photoelectric conversion element rows
From the charge transfer timing to the pair of vertical transfer
The ring on one side and the other on the other
As a result, the signal charge and
And the first charge including the noise charge is transferred to the other
The second charge composed of the noise charge is transferred to the transmission unit.
Control the charge transfer timing
Things. Therefore, according to the present invention, the charge of the sum of the signal charge and the noise charge of the photoelectric conversion element row and the noise charge are transferred to the vertical transfer units in separate columns provided on both sides of the photoelectric conversion element row. It is possible to read, separate and output each charge, and to remove the noise charge by subtracting the noise charge from the sum of the signal charge and the noise charge. Therefore, even when the signal charge is small in a high-speed shutter mode or the like, a solid-state imaging device with good smear characteristics and reduced noise due to dark current can be realized.

[0089]

In addition, even when the charge accumulation time in the vertical transfer section is long at a low transfer rate and the noise charge becomes large due to the dark current, the noise charge can be removed, so that the deterioration of S / N can be prevented. .

Further, since the dark current of the photoelectric conversion element at the time of high temperature operation can be corrected, the influence of the dark current at the time of high temperature operation can be reduced, and the S / N can be improved.

[0092]

[0093]

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

The vertical transfer units in the plurality of columns are different.
Multiple images can be transferred at the same time, and the vertical
Store the charges of multiple images transferred to the
Can be output. Therefore, multiple high-speed electronic
Shutter image can be obtained, and high-speed continuous imaging can be performed.

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[Brief description of the drawings]

FIG. 1 is a sectional view of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a solid-state imaging device (horizontal transfer unit, one-wire type) according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a transfer operation to a vertical transfer unit according to the second embodiment.

FIG. 4 is a plan view of a solid-state imaging device (two-wire horizontal transfer unit) according to a third embodiment of the present invention.

FIG. 5 is an enlarged plan view of a horizontal transfer unit according to the third embodiment.

6 (a) is a sectional view taken along line II of FIG. 5, and FIG. 6 (b) is a sectional view taken along line II-II of FIG.

FIG. 7 is a timing chart showing a transfer operation to the horizontal transfer unit of the third embodiment.

FIG. 8 is a plan view of a solid-state imaging device according to a fourth embodiment of the present invention.

FIG. 9 is an enlarged plan view of a main part of the solid-state imaging device according to the fourth embodiment.

FIG. 10 is a timing chart showing the operation of the vertical transfer according to the fourth embodiment.

FIG. 11 is a timing chart showing another vertical transfer operation of the fourth embodiment.

FIG. 12 is a potential diagram of the vertical transfer unit of the fourth embodiment.

FIG. 13 is a potential diagram showing addition of charges of two pixels in the vertical transfer unit of the fourth embodiment.

FIG. 14 is a cross-sectional view of a conventional solid-state imaging device.

FIG. 15 is a schematic diagram showing the movement of signal charges in a conventional solid-state imaging device.

FIG. 16 is an enlarged plan view of a main part of a conventional solid-state imaging device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate, 2 ... P ^- well, 3 ... photodiode, 4a, 4b ... vertical transfer part, 5 ... P ⁺ pixel isolation region, 6 ... insulating film, 7 ... gate electrode, 8, 9 ... light shielding metal Reference numeral 10: color filter, 11: micro lens.

Continuation of the front page (56) References JP-A-4-180479 (JP, A) JP-A-2-170683 (JP, A) JP-A-63-152279 (JP, A) JP-A-1-241985 (JP) JP-A-3-297288 (JP, A) JP-A-64-62979 (JP, A) JP-A-63-193560 (JP, A) JP-A-3-108888 (JP, A) 4-264773 (JP, A) JP-A-2-87784 (JP, A) JP-A-4-367177 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of photoelectric conversion element rows each consisting of a plurality of photoelectric conversion elements, and one row provided on each side of each of said photoelectric conversion element rows. A plurality of sets of vertical transfer units that are coupled via a photoelectric conversion element and a read gate unit, and the read gate units provided on both sides of each of the photoelectric conversion element columns, respectively, are independently controlled, and Transfer control means for transferring the charges of the photoelectric conversion element array to a pair of the vertical transfer sections on both sides of the photoelectric conversion element array; and sequentially transferring the charges sequentially output from the plural sets of vertical transfer sections in the horizontal direction. A solid-state imaging device having a horizontal transfer unit for transferring ,
From each photoelectric conversion element row, a pair of vertical transfer on both sides thereof
Charge transfer timing to one side and the other side
In each case, by making them different,
A first charge including a signal charge and a noise charge is stored in the transmitting unit.
Transferred to the other vertical transfer section, consisting of noise charges
The charge transfer timing is controlled so that the second charge is transferred.
A solid-state imaging device characterized by controlling . 2. The horizontal transfer unit according to claim 1, wherein the first charge and the second charge sequentially output from the plurality of sets of vertical transfer units are:
Characterized in that each is independently transferred,
The solid-state imaging device according to claim 1 . 3. The horizontal transfer unit transfers a first charge output from the one vertical transfer unit and a second charge output from the other vertical transfer unit. The solid-state imaging device according to claim 2 , wherein the solid-state imaging device has a two-row configuration with a second horizontal transfer unit. 4. A plurality of rows of photoelectric conversion elements each comprising a plurality of photoelectric conversion elements, and a plurality of rows each provided on both sides of each of said photoelectric conversion element rows. The plurality of photoelectric conversion elements of the corresponding photoelectric conversion element column are coupled via the readout gate unit, and the vertical transfer units in the second and subsequent columns are respectively coupled to the adjacent vertical transfer unit via the transfer gate unit. A set of vertical transfer units, the read gate unit and the transfer gate unit are controlled, and charges sequentially output from each photoelectric conversion element column are respectively transferred to a plurality of vertical transfer units on both sides of the photoelectric conversion element column. A solid-state imaging device comprising: transfer control means for transferring each of them; and a horizontal transfer unit for sequentially transferring only charges sequentially output from a selected one of the plurality of sets of vertical transfer units in a horizontal direction. Wherein each of the above photoelectric conversion element rows
From the charge transfer timing to the pair of vertical transfer
The ring on one side and the other on the other
As a result, the signal charge and
And the first charge including the noise charge is transferred to the other
The second charge composed of the noise charge is transferred to the transmission unit.
Thus, a solid-state imaging device characterized in that the charge transfer timing is controlled .