JP3271444B2 - BIP-2 operation circuit and BIP-2 check circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BIP-2 (Bit Interleaved Parity-2) arithmetic circuit used for a transmission device or the like.

[0002] One of the transmission methods specified by CCITT
Synchronous multiplex conversion (SDH: Synchronous Digital
Hierarchy) has a structure as shown in FIG. 6 and has a data format (for example, VC (for example, VC (first-order group), second-order group, or third-order group) used for the transmission apparatus. Virtual Container) -11, VC-2,
VC-3) are prepared, and these are, for example, 155.52.
Mb / s (STM (Synchronous Transport Module)-
1) is multiplexed and transmitted.

[0003] Parity bits are prepared in these data formats, and it is possible to monitor the quality of the transmission path by performing parity calculation on the transmission side and inserting it, and checking on the reception side. Since this parity operation can accommodate 84 channels (CH) in the case of VC-11 in STM-1, each VC-11
If a parity operation is performed by an individual circuit for each, an enormous circuit scale is required. However, a method of reducing the size of the circuit by performing time division processing after multiplexing with STM-1 is known. The present invention relates to a circuit for performing a parity operation while being multiplexed in an upper frame.

[0004]

2. Description of the Related Art First, the configuration of a transmission apparatus using a BIP-2 arithmetic circuit will be briefly described. FIG. 7 is a block diagram showing a conventional synchronous multiplexing / conversion apparatus, and FIG. 8 shows the contents of overhead bytes of TU-11. In FIG. 7, on the transmitting side, a multiplexing unit (MUX) 1
Thus, low-order group data, for example, 1.544 Mb / s data is multiplexed for, for example, 84 channels. At this time, the portion (byte) corresponding to the overhead portion of the upper frame includes:
All "1" s are inserted.

[0005] The VC-11POH adding unit 2 performs a BIP-2 operation on the multiplexed output of the multiplexing unit 1,
The operation result is inserted into the first two bits of the byte of V5 (FIG. 8). The output of the VC-11 POH adding unit 2 is TU-1
The 1-pointer adding unit 3 inserts overhead bytes V1 to V4 in accordance with the SDH regulations.

Further, a section overhead (SOH), a path overhead (POH) and the like are inserted into an output of the TU-11 pointer adding section 3 by an upper frame overhead adding section 4, and the electrical / optical conversion section (E / O) is provided. ) 5
Is converted into an optical signal and transmitted to an optical transmission line.

On the receiving side, the operation reverse to that of the transmitting side is performed. The optical signal from the optical transmission line is converted to an electric signal by the O / E 6, and
H, POH processing is performed, and the position of V5 is detected by V1, V2 in the TU-11 pointer termination unit 8. VC-11POH
The terminal unit 9 applies BIP-2 to the transmitted data.
Is performed, and the result is compared with the value inserted in V5. If the result does not match, an alarm is output to the outside.
Then, the demultiplexing unit (DMUX) 10 performs demultiplexing.

Next, a conventional BIP-2 calculation method will be described. In the MUX 1 on the transmitting side described above, for example, VC-1
When multiplexing 1 into, for example, STM-1, VC-11 is first mapped to TU-11 as shown in FIG. During the TU-11 frame format, a stuff byte (V) for absorbing input and output clock fluctuations is used.
In 3), one byte is prepared for one frame, and the stuff byte is deleted or increased to two bytes depending on the state of the input / output clock, and substantial data speed adjustment is performed.

This speed adjustment is performed individually for each TU-11, and the information is inserted into the overhead bytes (V1, V2 bytes) of the TU-11. In other words, when the parity calculation of the VC-11 is performed after being multiplexed on the STM-1 to reduce the size of the circuit, not only the time division processing is performed by a frame counter or the like, but also the overhead byte ( V1, V2), the presence or absence of a stuff byte must be checked, and a circuit for controlling the operation range based on the stuff byte must be provided separately.

Hereinafter, a specific circuit will be described. FIG. 10 is a block diagram of a conventional parity operation unit. Figure 1
1 and FIG. 12 are diagrams showing the calculation range of BIP-2 in the conventional example. 10, the stuff byte detecting unit 12 detects the stuff byte (V3 in FIG. 11) of the input data,
Output a signal.

On the other hand, the time division processing control section 11 outputs a frame pulse (FP) and a signal in response to a timing pulse input. The AND circuit 13 calculates the logical product of the signal obtained by inverting the phase of the above signal and the signal, and adds the logical product to the BIP-2 arithmetic circuit 14 as a data enable signal. The BIP-2 operation circuit 14 calculates BIP-2 for each frame of the input data based on the frame pulse (FP) and the data enable signal.

As shown in FIG. 11A, in a normal case where one byte of stuff byte (V3) is inserted, a parity operation is performed on the data in the hatched portion in FIG. Is performed. At the time of negative justification shown in FIG. 7B, it is considered that there is no stuff byte, and the V3 byte is packed by one byte. At the time of positive justification shown in FIG. 12C, V3 and one adjacent byte (total 2 bytes) are used.
It is controlled so that parity operation for (byte) is not performed.

In the transmitting device, the BIP-2 shown in FIG.
The operation result of the output of the operation circuit 14 is inserted into the first two bits of the V5 byte by the parity insertion circuit 15 and
-11 Output from the POH adding unit 2. This is VC-1
2, the parity calculation of VC-2 is performed in the same manner. Note that the parity of VC-11, VC-12, and VC-2 is called BIP-2.

[0014]

As described above, in the conventional circuit configuration, the presence or absence of a stuff byte (V3) is detected by V1 and V2 (pointers). The circuit scale was increased because a circuit for controlling the removal was used.

The present invention has been made in order to solve the above-mentioned problem. When performing BIP-2 operation on data input as it is in an upper frame such as STM-1 in SDH, the TU level is always used. Staff byte (V3)
BIP-2 which simplified the circuit by including
It is an object to provide an arithmetic circuit.

[0016]

The above problems can be solved by the following circuit configuration. A BIP-2 arithmetic circuit of a transmission device for multiplexing a plurality of lower frames in a new synchronous digital hierarchy (SDH) into an upper frame using a stuff byte for frequency adjustment, wherein the multiplexing is performed on the upper frame. In the encrypted data
When the stuff byte is included, the stuff byte is always included in the calculation range of BIP-2 .

(2) A BIP-2 check circuit of a transmission apparatus for multiplexing a plurality of lower frames in a new synchronous digital hierarchy (SDH) into an upper frame using a stuff byte for frequency adjustment. If a stuff byte is included in the multiplexed data after the pointer is changed for transfer,
When the BIP-2 check is performed in a time-sharing manner on the converted data , the stuff byte is always included in the calculation range.

[0018]

[Action]

(Claim 1) In a transmission apparatus for multiplexing a plurality of lower frames into an upper frame in a new synchronous digital hierarchy (SDH) defined by CCITT,
The stuff byte (V3) is initially set to "11111111". Since both the even-numbered and odd-numbered bits of this stuff byte are 4 bits, even if this stuff byte is included in the calculation range of BIP-2, The operation result does not change.

As a result, even if the stuff byte (V3) is increased or decreased for frequency adjustment and the position of the data for which parity is calculated is changed in the TU frame in SDH, the increase / decrease of the stuff byte is detected. BIP-
2 can be performed, so that the configuration of the operation circuit of BIP-2 can be simplified.

(Claim 2) After the pointer is changed for changing the frame, the stuff byte (V
3) is set to "11111111", so that when multiplexed data is checked for BIP-2 in a time-division manner on the receiving side, this stuff byte (V3) is set in the calculation range of BIP-2. Even if it is included, the operation result does not change. As a result, the configuration of the BIP-2 check circuit can be simplified.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of the present invention is that a stuff byte (V3)
Is "11111111", the even-numbered and odd-numbered bits are both 4 bits, and this stuff byte is
Focusing on the fact that the result does not change even in addition to the operation of IP-2, it is not necessary to detect the stuff byte for the operation of BIP-2. This will be described in detail below.

FIG. 1 shows a configuration diagram of a parity operation unit according to an embodiment of the present invention. In the figure, a time-division processing control unit 11 generates a frame pulse (FP) based on a timing pulse input, generates an enable signal, and applies the enable signal to a BIP-2 arithmetic circuit 14 to perform BIP-2 arithmetic on input data. Do.

FIG. 2 is a diagram showing a calculation range of BIP-2 in the embodiment. Normal time ((a) in the figure), negative justification ((b) in the figure), positive justification ((c) in the figure)
The position of the "H" level of the data enable signal indicating the operation range does not change. In the calculation range, the stuff byte is normally one byte larger in the normal justification, and the stuff byte is larger by two bytes in the positive justification. However, as described above, the stuff byte is "11111111". Have the same value.

FIG. 3 shows an example of the BIP-2 arithmetic circuit on the transmitting side. In the drawing, an exclusive-OR (EX-OR) circuit 16 obtains an EX-OR of the odd-numbered data, that is, the data of the first, third, fifth, and seventh bits of the 8-bit parallel input data. EX-OR The operation result of the circuit 16 and the EX of the immediately preceding data
EX-OR with Q terminal output of FF18, which is the result of -OR operation, is E
The result is obtained by the X-OR circuit 17, and the result is input to the D terminal of the FF18. This is sequentially obtained for input data within one frame by a clock.

EX-OR is when two input data are equal.
Since it has the characteristic of outputting "0" and "1" when it is not equal, in the case of even parity, when the final value related to the odd number of one frame output from the FF 18 is "0", V
Insert "0" into one of the first two bits of 5,
If the final value is "1", insert "1".

The same applies to the even-numbered data input to the EX-OR circuit 20, that is, the second, fourth, sixth, and eighth bit data. If the value is "0", "0" is inserted into the other two bits of the first two bits of V5, and the final value is "5".
At the time of "1", insert "1".

The present invention can be applied not only to the calculation of BIP-2 on the transmission side but also to the check of BIP-2 on the reception side. However, on the receiving side, the stuff byte (V3) is not always "11111" due to a transmission path error.
Since it is not always 111 ", a correct result cannot be obtained even if the present invention is applied and checked as it is after reception.

However, in the case of a synchronous multiplexing converter that replaces a pointer for a processing circuit (DMUX part) of a lower frame instead of a simple terminal device, "11111111" is newly inserted into the stuff byte (V3). So BI
The present invention can be applied by adopting an apparatus configuration in which the check of P-2 is performed after changing the frame.
FIG. 4 shows an example of the BIP-2 check circuit on the receiving side.

FIG. 5 shows a block diagram of a new synchronous multiplex converter according to an embodiment of the present invention. In the figure, a multiplexing unit (MUX) 1 outputs low-order group data, for example, 1.544 Mb /
The s data is multiplexed for, for example, 84 channels. At this time, "1" is inserted into all bytes corresponding to the overhead part of the upper frame. The multiplexed output of the multiplexing unit 1 is subjected to BIP-2 by the VC-11 POH adding unit 2 '.
And the result of the operation is inserted into the first two bits of the byte of V5.

The TU-11 pointer replacement unit 8 'on the receiving side detects the position of V5 based on V1 and V2, replaces the pointer, and newly inserts "11111111" into the stuff byte (V3). As a result, the VC-11 POH termination unit 9 can check the BIP-2 according to the present invention.

In the above embodiment, the low-order group data is
For the data of 1.544 Mb / s and STM-1 (155.52 Mb / s) multiplexed as a higher order group,
The case where the calculation of P-2 is performed by time division has been described,
The high-order group is not limited to STM-1 (155.52 Mb / s), and the present invention can be applied to multiplexed low-order group data of, for example, 1.544 Mb / s.

As a result, VC-11, VC-12, and VC-2 which are input while being mapped to the upper frame.
In the calculation of BIP-2, even if the stuff byte (V3) is increased / decreased for frequency adjustment in the TU frame and the position of the data for which parity is calculated changes, the increase / decrease of the stuff byte is detected and the calculation is performed. The calculation of BIP-2 can be performed without performing the operation of changing the range. As a result, the configuration of the calculation unit of BIP-2 can be simplified.

Further, after the frame transfer, the present invention can be applied to the check of BIP-2 on the receiving side, and the configuration of the check unit of BIP-2 can be simplified.

[0034]

As described above, according to the present invention, there is provided a transmission apparatus for multiplexing a plurality of lower frames into an upper frame in a new synchronous digital hierarchy (SDH) defined by CCITT. ,
The stuff byte (V3) is initially set to "11111111". Since both the even-numbered and odd-numbered bits of this stuff byte are 4 bits, even if this stuff byte is included in the calculation range of BIP-2, The operation result does not change.

As a result, even if the stuff byte (V3) is increased or decreased for frequency adjustment in the TU frame in SDH and the position of the data for which parity is calculated is changed, the increase / decrease of the stuff byte is detected. BIP-
2 can be performed, so that the configuration of the operation circuit of BIP-2 can be simplified.

(Claim 2) After the pointer is changed for changing the frame, the stuff byte (V
3) is set to "11111111", so that when multiplexed data is checked for BIP-2 in a time-division manner on the receiving side, this stuff byte (V3) is set in the calculation range of BIP-2. Even if it is included, the operation result does not change. As a result, the configuration of the BIP-2 check circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram (transmission side) of a parity operation unit according to an embodiment of the present invention;

FIG. 2 is a diagram showing a calculation range of BIP-2 in the embodiment.

FIG. 3 is an example BIP-2 arithmetic circuit diagram (transmitting side),

FIG. 4 is an example BIP-2 check circuit diagram (receiving side),

FIG. 5 is a block diagram showing the configuration of a new synchronous multiplex conversion device according to an embodiment of the present invention;

FIG. 6 is a diagram showing an example of an SDH multiplexing structure;

FIG. 7 is a block diagram of a conventional new synchronous multiplex conversion device;

FIG. 8 is a diagram showing overhead bytes of TU-11;

FIG. 9 is a diagram showing mapping of VC-11 to TU-11;

FIG. 10 is a block diagram of a conventional parity operation unit (transmitting side);

FIG. 11 is a diagram (part 1) showing a calculation range of a conventional BIP-2;

FIG. 12 is a diagram (part 2) illustrating a calculation range of the conventional BIP-2.

[Explanation of symbols]

1 is a multiplexer (MUX), 2 and 2 'are VC-11 POH adders, 3 is a TU-11 pointer adder, 4 is an upper frame overhead adder, and 5 is an electrical / optical converter (E / O). , 6 is the O / E, 7 is the upper frame overhead termination unit, 8 is the TU-11 pointer termination unit, 8 'is the TU-11 pointer replacement unit, 9 is the VC-11 POH termination unit, 10 is the demultiplexing unit (DMUX) ), 11 is a time-division processing control unit, 12 is a stuff byte detection unit, 13, 19, 23, 26, 31 is an AND circuit, 14 is a BIP-2 arithmetic circuit, 15 is a parity insertion unit, 16, 17, 20, 21, 23, 24, 27, 28, 29, 32 denote exclusive OR (EX-OR) circuits, and 18, 22, 25, 30 denote FFs.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-91090 (JP, A) JP-A-7-50652 (JP, A) JP-A-5-37497 (JP, A) International Publication 93/25029 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 1/00 H04J 3/00 H03M 13/00

Claims (2)

(57) [Claims] 1. A new synchronous digital hierarchy (SD)
A BIP-2 calculation circuit of the transmission apparatus for multiplexing to the upper frame using the stuff byte for frequency adjustment a plurality of lower frame in H), staff by in multiplexed data to said upper frame
A BIP-2 arithmetic circuit, wherein the stuff byte is always included in the operation range of the BIP-2 when the BIP-2 is included. 2. A new synchronous digital hierarchy (SD)
H) A BIP-2 check circuit of a transmission device for multiplexing a plurality of lower frames into an upper frame using stuff bytes for frequency adjustment in H), wherein the multiplexing is performed after pointers are changed for frame switching. Data contains stuff bytes,
A BIP-2 check circuit characterized in that when multiplexed data is checked for BIP-2 in a time-division manner, the operation range always includes the stuff byte.