JP3265118B2 - Random line selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random line selection device for controlling a video signal of a color liquid crystal panel.

[0002]

2. Description of the Related Art In a color liquid crystal panel, the display section of one field is different between the NTSC system and the PAL system.
It is 225H in the NTSC system and 25 in the PAL system.
7H. Therefore, the display section is set to 225 even in the PAL system.
If H, the color liquid crystal panel can be shared.
That is, in the PAL system, 257H × 7/8 ≒ 225H is obtained by thinning out 1H in 8H, and the display section of one field can be set to 225H.

In order to realize this, a conventional random line selection device has a configuration as shown in FIG. In this case, as a method of implementing line thinning, the horizontal synchronizing signal is invalidated once every 8H. That is, one horizontal synchronizing signal is invalidated at different positions in eight fields for eight horizontal synchronizing signals.

In FIG. 10, reference numeral 150 denotes a vertical synchronizing signal V
In the reset pulse generator which receives the _SYNC and horizontal synchronization signal H _SYNC, every time the vertical synchronizing signal V _SYNC is input, in response to the horizontal synchronizing signal H _SYNC immediately after that is, the vertical synchronization signal V _SYNC is input To generate a reset pulse. 200
It is a 3-bit field counter that repeatedly counts the vertical synchronizing signal V _SYNC example eight vertical synchronization signal V _SYNC as a clock input, initially generates an output corresponding to "0", thereafter the vertical synchronizing signal V _SYNC Each time it is input, an output corresponding to each value of “1”, “2”,..., “7”, “0” is sequentially and cyclically generated. That is, the field counter 200 generates the same output every eight fields.

[0005] 600 with a clock input horizontal synchronizing signal H _SYNC, as a reset input to reset pulse output from the reset pulse generator 0.99, H-line counter (ring repeatedly counts eight horizontal synchronization signal H _SYNC Counter), the count value of which is “0” immediately after reset, and thereafter “1”, “2”,
, "7", "0" sequentially and cyclically, and when the count value changes from "7" to "0", that is, every time eight horizontal synchronization signals H _SYNC are counted, the ripple carry output ( RC) 600d.

Reference numeral 350 designates a horizontal synchronization signal _HSYNC as a clock input, a reset pulse 150a output from the reset pulse generator 150 as a reset input, and a ripple carry output (RC) 600d of the H line counter 600.
For example, is an 8-bit (eight-stage) shift register that receives data as input data, and is the eighth horizontal synchronization signal H _{SY NC} after reset.
Occurs, the first ripple carry output is added to the data input, and the ninth horizontal sync signal H _SYNC is sequentially shifted every time the ninth horizontal sync signal H _SYNC is input and the ninth horizontal sync signal H _SYNC is output.
_{When SYNC} is input, a ripple carry output appears in the first bit, and when a tenth horizontal sync signal H _SYNC is input, a ripple carry output appears in the second bit, and the eleventh to sixteenth horizontal sync signals H _SYNC are output. 3 for each input
A ripple carry output appears at the ８8th bit. Also,
When the 16th horizontal synchronization signal _HSYNC is input, the second ripple carry output is added to the data input. When the 17th and subsequent horizontal synchronization signals _HSYNC are input, the first to eighth bits are input in the same manner as described above. A ripple carry output appears, and operates in the same manner.

A multiplexer 450 selectively outputs one of the eight bits of the shift register 350 in accordance with the output of the field counter 200. The multiplexer 450 thins out the horizontal synchronization signal H _SYNC to 8H once. That is, a thinning signal 450e for invalidating is generated. For example, when the field counter 200 counts the sixth vertical synchronization signal _VSYNC , that is, in the sixth field, the multiplexer 450 sets the shift register 35
The second bit of 0 is selectively output, and this signal becomes a thinning signal 450e.
When 0 counts the second horizontal synchronization signal _HSYNC , a ripple carry output appears, and the third horizontal synchronization signal HSYNC is output.
_SYNC will be thinned out.

[0008] 500 the output of the multiplexer 450, that is a gate to disable the horizontal synchronizing signal H _{SY NC} at a thinning signal, decimating horizontal synchronizing signal is disabled once the horizontal synchronization signal H _SYNC to 8H H _SS (= 500a ) Is output. The position of the horizontal synchronization signal H _{SYNC to} be thinned is 8
It changes one line at a time in the field cycle. Hereinafter, a specific configuration of each block of the random line selection device will be described.

FIG. 11 shows the random line selection device of FIG.
A specific block diagram of the shift register 350 in FIG.
Show. In FIG.
D flip-flops that make up the registers
Output D₁'~ D₈'. 150a is the reset pad
Reset pulse supplied from the pulse generator 150, 60
0d is a ripple supplied from the H line counter 600
Carry output. 39Q-46Q is D flip flow
Are the Q outputs of steps 39 to 46, and this is the output D ₁'~ D
₈'. This shift register 350 has a reset register.
After being reset by the lure 100a, the H line counter 6
Ripple carry output 600d is input from 00
And the horizontal synchronizing signal H_SYNCEach time the
The tree output is shifted one bit at a time.

FIG. 12 is a specific block diagram of the field counter 200 and the multiplexer 450 in the random line selection device of FIG. 12, reference numerals 47 to 49 denote D flip-flops constituting the field counter 200, and reference numerals 50 to 58 denote AND gates constituting the multiplexer 450. The field counter 200 changes the Q output and the / Q output of each of the D flip-flops 47 to 49 every time the vertical synchronization signal V _SYNC arrives. The multiplexer 45
0 is the Q output of D flip-flops 47-49 and / or
Corresponds to the state of the Q output, outputs one of the output D ₁ '~D _8' of the shift register 350 selectively.

FIG. 13 is a time chart of each part in FIGS. 13A shows the horizontal synchronizing signal H _SYNC , FIG. 13B shows the ripple carry output of the H line counter 600, and FIG. 13C shows the Q output of the D flip-flop 39 of the shift register 350, that is, the output D.
'Indicates, (d) the Q output that is output D ₂ of the D flip-flop 40 of the shift register 350' ₁ indicates,
(E) D flip-flop 4 of shift register 350
6 shows the Q output, that is, the output D ₈ ′, and (f) shows the output of the AND gate 500, that is, the thinned horizontal synchronizing signal H _SS . FIG. 13 is a time chart showing a state in which the multiplexer 450 selects the output D ₂ ′. If the multiplexer 450 selects an output other than the output D ₂ ′, the time chart is different from that in FIG. 13 and the position of the thinned horizontal synchronization signal H _SYNC is different.

[0012]

In the conventional random line selection device, the H line counter 600 generates a ripple carry output 8H after the H line counter 600 and the shift register 350 are reset by the vertical synchronization signal V _SYNC . When the multiplexer 450 selects D ₈ ′, the first thinning is performed after a lapse of 8H. That is, from the start of thinning, that is, the vertical synchronization signal V
_No decimation is performed once during 16H after the arrival of _SYNC .

Accordingly, an object of the present invention is to provide a random line selection device capable of starting thinning out immediately after the arrival of a vertical synchronization signal.

[0014]

According to the random line device of the present invention , a vertical synchronizing signal is inputted to one of an input terminal pair.
The horizontal synchronization input from the other of the input terminal pair at each arrival
Reset and preset pulses in response to signals
Reset preset pulse that outputs
Generator and m input signals (m is an arbitrary
(Integer) vertical sync signal is counted out sequentially.
Field counter to output to the
Signal to the input terminal of the first stage.
Applied to one of the input terminal pairs from the reset pulse generator
Reset by the reset pulse
Preset by the preset pulse given to
Horizontal synchronization signal applied to the clock input
Signal as a clock input and n bits (n is an arbitrary integer)
A system that outputs the data-shifted signal to the final-stage output terminal
Shift register and field counter output
The field in the n bits of the shift register
Select only one bit corresponding to the output of the
Decoder that supplies reset pulse and shift register
Input terminal signal and horizontal sync signal
For one horizontal synchronization signal for n horizontal synchronization signals, m horizontal synchronization signals
Thinning disabled in different positions in different fields
A logic gate for outputting a horizontal synchronizing signal.

[0015]

According to the structure of the present invention, the field counter repeatedly counts the number m of vertical synchronizing signals, and its output changes every time the vertical synchronizing signal arrives, that is, every time the field changes. The reset preset pulse generator generates a reset pulse every time the vertical synchronization signal arrives, that is, every time the field changes, then generates a preset pulse, and supplies the reset pulse and the preset pulse to the shift register. The decoder selectively supplies the preset pulse to only one bit corresponding to the output of the field counter in each bit of the shift register every time the field changes.

The shift register cyclically shifts data of a certain bit by using the horizontal synchronization signal as a clock input, and is reset by a reset pulse every time a vertical synchronization signal arrives, that is, every time a field changes.
Further, each time the horizontal synchronizing signal arrives from the preset state, it is cyclically shifted by one bit. Therefore, the final stage output terminal signal of the shift register appears once every nH, and the appearing position is different sequentially in the period of m fields.

As a result, the final stage output terminal of the shift register
A logic gate which receives a child signal and a horizontal synchronization signal as inputs has n
As for one horizontal synchronizing signal, a thinned horizontal synchronizing signal in which one horizontal synchronizing signal is invalidated at different positions in m fields is output.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a random line selection device according to an embodiment of the present invention. In FIG. 1, 10
_{Reference numeral} 0 denotes a reset preset pulse generator which receives the vertical synchronizing signal V _SYNC and the horizontal synchronizing signal H _SYNC as input, and each time the vertical synchronizing signal V _SYNC arrives, that is, the first horizontal pulse after the vertical synchronizing signal V _SYNC is input. A reset pulse 100a is generated in response to the synchronization signal H _SYNC , and the second horizontal synchronization signal H
_A preset pulse 100b is generated in response to _SYNC .

The reference numeral 200 designates, for example, 8 clocks of the vertical synchronization signal V _SYNC (an arbitrary integer m in the claims).
) Is a 3-bit field counter that repeatedly counts the number of vertical synchronization signals _VSYNC.
, And after that, every time the vertical synchronization signal V _SYNC is input, the output corresponding to each value of “1”, “2”,..., “7”, “0” is sequentially and cyclically generated. I do. That is, the field counter 200 generates the same output every eight fields.

Reference numeral 300 denotes a horizontal synchronization signal _HSYNC as a clock input, a reset pulse 100a and a preset pulse 100b output from the reset pulse generator 150 as a reset input and a preset input, respectively, and a final stage output terminal signal as a first stage input terminal, ie, data. This is a shift register of, for example, 8 bits (in the claims, an arbitrary integer n bits) that feeds back to the input terminal, and cyclically shifts data of a fixed number of bits (8 bits in this example).

A decoder 400 decodes the output of the field counter 200 to apply the preset pulse 100b to only one bit corresponding to the output value of the field counter 200 in each bit of the shift register 300. If presetting is performed, when one horizontal synchronizing signal H _SYNC arrives, the shift register 3
The first high-level signal is output from 00, and thereafter, a high-level signal is output every time eight horizontal synchronization signals H _SYNC arrive. If presetting is performed for the second bit, when seven horizontal synchronization signals H _SYNC arrive, the first high-level signal is output from the shift register 300,
Thereafter, a high level signal is output every time eight horizontal synchronization signals H _SYNC arrive. Even when the other bits are preset, the number of horizontal synchronization signals H _SYNC until the first high level signal is output is different, but the high level signal is output every time eight horizontal synchronization signals H _SYNC arrive. Is output.

[0022] 500 final stage output terminal signal and one horizontal synchronizing signal H _SYNC for each number corresponding to the bit number n of the shift register 300 and a horizontal synchronizing signal H _SYNC as inputs of the shift register 300, i.e. eight Horizontal synchronization signal H
One horizontal synchronization signal H _SYNC for _SYNC, a gate (logic gate) for outputting the thinned horizontal synchronizing signal H _SS was disabled in different positions in the eight fields.

In this random line selection device, the field counter 200 repeatedly counts eight (in the claims, an arbitrary integer m) vertical synchronizing signals V _SYNC, and outputs the vertical synchronizing signal V _SYNC. It changes each time it arrives, that is, every time the field changes. Also, the reset preset pulse generator 100 outputs the vertical synchronization signal V
Each time _SYNC arrives, that is, every time the field changes, a reset pulse 100a is generated.
00b, and supplies a reset pulse 100a and a preset pulse 100b to the shift register 300. Each time the field changes, the decoder 400 controls the field counter 20 in each bit of the shift register 300.
The preset pulse 100b is selectively supplied to only one bit corresponding to the output of 0.

The shift register 300 has a horizontal synchronizing signal H
_SYNC is used as a clock input to cyclically shift data of n bits, in this example, 8 bits. Each time the vertical synchronization signal V _SYNC arrives, that is, every time the field changes, the data is reset by the reset pulse 100a and further reset. In this state, each time the horizontal synchronization signal H _SYNC arrives, it is cyclically shifted by one bit. Therefore, the final stage output terminal signal 3 of the shift register 300
00c appears once every 8H, and the appearance position is different sequentially in eight field periods.

[0025] 500 final stage output terminal signal and one horizontal synchronizing signal H _SYNC for each number corresponding to the bit number n of the shift register 300 and a horizontal synchronizing signal H _SYNC as inputs of the shift register 300, i.e. eight Horizontal synchronization signal H
One horizontal synchronization signal H _SYNC for _SYNC, a gate (logic gate) for outputting the thinned horizontal synchronizing signal H _SS was disabled in different positions in the eight fields.

FIG. 2 shows a time chart of each part of the random line selection device of FIG. 2A shows the vertical synchronization signal V _SYNC , and FIG. 2B shows the horizontal synchronization signal H _SYNC.
(C) shows a reset preset pulse generator 10
0 shows a reset pulse 100a output from 0,
(D) is a reset preset pulse generator 100
Shows a preset pulse 100b output from
(E) shows an output 300c of the shift register 300,
(F) shows the thinned horizontal synchronizing signal H _SS (= 500c) output from the OR gate.

FIG. 3 is a specific block diagram of the reset preset pulse generator 100 in the random line selection device of FIG. In FIG.
It is a flip-flop. The vertical synchronization signal V _SYNC is applied as a clock input to the first stage D flip-flop 1, and the horizontal synchronization signal H _SYNC is applied as a clock input to the second and third stage D flip-flops 2 and 3.
The Q output of the second stage D flip-flop 2 is used as the reset input of the first stage, the reset pulse 100a is used, and the Q output of the third stage D flip-flop 3 is used as the preset pulse 100b. That is, the reset preset pulse generator 100 detects the arrival of the vertical synchronizing signal V _SYNC by the D flip-flop 1 of the first stage, and outputs the Q output of the D flip-flop 1 by the horizontal synchronizing signal H _SYNC.
The shift is performed by the flip-flops 2 and 3, and a reset pulse 100a and a preset pulse 100b are generated, respectively. In order to set the pulse width of the reset pulse 100a and the preset pulse 100b to 1H, the first stage D flip-flop 1 is reset by the Q output of the second stage D flip-flop 2.

FIG. 4 is a time chart of each part of the reset preset pulse generator 100 shown in FIG. In FIG. 4, (a) shows the vertical synchronizing signal V _SYNC , and (b) shows the horizontal synchronizing signal H _SYNC . (C) shows the Q output 1Q of the D flip-flop 1, (d) shows the Q output 2Q of the D flip-flop 2, that is, the reset pulse 100a, and (e) shows the Q output 3Q of the D flip-flop 3, that is, the preset pulse 100b. Is shown.

FIG. 5 shows the random line selection device of FIG.
Of the field counter 200 and the decoder 400
A specific block diagram is shown. In FIG. 5, 28 to 30
Are the D free lines constituting the field counter 200, respectively.
It is flip-flop. 31 to 38 are decoders 4 respectively.
00 and an output D ₁
~ D₈(= 31a to 38a). Fieldka
The counter 200 receives the vertical synchronization signal V_SYNCCount operation
Repeat, vertical sync signal V_SYNCEach time D arrives, each D
Q outputs 28Q, 29Q, 3 of lip flops 28-30
Change the 0Q and / Q outputs. Also, the decoder 40
0 is the Q output of D flip-flops 28-30 and / or
The state of the Q output, that is, the count of the field counter 200
Output D according to the event value (0 to 7)₁~ D₈Any one of
Is selectively set to high level “1” and the rest to low level
Set to “0”.

FIG. 6 is a time chart of each part of the field counter 200 and the decoder 400 of FIG. In FIG. 6, (a) shows the vertical synchronization signal V _SYNC . (B) shows the Q output 28Q of the D flip-flop 28, and (c) shows the Q output 29Q of the D flip-flop 29.
(D) shows the Q output 30 of the D flip-flop 30
Q is shown. (E) is the output D ₁ of the AND gate 31
(= 31a), (f) shows the output D ₂ (= 32a) of the AND gate 32, (g) shows the output D ₃ (= 33a) of the AND gate 33, and (h) shows the AND gate 3
4 shows the output D ₄ (= 34a), (i) shows the output D ₅ (= 35a) of the AND gate 35, (j) shows the output D ₆ (= 36a) of the AND gate 36, and (k) ) Indicates the output D ₇ (= 37a) of the AND gate 37, and (l)
Indicates the output D ₈ (= 38a) of the AND gate 38.

FIG. 7 is a specific block diagram of the shift register 300 in the random line selection device of FIG. In FIG. 7, 4 to 11, 12 to 19 are NAND gates, and 20 to 27 are D flip-flops. In this shift register 300, the decoder 40
The preset pulse 100b is supplied to the NAND gates 4 to 11 and 12 only in one bit which is "1" in the output of "0".
To 19 are applied to any of the D input terminals of the D flip-flops 20 to 27 constituting each stage of the shift register 300 via any one of the horizontal synchronizing signals H as clocks.
Preset in response to the arrival of _SYNC . 4a-19a
Are the outputs of the NAND gates 4 to 19 and 20Q to 27Q
Is the Q output of D flip-flops 20-27.

FIG. 8 shows each part of the shift register 300 shown in FIG.
3 shows a time chart. In FIG. 8, (a) is horizontal.
Synchronous signal H_SYNC(B) shows a reset pulse 100
(c) shows the preset pulse 100b,
(D) shows the output 4a of the NAND gate 4 and (e) shows the output 4a.
(F) shows the output 12a of the NAND gate 12.
Output 13 (Q output of D flip-flop 21) 1
3a (= 21Q), and (g) of the NAND gate 14
Output (Q output of D flip-flop 22) 14a (= 2
2H), and (h) shows the output (D signal) of the NAND gate 19.
Q output of lip flop 27) 19a (= 27Q = 30
0c). Note that FIG. ₁Only "1"
, That is, (D₁, D_Two, D_Three, ..., D₈) =
The waveform at (1, 0, 0,..., 0) is shown.

In this case, the shift register 300 is reset by the reset pulse 100a due to the arrival of the vertical synchronization signal _VSYNC , and the output of the NAND gate 4 shifts to the low level by the preset pulse 100b following the reset pulse 100a. Since the NAND gate 5 to 11 D ₁ to D ₈ is "0", the output is the preset pulses 100
At b, it does not change and remains at the high level. The output of the NAND gate 4 which has shifted to the low level causes the output of the NAND gate 12 to shift to the high level, and "1" is taken into the D flip-flop 21 by the next incoming horizontal synchronization signal _HSYNC . The width of the preset pulse 100b is 1
Since it is H, the period during which “1” is taken into the D flip-flop 21 is only for 1H, and thereafter, it is shifted every time the horizontal synchronization signal H _SYNC arrives. As a result, the shift register 300 preset to a different bit by one bit each time the vertical synchronization signal V _SYNC arrives generates a high-level voltage as an output 300c for 1H in an 8H cycle, and thins out different lines over 8 fields. Can be.

FIG. 9 shows the components of the shift register 300 shown in FIG.
3 shows a time chart. In FIG. 9, (a) is horizontal.
Synchronous signal H_SYNC(B) shows a reset pulse 100
(c) shows the preset pulse 100b,
(D) shows the output 5a of the NAND gate 5, and (e) shows the output 5a.
Output of the output gate 12 (Q output of the D flip-flop 20).
Force) 12a (= 20Q), (f) is a NAND gate
13 shows an output 13 a of the NAND gate 14.
Output (Q output of D flip-flop 22) 14a (= 2
2H), and (h) shows the output (D signal) of the NAND gate 19.
Q output of lip flop 27) 19a (= 27Q = 30
0c). Note that FIG. _TwoOnly "1"
, That is, (D₁, D_Two, D_Three, ..., D₈) =
The waveform at (0, 1, 0,..., 0) is shown.

This random line selection device decodes the output of the field counter 200, presets one bit of each bit of the shift register 300 according to the state thereof, and uses the output of the last stage of the shift register 300 as the input of the first stage. By using a direct decimation signal,
The thinning is started immediately after the arrival of the vertical synchronizing signal V _SYNC , so that the display can be accurately classified and the shift register 300 itself has a periodicity of 8H, so that the H line counter can be omitted.

In order to set the display period of one field of the PAL system to 225H, it is necessary to thin out the lines once every eight times. Therefore, the shift register 300 must be 8 bits (n = 8). However, the field counter 200 may have any eight field count (m = 8), four field count (m = 4), or any other field count. For example, if 4 fields are counted,
One line can be thinned out once every 8H between the four fields, but the fifth field has the same line thinning as the first field. As the number of fields is reduced, the lines to be decimated are fixed for each field, so that all information cannot be reproduced. For example, horizontal lines may disappear in a crosshatch image.

In order to conform to the NTSC system by omitting a part of the display section of the PAL system, it is necessary to omit the horizontal period of 257H to 225H, that is, to omit the horizontal synchronization signal once every eight times. , The shift register 300 requires 8 bits, but if there is a television system other than the PAL system and the display period of one frame is other than 257H, the number and the display period of one frame of the NTSC system, for example. The number n of bits of the shift register may be determined according to the ratio to 225H. The count number of the field counter is arbitrary.

[0038]

According to the random line selection apparatus of the present invention, the output of the field counter is decoded, and one bit of each bit of the shift register is preset according to the state, and the output of the last stage of the shift register is input to the first stage. In addition, by using the thinning signal directly, the thinning can be started immediately from the arrival of the vertical synchronizing signal, accurate display division can be achieved, and the shift register itself has periodicity for thinning. , H line counter can be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a random line selection device according to an embodiment of the present invention.

FIG. 2 is a time chart of each unit showing an operation of the random line selection device of FIG. 1;

FIG. 3 is a block diagram showing a specific configuration of a reset preset pulse generator in the random line selection device of FIG. 1;

FIG. 4 is a time chart of each part showing the operation of the reset preset pulse generator of FIG. 3;

FIG. 5 is a block diagram showing a specific configuration of a field counter and a decoder in the random line selection device of FIG. 1;

6 is a time chart of each unit showing the operation of the field counter and the decoder of FIG. 5;

FIG. 7 is a block diagram showing a specific configuration of a shift register in the random line selection device of FIG. 1;

8 is a time chart of each part showing the operation of the shift register of FIG. 7;

FIG. 9 is a time chart of each unit showing the operation of the shift register of FIG. 7;

FIG. 10 is a block diagram showing an example of a configuration of a conventional random line selection device.

11 is a block diagram showing a specific configuration of a shift register in the random line selection device of FIG.

12 is a block diagram showing a specific configuration of a field counter and a multiplexer in the random line selection device of FIG.

FIG. 13 is a time chart of each part showing the operation of the conventional random line selection device shown in FIGS. 10 to 12;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 reset preset pulse generator 200 field counter 300 shift register 400 decoder 500 OR gate 1-3 D flip-flop 4-11 AND gate 12-19 NAND gate 20-27 D flip-flop 28-30 D flip-flop 31-38 AND gate

Claims (1)

(57) [Claims] 1. A vertical synchronizing signal is input to one of an input terminal pair.
The horizontal input from the other of the input terminal pairs at each arrival
Reset pulse and preset pulse in response to the synchronization signal
Reset presets that output individual signals to output terminal pairs
A pulse generator, m pieces of input to the input terminal (m is an arbitrary integer) and <br/> field counter for outputting sequentially output terminal count signal of the vertical synchronizing signal of the last stage output terminal a structure for feeding back a signal to the first stage input terminal, the input terminal from the reset preset pulse generator
The reset pulse given to one of the
The preset that is set and given to the other of the input terminal pairs
Clock input from the state preset by
A signal obtained by shifting n-bit (n is an arbitrary integer) data by using a horizontal synchronization signal applied to the input terminal as a clock input
A shift register for output to the final stage output terminal, only selectively preset pulses by decoding the output of the previous SL field counter to 1 bit corresponding to the output of the field counter in the n bits of said shift register A decoder to be supplied, and a thinning-out operation in which one horizontal synchronizing signal is invalidated at different positions in m fields for the n horizontal synchronizing signals by inputting a final stage output terminal signal and a horizontal synchronizing signal of the shift register. And a logic gate for outputting a horizontal synchronizing signal.