JP3264921B2 - Data transfer control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transfer control technique and a technique particularly effective when applied to a data transfer method between a memory and an input / output device (I / O). It relates to technology that is effective for chip microcomputers and direct memory access (DMA) controllers.

[Conventional technology]

In a data processor system, between memory and input / output devices (I / O) without the intervention of a central processing unit (CPU),
For example, as a device that can directly transfer data,
A direct memory access (DMA) controller is provided.

DMA controllers are JP-A-59-53928, JP-A-61
-198351, JP-A-63-29868, JP-A-63-163560 and J
Various systems are proposed as disclosed in P-A-1-50153 and the like. In the DMA transfer method of these Japanese Patent Publications, data transfer is continuously performed for the number of times corresponding to the value of the transfer word count data stored in the transfer word count (transfer count or length) register for one transfer request. It is a method that is performed.

[Problems to be solved by the invention]

However, the conventional DMA controller simply transfers data between specific addresses at a higher speed than the CPU simply transfers data by using an instruction. As shown in FIG. Cannot transfer two data DATA1 and DATA2 at positions separated from each other by one transfer request. Therefore, DMA transfer cannot be used for complicated control of peripheral I / O such as ports.

For example, when it is desired to output a predetermined waveform pulse from a port of the CPU, it can be realized by periodically writing to the port using DMA transfer. Generally, a timer interrupt request is used for the DMA transfer request. In this case, in response to a transfer request from the timer, the DMA controller must write the data to the port and reset the conditions including clearing the timer flag.
However, the conventional DMA controller cannot realize pulse output control by DMA transfer because only one transfer can be realized for one transfer request.

An object of the present invention is to provide a data transfer method with improved transfer efficiency.

Still another object of the present invention is to provide a direct memory access controller and a single-chip microcomputer capable of realizing a data transfer method with improved transfer efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application is as follows.

That is, the data transfer method of the present invention is a data transfer method capable of realizing data transfer of an integral multiple of the value set in the transfer count register. For example, the decimal 10
Is set in the transfer count register,
It is possible to transfer 10 × n (n is an integer) data.

In order to realize such a transfer method, a direct memory access controller and a single-chip microcomputer according to the present invention include a transfer source address register for holding a transfer source address and a transfer destination address register for holding a transfer destination address. Are a pair of address register groups, a plurality of such address register groups are included. Further, the direct memory access controller or the microcomputer includes a transfer count register and a control register for designating a transfer mode. The control register includes therein a control bit (flag) for identifying the transfer mode. Bit). This control bit has a set state, ("1") and a clear state ("0"). When it is set, it specifies data transfer according to the present invention, and it is cleared. If so, specify conventional data transfer. Each of the registers described above can be configured by a static flip-flop circuit or the like, or can be set to a predetermined address in a semiconductor memory.

One example of the data transfer method according to the present invention is as follows. To simplify the description, it is assumed that the direct memory access controller includes first and second transfer source address registers, first and second transfer destination address registers, transfer count registers, and control registers. For example, when the direct memory access controller receives a data transfer request, first, first data to be transferred is read from, for example, an address of the semiconductor memory indicated by the first transfer source address data set in the first transfer source address register. At the same time, the first transfer source address data is updated. Next, the first data is written into, for example, a first data register indicated by the first transfer destination address data set in the first transfer destination address register, and the first transfer destination address data is updated. afterwards,
The state of the transfer mode designation control bit in the control register is checked.

If the control bit is set, the second data to be transferred is read out from the address of the semiconductor memory indicated by the second transfer source address data in the second transfer source address register and the second data is read out. 2 The transfer source address data is updated. Next, the second data is stored in the second transfer destination address register.
The data is written into, for example, the second data register indicated by the transfer destination address data, and the second transfer destination address data is updated. Then, the value of the count data set in the transfer count register is decremented by 1, and the process proceeds to the next data transfer.

If the control bit is in the clear state, the data transfer based on the second transfer source and second transfer destination address registers is not performed, and the value of the count data set in the transfer count register is decremented by one. Then, the process proceeds to the next data transfer. This data transfer is the same as the conventional data transfer.

(Operation)

Therefore, as shown in FIG. 5 (B), two data DATA1 and DATA2 at address positions separated from each other on the memory address space can be transferred by one transfer request. Therefore, DMA transfer can be used for complicated control of peripheral I / O such as a port.

For example, when a predetermined waveform pulse is output from an output port of a single-chip microcomputer, the data is periodically written to the data register of the output port using the DMA transfer of the present invention, so that the predetermined waveform pulse is output. Output can be realized. A timer interrupt request is used for such a DMA transfer transfer request. In this case, in response to one transfer request from the timer, the DMA controller must write the data to the internal registers of the output port and reset the conditions including the timer flag clear operation. The data transfer method according to the invention is effective.

〔Example〕

FIG. 1 shows a data processor system including a direct memory access controller (DMAC) according to the present invention.

The data processor system includes a memory device 20 for storing programs and data, a central processing unit (CPU) 10 for executing a program in the memory device 20 and performing predetermined data processing, and a time interval required for the data processor system. Timer module 21 for generating
And DMAC100. These circuits 10, 20, 21, 100 are connected via a system address bus 110 and a system data bus 115.

The DMAC 100 includes a bus & timing control circuit 1, a control register 2, a transfer request count register 3, an incrementer 4, a temporary register 5, and a transfer source address register 6a.
6b, transfer destination address registers 7a and 7b, an address bus 8, and a data bus 9.

The bus & timing control circuit 1 is provided with data transfer request signals DRQ1, DRQ from the CPU 10 or the input / output (I / O) device 30.
Upon receiving the interrupt request signal TIR from Q2 or the timer 21, the priority is determined and the control signal CN is received.
According to the state of T, the bus right is acquired from the CPU 10 which is regarded as the bus master, and the acknowledgment signal DACK is transmitted to the CP which is regarded as the bus master.
Operates to output to U10. As a result, the DMAC 100 is brought into a data transfer start state by acquiring the bus right, and the bus & timing control circuit 1 starts data transfer control. That is, the bus & timing control circuit 1 has the function of a bus arbiter. The control register 2 is a register for designating the data transfer mode and the size of the transfer data. The transfer request count register 3 is for storing the transfer request count. Register. The incrementer 4 is provided for updating the number of transfers or updating (incrementing and decrementing) the transfer address.
It is provided to temporarily hold data read from the O device.

The transfer source address registers 6a and 6b are registers for designating addresses where data to be transferred are stored, and can store different addresses.

The transfer destination address register 7a specifies a transfer destination address of the data stored at the address specified by the transfer source address register 6a. The transfer destination address register 7b specifies a transfer destination address of the data stored at the address specified by the transfer source address register 6b.

The control register 2 is a 16-bit register, configured as shown in FIG. 2, and includes the following control bits.

Control bit SZ1 indicates the size of data to be transferred in a data transfer operation performed using transfer source register 6a. For example, when SZ1 is set to the clear state “0”, 8-bit (1 byte) data is stored at the address specified by the address data in the transfer destination register 7a. When SZ1 is set to "1", 16-bit (one word) data is stored at the address indicated by the contents of the register 7a.

The control bit SI1 is the source address register 6a
Specifies whether or not to increment the address data stored in. When SI1 is cleared to “0”,
The address data in the register 6a is not incremented, and the data transfer in the fixed source address mode is performed. When SI1 is set to "1" and SZ1 is cleared to "0", register 6a
Is updated by the incrementer 4 by +1. SI1 is set to “1” and SZ1
Is set to "1", the address data in the register 6a is incremented by +2 after the data transfer is completed.
Will be updated by

The control bit DI1 is set in the transfer destination address register 7
Specifies whether to increment the address data in a. When DI1 is cleared to “0”, register 7a
Is not incremented, and data transfer in the destination address fixed mode is executed. When DI1 is set to "1" and SZ1 is set to "0", the address data in the register 7a is updated by +1 by the incrementer 4 after the data transfer is completed.
When DI1 is set to "1" and SZ1 is set to "1", the address data in the register 7a is updated by +2 by the incrementer 4 after the data transfer is completed.

The control bit FG1 is a flag characterizing the present invention, and the transfer source and transfer destination address registers 6b and
Specifies whether or not the data transfer based on 7b is to be executed after the data transfer based on the transfer source and transfer destination address registers 6a and 7a is completed.

Control bit SZ2 indicates the size of data to be transferred in a data transfer operation performed using transfer source register 6a. For example, if SZ2 is set to the clear state "0", 8-bit (1 byte) data is stored at the address specified by the address data in the transfer destination register 7b. When SZ2 is set to "1", 16-bit (one word) data is stored at the address indicated by the contents of the register 7b.

The control bit SI2 is set in the transfer source address register 6
Specifies whether to increment the address data stored in b. When SI2 is set to the clear state “0”, the address data in the register 6b is not incremented, and the data transfer in the fixed source address mode is executed. When SI2 is set to "1" and SZ2 is set to "0", the address data in the register 6b is updated by +1 by the incrementer 4 after the data transfer is completed. When SI2 is set to "1" and SZ2 is set to "1", the address data in the register 6b is updated by +2 by the incrementer 4 after the data transfer is completed.

The control bit DI2 is set in the transfer destination address register 7.
Specifies whether to increment the address data in b. When DI2 is cleared to “0”, register 7b
Is not incremented, and data transfer in the destination address fixed mode is executed. When DI2 is set to "1" and SZ2 is set to "0", the address data in the register 7b is updated by +1 by the incrementer 4 after the data transfer is completed.
When DI2 is set to "1" and SZ2 is set to "1", the address data in the register 7b is updated by +2 by the incrementer 4 after the data transfer is completed.

The control bit FG2 is a flag which characterizes the present invention similarly to the control bit FG1.

The clear state “0” of the control bit FG1 defines execution of only data transfer based on the transfer source address register 6a and the transfer destination address register 7a. The set state “1” of the control bit FG1 is the source address register 6
After the completion of the data transfer based on the transfer destination address register 7a and the transfer destination address register 7a, the data transfer based on the transfer source address register 6b and the transfer destination address register 7b is defined.

On the other hand, the clear state “0” of the control bit FG2 is
After the end of the data transfer based on the source and destination address registers 6b and 7b, the source and destination address registers
It defines that the next processing is transferred to the data transfer based on 6a and 7a. The set state "1" of the control bit FG2 is determined by, for example, setting the 7th to 5th bits of the control register 2 shown in FIG. 2 to SZ1 (SZ2) and SI1 (SI
2) and DI1 (DI2) are defined in the same manner, and the third transfer source and third transfer destination address registers are
When provided in the DMAC 100, it is defined that after the data transfer based on the transfer source and transfer destination address data 6b and 7b, the data transfer based on the third transfer source and third transfer destination address register is performed. Therefore, in the DMAC 100 as shown in FIG. 1, the set state "1" of the control bit FG2 is prohibited. In FIG. 2, "-" of the 7th bit to the 0th bit indicates a state that is undecided.

The decrement timing of the transfer request count data stored in the transfer request count register 3 is controlled by the state of the control bits FG1 and FG2. FG
If 1 is set to the clear state "0", after the data transfer based on the transfer source and transfer destination address registers 6a and 7a is performed once, the count data is decremented by -1 by the incrementer 4. . When FG1 is set to "1" and FG2 is cleared to "0", the data transfer and the source and destination address registers based on the source and destination address registers 6a and 7a
After the data transfer based on 6b and 7b is performed one by one continuously, the data of the number of times is decremented by -1 by the incrementer 4.

Therefore, when the FG1 is in the clear state "0", the data in the transfer request count register 3 is decremented at the timing shown in FIG. In the drawing, the portion indicated by A indicates data transfer based on the transfer source and transfer destination address registers 6a and 7a.

On the other hand, when FG1 is set to “1”, the seventh
At the timing shown in the figure, the transfer request count register 3
Is decremented. In FIG. 7, a portion indicated by A indicates data transfer based on the registers 6a and 7a, and a portion indicated by B indicates data transfer based on the registers 6b and 7b.

The bus & timing control circuit 1 regards the state of each control bit of the control register 2 set in an arrangement as shown in FIG. 2 as a control code, sequentially reads and decodes the state from the left side, and increments the incrementer 4 and the address register 6a. , 7a and 6b, 7b, the temporary register 5 and the like are sequentially output. Thereby, data transfer is performed.

Next, a description will be given of an operation procedure when the DMA controller 100 executes the conventional data transfer as shown in FIG. 5A and the data transfer between independent addresses as shown in FIG. 5B.

When executing such data transfer, the CPU 10 writes the corresponding transfer mode in the control register 2 in the DMA controller DMAC immediately before the start of transfer or at the time of initialization, and sets the transfer request count in the transfer request count register 3 and the transfer request count in the transfer request count register 3. The transfer source address data SA1 and SA2 are stored in the address registers 6a and 6b and 7b, respectively.
Are respectively set to the address data DA1 and DA2 of the transfer destination. In the case of the data transfer destination as shown in FIG. 5 (A), since the registers 6b and 7b are not used, the data SA
2, Writing of DA2 is not performed.

When the bus & timing control circuit 1 receives the transfer request DRQ1 from the CPU 10 or the interrupt request TIR from the timer module 21, the bus & timing control circuit 1 acquires the bus right from the CPU 10, which is the bus master. And
The bus & timing control circuit 1 includes the control register 2
The codes (SZ1, SI1, DI1) are sequentially read and decoded from the left side, and first, address data SA1 in the first transfer source address register 6a is output onto the address bus 8, and
Assert the read / write signal R / W to the read state “H” to access the read-side device (the memory 20 in this case). Thus, for example, 1-byte data DATA1 read from the memory 20 is temporarily stored in the temporary register 5 via the data bus 9. Next, the DMA controller outputs the address data DA1 in the first transfer destination address register 7a onto the address bus 8, and changes the read / write signal R / W to the write state (“L”) to change the write side (“L”). For example, the data register in the timer module is accessed, and the data DATA1 in the temporary register 5 is accessed.
Is output on the data bus 9. And control register 3
Depending on the state of the control bits SI1 and DI1, the address data SA1 and DA1 of the registers 6a and 7a may or may not be incremented. Thus, the first data transfer based on the transfer source and transfer destination address registers 6a and 7a is completed.

Next, the bus & timing control circuit 1 checks the flag FG1 in the control register 2 and terminates the transfer if it is in the clear state "0". The count data in the register 3 is decremented by -1 by the incrementer 4, and Written in register 3. Therefore, data transfer as shown in FIG. 5A is performed. On the other hand, if the flag FG1 is set to "1", the code (SZ2, SI2, DI2) next to the flag FG1 is read and the second transfer is started. That is, first, the address SA2 in the second transfer destination address register 6b is output to the address bus 8, and for example, 1-byte data DATA2 is read from the memory and put into the temporary register 5, and then the second transfer destination address register
7b, the address DATA2 is output, and the temporary register 5 is stored in the control register in the desired timer module 21.
Write the data DATA2 in. Then, the bus & timing control circuit 1 checks the flag FG2. If the flag FG2 is in the clear state "0", the bus right is released, the transfer is completed, and the count data in the transfer request count register 3 is sent to the incrementer 4. After decrement (−1), the data is written to the original register 3.

In this way, the DMAC 100 repeats data transfer each time the interrupt request DRQ1, 2 or TIR is input, and when the value of the transfer request number register 3 becomes "0", the DMAC 100 notifies the CPU 10 to that effect. CPU 10 sets transfer source address register 6
The data to be transferred to the I / O device is changed by rewriting the address data of a, 6b, 7a and 7b, and the values of the count register 3 and the control register 2 are reset.

The data transfer method as shown in FIG. 5B can be used particularly when a pulse having a predetermined waveform is output from an external terminal of a single-chip microcomputer. In this case, it is considered that the internal region surrounded by the two-dot chain line in FIG. 1 is formed in one single crystal semiconductor substrate (chip) such as silicon, and the wiring X and the external terminal Y exist. Will be considered. Although no external terminals other than the external terminal Y are shown in the drawing, those skilled in the art can easily understand that an actual single-chip microcomputer has a plurality of external terminals other than the terminal Y. Would.

 Hereinafter, a method of using data transfer according to the present invention will be described.

First, the timer module includes a free running counter (FRC) 200 as shown in FIG. The FRT 200 receives the clock signal φ inside and counts the number of clocks
A free running counter FRC202 constituted by a 16-bit up counter, an output compare register (OCR) 204 for storing data to be compared with the count value of the above FRC202, and a value of each of the above FRC and OCR. A comparison circuit (COMP) 206 for comparing and outputting a coincidence signal C when both coincide, a timer control register (TCR) 208 and a timer control / status register (TCSR) 208 for controlling the operation of the FRT, and a timer control logic. (TCL) 212. FRC, OCR, TCR and T above
CSR is a readable / writable register.
The read operation and the write operation are controlled by a read / write signal (R / W). In addition, FRC, OCR, TCR and
Each TCSR is coupled to the data bus 110,
Selection is made selectively by selection signals SEL0 to SEL3 output from an address decoder 214 that decodes an address signal on the address bus 115.

The TCR 208 internally has an output enable flag for specifying whether to permit output of the output compare signal FTO, and instructing whether to permit the output of the timer interrupt request TIR when the match signal C is generated from the COMP 206. Output interrupt enable flag. The TCSR 210 includes an output level control flag for designating the output level of the output compare signal FTO by the coincidence signal C.

When the output compare enable flag is set to “1”, the TCL 212 outputs the match signal C to the COMP20.
Upon receiving from step 6, it operates to output an FTO signal having the output level specified by the output level control flag. When the output level control flag is set to the clear state "0", the FTO signal is set to the D-level, and when the flag is set to the set state, the FTO signal is set to the high level. TCL212 above
When the output interrupt enable flag is set to "1" and the above match signal is received, it operates to output, for example, a high-level TIR signal.

FIG. 8 exemplarily shows, for example, a stepping motor 302 in the printer 300 as a controlled device controlled by the FRT. That is, an example is described in which the rotation speed and / or the torque of the motor 302 is controlled by the FTO signal.

FIG. 9 shows the order of data transfer and the relationship between the address space of the single-chip microcomputer and the order of data transfer. In this data transfer, DMAC
The control register 2 and the source and destination address registers 6a, 6b, 7a7b in 100 are initialized as shown in Table 1, and each time a timer interrupt (TIR) is input to the DMAC. To the data transfer destination Is being executed.

FIG. 10 shows the relationship between the operation waveform diagram of the data transfer FRT200 shown in FIG. 9 and the output level of the FTO signal.

In the figure, the thick solid line indicates the count-up state of the FRC 202, the two-dot chain line indicates the value of the OCR 204, the two-dot chain arrow indicates a change in the value of the OCR 204, and the dotted line indicates the contents of the OCR 204 and the count of the FRC 202. The value coincidence point, that is, the timing at which the TIR is output, and FTO indicates the output level of the FTO signal output from the external terminal Y. For ease of understanding, the figure shows the time distribution between the operation period of the CPU 10 and the data transfer period. The CPU operation period is indicated as CPU EX., Which indicates that the CPU 10 is executing the data processing program. ,... Indicate data transfer, J indicates an increment operation of the address of the address register 6b, and K indicates a decrement operation of the count register 3.

As a result, it is possible to output a predetermined waveform pulse (FTO) from the external terminal Y of the single-chip microcomputer, and change the pulse width after outputting the pulse a desired number of times. Therefore, if this is used for forming a control pulse of the step motor 302, it is possible to control the step motor 302 so that the degree of rotation gradually increases at first, and then becomes constant at a certain speed. Will be easily understood by

In the above embodiment, only one control register 2 is provided. However, a set of the control register 2 and the transfer destination and transfer source address registers 6a to 7b is provided for a plurality of channels, and a plurality of independent data transfer is performed. May be performed.

Further, a transfer number register for setting the number of words to be transferred or the like may be provided instead of or together with the transfer request number register 3, and the number of transfers in block transfer or the like may be entered.

Next, an embodiment in which the present invention is applied to a single-chip microcomputer so that the data transfer can be realized by a microprogram will be described.

FIG. 3 shows an example of the configuration of a single-chip microcomputer 102 to which the present invention is applied, and FIG. 4 shows an example of a microprogram control procedure for enabling data transfer between memory I / Os. ing.

In FIG. 3, reference numeral 11 denotes a microprocessor comprising a control unit of a microprogram control system and an execution unit including a computing unit and registers, 12 a programmable internal timer, 13 a timer interrupt TIR and an interrupt request IRQ from an external device. An interrupt control circuit 14 that receives the request and determines the priority order is a bus & timing control circuit including a bus arbiter function for acquiring a bus right and forming a control signal for an external device.

15 is an output port, 16 is an address decoder DEC
In this embodiment, two data registers DR for controlling the output state are provided in the port 15. The data registers DR1 and DR2 are cascaded, and the first-stage data register DR1 reads data on the data bus 19 by a control signal from the CPU 11, and the second-stage data register DR2 is a signal CM from the timer 12. Is configured to take in the data in the data register DR2 of the first stage.

Further, in this embodiment, the control register 2 shown in FIG. 1, the transfer request number register 3 and the transfer source are stored in a predetermined address area in an external memory (RAM) 20 connected to the address bus 18 and the data bus 19. Address register 6
a, 6b and transfer destination address registers 7a, 7b are allocated to execute data transfer between the memory 20 and the I / O by a microprogram control flow as shown in FIG.

Next, a procedure for transferring data from the external memory 20 to the register of the port 15 by a timer interrupt and outputting a predetermined pulse will be described with reference to the flowchart of FIG.

Timer interrupt from timer 12 to interrupt control circuit 13
When the TIR is input, the interrupt control circuit 13 sends a bus request signal BR to the bus & timing control circuit 14. The bus & timing circuit 14 acquires the bus right and outputs an acknowledge signal ACK to the CPU 11. CPU 11 interrupts data transfer (DTCIR
It is determined whether the interrupt is Q) or another interrupt (step S1). In the case of the data transfer interrupt DTCIRQ, the process proceeds to step S2, where the interrupt vector (DTC
Vector), that is, the CPU 11 reads the address of the control register 2 contained in the memory 20, and accesses the memory 20 using the address to access the contents of the control register 2 (transfer mode (SZ1, SI1, DI1), etc.). Is read (step S3). Then, the CPU 11 decodes the data size (SZ1) and the transfer mode (SI1, DI1), first reads the source address stored in the address of the memory 20 as the transfer source address register 6a, and reads the source address. Output on the address bus 18, thereby
Reads the data to be transferred by accessing the memory 20 (steps S4 and S5). Then the CPU goes to the above steps
It is determined whether the transfer source address should be updated based on the transfer mode (SI1) read in S3 (step S6). Port 15
If you want to output more motor drive pulses,
Since the output state needs to be inverted each time the timer interrupt TIR occurs, the transfer source address is incremented or decremented. In this case, steps S6 to S7
Then, the source address is incremented by one or two in accordance with the size designation section (SZ1), and is written to the source address register 6a. (Step S8).

Then, the CPU 11 reads the destination address stored in the transfer destination address register 7a in the memory 20 and outputs the destination address onto the address bus 18. At this time, the data to be transferred read in step S5 is output onto the data bus 19 (steps S9 and S10). When the destination address output on the bus 19 designates the port 15, the selection signal SEL1 of the data register DR1 in the port 15 is formed by the decoder 16, and the data on the bus 19 is transferred to the data register DR1. Is stored in

Thereafter, it is determined whether or not to update the transfer destination address based on the transfer mode DI1 read from the control register 2 in step S3 (step S11). When the output port is controlled by a timer interrupt, the transfer destination address is fixed. In this case, the process jumps from step S11 to S14, and the end flag FG1 in the control register 2 is set to “1” or “1”.
Is checked. When FG1 is "1", the process returns to step S4 to start the second transfer. In the second transfer, data for setting the time register (OCR in FIG. 8) (corresponding to the pulse width) in the timer 12 using the address registers 6b and 7b in the memory 20 is stored in the memory 20. Steps S4 to S14 are repeated to transfer from. In this case, when changing the rotation speed of the motor, the process proceeds from step S6 to S7 to update the transfer source address, and when the rotation speed is kept constant, the transfer source address may not be updated.

When the second data transfer is completed, the end flag FG2 is checked. If the clear state is “0”, the process proceeds to step S15, and the contents of the transfer request count register 3 (DTC
R) is read and decremented before register 3
The decremented value is written in the address (steps S16 and S17). Thereafter, it is determined whether or not the value of the register 3 (the number of transfer requests DTCR) has become "0" (step S1).
8) If it is not "0", wait for the next timer interrupt TIR as it is, and when the timer interrupt TIR is received, repeat the above steps S1 to S18, and perform port 15 in the same transfer mode.
Control the output state of

On the other hand, if it is determined in step S18 that the number of transfer requests has become “0”, the flow shifts to step S21 to start another interrupt process. In the case of controlling the drive pulse of the motor output from the port 15, the transfer mode can be changed by rewriting the control register 2 by this interrupt processing.

By such a procedure, for example, the pulse width is gradually increased from the start of rotation of the step motor to the 1000th pulse to gradually increase the rotation speed, and thereafter, the pulse width, that is, the rotation speed is kept constant. It is possible to control the motor so as to continuously output a pulse having a constant pulse width.

In the single-chip microcomputer of the above embodiment, the control register 2 and the transfer source and transfer destination address registers 6a to 7b are prepared in the external memory 20, but when the single-chip microcomputer has a built-in RAM, Needless to say, it may be prepared in such a case.

As described above, in the above embodiment, the set of the address register capable of setting the transfer source address and the transfer destination address is two.
A bit (FG1) for distinguishing between a transfer mode using only one of the address register sets and a transfer mode using both of the above address register sets is provided in a control register prepared for designating a transfer method. Since the control signal for data transfer is formed while decoding the control code of the control register, the transfer source address and the transfer destination address can be set two by two. Data transfer between independent addresses becomes possible. Further, since a bit (FG1) for distinguishing between one-time transfer and two-time transfer is provided in the control register, in addition to the above-mentioned two-time transfer newly enabled, one-time transfer in the conventional one-time transfer request. This has the effect that the function of the DMA controller that performs the transfer twice can be guaranteed.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the first embodiment, the DMA controller formed on a separate chip from the CPU has been described. However, the present invention can be applied to a DMA controller built in a single-chip microcomputer.

In the above description, the invention made by the inventor was mainly applied to a DMA controller and a single-chip microcomputer, which are the fields of application that served as the background. However, the present invention is not limited to this. It can be generally used for semiconductor circuits having functions.

〔The invention's effect〕

The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

In other words, it is possible to provide a DMA controller that can perform data transfer between two special addresses twice with one transfer request.
The output control of the pulse by the transfer becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a DMA controller, FIG. 2 is a diagram showing a configuration example of a control register, and FIG. 3 is an application of the present invention to a single-chip microcomputer. FIG. 4 is a flowchart showing a data transfer control procedure by a microprogram, FIG. 5 (A) is a memory map showing a data transfer method by a conventional DMA controller, and FIG. FIG. 6B is a memory map showing a data transfer method by the DMA controller of the present invention. FIG. 6 shows the decrement timing of the count register when the control bit FG1 is set to "0". FIG. 8 shows the configuration of the free running counter and the controlled device. Shown, FIG. 9 shows a sequence of data transfer, FIG. 10 shows an operation waveform diagram in the data transfer of Figure 9. 11: Microprocessor, 15: Port, 16: Decoder, DR1, DR2: Data register.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-267847 (JP, A) JP-A-2-72464 (JP, A) JP-A-2-259861 (JP, A) JP-A-54-267 124644 (JP, A) JP-A-2-176844 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/28

Claims (3)

(57) [Claims] A first storage unit for storing a first transfer source address; a second storage unit for storing a first transfer destination address; a third storage unit for storing a second transfer source address; A fourth storage unit for storing a second transfer destination address, a fifth storage unit for storing transfer request count data, and a control unit for controlling data transfer, the control unit comprising: A first control bit for controlling the first data transfer using the second storage means; a second control bit for controlling the second data transfer using the third and fourth storage means; A third control bit indicating that the first data transfer is repeatedly performed, and the other state has a third control bit indicating that the first and second data transfers are respectively performed continuously once each; 3rd control When the unit is in one of the above states,
The first data transfer is performed a number of times indicating the number of transfer requests, and when the third control bit is in the other state,
A data transfer control device, wherein the continuous transfer of the first and second data transfer is performed a number of times indicating the number of transfer requests. 2. The method according to claim 1, wherein the number of transfer requests is equal to the first number when the third control bit is in one state.
After the data transfer is performed, the value is decremented by one, and when the third control bit is in the other state, the first
And a data transfer control device which is decremented by one after the second data transfer is continuously performed. 3. The data transfer control device according to claim 3, wherein the data transfer control device includes a central processing unit.
A data transfer control device built in a chip data processor, comprising: a first operation in which the data transfer control device responds to a data transfer request; and a second operation in which the central processing unit responds to a data transfer request. .