JP3263980B2 - Identification signal discriminating apparatus, television receiver and video tape recorder including the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for determining an identification signal inserted in a specific line in a vertical blanking period of a video signal, and a television receiver and a video tape recorder having the same.

[0002]

2. Description of the Related Art Hi-vision test broadcasting has started, and television receivers capable of receiving high-vision broadcasting have begun to be put into practical use. However, a full-fledged high-vision receiver that restores a signal transmitted by the MUSE method to a high-vision baseband signal by a MUSE decoder and displays the signal on a high-definition monitor having an aspect ratio of 16: 9 and 1125 scanning lines is expensive. .

[0003] Therefore, a television receiver has been commercialized which converts a signal transmitted by the MUSE system into the NTSC system and displays it on a monitor so that high-definition broadcasting can be received at a low price. This includes a television receiver (hereinafter, referred to as wide vision) for displaying on a monitor having the same aspect ratio of 16: 9 as a high-vision receiver, and a television receiver (hereinafter, normal) for displaying on a monitor having an aspect ratio of 4: 3. Vision). However, the signal transmitted in the MUSE system is
The converted video signal is a video signal having an aspect ratio of 16: 9 (hereinafter, referred to as a 16: 9 video signal), so that an image having an accurate shape is displayed in wide vision, but a vertically long image is displayed in normal vision. Is displayed.
In order to display an image of an accurate shape in normal vision, blank portions are formed at the top and bottom of the screen with about 350 scanning lines (letterbox method). On the other hand, when a video signal having an aspect ratio of 4: 3 (hereinafter referred to as 4: 3 video signal) as in the current NTSC system is received, an image is displayed in an accurate shape in normal vision, but in wide vision. Unless the screen is enlarged by forming a blank portion on both sides of the screen or performing an aspect ratio conversion process, it is impossible to display an accurate shape.
FIG. 22 illustrates this situation.

Further, the aspect ratio of wide vision is 1
In order to utilize a 6: 9 monitor, it is mainly a VTR that an NTSC video signal is converted to a 16: 9 video signal.
Etc. are considered for package media. As described above, at present, wide vision having a monitor having an aspect ratio of 16: 9 and normal vision having a monitor having an aspect ratio of 4: 3 are mixed. Also, the video signal is a mixture of the 4: 3 video signal and the 16: 9 video signal. Then, as described above, in the television receiver, whether the input video signal is a 4: 3 video signal or not.
It is necessary to switch the signal processing depending on whether it is a 6: 9 video signal.

Accordingly, an identification code indicating the category of the video signal is inserted into a specific line in the vertical blanking period of the video signal, and the television receiver determines the identification code and performs signal processing according to the category of the video signal. There has been proposed a system for performing the above. FIG. 23 shows an identification signal used in this system, which is inserted at 20H and 283H in the vertical blanking period, and is composed of a reference signal and subsequent 20-bit data. The reference signal indicates that this waveform is an identification signal, and is composed of, for example, three bits of “010”. The data is composed of a 14-bit identification code and a 6-bit CRCC code. The identification codes include the following. (1) A squeeze mode signal indicating that the video signal is a 16: 9 video signal. (2) A letterbox signal for displaying an entire image when displaying an image having a certain aspect ratio on a screen having a smaller aspect ratio. (3) Letterbox signals with different aspect ratios (1:
1.8 to 9:16 Vista Vision size, 1: 2.2
Letterbox size signal identifying 〜1: 2.35 cinemascope size). (4) Panning information indicating which part of both sides of the screen to cut when displaying an image with a certain aspect ratio on a screen with a smaller aspect ratio.

A television receiver having a monitor with an aspect ratio of 16: 9 can perform appropriate signal processing corresponding to a category of a video signal by detecting and discriminating such an identification code.

[0007]

However, in the above-mentioned conventional system, the reference signal in the identification signal inserted into a specific line in the vertical blanking period of the video signal is determined, and the identification code in the data is subsequently determined. Since it is configured to make the determination, there are the following problems. (1) In the method of determining “High” (hereinafter abbreviated as “H”) and “Low” (hereinafter abbreviated as “L”) of a signal based on the level of the signal at a certain time, noise and the like are mixed. In this case, there is a high probability that the signal is erroneously determined as a normal reference signal. Assuming that the probability that the discrimination becomes “H” or “L” due to noise at the time of adopting the signal is １ ／, when a ³ -bit signal is used for discriminating the signal, 1/2 ³ = １ ／.
The noise is regarded as a legitimate signal by the establishment of. If the number of bits used for discrimination is increased in order to improve the accuracy of discrimination, the number of bits usable for data decreases accordingly. (2) The number of lines is determined from the vertical synchronizing signal and the horizontal synchronizing signal to prevent erroneous reading of signals other than the identification signal inserted into a specific line in the vertical blanking period of the video signal. It is proposed to read only the lines.

However, when the video signal having the identification signal inserted therein is recorded and reproduced on the VTR, and during the special reproduction, a pseudo vertical synchronization signal is inserted. The determination cannot be made, and the signal or noise of another line is read, or the identification signal is read. If the identification code cannot be determined correctly, it becomes impossible to perform appropriate signal processing corresponding to the category of the video signal. become. (3) It has been proposed to always monitor the range of the line in which the identification signal is considered to move in anticipation of the special reproduction, even during the normal reproduction. In order to distinguish the signals, a large amount of reference signals must be included in the identification signal, and the section that can be used for transmitting information becomes short.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an identification signal discriminating apparatus which can solve the above-mentioned problems and can increase the accuracy of discriminating a reference signal without reducing the number of bits used for data. Further, the present invention can be applied to a case where the vertical synchronization signal is not a normal one, that is, when the relationship between the vertical synchronization signal and the horizontal synchronization signal in the vertical blanking period of the video signal is different from the normal state. It is an object of the present invention to provide an identification signal discriminating apparatus which does not read the read data. It is another object of the present invention to provide an identification signal discriminating apparatus which does not drop data even when the vertical synchronization signal is not a proper one. Still another object of the present invention is to provide a television receiver capable of avoiding an unpleasant state such as a change in a screen aspect ratio in a short time even when a vertical synchronization signal is not a regular signal. I do. It is another object of the present invention to provide a video tape recorder capable of inserting correct data into a recorded video signal or a reproduced video signal even when a vertical synchronizing signal at the time of trick play or the like is not proper.

[0010]

According to a first aspect of the present invention, a reference signal having a predetermined bit and a data following the reference signal are inserted into a specific line in a vertical blanking period of a video signal. In the apparatus for discriminating an identification signal comprising: a means for detecting that the level within one bit of the reference signal is not inverted. According to a second aspect of the present invention, there is provided an apparatus for determining an identification signal inserted into a specific line in a vertical blanking period of a video signal and comprising a reference signal of predetermined bits and data subsequent to the reference signal, the apparatus comprising: A first means for separating the horizontal synchronization signal, a second means for temporarily storing the data for each vertical synchronization signal, and a determination as to whether the vertical synchronization signal separated by the first means is normal. The third means and the data temporarily stored in the second means are fetched and stored when the result of the determination by the third means is normal, and the data is fetched when the result is not valid. And a fourth means that does not perform the processing.

Further, the third invention is the third invention, wherein the third invention is the third invention.
Means is configured to determine whether the vertical synchronization signal is normal based on the number of horizontal synchronization signals within the vertical synchronization signal period. According to a fourth aspect of the present invention, in the second aspect, the third means determines whether or not the vertical synchronization signal is valid based on the length of the vertical synchronization signal period. According to a fifth aspect of the present invention, there is provided an apparatus for determining an identification signal which is inserted into a specific line in a vertical blanking period of a video signal and includes a reference signal of a predetermined bit and data following the reference signal, the apparatus comprising: First means for separating the horizontal synchronization signal, second means for temporarily storing the data for each vertical synchronization signal, and third means for determining whether the reference signal or the data is normal. A fourth means for judging the specific line from the vertical synchronizing signal and the horizontal synchronizing signal separated by the first means, and a line for which the third means judges a legitimate reference signal or data and the fourth means. A fourth means for fetching and storing the data temporarily stored in the second means when the discriminated line coincides with the specific line. .

Further, a sixth invention is an apparatus for determining an identification signal which is inserted into a specific line in a vertical blanking period of a video signal and comprises a reference signal of a predetermined bit and data following the reference signal, the apparatus comprising: First means for separating a vertical synchronization signal and a horizontal synchronization signal, second means for capturing a signal of a predetermined line during a vertical blanking period of a video signal, and first and second means for separating the vertical synchronization signal and the horizontal signal separated by the first means. A third means for detecting that a normal reference signal or data does not exist on a specific line determined from the synchronization signal; and, when an output of the third means exists, a range of a line to be taken in by the second means. And means for expanding the range.

According to a seventh aspect of the present invention, an identification signal which is inserted into a specific line of a vertical blanking period of a video signal in a television receiver and includes a reference signal of a predetermined bit and data following the reference signal is determined. First
Means, a second means for performing at least a process of enlarging the image in the horizontal direction in accordance with the data determined by the first means, and a third means for displaying the image processed by the second means. It is provided.

According to an eighth aspect of the present invention, an identification signal which is inserted into a specific line of a vertical blanking period of a video signal in a video tape recorder and comprises a reference signal of a predetermined bit and data following the reference signal is determined. First means for storing data, and when the recording video signal or reproduction video signal is a video signal for special reproduction, inserting the data stored in the first means into the recording video signal or reproduction video signal And second means for performing the operation.

[0015]

According to the first aspect of the present invention, since the identification signal discriminating apparatus is configured as described above, the accuracy of discriminating the reference signal can be increased without reducing the number of bits used for data. According to the second to fifth aspects of the present invention, when the vertical synchronization signal is not a regular signal, data is not read from the third means to the fourth means when the vertical synchronization signal is not a regular signal.
Eliminates reading incorrect data. Further, according to the sixth aspect, when the vertical synchronization signal is not a regular signal,
Since the second means widens the range of the signal capture line,
Eliminates data reading errors. Further, according to the seventh aspect, it is possible to avoid an unpleasant state in which the aspect ratio of the screen changes in a short time. According to the eighth aspect, correct data can be inserted into a recorded video signal or a reproduced video signal.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a first embodiment of the present invention. The horizontal synchronizing signal H and the vertical synchronizing signal V are separated from the input video signal by the sync separation circuit 5 and output to the timing generation circuit 6. The timing generation circuit 6 generates various timing signals such as operation clocks and operation timing control signals of each circuit constituting the identification signal discriminating apparatus from the horizontal synchronization signal H, the vertical synchronization signal V, and the clock of the frequency fsc generated by itself.

The input video signal is supplied to a data reading circuit 1.
Is input to The data reading circuit 1 includes, for example, a low-pass filter, a clamp circuit, and a comparator, and removes noise in an input video signal and converts the input video signal into binary data. Then, based on the timing signal output from the timing generation circuit 6, 20 bits of the data signal in FIG.

Further, the input video signal is sent to a signal discriminating circuit 4.
Is also entered. The signal discriminating circuit 4 discriminates, based on the timing signal output from the timing generating circuit 6, whether or not a normal reference signal exists at the timing of the reference signal shown in FIG. Then, when it is determined that a normal reference signal exists at the timing of the reference signal, a read pulse for reading data from the data temporary storage circuit 2 is output to the data storage circuit 3. Here, the data storage circuit 3 is constituted by a latch or the like, and 14 bits of the identification code excluding 6 bits of CRCC are read out of the 20 bits of the data signal temporarily stored in the data temporary storage circuit 2.

The operation clock supplied from the timing generation circuit 6 to each circuit is not shown (the same applies to the following embodiments). FIG. 2 is a block diagram showing a specific configuration of the signal discriminating circuit, and FIG. 3 is an explanatory diagram of its operation. Hereinafter, the operation of this embodiment will be described with reference to FIGS. Before the data, "01" as shown in (a)
Consider a case where a reference signal “0” is added.
Assuming that the signal level is read at a level at an intermediate position of each bit of the reference signal, when noise as shown in FIG. 2B is input, there is a probability of 1/2 ³ =, as shown in FIG. Misread "010". In addition, even a signal as shown in (d) is erroneously read as "010". As described above, the method of reading a signal only at a certain point in time has a high possibility of misreading when noise and the like are mixed.

Therefore, in this embodiment, (e1) to (e3)
When the signal level read between the gate signals is different from the normal value, it is determined that the signal is not the target reference signal. The timing generation circuit 6 generates a gate pulse having a width of about 1/2 to 1/4 of one bit of the input data as shown in (e1) to (e3). AND gates (e1) to (e3) are ANDed with the input video signal by the AND circuits 41 to 43, and the RS flip-flops 45 to 47 are operated by the output. When the input video signal is inverted in the section between the gate pulses (e1) to (e3), the output levels of the RS flip-flops 45 to 47 are inverted to "H".

When the output level of at least one of the RS flip-flops 45 to 47 for judging the 3-bit section of the input data goes to the "H" side, the NOR circuit 48 goes to "L". Therefore, the read pulse (e4) for storing data in the data storage circuit 3 is supplied to the AND circuit 49.
And cannot be read. The read pulse (e4) may be generated at an appropriate timing until the next vertical synchronizing signal V arrives, for example, immediately before the start of the next video signal period.

Each of the RS flip-flops 45 to 47 is reset by a reset pulse (e5) after the read pulse (e4) and before the next data comes. As described above, in the present embodiment, it is possible to distinguish the normal reference signal from the noise and the like by determining that there is no signal inversion in a certain section by utilizing the fact that the level of the noise or the like is quickly inverted. Therefore, if the number of bits used for discrimination is the same, discrimination can be performed with higher accuracy, and if the same precision is sufficient, fewer bits are required, and the number of bits that can be used for data transmission increases.

(Second Embodiment) FIG. 4 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a second embodiment of the present invention. Here, circuits corresponding to those in FIG. 1 are given the same numbers. The description of the portions corresponding to FIG. 1 is omitted (the same applies to the following embodiments). The horizontal synchronizing signal H and the vertical synchronizing signal V separated from the input video signal by the synchronizing separation circuit 5 are simultaneously inputted to the horizontal synchronizing signal discriminating circuit 7, and the number of the horizontal synchronizing signals H in the vertical synchronizing signal period is measured. When the number of horizontal synchronization signals H measured by the horizontal synchronization signal determination circuit 7 is equal to or greater than a prescribed value, a read pulse is output from the horizontal synchronization signal determination circuit 7 to the data storage circuit 3, The 14-bit category data in the temporarily stored 20-bit data is read into the data storage circuit 3 and updated to new category data. When the number of horizontal synchronizing signals H measured by the horizontal synchronizing signal discriminating circuit 7 is equal to or less than a prescribed value, no read pulse is output, so that the data in the data storing circuit 3 is not updated and is stored as it is immediately before. .

In this embodiment, the reason for judging whether the number of the horizontal synchronizing signals H is equal to or larger than a prescribed value is as follows. Since the vicinity of the vertical blanking period of the normal video signal is as shown in FIG. 5A (the color burst signal is omitted), the normal vertical synchronization signal separated therefrom is as shown in FIG. On the other hand, at the time of trick play, a pseudo vertical synchronization signal as shown in (C) is inserted, so that the video signal is as shown in (D). The vertical synchronizing signal V and the horizontal synchronizing signal H separated therefrom are as shown in (E1). However,
Since the insertion position of the pseudo vertical synchronizing signal differs depending on the type of the VTR or the like, there may be cases where the time relationship between the vertical synchronizing signal V and the pseudo vertical synchronizing signal is (E2) to (E4).
As can be seen, when the vertical synchronizing signal V and the pseudo vertical synchronizing signal overlap as in (E1) and (E3), special reproduction is performed by counting the number of horizontal synchronizing signals H in the vertical synchronizing signal period. Can be determined. Also, (E
In the case of separation as in (2) and (E4), the number of horizontal synchronizing signals H is equal to or less than the specified value in either the preceding section or the following section. .

FIG. 6 is a block diagram showing a specific configuration of the horizontal synchronizing signal discriminating circuit, and FIGS. 7 to 10 are explanatory diagrams of the operation thereof. Hereinafter, the operation of this embodiment will be described with reference to FIGS.

(1) Normal playback (FIG. 7) Inverter 76, JK flip-flop 77, NAN
Pulses a and b corresponding to the leading and trailing edges of the vertical synchronizing signal V are generated by the D gate 78 and the AND gate 79. The counter 73 is cleared by the pulse a, and the rising edge of the horizontal synchronizing signal c gated by the vertical synchronizing signal V is counted by the counter 73.
To count. The decoding circuit 74 is a circuit that becomes “L” when a certain number (four in the figure) or more. The D-flip-flop 75 is operated by the pulse b, and the value of the output d of the counter is reflected on the output e of the D-flip-flop 75. In this case, since d is "L", e remains "H". Read pulse f generated by timing generation circuit 6
Since the output e of the D-flip-flop 75 is "H", it is transmitted as it is to the data storage circuit 3 as a read pulse. The D flip-flop 75 is cleared by the clear pulse h generated by the timing generation circuit 6 after the read pulse and before the next data comes.

(2) At the time of variable speed reproduction corresponding to (E1) and (E3) (FIG. 8) Since the number of rising edges of the pulse c is less than 4, the output d of the decoding circuit 74 does not become "L". Therefore, the output e of the D flip-flop 75 becomes “L” by the pulse b. For this reason, the read pulse f cannot pass through the AND gate 80 and is not transmitted to the data storage circuit 3.

(3) At the time of variable speed reproduction corresponding to (E2) (FIG. 9) Since the number of rising edges of the pulse c is less than four in the section of the preceding vertical synchronizing signal V, the D-flip-flop is driven by the first pulse of the pulse b. The output e of 75 becomes "L". When the output e of the D-flip-flop 75 becomes "L", the horizontal synchronization signal H cannot pass through the AND gate 71, and thereafter, the pulse c is input to the counter 73,
The output e of the D-flip-flop 75 remains "L". Therefore, the read pulse f cannot pass through the AND gate 80 and is not transmitted to the data storage circuit 3 as in FIG.

(4) At the time of variable speed reproduction corresponding to (E4) (FIG. 10) Since four or more rising edges of the pulse c are counted in the section of the preceding vertical synchronizing signal V, the output d of the decoding circuit 74 becomes "L". Become. Therefore, the output e of the D-flip-flop 75 remains at “H”, and the pulse c is counted again in the subsequent section of the vertical synchronization signal V. The number of pulses c in this section is 4
Therefore, the output e of the D-flip-flop 75 becomes “L” at the end of this section. Therefore, the read pulse f
Cannot pass through the AND gate 80 and is not transmitted to the data storage circuit 3.

(Third Embodiment) FIG. 11 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a third embodiment of the present invention. The vertical synchronizing signal V separated from the input video signal by the synchronizing separation circuit 5 is sent to the length detecting circuit 8 and its length is determined. When the length of the vertical synchronizing signal V detected by the length detection circuit 8 is equal to or less than the specified value, a read pulse is output from the length detection circuit 8 to the data storage circuit 3 and temporarily stored in the data temporary storage circuit 2. The 14-bit category data in the 20-bit data is read into the data storage circuit 3 and updated to new data.
When the length of the vertical synchronizing signal V detected by the length detection circuit 8 is equal to or longer than the specified value, no read pulse is issued, so that the data in the data storage circuit 3 is not updated and is stored as it is immediately before.

In this embodiment, the reason for judging whether the length of the vertical synchronizing signal V is greater than or equal to a prescribed value is as follows. As shown in FIG. 5, vertical synchronizing signals separated at the time of trick play are as shown in (E1) to (E4). As can be seen, in any of the cases (E1) to (E4), the length of the separated vertical synchronization signal is longer than the normal vertical synchronization signal (B). Therefore, by detecting the length of the separated vertical synchronizing signal, it can be determined that the reproduction is the special reproduction.

FIG. 12 is a block diagram showing a specific configuration of the length detection circuit. Therefore, the separated vertical synchronization signal V
Is counted as a gate signal of the gate circuit 81 by the counter 82. When the vertical synchronizing signal V shown in FIGS. 5 (E1) to (E4) is used as a gate signal, the count value (N1) of the counter 82 is a regular vertical value shown in FIG. 5 (B). It is larger than the count value of the counter 82 when the synchronization signal is the gate signal (N0). Therefore, the data comparison circuit 83 uses the counter 82
Close the gate circuit 84 outputs a level "L" when the count value N1 is (a N2) values in anticipation of the margin to N0 greater than the, N2 following gate circuit outputs a level "H" when Open 84. As a result, the read pulse is not output to the data storage circuit 3 during the special reproduction,
The data in the data storage circuit 3 is not updated, but is stored as it was immediately before.

(Fourth Embodiment) FIG. 13 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a fourth embodiment of the present invention, and FIG. 14 is an explanatory diagram of the operation thereof. The horizontal synchronizing signal H and the vertical synchronizing signal V separated from the input video signal by the sync separation circuit 5 are input to a line discrimination circuit 9. The line determination circuit 9 generates a line determination signal from the horizontal synchronization signal H and the vertical synchronization signal V. The signal discriminating circuit 4 discriminates the reference signal added to the identification signal. When the line determined by the line determination circuit 9 and the line (eg, 20 lines, 283 lines) determined by the signal determination circuit 4 to have a normal reference signal match, the read pulse output by the timing generation circuit 6 Is output to the data storage circuit 3 through the AND gate 10, and 14-bit category data in the 20-bit data temporarily stored in the data temporary storage circuit 2 is read into the data storage circuit 3. If they do not match, the read pulse is not output to the data storage circuit 3, so that no data is transferred and the data before discrimination is stored. When the signal discrimination circuit 4 discriminates that there is no data in any line, that is, when a normal 4: 3 video signal is input, the signal discrimination circuit 4
Sends a clear pulse (not shown) to the data storage circuit 3 to clear the data.

In this embodiment, the reason why the signal discriminating circuit 4 judges whether the line judged by the line discriminating circuit 9 coincides with the line judged by the signal discriminating circuit 4 to have a normal reference signal is as follows. As shown in FIG. 14, (A) and (A) near the vertical blanking period of a normal video signal.
(B) (color burst signal is omitted). The normal vertical synchronizing signal V and the horizontal synchronizing signal H separated from the video signal are as shown in (C) (only the first field is displayed. The same applies hereinafter). For example, if the identification signal is inserted in 20 lines, the line discriminating circuit 9 detects the trailing edge of the vertical synchronizing signal V, and when 16 horizontal synchronizing signals H are counted, an output is generated at the time of 20 lines. Therefore, the signal coincides with the line on which the signal discriminating circuit 4 detects the reference signal.

However, at the time of trick play, a pseudo vertical synchronizing signal as shown in FIG.
become that way. Then, the synchronization signal separated from the video signal is as shown in (F). Based on this, after the vertical synchronization signal V ends in the line discrimination circuit 9, if 16 horizontal synchronization signals H are counted, 22 Since it is the time of the line, the signal discrimination circuit 4 does not match the line for detecting the reference signal.

Therefore, the data is read into the data storage circuit 3 when the line determined by the line determination circuit 9 as described above coincides with the line determined by the signal determination circuit 4 to have a valid reference signal. Then, the category data following the normal reference signal is read into the data storage circuit 3. Instead of the signal discriminating circuit 4 in this embodiment, a circuit for checking CRCC in data or a circuit for both discriminating a reference signal and checking CRCC can be used.

(Fifth Embodiment) FIG. 15 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a fifth embodiment of the present invention. The horizontal synchronizing signal H and the vertical synchronizing signal V separated from the input video signal by the sync separation circuit 5 are input to a line discrimination / gate generation circuit 11. The line discrimination / gate generation circuit 11 discriminates a line from the horizontal synchronization signal H and the vertical synchronization signal V, and creates a gate pulse for extracting a signal of a target line. The unsteady state determination circuit 12 determines the unsteady normal state from the input video signal, the horizontal synchronization signal H, and the vertical synchronization signal V. Here, the unsteady normal state is a state in which a regular reference signal or data does not exist in a specific line determined from the horizontal synchronization signal H and the vertical synchronization signal V, and for example, from a video signal during special reproduction of a VTR. This is a case where the horizontal synchronization signal H and the vertical synchronization signal V are separated. Then, when it is determined that the state is unsteady normal, a determination signal is sent to the line determination / gate generation circuit 11 to increase the gate width. The input video signal passes through the gate circuit 13 only during the period when the gate pulse is “H”.

The data discriminating / reading circuit 14 discriminates the discrimination signal by detecting the reference signal shown in FIG. 23 from the signals passed through the gate circuit 13 based on the timing signal output from the timing generation circuit 6, and follows. Read the data. In this embodiment, the reason for increasing the gate pulse width when it is determined to be in the unsteady normal state is as follows. As shown in FIG. 14, the video signal in which the identification signal is inserted into the 20th line and the 283th line is as shown in (A) and (B). The vertical synchronizing signal V and the horizontal synchronizing signal H separated from the video signal are as shown in (C) (only the first field is displayed, and so on). Therefore, in a normal state, for example, after the vertical synchronizing signal V ends from this synchronizing signal, the gate pulse G for one line is obtained when 16 horizontal synchronizing signals H are counted.
By creating 1, a signal of only 20 lines can be extracted.

However, since a pseudo vertical synchronizing signal as shown in (E) is inserted in an unsteady normal state such as during special reproduction, the video signal becomes as shown in (D). Then, the synchronization signal separated from the video signal is as shown in (F). Based on this, after the vertical synchronization signal V ends in the same manner as in the normal state, 16 horizontal synchronization signals H are added. If the gate signal G2 for one line is generated, a TV video signal for 22 lines is read. There is no definition of the length of the pseudo vertical synchronizing signal, and the insertion position also differs depending on the model of the VTR and the timing when the device enters the special reproduction mode. Therefore, it is impossible to specify a line from the timing of the vertical synchronizing signal.

Therefore, the unsteady normal state determination circuit 12 determines the unsteady normal state. This determination can be made, for example, using a combination of the signal determination circuit and the line determination circuit in the fourth embodiment. Then, when it is determined that the operation is in an unsteady normal state, a determination signal is sent to the line determination / gate generation circuit 11, and the period during which the gate pulse is set to “H” is extended. For example, the gate signal G3 is a gate pulse that becomes “H” from the time when the number of the horizontal synchronization signals H is counted to 5 to the time when the number of the horizontal synchronization signals H is counted 25 after the end of the vertical synchronization signal V.

In this way, since a signal other than the target identification signal is input, the probability of erroneously reading noise or the like increases, but the identification signal is not missed. here,
The period in which the gate pulse is set to "H" may be sequentially increased until the gate pulse becomes "H", such as by extending the period in which the gate pulse is set to "H" by one line for each field. Further, the operation of sequentially widening the period in which the gate pulse is set to “H” and the operation of shifting the center position of the gate pulse can be combined.

(Sixth Embodiment) FIG. 16 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a sixth embodiment of the present invention. This embodiment includes a portion for determining whether the reference signal and the data are correct, a portion for determining whether the vertical synchronization signal V is normal, and a portion for generating a timing signal for reading data into the data storage circuit 3. And a portion for reading data stored in the data storage circuit 3.

First, a portion for determining whether the reference signal and the data are correct will be described. This part includes the signal discriminating circuit 4, CRCC checking circuit 15, and AND
It is composed of a gate 16. The output of the data reading circuit 1 is input to the signal discriminating circuit 4 and the CRCC checking circuit 15. Since the signal discriminating circuit 4 has substantially the same configuration (without the AND gate 49) as the signal discriminating circuit of FIG.
The same numbers are given. The CRCC check circuit 15 is shown in FIG.
3 is monitored to see if there is any error in the data. If there is no error, the "H" level C
An RCC determination signal is output. The CRCC discrimination signal and the discrimination signal output from the signal discrimination circuit 4 and indicating the presence or absence of the normal reference signal are supplied to the AND gate 16.

Next, a description will be given of a portion for determining whether or not the vertical synchronization signal is normal. This part includes a length detection circuit 8, a first horizontal synchronization signal determination circuit 7, and a second horizontal synchronization signal determination circuit 17. The length detection circuit 8 and the first horizontal synchronization signal determination circuit 7 have substantially the same configurations as the length detection circuit 8 and the horizontal synchronization signal determination circuit of FIG. 6, respectively. Second horizontal synchronization signal determination circuit 1
Reference numeral 7 denotes a horizontal synchronization signal for one field period (from the trailing edge of the vertical synchronization signal V to the trailing edge of the next vertical synchronization signal V) using the horizontal synchronization signal H and the vertical synchronization signal V separated by the synchronization separation circuit 5. The number of H's is counted, and if this exceeds a predetermined value (eg, 280), an "H" level discrimination signal is output. Therefore, for example, if a noise bar occurs during special reproduction, it is counted as the horizontal synchronization signal H, so that the measured value exceeds 280 and becomes “L”.
A level discrimination signal is output. The determination signals of the length detection circuit 8, the first horizontal synchronization signal determination circuit 7, and the second horizontal synchronization signal determination circuit 17 are supplied to an AND gate 18.

Next, a portion for generating a timing signal for reading data into the data storage circuit 3 will be described. This part includes the half V killer circuit 19 and the line counter circuit 2
0. The half V killer circuit 19 includes a horizontal synchronization signal H and a vertical synchronization signal V separated by the synchronization separation circuit 5.
Is used to mask the next vertical synchronization signal V supplied from the synchronization separation circuit 5 from the detection of the trailing edge of the vertical synchronization signal V to the detection of a predetermined number (eg, 224) of horizontal synchronization signals H. have. Then, the line counter circuit 20
Is the vertical synchronizing signal V ′ output from the half V killer circuit 19
For example, a read pulse is generated from the horizontal synchronization signal H at the end of the vertical blanking period and supplied to the AND gate 21. This read pulse passes through the AND gate 21 when the AND gate 16 and the AND gate 18 are both at the "H" level, that is, when there is a normal reference signal, there is no error in the data, and the special reproduction is not being performed. Supplied to

Next, a description will be given of the most characteristic part of the present embodiment, that is, the part for reading data stored in the data storage circuit 3. This part includes an integration circuit 22 for data discrimination and a gate circuit 23. The data discriminating integration circuit 22 allows the output of the data storage circuit 3 to pass through the gate circuit 23 only when a signal (here, “H” level) determined to be correct m times continuously from the AND gate 16 is output. I do. Then, after a signal determined to be correct m times in succession comes, the signal is finally read into the data storage circuit 3 unless a signal determined to be erroneous n times (in this case, “L” level) comes in. Output data. FIG. 17 is a flowchart showing the operation of the data discriminating integration circuit, and FIG.
4, a block diagram showing a specific configuration of the data discriminating integration circuit when n = 3, and FIG. 19 is an operation timing chart thereof. Hereinafter, the operation of the data discriminating integration circuit 22 will be briefly described with reference to FIGS. Here, a is a count value counted up when the output of the AND gate 16 is “H” and counted down when the output is “L”. In addition, although the data discriminating integration circuit 22 is constituted by hardware logic, it is described as a flowchart for convenience of explanation.

First, the counter is reset when the power is turned on (S1 in FIG. 17). Next, the vertical synchronization signal V (FIG. 19)
Counting up or down is performed according to the level of the output c (FIG. 19C) of the AND gate 16 by the clock b (FIG. 19B) synchronized with (a)), and the following (1) to (5) Works like (1) When the counter value is 3 or more, the output c of the AND gate 16
Is "H", the counter is preset to "7" by the signal A in FIG. 18 (S2 in FIG. 17). (2) When the counter value is 5 or less, the output c of the AND gate 16
Is "L", the counter is preset to "0" by the signal B in FIG. 18 (S4 in FIG. 17). (3) The output c of the AND gate 16 when the counter value is 0 to 2
Is "H", the counter is set to count up by the signal D in FIG. 18 (S3 in FIG. 17). (4) The output c of the AND gate 16 when the counter value is 6 to 7
Is "L", the counter is set to count down by the signal C in FIG. 18 (S5 in FIG. 17). (5) If the counter value is 4 or more, the output d (FIG. 19 (d)) of the data discriminating integration circuit becomes "H" (S6 and S7 in FIG. 17). Therefore, the data read into the data storage circuit 3 is output through the gate circuit 23. (6) If the counter value is less than 4, output d (FIG. 19)
(D)) becomes “L” (S8 in FIG. 17). Therefore, the gate circuit 23 does not output the closing data.

FIG. 19 (e) shows that the counter value is simply 4
This is the output when the output is set to “H” when the above is reached, and is set to “L” when the output is 4 or less. In comparison with this, it is understood that the data output from the data storage circuit 3 is stable in the present embodiment shown in FIG.

FIG. 20 is a block diagram showing a schematic configuration of a television receiver provided with the identification signal discriminating apparatus according to the present invention, and an operation explanatory diagram thereof. In FIG. 20A, an input video signal is input to the identification signal determination device 101. The identification signal determination device 101 is, for example, the identification signal determination device according to the sixth embodiment, detects an identification code in an identification signal, and outputs a control signal according to the category. When the squeeze mode signal, the letterbox signal, and the signal indicating the Vistavision size are inserted as the identification code, the video signal is output horizontally by the letterbox zoom circuit 102 as shown in FIG. 16: 9 CRT 104 scaled vertically and vertically
Is output to When the squeeze mode signal is inserted as the identification code and the letterbox signal is not inserted, the deflection control of the CRT 104 is performed by the aspect ratio conversion circuit 103 as shown in FIG. The conversion of the aspect ratio may be performed in a video signal system.

FIG. 21 is a block diagram showing a schematic configuration of a video tape recorder provided with the identification signal discriminating apparatus according to the present invention. In FIG. 21, the input video signal is input to the identification signal discriminating device 105. The identification signal determination device 105 separates the vertical synchronization signal from the video signal and determines whether the video signal is a video signal for special reproduction. If it is determined that the video signal is for special playback,
The data held by switching the switching circuit 107 is supplied to the data insertion circuit 106 and inserted into a predetermined vertical blanking period of the video signal. Data insertion circuit 10
6 is recorded by the recording head 108. At the time of reproduction, the switching circuit 111 is switched under the control of the special reproduction mode signal output from the system controller 109, and the data held in the identification signal discriminating device 110 is supplied to the data insertion circuit 113, and reproduced by the reproduction head 112. It is inserted in a predetermined vertical blanking period of a video signal.

As described above, if the video tape recorder according to the embodiment of the present invention is used, the identification signal can be reinserted at the time of recording and reproduction. Therefore, at the time of dubbing, the video tape recorder on the reproduction side is set to the special reproduction mode. Even if this is done, the correct identification signal is recorded on the recording tape. It should be noted that the present invention is not limited to the above embodiments, and various modifications are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention. For example, while the above embodiments have been described with reference to an example of a video signal at the time of special reproduction of a video tape recorder, the present invention is also applicable to a video signal obtained by receiving a television broadcast signal having a poor S / N. can do.

[0052]

As described above, according to the present invention, the following effects can be obtained. (1) The accuracy of reference signal determination can be increased without reducing the number of bits used for data. (2) Incorrect data is read even when the vertical synchronizing signal is not normal, that is, when the relationship between the vertical synchronizing signal and the horizontal synchronizing signal during the vertical blanking period of the video signal is different from the normal state. Will disappear. (3) Even when the vertical synchronizing signal is not a regular signal, data is not missed. (4) Since reading of an erroneous identification code can be prevented, it is possible to prevent an unpleasant state such as a change in the screen aspect ratio in a short time. (5) Correct data can be inserted into a recorded video signal or a reproduced video signal even when the vertical synchronization signal at the time of special reproduction or the like is not proper.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a signal discriminating circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an operation of a signal discriminating circuit in the first embodiment of the present description.

FIG. 4 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a vertical synchronizing signal and a horizontal synchronizing signal according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a specific configuration of a horizontal synchronizing signal determination circuit according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of an operation at the time of normal reproduction of the horizontal synchronizing signal determination circuit according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating the operation of the horizontal synchronization signal discrimination circuit according to the second embodiment of the present invention during special reproduction.

FIG. 9 is an explanatory diagram of another special reproduction operation of the horizontal synchronization signal discrimination circuit according to the second embodiment of the present invention.

FIG. 10 is a diagram illustrating the operation of the horizontal synchronization signal discrimination circuit according to the second embodiment of the present invention at the time of yet another special reproduction.

FIG. 11 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a third embodiment of the present invention.

FIG. 12 is a block diagram showing a specific configuration of a length detection circuit according to a third embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a fourth embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of the identification signal discriminating apparatus according to the fourth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a fifth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of an identification signal discriminating apparatus according to a sixth embodiment of the present invention.

FIG. 17 is a flowchart showing the operation of the data discriminating integration circuit according to the sixth embodiment of the present invention.

FIG. 18: m = 4, n = 3 in the sixth embodiment of the present invention.
FIG. 4 is a block diagram showing a specific configuration of a data discriminating integration circuit in the case of FIG.

FIG. 19 is an operation timing chart of FIG. 18;

FIG. 20 is a block diagram showing a schematic configuration of a television receiver provided with the identification signal discriminating apparatus according to the present invention, and an operation explanatory diagram thereof.

FIG. 21 is a block diagram showing a schematic configuration of a video tape recorder including an identification signal discriminating apparatus according to the present invention.

FIG. 22 is an explanatory diagram showing a relationship between an image aspect ratio and a screen aspect ratio.

FIG. 23 is a waveform diagram of an identification signal inserted during a vertical blanking period.

[Explanation of symbols]

2 ... Data temporary storage circuit, 3 ... Data storage circuit, 4 ... Signal judgment circuit, 5 ... Synchronization separation circuit, 7 ... Horizontal synchronization signal judgment circuit, 8 ... Length detection circuit, 9 ... Line judgment circuit, 10 ...
AND gate, 13 gate circuit, 14 data discrimination
Reading circuit, 101, 105 ... identification signal discriminating device, 102
... Letter box zoom circuit, 103 ... Aspect ratio conversion circuit, 113,116 ... Data insertion circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-17387 (JP, A) JP-A-2-117287 (JP, A) JP-A-64-89780 (JP, A) JP-A-6-89780 6714 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^7/ 00-7/088

Claims (6)

(57) [Claims] An apparatus for determining an identification signal inserted into a specific line during a vertical blanking period of a video signal and composed of a reference signal of a predetermined bit and data following the reference signal, comprising: First means for separating a vertical synchronization signal and a horizontal synchronization signal corresponding to a synchronization signal period; (b) second means for temporarily storing the data for each vertical synchronization signal; and (c) the reference. Third means for determining that the reference signal is normal when there is no level inversion in one bit of the signal; and (d) fourth means for determining whether the data is normal.
(E) fifth means for determining the specific line from the vertical synchronization signal and the horizontal synchronization signal separated by the first means, and (f) the third means and the fourth means. And when the line determined to be a legitimate reference signal and the legitimate data matches the specific line determined by the fifth means, the second means temporarily stored in the second means. And a sixth means for fetching and storing data. 2. The fifth means determines whether or not the vertical synchronization signal separated by the first means is normal, and only when the vertical synchronization signal is normal, the specific line is identified. The identification signal determination device according to claim 1, wherein the identification signal is determined. 3. The apparatus according to claim 2, wherein said fifth means determines whether or not the vertical synchronization signal is normal based on the number of horizontal synchronization signals within the vertical synchronization signal period. Identification signal determination device. 4. The identification signal discriminating apparatus according to claim 2, wherein said fifth means discriminates whether the vertical synchronizing signal is normal or not based on the length of the vertical synchronizing signal period. . 5. A television receiver having an identification signal discriminating unit inserted into a specific line in a vertical blanking period of a video signal for discriminating an identification signal composed of a reference signal of a predetermined bit and data following the reference signal. In the above, the identification signal determination unit comprises: (a) first means for separating a vertical synchronization signal and a horizontal synchronization signal corresponding to a vertical synchronization signal period from a video signal; and (b) the data for each of the vertical synchronization signals. (C) third means for judging the reference signal as valid when there is no level inversion in one bit of the reference signal, and (d) the data is 4th to determine if it is legitimate
(E) fifth means for determining the specific line from the vertical synchronization signal and the horizontal synchronization signal separated by the first means, and (f) the third means and the fourth means. And when the line determined to be a legitimate reference signal and the legitimate data matches the specific line determined by the fifth means, the second means temporarily stored in the second means. A sixth means for capturing and storing data, wherein the television receiver enlarges and displays at least the image in the horizontal direction according to the data stored in the sixth means. 6. A recording / reproducing unit having an identification signal discriminating unit for discriminating an identification signal inserted into a specific line of a vertical blanking period of a recording or reproduction video signal and comprising a reference signal of a predetermined bit and data subsequent to the reference signal. In the apparatus, the identification signal determination unit includes: (a) first means for separating a vertical synchronization signal and a horizontal synchronization signal corresponding to a vertical synchronization signal period from a video signal; and (b) the data for each of the vertical synchronization signals. (C) third means for judging the reference signal to be normal when there is no level inversion in one bit of the reference signal, and (d) the data # 4 to determine if is legitimate
(E) fifth means for determining the specific line from the vertical synchronization signal and the horizontal synchronization signal separated by the first means, and (f) the third means and the fourth means. And when the line determined to be a legitimate reference signal and the legitimate data matches the specific line determined by the fifth means, the second means temporarily stored in the second means. And a sixth means for fetching and storing data.