JP3262941B2 - Subband split coded audio decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subband division coded audio decoder .

[0002]

2. Description of the Related Art In recent years, human auditory characteristics have been used skillfully,
The MPEG audio broadcasting, communication, and storage media standardized internationally by ISO / IEC as an encoding technology that hardly detects sound quality deterioration even when the audio signal is compressed to about 1/6 to 1/8. The use in is considered. Generally, a medium that receives and stores an encoded bit stream requires a decoder to reproduce an audio signal. Here, in a general encoding method, encoding is performed in units of frames. Therefore, when an error occurs in a bit stream, it is necessary to mute the entire frame.

There are various methods of muting, such as zero mute, zero cross mute, and soft mute. Soft mute, in which muting is performed smoothly without generating abnormal noise at the start and end of muting, is important. Yes, here muting assumes soft mute. This subband division coded audio decoder will be described by way of an example in which MPEG audio is used as a coding method. For MPEG audio, see ISO / IEC / JTC1 / SC2 “Info
rmation Technology-Coding of Moving Pictures and A
ssociated Audiofor Digital Storage Media up to abo
ut 1.5Mbit / s. Part3: Coding of audio information ”.

FIG. 10 is a block diagram of a conventional muting device of a subband division coded audio decoder. In the figure, 1 is a synchronization detector for synchronizing the input bit stream, 2 is a frame unpacking circuit for unpacking the bit stream, 3 is a CRC
4 is a bit allocation decoder for decoding the bit allocation unpacked by the frame unpacking circuit 2, 5 is a scale factor decoder for decoding the unpacked scale factor, and 6 is the unpacked sample. A sample inverse quantizer for performing an operation of C × (sample data + D) from coefficients C and D based on the data quantization level to obtain an inverse quantized value. Denormalizer for obtaining a denormalized value by multiplying the denormalized value by a scale factor; 8 is a subband synthesizer for performing subband synthesis on the denormalized value to calculate an audio output; 41 is the immediately preceding subband synthesizer; A frame memory for storing the audio data of the frame;
A switch circuit for switching the data in 1 to a multiplier 44 for muting or to a selector 45 according to a mute signal, 43 is a mute coefficient ROM having a coefficient for muting, 44 is a mute coefficient and a A multiplier 45 for multiplying data is a selector for switching according to a mute signal whether to output an output from the muting multiplier 44 or to output data in the frame memory as an output.

Next, the operation of the conventional example will be described. The synchronization of the input bit stream is detected by the synchronization detector 1. When synchronization is established, the header information is extracted by the frame unpacking circuit 2, and the layer,
Information necessary for decoding, such as presence / absence of CRC, bit rate, sampling frequency, and channel mode, is set. Further, the audio data is separated into bit allocation information, scale factor information, and sample data. If there is a CRC check bit, the CRC detector 3 checks for an error.

Next, the bit allocation information separated by the frame unpacking circuit 2 is input to a bit allocation decoder 4, and a quantization level is obtained.
The scale factor information is supplied to the scale factor decoder 5.
To obtain a scale factor value that is multiplied by the inverse quantized value of the associated sample. The samples are input to a sample inverse quantizer 6 and a bit allocation decoder 4
The coefficients C and D are selected based on the quantization level obtained by the above, and an inverse quantization value is obtained by an operation of C × (sample data + D). Next, the inverse quantized value is input to the inverse normalizer 7 and multiplied by the scale factor obtained by the scale factor decoder 5 to obtain an inverse quantized value. The dequantized value is sub-band synthesized by the sub-band synthesizer 8 and decoded as an audio signal.

Next, when the mute signal is detected, the audio output is sent to the multiplier 44 by the switch circuit 42. In the multiplier 44, the audio output is multiplied by a mute coefficient such as a linear function shown in FIG. 11 or a logarithmic function shown in FIG. 12 in the mute coefficient ROM 43, and the linear mute shown in FIG. 13 and the logarithm shown in FIG. A muting output as shown in Mute is obtained. The selector 45 selects the mute output from the multiplier 44 as the output signal. In order to prevent abnormal noise at the beginning of muting by this method, it is necessary to perform muting in a frame before a mute signal is output. Therefore, it is necessary to hold the data of one frame before in the frame memory 41.

[0008]

As described above, in the muting apparatus in the conventional subband division coded audio decoder, the memory 41 for holding the decoded audio signal of the previous frame for a predetermined period is used for muting. And the H / W scale is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made in order to solve the above-mentioned problems. It is possible to perform a soft muting operation without adding a new memory for holding a decoded audio signal. An object is to obtain a band division coded audio decoder .

[0010]

According to a first aspect of the present invention, there is provided a subband division coded audio decoder which multiplies a subband synthesizer by an orthogonal transformer, a window coefficient ROM, and a window coefficient and an orthogonal transform value. A multiplier, a "0" generator, a selector for switching the output of the "0" generator from the result of the multiplication by the multiplier when a mute signal is detected, and a window length 2MN (2M of the subband division number N (M: an integer) ) Times) memory, and outputs from the selectors X ₀ ^t , X ₁ ^t ,
... X _2MN-1 ^t, and the data in the memory is Y ₀
^t-1 , Y ₁ ^t-1 ,..., Y _2MN-1 ^t-1 , an addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y
₁ ^t, · · · · Y adding means for returning the _2MN-1 ^t in the memory, a buffer memory for latching a data Y ₀ ^t ~Y _N-1 ^t of addition result N (sub-band division number) samples It is provided with. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1)

According to a second aspect of the present invention, there is provided a sub-band division coded audio decoder, comprising: an orthogonal transformer, a window coefficient ROM, a multiplier for multiplying a window coefficient and an orthogonal transform value by a sub-band synthesizer; And a selector for switching the output from the multiplier to the output of the "0" generator when a mute signal is detected, and a window length of 2MN (2M of subband division number N).
(M: an integer) times the memory for storing data, and outputs from the selectors X ₀ ^t , X ₁ ^t ,... X _2MN-1 ^t
And the data in the memory is represented by Y ₀ ^t−1 , Y ₁ ^t−1,.
_.., Y _2MN-1 ^t−1 , the addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
_Adding means for _{returning 2MN-1} ^t to the memory ;
N (sub-band division number) samples of the data Y ₀ ^t to Y
Those having a controller and a switch stop input from the memory during one cycle of the buffer memory and unmute signal detection after latching the _N-1 ^t (2MN) to the summing means. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1)

According to a third aspect of the present invention, there is provided a subband division coded audio decoder comprising: an orthogonal transformer, a window coefficient ROM, and a first multiplier for multiplying a window coefficient by an orthogonal transform value. , “0” generator and when a mute signal is detected,
A selector for switching the result of the multiplication by the first multiplier to an output of a “0” generator, a memory for storing data of a window length of 2MN (2M (M: an integer) times the number of subband divisions N), X ₀ ^t , X ₁ ^t ,...
... and X _2MN-1 ^t, the data in the memory Y ₀ ^t-1,
When Y ₁ ^t−1 ,..., Y _2MN−1 ^t−1 , addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
· · Y _2MN-1 adding means back to said memory ^t, the sum N (sub-band division number) samples of the data Y
_A switch for latching the output of the buffer memory for latching ₀ ^{t to} Y _N-1 ^t and a buffer memory upon detection of a mute signal to a second multiplier, a mute output correction coefficient ROM, a correction coefficient, and a multiplication of the output value from the buffer memory. And a second selector for switching the output value of the second multiplier and the decoder to the output from the second multiplier. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1)

According to a fourth aspect of the present invention, there is provided a sub-band division coded audio decoder, comprising: an orthogonal transformer, a window coefficient ROM, a multiplier for multiplying a window coefficient and an orthogonal transform value by a sub-band synthesizer; And a selector for switching the output from the multiplier to the output of the "0" generator when a mute signal is detected, and a window length of 2MN (2M of subband division number N).
(M: an integer) times the memory for storing data, and outputs from the selectors X ₀ ^t , X ₁ ^t ,... X _2MN-1 ^t
And the data in the memory is represented by Y ₀ ^t−1 , Y ₁ ^t−1,.
_.., Y _2MN-1 ^t−1 , the addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
_Adding means for _{returning 2MN-1} ^t to the memory ;
N data (sub-band division number) samples Y ₀ ^t-1
~ Y _N-1 ^t-1 in addition to a buffer memory for latching the synchronization error detection signal output from the synchronization detector and the CRC error detection signal output from the CRC detector to the mute signal. is there. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1)

[0014]

The orthogonal transformer in the sub-band division coded audio decoder according to the present invention converts the sub-band data into data in the time domain, and the first multiplier applies a window to the orthogonal transform value. The adding means and the memory obtain the sub-band composite value by accumulating and adding the windowed data for a predetermined period.

The "0" generator and selector in the sub-band division coded audio decoder according to the first to fourth aspects of the present invention, when the mute signal is detected, add the value to be added by the adding means from the new windowed data to "0". , The accumulated addition data is attenuated, and the value to be added to the addition means is switched again to new windowing data after the mute signal is released. It is possible to do

The switch and the controller according to the second aspect of the present invention do not add the value in the memory to the input of the adding means for one cycle (2 MN) after the release of the mute signal. It is possible to perform soft muting from.

The switch, the mute output correction coefficient multiplier, and the second selector multiply the mute output in the buffer memory by the mute output correction coefficient when the mute signal is detected, and mute the corrected output. By outputting it as an output, soft mute can be performed.

A frame in which a synchronization error and a CRC error have occurred is provided by means for adding the synchronization error detection signal output from the synchronization detector and the CRC error signal output from the CRC detector to a mute signal. It is possible to mute the abnormal noise.

[0019]

【Example】

Embodiment 1 FIG. Hereinafter, the present invention will be described with reference to the drawings. FIG.
Is a block diagram of the MPEG audio decoding apparatus according to the first embodiment of the present invention, wherein the same reference numerals as those in FIG. 10 denote the same or corresponding parts, and 10 denotes an OR gate.
A mute signal, a synchronization error detection signal, and a CRC error detection signal are input, and the output is
As a mute signal.

FIG. 2 is a block diagram of the subband synthesizer and the muting device of the decoder according to the first embodiment. In the figure, 11 is an orthogonal transformer for converting subband samples into data in the time domain, 12 is a ROM having a window coefficient of a window length of 512, 13 is a multiplier for multiplying the orthogonal transformed value by a window coefficient, and 14 is a multiplier. 0 "generator 15 is mute signal detection at the time of" selectors for switching the data from the 0 "generator, the ring memory for holding data of 512 words is 16, outputs X ₀ ^t from the selector 15 17, X ₁
^.. , X ₅₁₁ ^t, and when the data in the ring memory is Y ₀ ^{t −1} , Y ₁ ^{t −1} ,..., Y ₅₁₁ ^{t −1} , Y _i ^t = Y _{i + ^{32 t-1 + X i t}} (i = 0 ··· 479) performs ^{_{Y i t = X i t (}} i = 480 ··· 511) comprising the addition, the result ^{_{Y 0 t, Y 1 t,}} ···・ Y
Adding means for returning the ₅₁₁ ^t to the ring memory 18 is 32 samples Y ₀ ^t to Y of the addition result of the adding means 17
_This is a 32-word buffer memory that latches ₃₁ ^t .

FIG. 3 shows a muting waveform output from the muting device of the subband division coded audio decoder according to the first embodiment of the present invention.

FIG. 4 is another block diagram of the subband synthesizer and the muting device of the decoder according to the first embodiment. In the figure, 11 to 18 are the same as those shown in FIG. 2, 21 is a switch circuit for turning on / off the input from the ring memory to the adding means, 22
Is a control circuit for controlling the switch so as to stop the input from the ring memory to the adding means for one cycle after the detection of the mute signal.

Next, the operation of the first embodiment will be described. M
The synchronization of the MPEG audio bit stream input to the PEG audio decoding device is detected by the synchronization detector 1. When synchronization is established, the header information is extracted by the frame unpacking circuit 2, and the layer,
The presence / absence of CRC, bit rate, sampling frequency, presence / absence of padding, channel mode and the like are set. Also, the audio data is bit allocation information,
Scale factor information is separated into sample data.
If there is a CRC check bit, the CRC detector 3 checks for an error.

Next, the bit allocation information separated by the frame unpacking circuit 2 is input to a bit allocation decoder 4, and a quantization level is obtained. The scale factor information is input to the scale factor decoder 5 to obtain a scale factor value by which the inverse quantization value of the relevant sample is multiplied. sample,
Coefficients C and D are selected based on the quantization level input to the sample inverse quantizer 6 and obtained by the bit allocation decoder 4, and C (sample data + D)
An inverse quantization value is obtained by the following operation. Next, the dequantized value is input to the denormalizer 7 and multiplied by the scale factor obtained by the scale factor decoder 5 to obtain a denormalized value. The inverse quantization value is calculated by the subband synthesizer 8
, And is decoded as an audio signal.

A synchronization error detection signal when an error is detected by the synchronization detector 1 and a CRC error detection signal when an error is detected by the CRC detector 3 are output via an OR gate 10 to a mute signal. Is added to
The signal is input to the muting device of the subband synthesizer 8.

Next, the operation of the subband synthesizer and the muting device having the configuration shown in FIG. 2 will be described. According to the ISO / IEC standard, subband synthesis is ΣN × S
(N: cosine coefficient, S: subband sample), an orthogonal transformation of D × U (D: window coefficient, U: orthogonal transformation value), and cumulative addition of ΣW (W = D × U). . Therefore, in order to realize the subband synthesizer, it is necessary to perform the following operations in each circuit and each circuit shown in FIG. The orthogonal transform unit 11 multiplies the 32 subband samples obtained by the inverse normalizer 7 by an orthogonal transform matrix to obtain an orthogonal transform value of 512 samples. Next, the multiplier 13 calculates a window coefficient R for the orthogonal transformation value.
The window coefficient in the OM 12 is multiplied and input to the selector 15. Then, in the adder unit 17, an output X ₀ ^t from the selector 15, X ₁ ^t, and · · · · X ₅₁₁ ^t, the data Y ₀ ^t-1 in 512 words ring memory ^{_{16, Y 1 t-1,}} ·
... Y ₅₁₁ ^t-1 is added according to the following equation, and as a result Y ₀
^t , Y ₁ ^t ,..., Y ₅₁₁ ^t are recorded in the ring memory 16 again. ^{_{Y i t = Y i + 32}} t-1 + X i t (i = 0 ··· 479) Y i t = The ^{_{X i t (i = 480 ···}} 511), 32 pieces of addition results of the adding means 17 of sample Y
₀ ^{t to} Y ₃₁ ^t are latched in the 32-word buffer memory 18 and become output data.

When a muting signal is input to the muting apparatus of the sub-band division coded audio decoder as described above, the selector 15 sets the input to the adding means 17 of the sub-band synthesizer to a "0" generator. Switch to the output from 14. As a result, the output gradually attenuates as shown in FIG. 3, becomes 0 after 512 samples, and soft muting is performed.

As described above, when the muting signal is detected, the data input to the adding means of the subband synthesizer is switched to the output from the "0" generator to obtain the soft muting output. Soft muting can be performed without increasing the memory for muting and the multiplier.

Next, when the release of the muting signal is detected, the input to the adding means 17 is switched again by the selector 15 to the multiplication result of the multiplier 13. According to this method, the output gradually increases as shown in FIG. 3 and returns to a correct output value after 512 samples.

As described above, when the muting signal release is detected, the input to the adding means of the subband synthesizer is switched to the multiplication result again, so that the muting memory and the multiplier are not increased. Muting can be released.

Also, by adding a synchronization error detection signal obtained by the synchronization detector 1 and a CRC error detection signal obtained by the CRC detector 3 as a muting signal, abnormal noise is not generated in a frame where an error occurs. Becomes possible.

Next, as another method, the operation of the muting device having the structure shown in FIG. 4 will be described. The subband samples input to the subband synthesizer are 11 to
The muting operation is performed in the circuit 18 by the same operation as in the example of FIG. However, when the switch control circuit 22 detects the release of the mute signal, the switch circuit 21 is turned off so as to stop the input from the ring memory 16 to the addition means 17 for one cycle, so that the output once becomes 0 after the release of the muting, and from 0. Gradually increased, 5
It returns to the correct output value after 12 samples.

As described above, when the muting signal is released,
Since the input from the ring memory 16 to the adding means 17 is cut off, muting can be released without increasing the number of muting memories and multipliers.

Embodiment 2 FIG. FIG. 5 is a block diagram of a subband synthesizer and a muting device of a subband division coded audio decoder according to Embodiment 2 of the present invention.
In the figure, the same reference numerals as those in FIGS. 2 and 4 denote the same or corresponding parts, respectively. Reference numeral 31 denotes a mute output after subband synthesis in a 32-word buffer memory 18 when a mute signal is detected. A switch circuit for switching; 32, a mute output correction coefficient ROM having a coefficient for correcting the mute output after subband synthesis; 33, a mute output correction coefficient for correcting the mute output after subband synthesis to a predetermined mute output ROM3
A multiplier 34 that multiplies the correction coefficient in 2 is a selector that switches the output to the correction mute value from the multiplier 33 when a mute signal is detected.

FIG. 6 shows the window coefficient ROM1 of the subband synthesizer and the muting device of the decoder according to the first and second embodiments.
FIG. 4 is a diagram showing a window coefficient in FIG.

FIG. 7 shows the attenuation coefficient of the muting waveform in the subband synthesizer and the muting device of the decoder according to the first embodiment. The value obtained by adding the window coefficient of FIG. It is shown.

FIG. 8 shows an example of the correction coefficient in the mute output correction coefficient ROM 32 in the sub-band synthesizer and muting device of the decoder according to the second embodiment. The mute waveform of the first embodiment as shown in FIG. FIG. 14 shows coefficients to be corrected to a linearly reduced mute waveform as shown in FIG.

FIG. 9 shows another example of the correction coefficient in the mute output correction coefficient ROM 32 in the subband synthesizer and the muting device of the decoder according to the second embodiment, and the mute of the first embodiment as shown in FIG. Fig. 14 shows the waveform.
7 shows coefficients to be corrected to a logarithmic decreasing mute waveform as shown in FIG.

Next, the operation of the second embodiment will be described. The sub-band samples are sub-band synthesized by the circuits 11 to 18, and when a mute signal is detected, a muting output is obtained by adding data from a "0" generator. This muting waveform has a slightly larger amplitude than the original waveform before attenuation as shown in FIG. In order to convert this waveform into a linearly decreasing waveform or a logarithmic decreasing waveform as shown in the conventional example, when a mute signal is detected, the switch 31 is switched to operate the 32-word buffer memory 1.
The data in 8 is applied to the input of the multiplier 33 and multiplied by the coefficient in the mute output correction coefficient ROM 32. Then, the output at the time of mute is switched to the multiplication result by the selector 34.

Here, the buffer memory 18 at the time of mute is used.
The following can be said about the output waveform from. Since the 512-word ring memory holds the value obtained by cumulative addition while shifting by 32 samples by the adding means 17, the oldest 32 samples have been subjected to 16 cumulative additions, and thereafter 15 times for every 32 samples. Batch, 14 times... 1 time of cumulative addition data. After the mute signal is detected, "0" is added by the selector 15, so that the data in the ring memory may be output as it is as the output of the adding means. Therefore, it is considered that the data in the ring memory is multiplied by the cumulative addition value of the window coefficients. The cumulative addition value of the window coefficient is as shown in FIG. 7, and matches the shape of the envelope of the mute waveform in FIG. Therefore, the correction coefficient required to correct the attenuated waveform as shown in FIG. 7 to the muting output as shown in FIGS. 13 and 14 of the conventional example is the window coefficient of the window coefficient shown in FIG. Assuming that the cumulative addition value is C _i and the mute coefficients shown in FIGS. 11 and 12 are D _i , the correction coefficient is obtained as D _i / C _i . FIG. 8 and FIG. 9 show the correction coefficients in the case of performing the linear decreasing muting and the logarithmic decreasing muting, respectively.

As described above, when the muting signal is detected, the data input to the adding means is switched to the output from the "0" generator, and the output value is multiplied by the correction coefficient to thereby obtain a predetermined value. Is configured to obtain the soft muting output of the above, so that predetermined soft muting can be performed without increasing the memory for muting.

[0042]

According to the first aspect of the present invention, when a muting signal is detected, the data input to the adding means is switched to "0", and when the muting signal release is detected, the data is sent to the adding means. Is returned to the multiplication result again, which has the effect of enabling a soft muting operation without increasing the number of memories and multipliers.

According to the second aspect of the present invention, when the muting signal is detected, the data input to the adding means is switched to "0", and when the release of the muting signal is detected, the input to the adding means is changed. Is returned to the multiplication result again, and the data in the memory is not added to the input of the accumulative addition for one more cycle, so that the soft muting operation can be performed without increasing the memory and the multiplier.

According to the third aspect of the present invention, when the muting signal is detected, the data input to the adding means of the sub-band synthesizer is switched to "0" to multiply the output data by the correction coefficient. This has the effect of enabling predetermined soft muting without increasing the memory.

According to the fourth aspect of the present invention, by adding the synchronization error detection signal and the CRC error detection signal to the muting signal, there is an effect that abnormal noise is not produced at the time of error.

[Brief description of the drawings]

FIG. 1 is a block diagram of an MPEG audio decoding device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a subband synthesizer and a muting device of a decoder according to the first embodiment.

FIG. 3 is a diagram illustrating a muting waveform output by a muting device of the subband division coded audio decoder according to the first embodiment.

FIG. 4 is another block diagram of the subband synthesizer and the muting device of the decoder according to the first embodiment.

FIG. 5 is a block diagram of a subband synthesizer and a muting device of a subband division coded audio decoder according to Embodiment 2 of the present invention;

FIG. 6 is a diagram illustrating window coefficients in a window coefficient ROM 12 of a subband synthesizer of a decoder and a muting device according to the first and second embodiments.

FIG. 7 is an attenuation coefficient of a muting waveform in the subband synthesizer and the muting device of the decoder according to the first embodiment.

FIG. 8 illustrates a mute output correction coefficient R in a subband synthesizer and a muting device of a decoder according to a second embodiment.
It is an example of a correction coefficient in OM32.

FIG. 9 illustrates a mute output correction coefficient R in a subband synthesizer and a muting device of a decoder according to a second embodiment.
It is another example of the correction coefficient in OM32.

FIG. 10 is a block diagram of a muting device of a conventional subband division coded audio decoder.

FIG. 11 shows a mute coefficient ROM in a muting device of a conventional subband division coded audio decoder.
FIG. 6 is a diagram showing an example of coefficient data in the section.

FIG. 12 shows a mute coefficient ROM in a muting device of a conventional subband division coded audio decoder.
FIG. 9 is a diagram showing another example of coefficient data in the section.

FIG. 13 is a diagram illustrating an example of a muting output in a muting device of a conventional subband division coded audio decoder.

FIG. 14 is a diagram illustrating another example of the muting output in the muting device of the conventional subband division coded audio decoder.

[Explanation of symbols]

1 synchronization detector, 2 frame unpacking circuit, 3
CRC detector, 4-bit allocation decoder, 5
Scale factor decoder, 6 inverse quantizer, 7 inverse normalizer, 8 subband synthesizer, 10 OR gate, 11
Orthogonal transformer, 12 512 window coefficient ROM, 13 multiplier, 14 "0" generator, 15 selector, 16 ring memory, 17 accumulative addition means, 18 32 word buffer memory, 21 switch circuit, 22 switch control circuit, 31 switch Circuit, 32 mute output correction coefficient ROM, 33 correction coefficient multiplier, 34 output selector.

Claims (4)

(57) [Claims] 1. A decoder for receiving a bit stream coded according to a sub-band division coding method and reproducing a digital audio signal after decoding by sub-band synthesis, wherein the sub-band synthesizer includes an orthogonal transformer and a window coefficient. RO
A multiplier for multiplying M, the window coefficient, and the orthogonal transformation value, a “0” generator, a selector for switching between the multiplication result of the multiplier and an output of the “0” generator, and a window length 2MN (the number of subband divisions) A memory for storing data of 2M (M: integer) times N and outputs from the selector are X ₀ ^t , X ₁ ^t ,.
... and X _2MN-1 ^t, the data in the memory Y ₀ ^t-1,
When Y ₁ ^t−1 ,..., Y _2MN−1 ^t−1 , addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
· · Y _2MN-1 adding means back to said memory ^t, the sum N (sub-band division number) samples of the data Y
A sub-band division unit comprising a buffer memory for latching ₀ ^{t to} Y _{N -1} ^t , and performing soft muting by switching the input to the adding means to “0” by the selector when a mute signal is detected. Encoded audio decoder . ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1) 2. A decoder for receiving a bit stream coded according to a sub-band division coding method and reproducing a digital audio signal after decoding by sub-band synthesis, wherein the sub-band synthesizer includes an orthogonal transformer and a window coefficient. RO
A multiplier for multiplying M, the window coefficient, and the orthogonal transformation value, a “0” generator, a selector for switching between the multiplication result of the multiplier and an output of the “0” generator, and a window length 2MN (the number of subband divisions) A memory for storing data of 2M (M: integer) times N and outputs from the selector are X ₀ ^t , X ₁ ^t ,.
... and X _2MN-1 ^t, the data in the memory Y ₀ ^t-1,
When Y ₁ ^t−1 ,..., Y _2MN−1 ^t−1 , addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
· · Y _2MN-1 adding means back to said memory ^t, the sum N (sub-band division number) samples of the data Y
A buffer memory for latching ₀ ^{t to} Y _N-1 ^t , and a switch and a controller for switching whether or not to add data in the memory to the input of the adding means. When a mute signal is detected, the selector inputs the data to the adding means. To "0" and one cycle (2MN) after the detection of the release of the mute signal by the switch and the controller.
A sub-band division coded audio decoder which performs soft muting by not adding data in a memory to an input of an adding means during the period. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1) 3. A decoder for receiving a bit stream coded according to a sub-band division coding method and reproducing a digital audio signal after decoding by sub-band synthesis, wherein the sub-band synthesizer includes an orthogonal transformer and a window coefficient. RO
A first multiplier for multiplying M, the window coefficient, and the orthogonal transformation value;
A “0” generator, a first selector for switching between a multiplication result by the first multiplier and an output of the “0” generator,
Window length 2MN (2M of subband division number N (M: integer)
And memory for storing times) of data output from the first selector X ₀ ^t, X ₁ ^t, and ···· X _2MN-1 ^t,
The data in the memory is represented by Y ₀ ^t−1 , Y ₁ ^t−1 ,.
_{When 2MN-1} ^t-1 is used, addition is performed as shown in the following equation, and as a result, Y ₀ ^t , Y ₁ ^t ,... Y _2MN-1 ^t are _returned to the memory, a switch and a mute output correction coefficient ROM to send the output of the buffer memory and the buffer memory for latching a data Y ₀ ^t ~Y _N-1 ^t of addition result N (sub-band division number) samples in the second multiplier A second multiplier for multiplying a correction coefficient by an output value from the buffer memory; and a second selector for selecting whether to output from the second multiplier or output from the buffer memory, and when a mute signal is detected, The first selector switches the input to the adding means to "0", and the switch inputs the output of the buffer memory to the second multiplier and multiplies it by a mute output correction coefficient to perform predetermined soft muting. Subband division encoded audio decoder, wherein the door. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1) 4. A decoder for receiving a bit stream coded by a sub-band division coding method and reproducing a digital audio signal after decoding by sub-band synthesis. RO
A multiplier for multiplying M, the window coefficient, and the orthogonal transformation value, a “0” generator, a selector for switching between the multiplication result of the multiplier and an output of the “0” generator, and a window length 2MN (the number of subband divisions) A memory for storing data of 2M (M: integer) times N and outputs from the selector are X ₀ ^t , X ₁ ^t ,.
... and X _2MN-1 ^t, the data in the memory Y ₀ ^t-1,
When Y ₁ ^t−1 ,..., Y _2MN−1 ^t−1 , addition as shown in the following expression is performed, and as a result, Y ₀ ^t , Y ₁ ^t ,.
· · Y _2MN-1 adding means back to said memory ^t, the sum N (sub-band division number) samples of the data Y
_A sub-band division coded audio decoder comprising a buffer memory for latching ₀ ^{t to} Y _N-1 ^t and performing muting by switching the input to the addition means to “0” by the selector when a mute signal is detected. A sub-band division coded audio decoder characterized in that a synchronization error detection signal from a synchronization detector and a CRC error detection signal from a CRC detector are used as mute signals. ^{_{Y i t = Y i + N}} t-1 + X i t (i = 0 ··· 2MN-1-N) Y i t = X i t (i = 2MN-N ··· 2MN-1)