JP3261729B2 - Linear interpolation method and its circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing linear interpolation method suitable for digital audio equipment such as a CD player and a circuit therefor.

[0002]

2. Description of the Related Art A conventional interpolation operation method of a linear interpolation circuit always performs an operation by using correct data before and after the n consecutive error data, if the data error is within n consecutive errors. , By changing the multiplication coefficient in the calculation,
It is characterized by obtaining from the first error data to the n-th error data.

FIG. 3 shows an operation method of a linear interpolation circuit capable of performing linear interpolation if there are no more than eight consecutive data errors. Hereinafter, the calculation method of the conventional interpolation circuit will be described with reference to FIG.

When the number of error data (the number of error data) shown in FIG.

[0005]

(Equation 1)

[0006] When the number of error data shown in FIG.

[0007]

(Equation 2)

[0008] When the number of erroneous data shown in FIG. 3C is 9, the calculation method is to replace the previous correct data with the replaced data (previous value hold data).
And the interpolation calculation is performed using the calculation method shown in FIG.

[0009]

(Equation 3)

FIG. 4 shows an example of the configuration of the above-described conventional linear interpolation circuit. Hereinafter, the configuration of the conventional linear interpolation circuit will be described with reference to FIG.

In FIG. 4, reference numeral 1 denotes a data shift register for sequentially shifting input data 21 of a linear interpolation circuit. An error flag shift register 2 sequentially shifts an error flag indicating an error in the input data.
Reference numeral 3 denotes a flag decoder that reads an output signal from the error flag shift register 2 and controls each circuit. Reference numeral 4 denotes one of output data of individual stages of the data shift register 1 in accordance with a control signal from the flag decoder 3.
It is a selector to choose one. Reference numeral 5 denotes a register for temporarily holding data selected by the first switch 6. 6 selects the output data of the last stage of the data shift register 1 by the control signal from the flag decoder 3 and shifts it to the register 5, or selects the data temporarily held and output from the register 5 and feeds it back to the register 5 This is a first switch for switching whether to input. Reference numeral 7 denotes a ROM that stores coefficients used for interpolation calculation. Reference numeral 8 denotes a coefficient A stored in the ROM 7 which is determined by the data temporarily held and output by the register 5 and the control signal from the flag decoder 3.
Is a first multiplier that performs multiplication with the following. Reference numeral 9 denotes a second multiplier for multiplying output data from the selector 4 and a coefficient B stored in the ROM 7 determined by a control signal from the flag decoder 3. An adder 10 adds the output data of the first multiplier 8 and the output data of the second multiplier 9. 11 is the output data from the first switch 6 and the adder 10
Is a second switch for switching output data from.
Then, the output data from the second switch 11 is used as the output of the entire linear interpolation circuit.

The operation of the linear interpolation circuit configured as described above will be described below with reference to FIG.

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is at the last stage of the data shift register 1, an output signal indicating that the data D0 is correct data is output to the error flag shift register 2. Is output to the flag decoder 3 so that the flag decoder 3
The control signal is output to the switch 6 and the second switch 11. With this signal, the first switch 6 selects the output data of the last stage of the data shift register 1, and the second switch 11 selects the output data of the first switch 6.
The register 5 temporarily holds the output data of the last stage of the data shift register in the next clock cycle. At this time, the output of the entire linear interpolation circuit is the output data of the last stage of the data shift register (in this case,
Data D0) is output.

Next, when the input data D1 is shifted in the next clock cycle and is at the final stage of the data shift register 1, the error flag shift register 2 outputs an output signal indicating that the data D1 is erroneous data. By outputting to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 6 and the second switch 11. By this signal, the first switch 6 causes the register 5
Selects the data temporarily held and output (in this case, data D0), and the second switch selects the output data from the adder 10. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the flag decoder 3
From among the coefficients stored in the ROM 7, the coefficient A used in the first multiplier 8 (in this case, the coefficient A = 8/9) and the coefficient B used in the second multiplier 9 In this case, coefficient = 1/9) is determined. Then, the first multiplier 8
Is the data temporarily held in the register 5 and output and the coefficient A
The second multiplier 9 multiplies the output data (in this case, data D9) of the data shift register 1 selected by the selector 4 by the coefficient B. And
The adder 10 adds the output data of the first multiplier 8 and the output data of the second multiplier 9. Therefore, the output data of the adder 10 is used as the output of the entire linear interpolation circuit. At this time, in the next clock cycle, the register 5 stores the data selected by the first switch (in this case, the data D
0) is temporarily held.

In the case of FIG. 3C, when all the data in the data shift register 1 are erroneous, the flag decoder 3 operates according to the output signal of the error flag shift register 2 by the first switch 6 and the second switch. The control signal is output to 11. With this signal, the first switch 6 selects the data temporarily held and output by the register 5 (data D0 in this case), and the second switch 11 selects the output data of the first switch 6. Therefore, the output of the entire linear interpolation circuit at this time is temporarily held by the register 5 and output. This means that the correct data before the erroneous data is held at the previous value.

[0016]

However, in the above-mentioned conventional configuration, since the number of coefficients used for the interpolation calculation is large,
There is a problem that the capacity of the ROM containing the above coefficient is large.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a linear interpolation circuit capable of greatly reducing the capacity of a ROM containing the above-mentioned coefficients by reducing the number of coefficients used for interpolation calculation. With the goal.

[0018]

In order to achieve this object, a linear interpolation circuit according to the present invention is arranged so that, if data errors are within n consecutive data, the first of the n consecutive error data is first used. When performing the interpolation operation on the data of the above, the first interpolation operation is performed using the correct data before and after the n consecutive error data, and when performing the interpolation operation on the second data, The calculation is performed by using the first interpolation data obtained by the interpolation calculation and the correct data after the n consecutive error data. Similarly, when performing an interpolation operation on the m-th (m ≦ n) data, the (m−1) -th interpolation data already obtained by the above-mentioned interpolation operation and the correct data after the above-mentioned n consecutive error data are obtained. It is configured to perform the calculation using.

[0019]

With this configuration, the number of coefficients used in the interpolation operation of the linear interpolation circuit of the present invention can be reduced, so that the capacity of the ROM containing the coefficients used in the interpolation operation can be reduced.

[0020]

(Embodiment 1) The configuration of a first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a linear interpolation circuit according to a first embodiment of the present invention. In FIG. 1, a data shift register 1, an error flag shift register 2, a flag decoder 3, a selector 4, a register 5, and a ROM 7 are the same as in the conventional configuration. 12 is the flag decoder 3
The output data of the last stage of the data shift register 1 is selected and input to the register 5 in accordance with the control signal from the CPU, or the data temporarily held and output in the register 5 is selected and fed back and input to the register 5; , A first switch for selecting whether the output data of the operation unit 13 is selected and input to the register 5. Reference numeral 13 denotes an operation unit that performs processing by a predetermined operation using data temporarily held and output by the register 5 and output data from the selector 4. Reference numeral 14 denotes a second switch for switching between output data from the first switch 12 and output data from the operation unit 13.
The data selected by the second switch 14 is used as the output of the entire linear interpolation circuit. In the operation unit 13, reference numeral 15 denotes a first multiplier for multiplying the data temporarily held and output by the register 5 and a coefficient A built in the ROM 7 determined by a control signal from the flag decoder 3. 16 is a coefficient B stored in the ROM 7 determined by the output data from the selector 4 and the control signal from the flag decoder 3.
Is a second multiplier for multiplying by. 17 is the first multiplier
This is an adder for adding the output data from the second multiplier 16 to the output data from the second multiplier 16. The output data from the adder 17 is used as the output of the arithmetic unit 13.

The operation method and operation of the linear interpolation circuit configured as described above will be described with reference to FIG.

FIG. 3 shows a calculation method of a linear interpolation circuit capable of performing linear interpolation if there are no more than eight consecutive data errors. The operation method of the linear interpolation circuit of the first embodiment is as follows.
When the number of error data (number of error data) shown in FIG. 3A is 1, the calculation method shown in (Equation 1) is performed similarly to the conventional example, and the number of error data shown in FIG. When

[0024]

(Equation 4)

## EQU1 ## When the number of erroneous data shown in FIG. 3C is 9, the data is replaced with the previous correct data, and the replaced data (previous value hold data) is used.
The interpolation calculation is performed using the calculation method shown in FIG.

[0026]

(Equation 5)

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is in the last stage of the data shift register 1, an output signal indicating that the data D0 is correct is output to the error flag shift register 2. Is output to the flag decoder 3 so that the flag decoder 3
The control signal is output to the switch 12 and the second switch 14. By this signal, the first switch 12 outputs the final stage output data of the data shift register 1 (in this case, the data D
0), and the second switch 14 selects the output data from the first switch 12. As a result, the register 5 stores the data shift register 1 in the next clock cycle.
Temporarily holds the output data of the last stage of. At this time, the output of the linear interpolation circuit outputs the final stage output data of the data shift register 1.

Next, when the input data D1 is shifted in the next clock cycle and is at the final stage of the data shift register 1, the error flag shift register 2 outputs an output signal indicating that the data D1 is erroneous data. By outputting to the decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. According to this signal, the first switch 12 selects the output data of the arithmetic unit 13 and the second switch 14 selects the output data from the arithmetic unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, according to the control signal from the flag decoder 3, the coefficient A used in the first multiplier 15 (in this case,
The coefficient A = 8/9) and the coefficient B (the coefficient = 1/9 in this case) used for the second multiplier 16 are determined. And a first multiplier
Reference numeral 15 multiplies the data temporarily stored in the register 5 (the data D0 in this case) and the coefficient A, and the second multiplier 16 outputs the output data of the data shift register 1 selected by the selector 4 (this data). Case: Multiply the data D9) by the coefficient B. The output data of the data shift register 1 selected by the selector 4 is always correct data after n consecutive error data. Then, the adder 17 adds the output data of the first multiplier 15 and the output data of the second multiplier 16. Therefore, the output data of the adder 17 is used as the output of the entire linear interpolation circuit. Also, at this time,
The register 5 temporarily holds the data selected by the first switch, that is, the output data of the operation unit 13 (interpolation data D1 in this case) in the next clock cycle.

Further, when the input data D2 is shifted in the clock cycle and is at the last stage of the data shift register 1, this data D2 is shifted in the same manner as when the input data D1 is at the last stage of the data shift register 1. When the error flag shift register 2 outputs an output signal indicating error data to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. With this signal, the first switch
12 selects the output data of the operation unit 13 and the second switch 14
Selects output data from the operation unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the ROM 7 is controlled by a control signal from the flag decoder 3.
Among the coefficients built in the first and second coefficients, the coefficient A used in the first multiplier 15 (coefficient A = 7/8 in this case) and the coefficient B used in the second multiplier 16 (coefficient = 1/8 in this case) ) Is determined. The first multiplier 15 multiplies the data temporarily stored in the register 5 (the interpolation data D1 in this case) by the coefficient A, and the second multiplier 16 performs the multiplication for the data selected by the selector 4. The output data of the shift register 1 (data D9 in this case) is multiplied by a coefficient B. Then, the adder 17 adds the output data of the first multiplier 15 and the output data of the second multiplier 16. Therefore, the output data of the adder 17 is used as the output of the entire linear interpolation circuit. Also, at this time,
The register 5 temporarily holds the data selected by the first switch, that is, the output data of the operation unit 13 (in this case, the interpolation data D2) in the next clock cycle.

Thereafter, interpolation is performed for all eight consecutive error data while repeating the same operation.

In the case of FIG. 3C, when all the data in the data shift register 1 are erroneous, the flag decoder 3 outputs the first switch 12 and the second switch 12 by the output signal of the error flag shift register 2. The control signal is output to 14. With this signal, the first switch 12 selects the data temporarily held and output by the register 5 (data D0 in this case), and the second switch 14 selects the output data from the first switch 12. Therefore, the output of the entire linear interpolation circuit at this time is temporarily held by the register 5 and output. This means that the correct data before the error is held at the previous value. Then, using the previous value hold data, interpolation is performed using the same calculation method as in the case of FIG.

Table 1 compares the number of coefficients used in the interpolation operation of the linear interpolation circuit in the present embodiment and the conventional case.

[0033]

[Table 1]

As apparent from Table 1 above, the first
Since the number of coefficients used for the interpolation operation can be made equal to or less than that of the conventional case, the linear interpolation circuit in the case of the first embodiment has an excellent effect in that the capacity of the ROM incorporating the above coefficients can be reduced.

(Embodiment 2) The configuration of a second embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a configuration diagram of a linear interpolation circuit according to a second embodiment of the present invention. 2, a data shift register 1, an error flag shift register 2, a flag decoder 3, a selector 4, a register 5, a ROM 7, a first switch 12, and a second switch 14 are the same as those in FIG. . The operation unit 13 differs from the configuration of FIG. 1. In the operation unit 13, reference numeral 18 denotes a subtractor that subtracts data temporarily held by the register 5 and output from the data output from the selector 4. A multiplier 19 multiplies output data from the subtracter 18 by a coefficient A stored in the ROM 7 determined by a control signal from the flag decoder 3. An adder 20 adds the output data from the multiplier 19 and the output data temporarily held and output by the register 5. The output data from the adder 20 is used as the output of the operation unit 13.

The operation method and operation of the linear interpolation circuit configured as described above will be described with reference to FIG.

FIG. 3 shows a method of calculating a linear interpolation circuit capable of performing linear interpolation if there are no more than eight consecutive data errors. The method of calculating the interpolation data in the case of the second embodiment is such that when the number of error data (the number of error data) shown in FIG.

[0039]

(Equation 6)

When the number of error data shown in FIG. 3B is 8,

[0041]

(Equation 7)

Is as follows. When the number of erroneous data shown in FIG. 3C is 9, the data is replaced with the previous correct data, and the replaced data (previous value hold data) is used.
The interpolation calculation is performed using the calculation method shown in FIG.

[0043]

(Equation 8)

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is at the last stage of the data shift register 1, an output signal indicating that the data D0 is correct is output to the error flag shift register 2. Is output to the flag decoder 3 so that the flag decoder 3
The control is output to the switch 12 and the second switch 14. By this signal, the first switch 12 outputs the final stage output data of the data shift register 1 (in this case, data D0).
And the second switch 14 selects the output data of the first switch 12. As a result, the register 5 temporarily holds the output data of the last stage of the data shift register 1 at the next clock. At this time, the output of the entire linear interpolation circuit outputs the output data of the last stage of the data shift register 1.

Next, when the input data D1 is shifted in the next clock cycle and is in the last stage of the data shift register 1, the error flag shift register 2 outputs an output signal indicating that the data D1 is erroneous data. By outputting to the decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. According to this signal, the first switch 12 selects the output data of the arithmetic unit 13 and the second switch 14 selects the output data from the arithmetic unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, according to a control signal from the flag decoder 3, a coefficient A used in the multiplier 19 (in this case, coefficient A = 1 /
9) is determined. Then, the subtractor 18 subtracts the data temporarily stored and output by the register 5 (data D0 in this case) from the output data of the data shift register 1 selected by the selector 4 (data D9 in this case). The output data of the data shift register 1 selected by the selector 4 is always correct data after n consecutive error data. Then, the multiplier 19 multiplies the output data of the subtractor 18 by the coefficient A. Then, the adder 20 adds the output data of the multiplier 19 and the data temporarily held and output by the register 5. Therefore, the output data of the adder 20 is used as the output of the entire linear interpolation circuit.
The register 5 stores the first clock in the next clock cycle.
, The data selected by the switch
Thirteen output data (in this case, interpolation data D2) are temporarily held.

Further, when the input data D2 is shifted in the clock cycle and is at the last stage of the data shift register 1, this data D2 is shifted in the same manner as when the input data D1 is at the last stage of the data shift register 1. When the error flag shift register 2 outputs an output signal indicating error data to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. With this signal, the first switch
12 selects the output data of the operation unit 13 and the second switch 14
Selects output data from the operation unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the ROM 7 is controlled by a control signal from the flag decoder 3.
Coefficient A to be used for the multiplier 19 from among the coefficients built in
(In this case, coefficient A = 1/8) is determined. And the subtractor 18
Is the data temporarily stored and output by the register 5 from the output data of the data shift register 1 selected by the selector 4 (data D9 in this case).
The interpolation data D 2 ) is subtracted. Then, the multiplier 19 multiplies the output data of the subtractor 18 by the coefficient A. Then, the adder 20 adds the output data of the multiplier 19 and the data temporarily held and output by the register 5. Therefore, the output data of the adder 20 is used as the output of the entire linear interpolation circuit.
The register 5 stores the first clock in the next clock cycle.
, The data selected by the switch
Thirteen output data (in this case, interpolation data D 3 ) are temporarily held.

Thereafter, interpolation is performed for all eight consecutive error data while repeating the same operation.

In the case of FIG. 3C, when all the data in the data shift register 1 are erroneous, the flag decoder 3 outputs the first switch 12 and the second switch 12 by the output signal of the error flag shift register 2. The control signal is output to 14. With this signal, the first switch 12 selects the data temporarily held and output by the register 5, and the second switch 14 selects the output data of the first switch 12. Therefore, the output of the entire linear interpolation circuit at this time is temporarily held by the register 5 and output. This means that the correct data before the error is held at the previous value. Then, using the previous value hold data, interpolation is performed using the same calculation method as in the case of FIG.

As described above, by configuring the circuit of the arithmetic unit 13, the comparison of the number of coefficients used in the interpolation operation of the linear interpolation circuit between the case of the present embodiment (Table 1) and the conventional case can be obtained. Obviously, the linear interpolation circuit in the case of the second embodiment can make the number of coefficients used for the interpolation calculation equal to or less than that of the conventional case.
An excellent effect is obtained in that the capacity of the OM can be significantly reduced. Further, the second embodiment can obtain more excellent effects than the first embodiment.

[0050]

As described above, the linear interpolation method according to the present invention
Is n or more consecutive error data in the linear interpolation circuit.
First, when performing the interpolation calculation of
Using the correct two data before and after the data,
Only the interpolation operation of the first error data adjacent to the data
The first interpolated data is used, and then calculated by the above-described interpolation operation.
Handles the first interpolated data obtained as correct data
And performs an interpolation operation on the remaining consecutive n-1 error data.
At this time, the first data before and after the (n-1) error data are again used.
Using two correct data including interpolation data of
Performs only the interpolation operation on the error data adjacent to the new data,
Thereafter, the same operation is repeated sequentially, and finally n continuous
Is performed for all the error data. Also,
The linear interpolation circuit performs an interpolation operation on the first data of the n consecutive error data if the data error is within n consecutive error data. performing a first interpolation operation using the front and rear correct data, when the next interpolation operation two first data, and one th interpolated data that has been already obtained by the interpolation operation, the continuous n The operation is performed using the correct data after the error data. Similarly, when the m-th (m ≦ n) data is subjected to the interpolation calculation, the m-th data already obtained by the above-described interpolation calculation is
The calculation is performed by using the first interpolated data and the correct data after the n consecutive error data.

With the above configuration, the linear interpolation circuit of the present invention uses the correct two data before and after
Only the interpolation operation of the first error data adjacent to
1 interpolation data, and then correct the first interpolation data.
Data and use it for the next interpolation operation.
Since the same operation is performed next, the number of coefficients used for the interpolation operation can be reduced, and R
An excellent linear interpolation circuit capable of reducing the capacity of the OM can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a linear interpolation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a linear interpolation circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a method of calculating linear interpolation for explaining the operation of a linear interpolation circuit in the first embodiment, the second embodiment, and the conventional example.

FIG. 4 is a configuration diagram of a conventional linear interpolation circuit.

[Explanation of symbols]

 1 data shift register 2 error flag shift register 3 flag decoder 4 selector 5 register 6,11,12,14 switch 7 ROM 8,9,15,16,19 multiplier 10,17,20 adder 18 subtractor

────────────────────────────────────────────────── ─── Continued from the front page (72) Inventor Takeyuki Takayama 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. -39990 (JP, B1) JP-B 61-30344 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00

Claims (5)

(57) [Claims] When performing an interpolation operation on n or more consecutive error data in a linear interpolation circuit, first, the n
Using two correct data before and after the error data,
Only interpolation operation of the first error data adjacent to the correct data as the first interpolation data I line, handling the next first interpolated data obtained by interpolation of the as the correct data, the remaining continuous n When performing an interpolation operation on -1 error data, error data adjacent to the correct data is again used by using two correct data including the first interpolation data before and after the n-1 error data. A linear interpolation method characterized in that only the interpolation calculation of the above is performed, and thereafter, the same calculation is sequentially repeated, and finally the interpolation calculation of all n consecutive error data is performed. 2. In a linear interpolation circuit, if the number of data errors is within n consecutive data, when the first data of the n consecutive error data is interpolated first, the n consecutive error data is calculated. the using of the front and rear of the correct data of the error data 1
Performs interpolation operation, the next time you interpolation calculation 2 -th data is already complement of one eye obtained by the interpolation operation
When the calculation is performed using the interim data and the correct data after the above-mentioned n consecutive error data, and the m-th (m ≦ n) data is similarly subjected to the interpolation calculation, the interpolation calculation has already been performed. And the (m-1) th interpolation data
2. The linear interpolation method according to claim 1, wherein the calculation is performed using correct data after the error data. 3. A data shift register for sequentially shifting input data of the linear interpolation circuit when configuring the linear interpolation circuit, and an error flag shift register for sequentially shifting an error flag indicating an error in the input data. And a flag decoder that reads an output signal from the error flag shift register and controls each circuit.
A selector for selecting one of output data of individual stages of the data shift register according to a control signal from the flag decoder, a register for temporarily holding data selected by a first switch, Whether to select the output data of the last stage of the data shift register by the control signal and input it to the register, or select the data temporarily held and output by the register, feed it back, and input it to the register, A first switch for selecting whether to output operation unit output data and inputting the data to the register, and an operation for performing processing by a predetermined operation using output data from the first switch and output data from the selector And output data from the first switch according to a control signal from the flag decoder. A second switch for selecting whether to select the operation unit output data, and to output data from the second switch as output data of the entire linear interpolation circuit. A linear interpolation circuit based on the linear interpolation method according to claim 2. A first multiplier configured to multiply data temporarily held and output by the register and a coefficient determined by a control signal from the flag decoder when configuring the arithmetic unit; and the selector. A second multiplier for multiplying the output data from the multiplication by a coefficient determined by a control signal from the flag decoder, and the output data from the first multiplier and the output data from the second multiplier. 4. The linear interpolation circuit according to claim 3, further comprising an adder for adding, wherein data output from the adder is used as output data of a calculation unit . 5. A subtracter for subtracting data temporarily held and output by said register from output data from said selector when configuring said arithmetic unit, and a data output from said subtractor and said flag decoder. A multiplier for multiplying by a coefficient determined by the control signal of (i), and an adder for adding data temporarily held and output by the register and output data from the multiplier, and output from the adder. 4. The linear interpolation circuit according to claim 3, wherein the data is output data of the operation unit .