JP3257535B2 - Logical collator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in a logic matching system in which a circuit element having the same name is divided into two small circuits between two logic circuits, and a logic check is performed on the divided small circuits. Related to the device .

[0002]

2. Description of the Related Art In the design of a logic circuit, it may be necessary to modify the configuration of the logic circuit after the design is already completed, for example, to adjust the delay time. In this case, only the configuration of the logic circuit must be changed without changing the logic of the logic circuit. Therefore, it is necessary to verify the logical equivalence of the two logic circuits before and after the correction. Examining the equivalence of two logic circuits in this way is called logical collation, and a method using a BDD (Binary Decision Tree) or a Boolean expression (product-sum logical expression) is generally used. Conventionally, 2
In the logical comparison of two logic circuits, a large amount of time is required for the matching process when the scale of the logic circuit becomes large. Therefore, the two logic circuits are divided into small circuits by using a circuit element having the same name as a cutoff between the two logic circuits. Logical matching was performed on small circuits. This method is disclosed in detail in, for example, JP-A-1-237473.

[0003]

By the way, as described above,
In a method in which a circuit element having the same name is divided into small circuits between two logic circuits as a cut and a logical check is performed on the divided small circuits, when performing a logical change across the cut circuit element, a logical check is performed. May incorrectly result in a mismatch. For example, in the case of the logical comparison between the “before correction” circuit and the “after correction” circuit as shown in FIG. 2, since each circuit is divided into small circuits by the circuit element “SEL” having the same name, the logical comparison is 1 ( Before modification: A-I1) (After modification:
A-V1-I1), 2 (before modification: B-I2) (after modification:
B-V2-I2), 3 (before modification: C-I3) (after modification:
CI-3), 4 (before modification: O-D) (after modification: O-V3)
-D) is performed by a combination of four sets of small circuits. in this case,
The logic of the whole circuit should be the same before and after the correction, but the result of the logical comparison divided into small circuits will be mismatched at 1, 2, and 4 among the combinations of the small circuits, Normal logical collation results cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in a logic matching device for verifying the equivalence of two logic circuits, a logic circuit having the same name is used between the two logic circuits. When the logical comparison is performed by dividing the circuit into small circuits and a logical mismatch due to inverted logic occurs as a result, the logic of the small circuit in the input direction of the circuit element having the same name that generated the small circuit is compared with the small circuit where the mismatch occurred. In the case where the logical matching is performed in consideration of the matching result and the logic of the same-named circuit element, the processing time required for the logical matching is reduced, and the logical change is performed across the circuit element to be cut. It is another object of the present invention to provide a logical matching device capable of obtaining a normal logical matching result.

[0005]

According to a first aspect of the present invention, there is provided a logical matching apparatus, comprising:
The first and second logic circuits before and after
First and second logic circuit storage means, and the first and second logic circuits
From the logic circuit stored in the circuit storage means to the circuit of the same name
The element is extracted, and the circuit element of the same name
1. Logic circuits stored in the second logic circuit storage means
Circuit element extraction method to extract small circuit from output direction
Stage and a logical reference to each of the extracted small circuits.
First logical collation executing means for performing a combination,
As a result of logical matching by the matching means,
If there is a match, the corresponding small circuit is sequentially regenerated by the small circuit.
And terminates the process if there is no logic mismatch due to inversion logic.
Logical comparison result determination means that completes the
The same name that became the starting point when creating a matching small circuit
From the circuit elements, the input signal of the circuit element of the same name in the input direction
Refers to the logical comparison result of the small circuit connected to
If the result does not match the logic of the inverted logic,
If the logic matches, a circuit element with the same name as a normal input signal
Small times after correction that resulted in logic mismatch due to inverted logic
Correct the input of the small circuit connected to the
A small circuit connected to the small circuit before correction is added as a normal input signal.
Small circuit regenerating means for newly generating and small circuit regenerating means
Logical comparison for each of the small circuits regenerated by
And a second logical collation executing means for performing .

[0006]

According to the present invention, in a logic matching device for verifying the equivalence of two logic circuits, a logic circuit is divided into small circuits by circuit elements having the same name between the two logic circuits, and the logic matching is performed. When a logic mismatch occurs due to logic, the logic matching result of the small circuit in the input direction of the same-named circuit element that generated the small circuit and the logic of the same-named circuit element are considered for the small circuit in which the mismatch occurred. Performs logical matching, thereby reducing the processing time required for logical matching and obtaining a normal logical matching result even when performing a logical change across circuit elements to be cut. And improve reliability.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention. The logical matching device of the present invention includes logic circuit storage means 1 and 2, circuit element extracting means 3 with the same name, circuit element storing means 4 with the same name, small circuit extracting means 5, small circuit storing means 6, logical matching executing means 7, logical matching A result storage means 8, a logical collation result determination means 9, a small circuit creation means 10 by inversion input,
It is composed of a small circuit storage means 11 by inversion input, a logic matching execution means 12, and a logic matching result storage means 13.

In FIG. 1, the logic circuit storage means 1 stores a logic circuit before correction to be subjected to logical comparison, and the logic circuit storage means 2 stores a corrected logic circuit to be subjected to logical comparison. Is done. The circuit element extracting means 3 having the same name
From the logic circuit stored in the logic circuit storage means 1 and the logic circuit stored in the logic circuit information 2, a circuit element having the same name is extracted and stored in the circuit element storage means 4 with the same name. The small circuit extracting means 5 uses the circuit element stored in the circuit element storing means 4 of the same name as a cut-off point to extract the logical circuit stored in the logical circuit storing means 1 and the logical circuit stored in the logical circuit storing means 2. The small circuit is extracted from the output direction and stored in the small circuit storage means 6. The logical matching executing means 7 performs a logical matching on the small circuit stored in the small circuit storing means 6 and stores the result in the logical matching result storing means 8.

If the logical comparison result stored in the logical comparison result storage means 8 includes a result of “logical mismatch due to inverted logic”, the logical matching result determination means 9 determines the small circuit having the mismatch result. Small circuit creation means 10 by inverting input
, And if there is no “logic mismatch due to inversion logic” result, all processes are terminated. The inverting input small circuit creating means 10 connects the input signal of the same-named circuit element in the input direction from among the same-named circuit elements that have become the cut ends when creating a small circuit that has “logic mismatch due to inverted logic”. The logic matching result of the small circuit is referred to, and if the result is "logic mismatch due to inverted logic", it is regarded as an inverted input signal, and if the result is logically matched, it is regarded as a normal input signal. A new small circuit connected to the small circuit after the correction and a small circuit connected to the small circuit before the correction as all normal circuit input signals of the same-named circuit elements are newly generated.
Small circuit storage means 11 by inverting the generated small circuit
To be stored. The logical comparison executing means 12 performs a logical comparison on the small circuit stored in the small circuit storing means 11 by inverting input, and stores the execution result in the logical matching result storing means 13.
To be stored. The above-described series of operations from the logical collation result determination means 9 to the logical collation result storage means 13 are performed on all the small circuits which are stored in the logical collation result storage means 8 and have resulted in “logical mismatch due to inverted logic”. Do it for Here, as a method of executing the logical comparison, here, conversion and comparison are performed using a Boolean expression (product-sum logical expression), that is, each of the two logic circuits is converted into a Boolean expression.
A method of illuminating whether a predetermined condition is satisfied is adopted. Since the specific method deviates from the gist of the present invention, further details are omitted.

FIGS. 2 and 3 are diagrams cited for explaining the operation principle of the present invention. FIG. 2 is a diagram showing the configuration of a logic circuit before and after correction with a truth table. Each of the figures shows an example of a regenerated small circuit with a truth table. The present invention relates to a logic matching method for verifying the equivalence of two logic circuits, performing logic matching by dividing a logic circuit into small circuits by using circuit elements having the same name between the two logic circuits, and performing logic matching based on inverted logic as a result. If a mismatch occurs, the logic matching is performed on the small circuit in which the mismatch has occurred in consideration of the logic matching result of the small circuit in the input direction of the same name circuit element that generated the small circuit and the logic of the same name circuit element. The feature of performing is as described above.

Specifically, in FIG. 2, the "before" and "after" circuits have the same logic as shown in the truth table (when input I3 is "0", α of input I1 is output to D). , When the input I3 is “1”, β of the input I2 is output to D). When the logical matching is performed by the method of the present invention, 2
In each of the circuits, a circuit element “before correction” and a circuit “after correction” are divided into small circuits by a circuit element “SEL” having the same name. As a result of the division, A-I1 (SEL), B
-I2 (SEL), C-I3 (SEL), O (SEL) -D sub-circuits are generated, and A-V1
-I1 (SEL), B-V2-I2 (SEL), C-I3
A small circuit of (SEL), O (SEL) -V3-D is generated. The logical collation operation is 1 (before modification: A-I1) (after modification: A-V1-I1), 2 (before modification: B-I2) (after modification: B-V2-I2), 3 (before modification: C-I3) (after correction: C-I3), 4 (before correction: O-D) (after correction: O-
V3-D).

Here, among the four sets of logical comparison results, 3 is "logical match", 1, 2, and 4 are "logical mismatch by inverted logic", and the small circuit 1 in which "logical mismatch by inverted logic" occurs. About (2) and (4), (1) (2)
It is regenerated in the procedure of. (1) The small circuit 1 connected to the input signal of the circuit element “SEL” having the same name, which is a cut when the four small circuits are generated,
Reference is made to the logical comparison results of 2 and 3, and 1 and 2 are logically inconsistent by inverted logic, and 3 is logically coincident. Therefore, the input signals I1 and I2 of "SEL" are inverted logical, and I3 is normal "S".
EL "is connected to the modified small circuit of 4. (2)" S "in which the input signals I1, I2 and I3 are made normal signals
EL "is connected to the small circuit before the correction of 4. The small circuit shown in FIG. 3 is generated according to the above procedure, and the generated small circuit is subjected to logical comparison again.
The result of the logical comparison here is “logical match”, and the circuit before correction and the circuit after correction in FIG. 2 are proved as “logical match”. In the logical matching method described above, a circuit element having the same name is divided into small circuits between two logical circuits, and the logical matching is performed on the divided small circuits, thereby shortening the processing time of the logical matching. In addition, it is possible to obtain a normal logical collation result.

FIGS. 4 to 6 are diagrams cited for explaining the specific operation of the embodiment of the present invention shown in FIG. 1, and are each a circuit configuration example (1) of a logic circuit before and after correction.
, A diagram showing a combination example (1) of small circuits in a table format, and a diagram showing a configuration example (1) of a small circuit before and after a regenerated correction. FIG. 4 shows the logic circuit storage means 1.
4 is stored, and the logic circuit storage means 2 stores the "after correction" circuit of FIG. The logic circuit element extraction means 3 extracts the circuit elements “SEL” and “A1” having the same name in the circuits stored in the logic circuit storage means 1 and the logic circuit storage means 2 and stores them in the circuit element storage means 4 having the same name. I do. The small circuit extracting means 5 extracts the circuit elements “SEL” and “A1” having the same name stored in the circuit element storing means 4 from the respective circuits stored in the logical circuit storing means 1 and the logical circuit storing means 2. As a cut end, a small circuit is extracted from the output direction, and a combination of the six small circuits shown in FIG. Logical matching execution means 7
Performs logical comparison on the six combinations of small circuits stored in the small circuit storage unit 6 and stores the execution result in the logical comparison result storage unit 8. The logical matching result storage means 8 stores the result of “logical match” for the small circuit of the combination shown in FIG. 5, and the result of “logical mismatch by inverted logic” for the small circuit of the combination. The result is stored. Here, the logical-matching-result determining means 9 sequentially searches the logical-matching results stored in the logical-matching-result storing means 8 for combinations of small circuits having “logical mismatch due to inverted logic”. , The combination of the small circuits shown in FIG.

The small-circuit creating means 10 based on the inverting input outputs the input signal "SE" of the circuit elements "SEL" and "A1" of the same name, which have been cut when creating the small circuit of FIG.
Referring to the result of logical comparison of the small circuit connected to each input signal of "L", the result of FIG.
Since the result of FIG. 5 connected to “I2” is “logic mismatch due to inverted logic”, the input signals “I1” and “I2” of “SEL” are used as inverted input signals, and “I3”
5 is "logically coincident", the circuit in which the input signal "I3" of "SEL" is a normal input signal is connected to the modified small circuit in FIG.
A circuit in which all the input signals "I1", "I2", and "I3" of "SEL" are normal input signals is connected to the small circuit before correction in FIG. 5, and the circuit shown in FIG. It is stored in the small circuit storage means 11. The logical collation executing means 12 performs logical collation on the circuit of FIG. 6 stored in the small circuit storage means 11 based on the inverted input, and outputs the logical collation result “logical match” to the logical collation result storage means 13. Store. The fact that the circuit of FIG.
The portion enclosed by a dotted line in the circuit before correction in FIG. 4 and the portion enclosed by a dotted line in the circuit after correction indicate "logical coincidence".

FIGS. 7 to 9 are diagrams cited for explaining the specific operation of the embodiment of the present invention shown in FIG. 1, and are diagrams showing circuit configuration examples (2) of a logic circuit before and after correction, respectively. FIG. 9 is a diagram showing a combination example (2) of a small circuit in a table format, and a diagram showing a configuration example (2) of a small circuit before and after a regenerated correction. FIG. 7 shows the logic circuit storage means 1.
The circuit before “correction” is stored, and the circuit after “correction” in FIG. 7 is stored in the logic circuit storage means 2. The logic circuit element extraction means 3 of FIG. 1 extracts circuit elements "SEL" and "B1" having the same name from the circuits stored in the logic circuit storage means 1 and the logic circuit storage means 2, and stores the same circuit element storage means. 4 is stored. The small circuit extracting means 5 extracts the circuit elements "SEL" and "B1" of the same name stored in the circuit element storing means 4 from the respective circuits stored in the logical circuit storing means 1 and the logical circuit storing means 2. As a cut, a small circuit is extracted from the output direction, and a combination of the five small circuits shown in FIG. 8 is stored in the small circuit storage means 6 in FIG.

The logical matching executing means 7 is provided with the small circuit storing means 6
The logical matching is performed on the small circuits of the five combinations stored in the logical matching result storage unit 8. The logical matching result storage means 8 stores the result of “logical match” for the small circuit of the combination of FIG.
The result of "logic mismatch due to inverted logic" is stored for the small circuit of the combination. The logical collation result determining means 9 in FIG. 1 sequentially searches the logical collation results stored in the logical collation result storage means 8 for a combination of small circuits having "logical mismatch due to inverted logic". , FIG.
Are passed to the small circuit creating means 10 based on the inverting input of FIG.

The small-circuit creating means 10 based on the inverting input refers to the logical collation result of the small circuit connected to the input signal of the circuit element "B1" of the same name, which has become a starting point when the small circuit of FIG. 8 is created. Since FIG. 8 connected to “I” is “logically coincident”, it is further connected to each input signal of the circuit element “SEL” of the same name, which has become a cut when creating a small circuit. Refers to the logical matching result of the small circuit
Since the result of FIG. 8 connected to “I1” and the result of FIG. 8 connected to “I2” are “logic mismatch due to inverted logic”, the input signal “I1” of “SEL”
Since the result of FIG. 8 connected to “I3” and “I3” is “logical coincidence”, “S
The circuit in which the input signal "I3" of EL is a normal input signal is connected to the modified small circuit of FIG. 8, and the input signals "I1", "I2" and "I3" of "SEL" are all normally input. A circuit in which the signal circuit is connected to the small circuit before correction shown in Fig. 8 is created, and the circuit shown in Fig. 9 is stored in the small circuit storage means 11 using inverted input. The logical comparison is performed on the circuit of FIG. 9 stored in the storage unit 11, and the “logical match” as the logical comparison result is stored in the logical comparison result storage unit 13.
The fact that the circuit in FIG. 9 is “logically coincident” indicates that the circuit before modification and the circuit after modification in FIG. 7 are “logically coincident”. In the embodiment of the present invention, both the logic circuit storage unit and the logic comparison execution unit are described as first and second and are treated as separate units. There is no problem at all.

[0019]

As described above, according to the present invention, in a logic matching method for verifying the equivalence of two logic circuits, the logic circuit is divided into small circuits by using circuit elements having the same name between the two logic circuits. If the matching is performed and a logic mismatch occurs due to the inverted logic, the small circuit where the mismatch occurred
The logic matching is performed by taking into account the logic matching result of the small circuit in the input direction of the same-named circuit element that generated the small circuit and the logic of the same-named circuit element. It is possible to obtain a normal logical comparison result even when shortening and making a logical change across circuit elements to be cut.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram cited for explaining the operation principle of the present invention, and is a diagram showing a configuration example of a logic circuit before and after correction with a truth table.

FIG. 3 is a diagram cited for explaining the operation principle of the present invention, and is a diagram illustrating a configuration example of a small circuit regenerated from a small circuit before and after correction with a truth table.

FIG. 4 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing a configuration example (1) of a logic circuit before and after correction.

5 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing an example (1) of a combination of small circuits in a table format.

6 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing an example (1) of a small circuit regenerated from a small circuit before and after correction.

7 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing a configuration example (2) of a logic circuit before and after correction.

8 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing an example (2) of a combination of small circuits in a table format.

9 is a diagram cited for explaining the operation of the embodiment of the present invention shown in FIG. 1, and is a diagram showing an example (2) of a small circuit regenerated from a small circuit before and after correction.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Logic circuit storage means (1st), 2 ... Logic circuit storage means (2nd), 3 ... Same name circuit element extraction means, 4 ... Same name circuit element storage means, 5 ... Small circuit extraction means, 6 ... Small circuit storage Means 7 ... Logical collation execution means (first), 8 ... Logical collation result storage means, 9 ... Logical collation result determination means, 10 ... Small circuit creation means (small circuit regeneration means) by inversion input, 11 ... Inversion input 12 ... Logical collation executing means (second), 13 ... Logical collation result storage means

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 664

Claims (1)

(57) [Claims] Claims: 1. Before and after correction to be subjected to logical comparison
First and second logic circuit storage where respective logic circuits are stored
Means stored in the first and second logic circuit storage means.
Circuit element of the same name is extracted from the logic circuit
The first and second logic circuits are stored by using a circuit element as a cut.
From the logic circuit stored in the means to the output direction of the small circuit
Means for extracting circuit element having the same name
A first logic that performs a logic match on each of the circuits
Matching execution means and logical matching by the first logic matching means
As a result, if there is a logic mismatch due to inversion logic,
The small circuit is sequentially passed to the small circuit regenerating means, and the logic is inverted.
If there is no logical mismatch, terminate the process.
And a small circuit whose logic is inconsistent due to inverted logic.
Input from the circuit element of the same name
Of the small circuit connected to the input signal of the circuit element of the same name in the direction
Refers to the logical collation result, and the result is the logic
If they do not match, use the inverted input signal.
The logic of the same name circuit element as the force signal is inverted logic.
The small circuit connected to the corrected small circuit
All the input of the name circuit element as a normal input signal before correction
Small circuit regeneration that newly generates a small circuit connected to the small circuit
Means and a small circuit regenerated by the small circuit regenerating means
Of the second logical matching to perform logical matching for each of
A logical matching device comprising: