JP3253268B2 - Gradation correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for displaying a multi-screen image on a television receiver or an image display device.
The present invention relates to a tone correction device used for correcting the tone of each image, and more particularly to a device for reducing the amount of circuits and memory used in the device.

[0002]

2. Description of the Related Art In recent years, as color television receivers have become larger and have higher image quality, in order to make images appear clearer, the gradation is corrected by passing a video signal through a non-linear amplifier. A tone correction device for expanding a dynamic range of an image has been given importance. Also, T
In the field of V, the number of screens has been increased, and TVs capable of displaying different programs on two screens obtained by dividing one screen into two areas have become mainstream. In such a case, there has been already proposed a tone correction device having a configuration capable of performing independent tone correction on two screens.

A conventional tone correction device used in a color television receiver having the above functions will be described below. FIG. 19 shows a block diagram of a conventional tone correction device. In FIG. 19, reference numeral 1 denotes an A / D converter for A / D converting a luminance component (hereinafter, referred to as a luminance signal) of an input image signal.
/ D converter. Reference numeral 71 denotes a first histogram memory for extracting a luminance histogram of the input luminance signal. 72
Denotes a first histogram memory interface (hereinafter, referred to as i / f) circuit that controls writing and reading of the first histogram memory 71. Similarly, reference numeral 73 denotes a second histogram memory for extracting a luminance histogram of the input luminance signal. Similarly, reference numeral 74 denotes a second histogram memory i / f circuit for controlling writing and reading of the second histogram memory 73. Reference numeral 4 denotes an arithmetic control unit, which stores the first histogram memory 71, the second
From the luminance histogram data in the histogram memory 73, an operation for calculating a cumulative histogram or further calculating a correction table is performed. Reference numeral 5 denotes a program ROM for storing a calculation program of the calculation control unit 4. Reference numeral 6 denotes a first register RAM, which stores parameters used for calculating data to be stored in a first correction table memory 11 described later. 7 is a second register RAM,
A parameter used to calculate data to be stored in a second correction table memory 13 described later is stored. A first correction table memory 11 stores the correction data calculated by the arithmetic control unit 4. Similarly, a second correction table memory 13 stores the correction data calculated by the arithmetic control unit 4. Generally, a memory address input to these correction table memories 11 and 13 is regarded as a luminance level, and individual correction data is stored at that address.

[0004] Reference numeral 10 denotes a first correction table memory i / f circuit, which controls writing and reading of the first correction table memory 11. Similarly, reference numeral 12 denotes a second correction table memory i / f circuit, which controls writing and reading of the second correction table memory 13.

Reference numeral 18 denotes a synchronization processing circuit which recognizes and grasps phase information such as vertical and horizontal display start points of a video luminance signal, and performs timing control of each memory and circuit. A first selector 14 selects the output of the first correction table memory i / f circuit 10 and the output of the A / D converter 1, and outputs the selection result to the first correction table memory. 11 as an address. That is, when the first correction table memory 11 performs the write operation, the output of the first correction table memory i / f circuit 10 is selected, and when the first correction table memory 11 performs the read operation, the digital video signal which is the output of the A / D converter 1 is selected. Is input to the address of the first correction table memory 11. A second selector 15 selects the output of the second correction table memory i / f circuit 12 and the output of the A / D converter 1 and stores the selection result in the second correction table memory 13 at the address thereof. Enter as That is, when the second correction table memory 13 performs the write operation, the second correction table memory i
/ F circuit 12 is selected, and at the time of a read operation,
A digital video signal output from the A / D converter 1 is selected and input to an address of the second correction table memory 12. A third selector 16 selects an output signal from the first correction table memory 11 and an output signal from the second correction table memory 13. 17 is D /
The A converter converts the digital signal from the third selector 16 into an analog signal.

[0006] The operation of the gradation correction circuit configured as described above will be described below. First, an input luminance signal is input to the A / D converter 1, converted into a digital signal, and output as a converted input luminance signal. When there are a plurality of types of screens, for example, two screens, input luminance signals corresponding to different screens are converted and output as converted input luminance signals b1 and b2, respectively. The first histogram memory i / f circuit 72 and the second histogram memory i / f circuit 74 use the converted input luminance signals b1 and b2 as addresses of the first histogram memory 71 and the second histogram memory 73, respectively.
Each time it is accessed, the data at that address is added by "1" and returned to the respective histogram memories 71 and 73. Further, a restriction is made so that the frequencies of the first histogram memory 71 and the second histogram memory 73 do not exceed a certain level. By performing this operation for one vertical scanning period, a luminance histogram of the input luminance signal is detected. The first histogram memory 71 and the second histogram memory 71
The contents of the histogram memory 73 are as follows:
Alternatively, the data is cleared at intervals of an integral multiple thereof, and all data becomes “0”. When a plurality of types of images exist in one vertical scanning period, a first histogram memory 71 and a second histogram memory 73 are allocated to each image, and the first histogram memory i / f circuit 72 ON only when the luminance signal (b1) of the screen to which the histogram memory 71 is assigned, and the second histogram memory i / f circuit 74
O only when the luminance signal (b2) of the screen to which 3 is assigned
It becomes N. That is, ON / OFF of data addition of the histogram memory is performed at the time of switching between a plurality of types of images.

A first histogram memory 71 will now be described.
7 shows the processing contents of the calculation control unit and the correction table for the screen data b1 assigned to. The arithmetic control unit 4 reads the data of the first histogram memory 71,
The minimum luminance level (YMIN) of the luminance signal of the screen allocated to the first histogram memory 71 and the total frequency (TPX) written in the histogram are detected,
Calculate the variance (DST). Further, the average value (APL) of the luminance levels at all sample points is calculated.

Using the four control parameters (YMIN, TPX, DST, APL) thus obtained,
Base value (BSE = initial value of added value), cumulative start point (RST), cumulative end point (RED)
Are respectively calculated.

Next, again, the first histogram memory 7
The data is read out from the data No. 1 and calculations such as a limiter (see FIG. 20 (b)) and addition of a constant value (see FIG. 20 (c)) are performed based on the calculated control parameters, and the results are corrected. The histogram data is assumed to be c. Here, the larger the fixed value (base value) to be added, the closer the cumulatively added curve is to a straight line, and the smaller the value, the more the cumulatively added curve is flattened.

Then, the cumulative start point (RST)
And the cumulative end point (RED), the cumulative histogram data d of the corrected histogram data c is calculated within the range. This situation is shown in FIG. 20 (c) and FIG.
The curve L1 shown in FIG. Next, the arithmetic control unit 4 calculates a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum output luminance level h, and performs a normalization process on each data g of the cumulative histogram based on this coefficient. After performing, the result i is stored in the first correction table memory 11. At this time, by controlling the maximum output luminance level h, operations such as automatic contrast control (ACL) and automatic bright control (ABL) can be performed. This operation is shown in FIG.

A signal having a wide dynamic range has a cumulative histogram close to a straight line (see a straight line L2 in FIG. 21A). Therefore, the cumulative histogram of the input video luminance signal (see the curve L1 in FIG.
(See (a) line L2)) is performed by the correction table operation.

First correction table memory i / f circuit 10
Reads the data j by using the converted input luminance signal b1 on the screen assigned to the first histogram memory 71 as an address and obtains a first corrected output luminance signal k1.
FIG. 21C shows a histogram of the corrected luminance signal.

[0013] The above arithmetic control unit 4, and also to screen the data b2 assigned to the second histogram memory 73 is processed using the correction table, the second correction table memory 1 3, and a second done similarly using the correction table memory i / f circuit 1 2, the second corrected output signal k
Get 2

Next, the third selector 16 applies the first correction output signal k1 to the screen area allocated to the first histogram memory 71, and outputs the first corrected output signal k1 to the second histogram memory 7.
For the screen area assigned to No. 3, the second correction output signal k2 is switched to output the correction output signal k. Then, the D / A converter 17 converts the output signal k from the third selector 16 into an analog signal and outputs it.

The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above. In the gradation correction device configured as described above, when displaying a plurality of videos on the display screen,
An independent histogram of each screen can be obtained, and an accurate gradation correction table (lookup table) can be obtained.

In the following, another conventional gradation correction device of this type will be described. FIG. 22 is a block diagram showing a conventional tone correction device. In FIG. 22, FIG.
Reference numeral 75 denotes a first feature detection circuit for detecting, for example, a maximum value and a minimum value as features of the video signal output from the first histogram i / f circuit 72. is there. Similarly, reference numeral 76 denotes a second feature detection circuit that detects, for example, a maximum value and a minimum value as features of the video signal output from the second histogram i / f circuit 74.

The operation of another conventional gradation correction circuit configured as described above will be described below.
First, an input luminance signal is input to the A / D converter 1 and converted into a digital signal. The A / D converter 1 outputs this as a converted input luminance signal to the next circuit. Multiple screens,
For example, when there are two screens, the input luminance signals of different screens are converted.
b2. First histogram memory i / f circuit 72
Outputs an input luminance signal b1 to a first feature detection circuit 75. The feature detection circuit 75 detects, for example, a maximum value and a minimum value as characteristics of the input luminance signal b1, and outputs a first histogram memory i / f circuit. 72. Similarly, the second histogram memory i / f circuit 74 outputs the input luminance signal b2
Is output to the second feature detection circuit 76, and the feature detection circuit 76 outputs, as a feature of the input luminance signal b2, for example, a maximum value,
The minimum value is detected and output to the second histogram memory i / f circuit 74. These features are the first register RAM
6. The data is held in the second register RAM 7 and used in the next field.

First histogram memory i / f circuit 7
2, the second histogram memory i / f circuit 74 inputs the converted input luminance signal b1, b2 first histogram main <br/> mode Li 7 1 respectively, as the address of the second histogram memory 7 3, Each time the first histogram memory 71 and the second histogram memory 73 are accessed, the address data is added by "1" and returned to the histogram memory. In addition, a restriction is made so that the frequency of data in the first histogram memory 71 and the second histogram memory 73 does not exceed a certain level. First feature detection circuit 7
Histogram detection is performed using a small-capacity histogram memory by restricting the sample of the converted input luminance signal based on the maximum value and minimum value as the features of the screen one field before obtained by the fifth or second feature detection circuit 76. be able to. By performing this operation for one vertical scanning period, a luminance histogram of the input luminance signal a is detected.

The first histogram memory 71 and the second histogram memory 71
Is cleared, and all data is set to "0". Similarly, the maximum value and the minimum value as the features of the screen are replaced with the content newly detected, that is, the content detected in the current field, every one vertical scanning period or every integer multiple thereof. When a plurality of types of images exist in one vertical scanning period, the first histogram memory 71 and the first feature detection circuit 75, the second histogram memory 73, and the second feature detection circuit 7 for each image.
6 is assigned, and the first histogram memory i / f circuit 72 is a luminance signal (b1) of the screen to which the first histogram memory 71 and the first feature detection circuit 75 are assigned.
ON only when the second histogram memory i / f
The circuit 74 includes a screen luminance signal (b2) to which the second histogram memory 73 and the second feature detection circuit 76 are assigned.
ON only in the case of). That is, data addition of the histogram memory and ON / OFF of the feature detection are performed when a plurality of types of images are switched. Hereafter, the processing contents of the arithmetic control unit 4 and the correction table for the screen data b1 assigned to the first histogram memory 71 will be described.

The data in the first histogram memory 71 is read out by the arithmetic and control unit 4, and the data is stored in the first histogram memory 7
The minimum luminance level (YMIN) of the luminance signal of the screen assigned to 1 and the total frequency (TPX) written in the histogram are detected, and the variance (DST) is calculated. Furthermore, the average value of the luminance levels (AP
L) is calculated. These four control parameters (YMIN,
Using TPX, DST, APL), the base value (BS
E = initial value of added value), cumulative start point (R
ST), and calculate three control parameters of a cumulative end point (RED).

Next, data is read out again from the first histogram memory 71, and a limiter (see FIG. 20 (b)) and addition of a constant value (base value) (FIG. c)), and the result is used as corrected histogram data c. Here, the larger the fixed value (base value) to be added, the closer the cumulatively added curve is to a straight line, and the smaller the value, the more the cumulatively added curve is flattened.

Then, the cumulative start point (RST)
And the cumulative end point (RED), the cumulative histogram data d of the corrected histogram data c is calculated within the range. This situation is shown in FIG. 20 (c) and FIG.
This is shown in curve L1) of 1 (a).

Next, the arithmetic and control unit 4 calculates a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum output luminance level h, and normalizes each data g of the cumulative histogram based on this coefficient. After performing the conversion process, the result i is stored in the first correction table memory 11. At this time, by controlling the maximum output luminance level h, operations such as automatic contrast control (ACL) and automatic brightness control (ABL) can be realized. This operation is shown in FIG. 21 (b).

For a signal having a wide dynamic range, the cumulative histogram is close to a straight line (straight line L2 in FIG. 21A). Therefore, a correction table operation is performed to correct the cumulative histogram (curve L1 in FIG. 21 (a)) of the input video luminance signal close to a straight line (straight line L2 in FIG. 21 (a)).

First correction table memory i / f circuit 10
Reads the data j using the converted input luminance signal b1 on the screen assigned to the first histogram memory 71 as an address to obtain a first corrected output luminance signal k1. FIG. 21C shows a histogram of the corrected luminance signal.

The above-described operation control unit 4 and correction table operation are performed on the second correction table memory 1 for the screen data b2 assigned to the second histogram memory 73.
Third, the same operation is performed using the second correction table memory i / f circuit 12, whereby the second correction output signal k2 is obtained.
Get.

Next, the third selector 16 applies the first correction output signal k 1 to the screen area allocated to the first histogram memory 71 and the second histogram memory 7.
The second correction output signal k2 is switched for the screen area assigned to No. 3 and output as the correction output signal k. Then, the D / A converter 17 converts the output signal k from the third selector 16 into an analog signal 1 and outputs it. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

In another conventional gradation correcting apparatus configured as described above, when displaying a plurality of images on a display screen, an independent histogram of each screen can be obtained. A histogram can be obtained with a small memory capacity utilizing characteristics, and an accurate gradation correction table (look-up table) can be obtained.

[0029]

The conventional gradation correcting apparatus is configured as described above. In order to accurately correct a plurality of images on a display screen, a circuit corresponding to the number of images is required. There is a problem that an amount and a memory amount are required. In addition, there is a problem that a histogram extraction method for a plurality of images on a display screen is determined to be one, and similar gradation correction is performed on screens having different characteristics.

Furthermore, the frequency distribution of the amplitude level that can accumulate only a predetermined frequency (the number of bits of one address) for one luminance level and can accumulate whatever the level is taken However, there is a problem that the maximum frequency is limited.

The present invention has been made in order to solve the above-described problems. A plurality of images on a display screen can be displayed without increasing the amount of use of a histogram memory and the amount of a histogram memory i / f circuit. It is an object of the present invention to obtain a gradation correction device capable of performing gradation correction. It is another object of the present invention to obtain a gradation correction device capable of performing a histogram accumulation process and a gradation correction process according to each screen by switching a histogram accumulation method for each screen.

It is another object of the present invention to provide a tone correction device capable of changing the maximum frequency of a frequency distribution of amplitude levels that can be accumulated in one range for a plurality of types of frequency distribution extraction methods. Further, in the above-described other conventional configuration, in order to accurately correct a plurality of images on the display screen and to accurately detect the characteristics of each screen, a circuit corresponding to the number of images is required. There is a problem that an amount and a memory amount are required.

The present invention has been made in order to solve the above-mentioned problems of the conventional device, and has two points on the display screen.
Even when displaying a plurality of images larger than the screen, the amount of use of the histogram memory is not increased, and the feature detection for controlling the data accumulation is supported by a single feature detection circuit without increasing the circuit amount. In addition to realizing the gradation correction process described above, the sample area set in each field only needs to be set to the same sample area as the data extraction area and the feature detection area. It is an object of the present invention to obtain a gradation correction device that can increase the degree of freedom of a sample area, for example, can sample both screens even when the image is displayed.

Also, when a plurality of images are displayed on the display screen, the amount of histogram memory used is not increased, and the feature detection for controlling the data accumulation is increased by using only one feature detection circuit. Tone correction processing corresponding to a plurality of screens can be realized without increasing the number of circuits of the histogram memory i / f circuit, and the accuracy of control can be increased because of the control. The aim is to obtain a device.

[0035]

According to a first aspect of the present invention, there is provided a gradation correcting apparatus for correcting a gradation of each screen when a plurality of screens are simultaneously displayed on one screen. There is provided a histogram memory for storing the frequency distribution of the amplitude levels of the video signals of the respective screens by switching the video signals of the respective input screens at a specific cycle, A histogram interface circuit for writing and reading frequency distribution data to and from the histogram memory so as to store the frequency distribution of the amplitude level of the video signal of each screen by switching the signal at a specific cycle; When the cumulative luminance distribution is calculated by taking out the data of the luminance frequency distribution through the histogram interface circuit for In addition, control parameters are set so that the obtained cumulative luminance distribution has a desired shape, the luminance frequency distribution is corrected using the control parameters, and the level of the input luminance signal is corrected using the corrected luminance frequency distribution. And a plurality of look-up table memories for holding a correction table for the video signals of the plurality of screens created by the arithmetic control unit for at least the specific period, and an image of each screen. type a luminance signal each time the signal is input by switching the plurality of look-up table memory, and an image switching selector for outputting a corrected luminance signal for each image using the correction table above SL look-up table memory It is like that.

According to a second aspect of the present invention, in the tone correcting apparatus according to the first aspect of the present invention, the histogram memory interface circuit includes a plurality of image signals for a plurality of screens. As the specific period, the luminance signal is fetched by sequentially switching at a period of each field of the video signal or a period of a multiple thereof, and the luminance frequency distribution of one video signal is selected from a plurality of video signals displayed on the same screen. Is extracted so as to be given to the histogram memory.

According to a third aspect of the present invention, in the tone correcting apparatus of the first aspect, the histogram interface circuit includes a plurality of types of frequency distribution extraction units, Is used by switching the frequency distribution extraction unit for each extraction region.

According to a fourth aspect of the present invention, in the tone correcting apparatus according to the third aspect, the histogram interface circuit includes a plurality of types of frequency distribution extracting sections for the extraction area. The switching is performed in synchronization with the switching.

Further, according to a fifth aspect of the present invention, there is provided a gradation correcting apparatus for storing a frequency distribution of amplitude levels of an input video signal, extracting the frequency distribution, and storing the histogram distribution in the histogram memory. Histogram memory interface circuit for writing and reading, and arithmetic control for creating a correction formula or a correction table for correcting the level of an input luminance signal using data of the luminance frequency distribution extracted from the histogram memory interface circuit And a correction table for holding a correction table or a correction table for a screen created by the arithmetic and control unit, wherein the histogram memory interface circuit includes a first address of the first address of the histogram memory. Data storage signal output when memory is full Receiving, the reset unit a first reset signal for resetting the memory address transmitted to the histogram memory, the data storage signal second
And a data storage signal transmission unit for transmitting the data to the memory at the address of (i).

According to a sixth aspect of the present invention, in the tone correcting apparatus of the fifth aspect, the histogram memory interface circuit includes a plurality of types of frequency distribution extracting units, and The operation of the unit and the data storage signal transmission unit is controlled by the operation status of the plurality of types of frequency distribution extraction units.

Further, according to the gradation correcting apparatus of the present invention, when displaying a plurality of screens simultaneously on one screen,
A gradation correction device for correcting gradations of respective screens, wherein a histogram memory stores a frequency distribution of amplitude levels of the video signals of the respective screens by switching input video signals of the respective screens at a specific cycle. A feature detection circuit that detects a feature of an amplitude level of an input video signal; a histogram interface circuit that controls writing and reading to and from the histogram memory and controls input and output of a video signal to and from the feature detection circuit. An arithmetic control unit that creates a correction formula or a correction table for correcting the level of the input video signal using data of the frequency distribution of the video signal extracted from the histogram interface circuit; and A plurality of correction table memories for holding correction formulas or correction tables for video signals of a plurality of screens, and each screen A screen switching selector that switches the plurality of correction table memories each time a video signal is input, inputs a video signal, and outputs a corrected video signal of each screen using the correction formula or the correction table of the correction table memory. The histogram interface circuit controls an area corresponding to a video signal of one screen from among the plurality of screens displayed on the same screen as a frequency distribution extraction area, and the histogram interface circuit includes: Controlling the area corresponding to the video signal of one screen from among the plurality of screens displayed on the same screen to be a feature detection area, the histogram interface circuit including a plurality of registers, The feature data detected by the feature detection circuit can be retained for a certain period of time A.

In the tone correcting apparatus according to an eighth aspect of the present invention, in the tone correcting apparatus according to the seventh aspect, the histogram interface circuit is configured to set the frequency distribution extraction area for each field or a multiple of the field. Switching is performed at intervals, and the feature detection area is switched at intervals of each field or a multiple of the field.

Further, according to the gradation correcting apparatus of the ninth aspect of the present invention, when displaying a plurality of screens simultaneously on one screen,
A gradation correction device for correcting gradations of respective screens, wherein a histogram signal is stored by switching a video signal of each input screen at a specific cycle and storing a frequency distribution of amplitude levels of the video signals of the respective screens. And a feature detection circuit for switching the input video signal of each screen at a specific cycle to detect a feature of an amplitude level of the video signal of each screen, control of writing and reading to and from the histogram memory, and A histogram interface circuit for controlling input / output of a video signal to a detection circuit, and a correction formula or correction for correcting a level of the input video signal using data of a frequency distribution of the video signal extracted from the histogram interface circuit An arithmetic control unit for creating a table, and a correction formula or a correction equation for video signals of a plurality of screens created by the arithmetic control unit A plurality of correction table memories that hold a correct table, and each time a video signal of each screen is input, the plurality of correction table memories are switched to input a video signal, and a correction formula or a correction table of the correction table memory is used. A screen switching selector for outputting a corrected video signal of each screen, wherein the histogram interface circuit extracts a frequency distribution area corresponding to the video signal of one screen from the plurality of screens displayed on the same screen. The histogram interface circuit controls the area corresponding to the video signal of one screen from among the plurality of screens displayed on the same screen as the feature detection area. The histogram interface circuit determines that the screen of the feature detection area will be the frequency distribution extraction area next. It is those that were to switch to.

According to a tenth aspect of the present invention, in the tone correcting apparatus of the ninth aspect, the histogram interface circuit includes a step of setting the frequency distribution extraction area for each field or a multiple of the field. Switching is performed at intervals, and the feature detection area is switched at intervals of each field or a multiple of the field.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram of a gradation correction apparatus according to a first embodiment of the present invention, and corresponds to the first and second aspects of the present invention. In the first embodiment, gradation correction for video signals of a plurality of screens is performed using one histogram memory and one histogram memory i.
/ F circuit. FIG.
, 1 is A for A / D converting the input video signal
/ D converter. Reference numeral 2 denotes a histogram memory for storing a histogram of the luminance level of the A / D converted input video signal. Generally, an address input of the memory is regarded as a luminance level of the input signal, and the contents of the address represent the frequency. Become. Reference numeral 3 denotes a histogram memory i / f circuit, which controls writing and reading of the histogram memory 2.

When data is written to the histogram memory 2 by the histogram memory i / f circuit 3, A / A
The output image of the D converter 1 is input to an address, and the distribution frequency is added as data according to the luminance level.
Also, the process of reading out the extracted histogram distribution is as follows:
This is performed via a bus selector 25 constituting a histogram memory i / f circuit 3 described later.

Reference numeral 4 denotes an arithmetic control unit, which performs calculations for calculating a cumulative histogram from the data in the histogram memory 2 and further calculating a correction table. Reference numeral 5 denotes a program ROM for storing a calculation program of the calculation control unit 4. 6 is a first register RAM, a first screen,
For example, parameters used to calculate data stored in the correction table memory of the sampling window D1 in FIG. 3B are stored. Reference numeral 7 denotes a second register RAM which stores parameters used for calculating data to be stored in the second table, for example, the correction table memory of the sampling window D2 in FIG. 3B.

Reference numeral 11 denotes a first correction table memory.
The correction data of the first screen calculated by the arithmetic and control unit 4 is stored. Similarly, reference numeral 12 denotes a second correction table memory, which stores the correction data of the second screen calculated by the arithmetic and control unit 4. Generally, an address input to the memory is regarded as a luminance level, and the contents of the address represent correction data.

Reference numeral 10 denotes a first correction table memory i / f circuit, which controls writing and reading of the first correction table memory 11. Similarly, reference numeral 12 denotes a second correction table memory i / f circuit, which controls writing and reading of the second correction table memory 13. 14 is the first
Selector selects the output of the first correction table memory i / f circuit 10 and the output of the A / D converter 1 and inputs the selection result as an address of the first correction table memory 11. That is, the first correction table memory 1
When 1 is a write operation, the first correction table memory i /
The output of the f-circuit 10 is selected.
A digital video signal output from the A / D converter 1 is selected and input to an address of the first correction table memory 11.

Reference numeral 15 denotes a second selector, which outputs the output of the second correction table memory i / f circuit 12 and the A / D converter 1
And outputs the selection result as an address of the second correction table memory 13. That is, the second
When the correction table memory 13 performs the write operation, the output of the second correction table memory i / f circuit 12 is selected. On the other hand, during the read operation, the digital video signal output from the A / D converter 1 is selected. Select and input to the address of the second correction table memory 13.

Reference numeral 16 denotes a third selector, which selects an output signal from the first correction table memory 11 and an output signal from the second correction table memory 12. 17 is D /
The A converter converts the digital signal from the third selector 16 into an analog signal. A field counter 19 generates a field identification signal. The field identification signal is, for example, a signal that is repeatedly turned on / off for each field in the case of two screens. Reference numeral 18 denotes a synchronization processing circuit for recognizing and grasping phase information such as the vertical and horizontal display start points of the video luminance signal and controlling the timing of each memory and circuit.

FIG. 2 is a block diagram describing the histogram memory i / f circuit 3 in detail. An adder 21 adds "1" to the data output from the histogram memory 2. Reference numeral 22 denotes a limiter circuit for preventing overflow when "1" is added to the data output from the histogram memory 2. Reference numeral 23 denotes a first sample window register which stores the position information of the first screen, for example, the sampling window D1 in FIG. 24 is a second screen,
For example, it is a second sample window register that stores the position information of the sampling window D2 in FIG. Here, the position information is, for example, information that the first screen starts at what line in the vertical direction and ends at what line, or information that starts from what pixel in the horizontal direction and ends at what pixel. Reference numeral 25 denotes a first sample window register 23 and a second
Is a selector for switching and selecting the sample window register 24 for output. Reference numeral 26 denotes a pixel counter, which counts the position on the screen of a currently processed pixel (signal input from the A / D converter 1) based on information from the synchronization processing circuit 18. It is a counter. 2
A first comparison unit 7 compares the position information of the current pixel by the pixel counter 26 with the position information of the sampling window output from the selector 25, and generates an enable signal when the current pixel exists inside the sampling window. It is a vessel.
Reference numeral 28 denotes a selector for selecting whether to add "1" to the data output based on the enable signal output from the first comparator 27. Reference numeral 29 denotes an output position register for storing information on when to output data output from the histogram memory 2 to the arithmetic control unit 4. Reference numeral 30 denotes a second comparator which compares the output of the pixel counter 26 with the output of the output position register 29, and outputs an enable signal when they match. Reference numeral 31 denotes a selector for selecting whether or not to output the contents of the histogram memory 2 to the arithmetic and control unit 4 according to the enable signal from the second comparator 30.

The operation of the gradation correction circuit configured as described above will be described below. First, an input luminance signal is input to the A / D converter 1, converted into a digital signal, and output as a converted input luminance signal. When there are a plurality of types of screens, for example, two screens, input luminance signals of different screens are converted to b1 and b2, respectively. The luminance signals b1 and b2 are input to the histogram memory 2 as addresses, and data at the addresses are input to the histogram memory i / f circuit 3.
The histogram memory i / f circuit 3 selects which screen of the two screens to store the luminance histogram in the histogram memory 2 based on the field identification signal output from the field counter 19. Since an enable signal is generated from the first comparator 27 only at the time of the selected screen, only when an input signal of the selected screen, for example, b1, comes, the data of the address is added by "1" and the histogram memory 2 is added. Return to Further, a restriction is made so that the frequency of the histogram memory 2 does not exceed a certain level. Generally, during a period during which a luminance histogram is being extracted (a period during which sampling is being performed), data processing is completed while an address is accessed once. By performing this operation for one vertical scanning period, a luminance histogram of the selected luminance signal b1 is detected. The contents of the histogram memory 2 are cleared every vertical scanning period or a period of an integral multiple thereof, and all data becomes "0". When the contents of the histogram memory 2 reach the position written in the output position register 29, the contents are output to the arithmetic control unit 4.

Next, the data in the histogram memory 2 is read out by the arithmetic and control unit 4, and the minimum luminance level (YMI) of the screen luminance signal assigned to the histogram memory 2 respectively.
N), detect the total frequency (TPX) written in the histogram and calculate the variance (DST). Further, the average value (APL) of the luminance levels at all sample points is calculated. These four control parameters (YMIN, TPX, D
Using ST, APL), three control parameters of a base value (BSE = initial value of the added value), an accumulated start point (RST), and an accumulated end point (RED) are calculated.

Next, data is read from the histogram memory 2 again, and a limiter (see FIG. 20 (b)) or addition of a constant value (see FIG.
(see (c)), and the result is used as corrected histogram data c. Here, the larger the constant value (base value) to be added, the closer the cumulatively added curve is to a straight line, and the smaller the value, the flattened the cumulatively added curve.

Then, the cumulative start point (RST)
And the cumulative end point (RED), the cumulative histogram data d of the corrected histogram data c is calculated within the range. This situation is shown by a curve L1 in FIGS. 20 (c) and 21 (a).

Next, the arithmetic control unit 4 obtains a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum output luminance level h, and normalizes each data g of the cumulative histogram based on this coefficient. Perform processing. The arithmetic control unit 4 determines that the luminance data stored in the histogram memory 2 is
The correction table memories 11 and 13 and the correction table memory i / f circuit 1 depend on which of the second screen data is used.
0 and 12 are selected and the result i of the normalization processing is stored in the selected correction table memory 10 (in the case of the first embodiment, the correction table memory 11, the correction table memory i /
f circuit 10 is selected). At this time, by controlling the maximum output luminance level h, operations such as automatic contrast control (ACL) and automatic bright control (ABL) can be performed. This operation is shown in FIG.
This is shown in (b). For a signal with a wide dynamic range, the cumulative histogram is close to a straight line (straight line L2 in FIG. 21A). Therefore, the cumulative histogram of the input image luminance signal (curve L1 in FIG. 21A) is converted to a straight line (straight line L in FIG. 21A).
Correction work for approaching 2) is performed by a correction table operation.

That is, the first correction table memory 11
Reads the data j using the converted input luminance signal b1 on the screen assigned to the histogram memory 2 as an address to obtain a corrected output luminance signal k1. FIG. 21C shows a histogram of the corrected luminance signal.

Next, the third selector 16 switches the first correction output signal k1 for the first screen area and the second correction output signal k2 for the second screen area in accordance with the screen area, respectively. Output k. And D /
The A converter 17 converts the output signal k from the third selector 16 into an analog signal and outputs it. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

As described above, according to the first embodiment, a histogram is obtained for each field, a screen for setting a correction table is switched, and gradation correction of each screen is performed independently. As described above, the amount of memory of the histogram memory is not required for the number of screens, and the optimum gradation correction of a plurality of screens can be realized only by the histogram memory for one screen.

In the above description, when the histogram memory i / f circuit 3 extracts the frequency distribution of the amplitude level of the video signal, the case where the target video extraction area is switched for each field has been described. However, the video signal to be extracted may be switched at a cycle of a multiple of the field.

Embodiment 2 FIG. 4 is a block diagram of a tone correction device according to a second embodiment of the present invention.
This corresponds to claims 3 and 4 of the present application. In the second embodiment, the circuit can be simplified as compared with the first embodiment. 4, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and the main points different from FIG.
There is no field counter. Reference numeral 41 denotes a histogram memory i / f circuit, which controls writing and reading of the histogram memory 2. FIG. 5 is a block diagram describing the histogram memory i / f circuit 41 in detail. The same parts as those of the gradation correction apparatus shown in FIG.
The / f41 circuit is an i / f circuit for extracting histograms of two modes as shown in FIGS. 6 (a) and 6 (b). That is, in mode 1, an effective histogram extraction process is performed on a screen in which the gradation of the image signal exists only at the intermediate level, and in mode 2, a screen in which the gradation of the image signal exists throughout the signal level Perform effective histogram extraction processing. In FIG. 5, reference numeral 51 denotes A / D
This is a 5-bit shifter that shifts the image signal (8 bits) input from the converter 1 by 5 bits to 3 bits. 52
Is an image signal (8 bits) input from the A / D converter 1
Is a 4-bit shifter that shifts 4 bits to 4 bits. A register 53 stores the MIN value of the histogram extraction processing. Numeral 54 denotes a 4-bit signal output from the 4-bit shifter 52 and the MI held in the register 53.
The third comparator outputs a 4-bit signal when the MIN value is smaller than the N value, and outputs "0" otherwise. Reference numeral 55 denotes a register that stores the MAX value of the histogram extraction processing. The reference numeral 56 compares the 4-bit signal output from the third comparator 54 with the MAX value held in the register 55, and when the MAX value is larger,
The fourth comparator outputs a bit signal, and outputs "0" otherwise. Reference numeral 57 denotes a 5-bit screen switching signal output from the synchronization processing unit 18 at a certain timing.
A selector that selects either the shifter 51 or the fourth comparator 56 and outputs the selected address to the histogram memory.

The operation of the gradation correction circuit having the above configuration will be described below. Reference numeral 23 denotes a first sample window register, which is a first screen, for example, FIG.
It is assumed that the position information of the sampling window A of FIG. 3B is stored. Reference numeral 24 denotes a second sample window register which stores the position information of the second screen, for example, the sampling window B of FIG. 3B. It is assumed that Also, assume that the first screen is subjected to the mode 1 histogram extraction processing in FIG. 6 and the second screen is subjected to the mode 2 histogram extraction processing in FIG.

When the first screen is selected by the screen switching signal, the addition enable signal from the first comparator 27 is such that the image signal input from the A / D converter 1 is the first enable signal.
And the cumulative addition is performed in the histogram memory 2. In synchronization with this, the selector 57 selects the 4-bit signal output from the 4-bit shifter 52 and compared with the MIN value and the MAX value by the comparators 54 and 56, and outputs it to the histogram memory 2 as an address. Similarly, when the second screen is selected by the screen switching signal, the addition enable signal from the first comparator 27 corresponds to the image signal input from the A / D converter 1 as the second screen. This occurs at times and the cumulative addition is performed in the histogram memory 2. In synchronization with this, the selector 57 selects the 3-bit signal output from the 5-bit shifter 51 and outputs it to the histogram memory 2 as an address. In this way, a histogram like the mode 1 shown in FIG. 6A is extracted for the first screen, and a mode 2 shown in FIG. 6B is extracted for the second screen.
Can be extracted.

As described above, according to the second embodiment, when a plurality of images are displayed on the display screen, the histogram accumulation processing is switched for each screen by the screen switching signal. The combined histogram accumulation and gradation correction processing can be realized,
The circuit can be more simplified than in the first embodiment.

Embodiment 3 Next, Embodiment 3 of the present invention
Will be described. FIG. 7 is a block diagram showing a gradation correcting apparatus according to a third embodiment of the present invention, and corresponds to the fifth and sixth aspects of the present invention. In the third embodiment, one correction table memory and one correction table memory i / f circuit can be provided. In FIG. 7, reference numeral 100 denotes a histogram memory i / f circuit, which controls writing and reading of the histogram memory 2. FIG. 8 is a block diagram describing the configuration of the histogram memory i / f circuit 100 in detail. 8, the same components as those of the tone correction device shown in FIG. 5 are denoted by the same reference numerals, and the description of the operation is omitted here. The histogram memory i / f circuit 100 in FIG. 8 selects one of the two mode histograms as shown in FIG. 6 and performs histogram extraction. In FIG. 8, reference numeral 81 denotes whether to reset the histogram memory 2 by a mode signal sent from the program ROM 5,
A selector for selecting whether to perform a limiter. Reference numeral 82 denotes a selector which outputs a signal indicating whether or not to change the address of the histogram memory to be accessed, based on the mode signal sent from the program ROM 5 and the output signal from the selector 28. An adder 83 adds 8 to the signal output from the selector 57. Numeral 84 denotes a signal output from the selector 57 and "8" output from the adder 83.
Is selected according to the output result of the selector 82, and is output to the histogram memory 2 as an address. Reference numeral 85 denotes a third sample window register holding the position information of a sample window for which a histogram sample is to be performed.

The operation of the gradation correction circuit configured as described above will be described below. Now, it is assumed that the histogram has 16 addresses. Here, the selector 57 and the selector 84 are defined to select the upper stage when the control signal is "0" and the lower stage when the control signal is "1". When the mode signal is "0", the selector 57
Selects the output signal of the 5-bit shifter 51 and extracts a histogram as in mode 2 shown in FIG. 9B. At this time, the selector 82 receives the limiter signal output by the limiter 22 when the data at the address N of the histogram memory becomes full, and outputs "1" only at that time.
After that, "0" is always output. The selector 84 is the selector 8
Only when "1" is output from 2, the output of the adder 83 is selected and (N + 8) is output as an address to the histogram memory. In the selector 81, the histogram memory 2
When the limiter becomes full, a limiter signal is output by the limiter 22. Regardless of the value of the limiter signal, "1" is always output to the adder, and "1" is always added to the data in the histogram memory 2. You. In this way, when the mode signal is "0", the memory of the address N and the memory of the address (N + 8) can be used for one level.

On the other hand, when the mode signal is “1”, the selector 57 outputs the signal from the 4-bit shifter 52 to the comparator 5.
At steps 4 and 56, the 4-bit signal compared with the MIN value and the MAX value is selected, and a histogram as in mode 1 shown in FIG. 9A is extracted. At this time, the selector 82 always outputs "
0 ", the selector 84 outputs the output of the selector 57 as it is to the histogram memory as an address. The selector 81 directly selects the limiter signal output by the limiter 22 when the histogram memory is full, No further addition is made to the histogram data.

FIG. 10 shows the counting operation when the mode signal is "1" and when the mode signal is "0". As described above, according to the third embodiment, the mode is switched by the mode signal, and one of the two mode histograms is selected to extract the histogram.
When a plurality of types of frequency distributions are extracted, the maximum frequency of the frequency distribution of the amplitude level that can be accumulated in one level can be changed, and the gradation correction process that effectively uses the histogram memory can be realized.

Embodiment 4 FIG. 11 is a block diagram showing a configuration of a tone correction apparatus according to a fourth embodiment of the present invention, and corresponds to the seventh and eighth aspects of the present invention. In the fourth embodiment, a single feature detection circuit can be provided together with the histogram memory and the histogram memory i / f circuit. 11, the same reference numerals as those in FIG. 1 denote the same or corresponding components. Reference numeral 20 denotes a feature detection unit that detects, for example, a maximum value and a minimum value as features of the video signal output from the histogram i / f circuit 3. The feature detection circuit 20, the histogram memory 2, and the histogram memory i / f circuit 3 are provided one each, although there are two video signals to be subjected to gradation correction.

FIG. 12 shows a histogram memory i / f circuit 3.
FIG. 3 is a block diagram describing the configuration of the configuration in detail. In the figure, reference numeral 201 denotes an adder for adding “1” to the data output from the histogram memory 2. Reference numeral 202 denotes a limiter circuit for preventing overflow when "1" is added to the data output from the histogram memory 2. 203
Is a first sample window register that stores position information of the first screen, such as the sampling window D1 in FIG. Reference numeral 204 denotes a second sample window register which stores position information of the second screen such as the sampling window D2 in FIG. Here, the position information is, for example, information such that the first screen starts from what line in the vertical direction and ends on what line, and starts from what pixel in the horizontal direction and ends on what pixel. Reference numeral 205 denotes a selector for switching between the first sample window register 203 and the second sample window register 204 according to a field identification signal sent from the field counter 19. Reference numeral 206 denotes a pixel counter which counts the position of a pixel currently being processed, that is, a signal input from the A / D converter 1 on the screen based on information from the synchronization processing circuit 18. This is a pixel counter. 207 first for generating an enable signal when comparing the position information of the sampling window output from the position information and the selector 205 of the current pixel by pixel counter 206, the current pixel is present in the interior of the sampling window < br /> is a comparator. Reference numeral 208 denotes a selector for selecting whether to add "1" to the data output according to the enable signal output from the first comparator 207. An output position register 209 stores information on when to output data output from the histogram memory 2 to the arithmetic control unit 4. 210 compares the output of the pixel counter 206 with the output of the output position register 209,
This is the second comparator that outputs an enable signal when these match. Reference numeral 211 denotes a selector for selecting whether or not to output the contents of the histogram memory 2 to the arithmetic control unit 4 according to an enable signal from the second comparator 210.
Numerals 212, 214, and 216 hold three threshold values (these correspond to L1, L2, and L3 in the histogram diagram of FIG. 5) of the level of the histogram of the first screen obtained by the feature detection circuit 20. 1 register. Similarly,
Reference numerals 213, 215, and 217 denote second registers that hold three threshold values of the level of the histogram of the second screen obtained by the feature detection circuit 20. 218, 219, 2
Reference numeral 20 denotes a selector which switches to either the threshold value of the first screen or the threshold value of the second screen according to the field identification signal sent from the field counter 19 and outputs it to the register group. It is synchronized with the switching operation of the selector 205. 221, 222, 223
Is the first output of each of the register groups 212 to 217 for each threshold value.
Is a selector for switching to either the threshold value of the second screen or the threshold value of the second screen. 224 is the selector 22
A fourth comparator that compares the threshold value output from the first, second, and 223 with the level of the video signal and outputs the corresponding address value to the histogram memory; 225 is the first
Is a selector for selecting whether or not to output a video signal to the feature detection circuit 20 according to the enable signal output from the comparator 207.

The histogram memory i / f circuit 3 of FIG.
When writing data to the A / D converter 1, the output image of the A / D converter 1 is compared with the threshold value, and the distribution frequency is determined according to the address (address corresponding to the threshold value) corresponding to the comparator that has output the enable signal. Is added as data. Further, the process of reading the extracted histogram distribution is performed via the bus selector 211. Returning to FIG. 11, reference numeral 20 denotes a feature detection circuit for detecting a feature of the input video signal. FIG. 13 is a diagram showing the feature detection circuit 20 in detail.

In the fourth embodiment, the feature detection means detecting the maximum value and the minimum value in one field of the input signal. In FIG. 13, reference numeral 301 includes a register and a comparator inside, and detects the maximum value by comparing the level value of the input signal with the held level value and holding the larger one in the register. Is a maximum value detection circuit. Similarly, reference numeral 302 internally includes a register and a comparator, compares the level value of the input signal with the held level value, and holds the smaller one in the register to detect the minimum value. This is a minimum value detection circuit. Reference numeral 303 denotes a threshold value calculation circuit, which is held once per field by a signal from the synchronization processing circuit and held by the maximum and minimum value detection circuit 302 of the video signal level in the field held by the maximum value detection circuit 301. The three threshold values (L1, L2, L3) in FIG. 15 are calculated using the minimum value of the video signal level in the field thus output, and output to the histogram i / f circuit 3.

Referring back to FIG. 11, reference numeral 4 denotes an arithmetic control unit, which performs calculations for calculating a cumulative histogram from data in the histogram memory 2 and further calculating a correction table. Reference numeral 5 denotes a program ROM for storing an arithmetic program of the arithmetic control unit 4. 6 is the first register RA
M, for example, a first window such as the sampling window D1 in FIG.
The parameter used to calculate the data stored in the correction table memory of the screen is stored. Reference numeral 7 denotes a second register RAM which stores parameters used for calculating data to be stored in the correction table memory of the second screen, such as the sampling window D2 in FIG. Reference numeral 11 denotes a first correction table memory which stores the correction data of the first screen calculated by the arithmetic and control unit 4. Similarly, 13 is the second
And stores the correction data of the second screen calculated by the arithmetic and control unit 4. In general, a luminance level is input to an address input of a memory, and correction data is input to a data input thereof, and these are stored.
Reference numeral 10 denotes a first correction table memory i / f circuit, which controls writing and reading of the first correction table memory 11. Similarly, reference numeral 12 denotes a second correction table memory i.
/ F circuit, which controls writing and reading of the second correction table memory 13. 14 is a first selector, the first correction table memory i / f to select the output of the circuit 1 0 output and the A / D converter 1, the first selection results
Is input to the correction table memory 1 1 as its address. When the first correction table memory 11 performs a write operation, the output of the first correction table memory i / f circuit 10 is selected. When the first correction table memory 11 performs a read operation, a digital video signal output from the A / D converter 1 is selected. First correction table memory 11
Enter the address. 15 is a second selector,
The output of the second correction table memory i / f circuit 12 and A /
The output of the D converter 1 is selected, and the selection result is input to the first correction table memory 13 as its address. Second
Of the second correction table memory (LUT: Look Up Table) memory i /
The output of the f-circuit 12 is selected, and the digital video signal which is the output of the A / D converter 1 at the time of the read operation is selected and input to the address of the second correction table memory 13. Reference numeral 16 denotes a third selector, which stores the first correction table memory 11
And the output signal from the second correction table memory 13 are selected. Reference numeral 17 denotes a D / A converter, which converts a digital signal from the third selector 16 into an analog signal. A field counter 19 generates a field identification signal. The field identification signal is, for example, a signal that is repeatedly turned on / off for each field in the case of two screens. Reference numeral 18 denotes a synchronization processing circuit which recognizes and grasps phase information such as a vertical and horizontal display start point of a video luminance signal, and performs timing control of each memory and circuit.

Embodiment 4 configured as described above
The operation of the gray scale correction circuit according to the first embodiment will be described below. First, the input luminance signal a is input to the A / D converter 1 and converted into a digital signal. The A / D converter 1 outputs this to the next-stage circuit as a converted input luminance signal b. When there are a plurality of types of screens (for example, two screens), input luminance signals of different screens are respectively converted. These are respectively referred to as b1 and b2 (for example, in the case of two screens,
The signal of the sampling window D1 in FIG. 14 is denoted by b1, and the signal of the sampling window D2 is denoted by b2. ). The histogram memory i / f circuit 3 selects which of the two screens the luminance histogram is to be stored in the histogram memory based on the field identification signal output from the field counter 19. The enable signal is generated from the comparator 207 only when the screen is selected by the selector 205 and the comparator 207. For example, assume that the sampling window D1 in FIG. 14 is selected in the current field. At that time, the selectors 221, 222, and 223 are connected to the sampling window D1.
Side, that is, the registers 212, 214, and 216 are selected, and the value is input to the comparator 224 and compared with the input video signal b1. As a result of the comparison, the comparator 224 determines an address according to which level of the levels A1 to A4 of the histogram in FIG. Only when an enable signal arrives from the comparator 207, the adder 201 adds the data of the address by "1" and returns the data to the histogram memory. Further, a restriction is made so that the frequency of the histogram memory 2 does not exceed a certain level. Generally, data processing is completed while an address is accessed once during a period during which a luminance histogram is being extracted (a period during which sampling is being performed). By performing this operation for one vertical scanning period, a luminance histogram of the selected luminance signal b1 is detected. The contents of the histogram memory 2 are cleared every one vertical scanning period or a period of an integral multiple thereof, and all data is set to "0". The contents of the histogram memory 2 are output to the arithmetic control unit 4 when the contents correspond to the position written in the output position register 29.

Now, within the same field, only the enable signal output from the first comparator 207 of the histogram i / f circuit 3 in FIG. 12 and the video signal corresponding to the sampling window D1 of the input signal by the selector 225 Output to the feature detection circuit 20. The feature detection circuit 20 detects the maximum value and the minimum value of the video signal level in the sampling window D1, and calculates three threshold values accordingly. This is performed once per field at a timing other than the sampling window. The calculated three thresholds are input to the threshold registers 212, 214, and 216 of the sampling window D1 by the selectors 218, 219, and 220 of the histogram i / f circuit 3 in FIG. (The two fields in this embodiment). That is, in this embodiment, the histogram extraction control is always performed by the feature of the same screen two fields before. The same operation as that of D1 is performed for the sampling window D2.
And D2 are alternately performed for each field.

Next, the arithmetic and control unit 4 reads out the data of the histogram memory 2 and obtains the minimum luminance level (YMI) of the luminance signal of the screen assigned to the histogram memory 2 respectively.
N), detect the total frequency (TPX) written in the histogram and calculate the variance (DST). Further, the average value (APL) of the luminance levels at all sample points is calculated. These four control parameters (YMIN, TPX, D
Using ST, APL), three control parameters of a base value (BSE = initial value of the added value), an accumulated start point (RST), and an accumulated end point (RED) are calculated.

Next, data is read from the histogram memory 2 again, and a limiter (see FIG. 23 (b)) or addition of a constant value (see FIG. 23 (b)) is performed based on the calculated control parameters.
(see (c)), and the result is used as corrected histogram data c. Here, the larger the constant value (base value) to be added, the closer the cumulatively added curve becomes to a straight line,
Further, the smaller the value is, the flatter the curve obtained by cumulative addition is.

Then, the cumulative start point (RST)
And the cumulative end point (RED), the cumulative histogram data d of the corrected histogram data c is calculated within the range. This situation is shown in FIG. 23 (c) and FIG.
The curve L1 shown in FIG.

Next, the arithmetic control unit 4 obtains a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum output luminance level h, and normalizes each data g of the cumulative histogram based on this coefficient. Perform the conversion process. Operation control unit 4
The first, second, and third are based on which of the first and second screens the luminance data stored in the histogram memory 2 is.
Of the first and second correction table memories 11 and 13 and the first and second correction table memory i / f circuits 10 and 12, and the first correction table memory 11 (in this example) which selects the result i of the normalization processing. In the case, the first correction table memory 1
1. The first correction table memory i / f circuit 10 is selected. ). At this time, by controlling the maximum output luminance level h, the automatic contrast control (AC
L) and operations such as automatic bright control (ABL). This operation is shown in FIG. For a signal having a wide dynamic range, the cumulative histogram is close to a straight line (straight line L2 in FIG. 24A). Therefore, a correction table operation is performed by a correction table operation to bring the cumulative histogram of the input video luminance signal (curve L1 in FIG. 24A) closer to a straight line (straight line L2 in FIG. 24A).

The first correction table memory 11 reads out the data j using the converted input luminance signal b1 on the screen assigned to the histogram memory 2 as an address, and obtains a corrected output luminance signal k1. FIG. 24C shows a histogram of the corrected luminance signal.

Next, the third selector 16 switches the first correction output signal k1 for the first screen area and the second correction output signal k2 for the second screen area in accordance with the screen area, respectively. Output k. And D /
The A converter 17 converts the output signal k from the third selector 16 into an analog signal 1 and outputs it. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

As described above, by switching the screen for storing data in the histogram memory for each field, the amount of use of the histogram memory is not increased, and the feature detection for controlling data storage is also switched for each field in which the feature is detected. Therefore, since only one feature detection circuit is required, the gradation correction processing corresponding to a plurality of screens can be realized without increasing the circuit amount and without increasing the circuit amount of the histogram memory i / f circuit. As the sample area set in each field, it is only necessary to set the same sample area as the data extraction area and the feature detection area. For example, even if two screens overlap, it is possible to sample both screens. Degree of freedom can be increased.

Embodiment 5 FIG. 16 is a block diagram showing a configuration of a gradation correcting apparatus according to a fifth embodiment of the present invention, and corresponds to claims 9 and 10 of the present application. In the fifth embodiment, not only one histogram memory and one histogram memory i / f circuit can be provided, but also one feature detection circuit, and the effect of gradation correction can be obtained quickly. It is. The same parts as those of the tone correction device shown in FIG. 11 are denoted by the same reference numerals, and the description of the operation of those parts will be omitted.

In FIG. 16, reference numeral 61 denotes a histogram i /
An f circuit controls writing and reading of the histogram memory 2. FIG. 17 shows a histogram memory i / f.
FIG. 13 is a block diagram describing the configuration of the circuit 61 in detail. The same parts as those of the histogram memory i / f circuit shown in FIG. In FIG. 17, reference numeral 601 denotes a selector for switching between the first sample window register 203 and the second sample window register 204 according to a field identification signal sent from the field counter 19, and selects a register opposite to the selector 205. . 60
2 is a third comparison for comparing the position information of the current pixel by the pixel counter 206 with the position information of the sampling window output from the selector 601 and generating an enable signal when the current pixel is inside the sampling window. And generates an enable signal in a sampling window opposite to that of the first comparator 207. 603 is a third comparator 702
Is a selector for selecting whether or not to output a video signal to the feature detection circuit 20 according to the enable signal output from the selector. Thus, the sampling window from which the histogram is extracted and the sampling window from which the feature is detected are always the opposite sampling windows. Reference numerals 604, 605, and 606 are registers for holding three threshold values output from the feature detection circuit. Since there are three threshold values at which the feature is detected one field before, it matches the feature one field before the sampling window for histogram extraction in the current field.

The operation of the gradation correction circuit configured as described above will be described below. In the current field, it is assumed that the sampling window D1 in FIG. 14 is assigned to a sampling window for extracting a histogram.
Accordingly, the selector 205 in FIG. 17 selects the first sampling window register 203 corresponding to D1, and the selector 601 selects the second sampling window register 204 corresponding to the sampling window D2. Therefore, an enable signal is generated from the first comparator 207 in the sampling window D1 area, and the data in the D1 area is stored in the histogram memory 2 as histogram data. An enable signal is generated from the third comparator 602 in the sampling window D2 region, and data in the D2 region is output to the feature detection circuit 20 as feature detection data. The three threshold registers have the characteristics of the sampling window of the previous field, that is, the three values calculated from the maximum and minimum levels.
Two thresholds are maintained. The sampling window for detecting the feature of the previous field matches the sampling window for extracting the histogram of the current field, so that the histogram can be extracted with high accuracy. FIG. 18 shows a sampling window for each field and a timing chart of histogram extraction and feature detection.

In this way, even when a plurality of images are displayed on the display screen, the screen for storing data in the histogram memory is switched for each field without increasing the amount of use of the histogram memory. In the feature detection for controlling the accumulation, the screen for detecting the feature is switched for each field, so that only one feature detection circuit does not increase the circuit amount and the histogram memory i / f.
It is possible to realize gradation correction processing corresponding to a plurality of screens without increasing the circuit amount of the circuit, and to control the histogram extraction of the current field using the characteristics of the screen one field before, so that the control accuracy is improved. Can increase.

[0088]

As described above, according to the gradation correcting apparatus of the first aspect of the present invention, when a plurality of screens are simultaneously displayed on one screen, the gradation of each screen is corrected. A correction device, wherein the input video signal of each screen is switched at a specific cycle to store a frequency distribution of the amplitude level of the video signal of each screen; A histogram interface circuit that controls writing and reading of frequency distribution data to the histogram memory so as to store the frequency distribution of the amplitude level of the video signal of each screen by switching the video signal of the screen at a specific cycle; The luminance frequency distribution data is extracted from the histogram memory via the histogram interface circuit and the cumulative luminance distribution is calculated. Control parameters are set so that the obtained cumulative luminance distribution has a desired shape, the luminance frequency distribution is corrected using the control parameters, and the level of the input luminance signal is corrected using the corrected luminance frequency distribution. And a plurality of look-up table memories for holding a correction table for the video signals of the plurality of screens created by the arithmetic control unit for at least the specific period, and an image of each screen. type a luminance signal each time the signal is input by switching the plurality of look-up table memory, and an image switching selector for outputting a corrected luminance signal for each image using the correction table above SL look-up table memory So that
Takes a histogram at each specific cycle, switches the screen for setting the correction table, and performs tone correction for each screen independently
It is possible to realize gradation correction processing corresponding to a plurality of screens without increasing the amount of histogram memory used and the amount of histogram memory interface circuits, thereby reducing manufacturing costs and miniaturizing the apparatus. Is obtained.

Further, according to the gradation correcting device of the present invention, in the gradation correcting device of the present invention, the histogram memory interface circuit converts the video signals of a plurality of screens into video signals. On the other hand, as the specific period, a luminance signal is fetched by sequentially switching at a period of each field of the video signal or a period of a multiple thereof, and the luminance of one video signal is selected from a plurality of video signals displayed on the same screen. Since the frequency distribution is controlled so as to be extracted and given to the above-mentioned histogram memory, a histogram is taken at each cycle of one field or at a cycle of a multiple thereof, and the screen for setting the correction table is switched. It can be performed independently tone correction, increasing the circuit complexity of usage, and the histogram memory interface circuit of the histogram memory And no, it is possible to realize a gradation correction process corresponding to the plurality of screens, reduce the manufacturing cost,
Also, the effect that the size of the device can be reduced can be obtained.

Further, according to the tone correction device of the third aspect of the present invention, in the tone correction device according to the first aspect, the histogram interface circuit includes a plurality of types of frequency distribution extraction units. When a plurality of images are displayed on the display screen by using a plurality of types of frequency distribution extraction units by switching for each extraction region, the histogram accumulation process is switched for each screen by a screen switching signal.
Since the so that using a histogram cumulative tailored to each screen, and it is possible to realize a gradation correction processing, there is an advantage that it is possible to achieve reduction in manufacturing cost, and the size of the apparatus.

According to the tone correcting apparatus of the present invention, the histogram interface circuit extracts the plurality of types of frequency distribution extracting sections. Since the switching is performed in synchronization with the switching of the areas, it is possible to realize histogram accumulation and gradation correction processing suitable for each screen, to reduce the manufacturing cost, and to reduce the size of the apparatus. The effect is obtained.

Further, according to the gradation correcting apparatus of the present invention, a histogram memory for storing a frequency distribution of amplitude levels of an input video signal, and a histogram memory for extracting the frequency distribution and storing the histogram memory A histogram memory interface circuit for writing and reading data to and from the histogram memory interface circuit, and a correction formula or a correction table for correcting the level of the input luminance signal using the data of the luminance frequency distribution extracted from the histogram memory interface circuit. In a gradation correction device comprising an arithmetic control unit and a correction table for holding a correction formula or a correction table for a screen created by the arithmetic control unit, the histogram memory interface circuit includes a first memory of the histogram memory. Data type output when memory at address is full Receiving the signals, as comprising a reset unit for transmitting a reset signal for resetting the memory of the first address in the histogram memory, a data storage signal transmission unit for transmitting the data stored signals in a memory of the second address Therefore , the mode is switched by the mode signal, and one of the two mode histograms is selected to extract the histogram.
It can, in performing the extraction of a plurality of types of frequency distribution, 1
It is possible to change the maximum frequency of the frequency distribution of the amplitude level that can be accumulated in one range, thereby realizing a gradation correction process using the histogram memory effectively.
The effects of reducing the manufacturing cost and the size of the device can be obtained.

According to the tone correcting apparatus of the present invention, the histogram memory interface circuit includes a plurality of types of frequency distribution extracting units. The reset unit and the data storage signal transmission unit are controlled by the operation status of the plurality of types of frequency distribution extraction units. Therefore, when extracting a plurality of types of frequency distributions, one range is used. It is possible to change the maximum frequency of the frequency distribution of the amplitude level that can be accumulated in the memory, thereby realizing a gradation correction process using the histogram memory effectively, reducing the manufacturing cost and miniaturizing the apparatus. The effect is that it can be achieved.

According to the gradation correcting apparatus of the present invention, when displaying a plurality of screens simultaneously on one screen, the gradation correcting apparatus corrects the gradation of each screen. A histogram memory for storing the frequency distribution of the amplitude levels of the video signals of the respective screens by switching the video signals of the respective input screens at a specific cycle, and detecting the amplitude level characteristics of the input video signals. A detection circuit, a histogram interface circuit for controlling writing / reading to / from the histogram memory, and a control of input / output of a video signal to / from the feature detection circuit, and frequency distribution data of the video signal extracted from the histogram interface circuit An arithmetic control unit that creates a correction formula or a correction table for correcting the level of the input video signal using
By switching between the plurality of correction table memories that hold correction formulas or correction tables for the video signals of the plurality of screens created by the arithmetic control unit and the plurality of correction table memories each time a video signal of each screen is input. A screen switching selector for inputting a video signal and outputting a corrected video signal of each screen using a correction formula or a correction table in the correction table memory, wherein the histogram interface circuit is displayed on the same screen. An area corresponding to a video signal of one screen is controlled so as to be a frequency distribution extraction area from among the screens, and the histogram interface circuit performs the control of one screen from among the plurality of screens displayed on the same screen. In addition to controlling the area corresponding to the video signal to be the feature detection area, the histogram interface Circuit comprises a plurality of registers,
Since the feature data detected by the feature detection circuit can be held for a certain period of time, the feature detection for controlling data accumulation can be performed without detecting an increase in the amount of use of the histogram memory. In order to switch screens, it is possible to realize gradation correction processing corresponding to a plurality of screens without increasing the amount of circuits with only one feature detection circuit and without increasing the amount of circuits of the histogram memory interface circuit. The sample area set in step 4 is the data extraction area and feature detection
It is only necessary to set the same sample area as the R> area. For example, even when two screens are overlapped, it is possible to realize a gradation correction process that increases the degree of freedom of the sample area, for example, it is possible to sample both screens. Effects can be obtained.

According to the gradation correcting apparatus of the present invention, in the gradation correcting apparatus of the present invention, the histogram interface circuit may be configured to set the frequency distribution extraction area for each field or for each field. The feature detection area is switched at a cycle of a multiple, and the feature detection area is switched at a cycle of a field or a multiple of the field. Therefore, the feature detection for controlling data accumulation can be performed without increasing the amount of use of the histogram memory. In order to switch the screen to be detected, it is possible to realize a gradation correction process corresponding to a plurality of screens without increasing the circuit amount by only one feature detection circuit and without increasing the circuit amount of the histogram memory interface circuit. The sample area set in the field is the same as the data extraction area and feature detection area. It is only necessary to set a sample area. For example, even when two screens overlap, it is possible to obtain the advantageous effect of realizing a gradation correction process in which the degree of freedom of the sample area is increased, for example, both samples can be sampled. .

According to the tone correcting apparatus of the ninth aspect of the present invention, when displaying a plurality of screens simultaneously on one screen, the tone correcting apparatus corrects the tone of each screen. The video signal of each input screen is switched at a specific cycle, and a histogram memory for storing the frequency distribution of the amplitude level of the video signal of each screen, and the video signal of each input screen is switched at a specific cycle. A feature detection circuit for detecting a feature of the amplitude level of the video signal of each screen;
A histogram interface circuit that controls writing and reading to and from the histogram memory and controls input and output of a video signal to and from the feature detection circuit; and input using the frequency distribution data of the video signal extracted from the histogram interface circuit. An arithmetic control unit for creating a correction formula or a correction table for correcting the level of the video signal, and a plurality of correction table memories for holding the correction formulas or the correction tables for the video signals of a plurality of screens created by the arithmetic control unit Each time a video signal of each screen is input, switches the plurality of correction table memories to input a video signal, and outputs a corrected video signal of each screen using the correction formula or the correction table of the correction table memory. A screen switching selector, wherein the histogram interface circuit comprises: An area corresponding to a video signal of one screen among a plurality of screens displayed on the same screen is controlled to be a frequency distribution extraction area, and the histogram interface circuit is displayed on the same screen. The histogram interface circuit controls the area corresponding to the video signal of one screen from a plurality of screens to be a feature detection area, and the histogram interface circuit determines that the screen of the feature detection area is the frequency distribution extraction area next. In this way, the histogram interface circuit performs one of the multiple screens displayed on the same screen.
The histogram interface circuit controls the area corresponding to the video signal of one screen to be a frequency distribution extraction area, and the histogram interface circuit supports the video signal of one screen from the plurality of screens displayed on the same screen. performs control such that the feature detection area region, the histogram interface circuit be switched as screen of the feature detection area then becomes the frequency distribution extraction area
In this case , the amount of the histogram memory used is not increased, and the feature detection for controlling the data accumulation is performed by switching the screen for detecting the feature for each field. It is possible to realize gradation correction processing corresponding to a plurality of screens without increasing the amount of interface circuits, and to control the extraction of the histogram of the current field using the characteristics of the screen one field before. The advantageous effect that the tone correction processing in which the number increases can be realized can be obtained.

Further, according to the gradation correcting apparatus of the tenth aspect of the present invention, in the gradation correcting apparatus according to the ninth aspect, the histogram interface circuit may be configured to set the frequency distribution extraction area for each field or for each field. Since the feature detection area is switched on a field-by-field basis or on a cycle of a multiple of the field, the feature detection area is switched on a field-by-field basis without increasing the amount of use of the histogram memory. In addition, it is possible to realize a gradation correction process corresponding to a plurality of screens without changing the amount of circuits with only one feature detection circuit and without increasing the amount of circuits of the histogram memory interface circuit. Histogram extraction of current field using feature of screen one field before Advantageous effect that it is possible to realize a gradation correction processing to increase the control precision in order to control is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a tone correction device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a histogram memory i / f circuit included in the gradation correction device according to the first embodiment.

FIG. 3 is a diagram for explaining an example of a histogram sampling window of the tone correction device according to the first embodiment.

FIG. 4 is a block diagram of a tone correction device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a histogram memory i / f circuit included in the gradation correction device according to the second embodiment.

FIG. 6 is a diagram showing an example of an extraction histogram of the gradation correction device according to the second embodiment.

FIG. 7 is a block diagram of a tone correction device according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a histogram memory i / f circuit included in the gradation correction apparatus according to the third embodiment.

FIG. 9 is a diagram showing an example of an extraction histogram of the gradation correction device according to the third embodiment.

FIG. 10 is a diagram showing an example of data accumulation of the gradation correction device according to the third embodiment.

FIG. 11 is a block diagram of a tone correction device according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a histogram memory i / f circuit included in the gradation correction device according to the fourth embodiment.

FIG. 13 is a block diagram of a feature detection circuit included in the tone correction device according to the fourth embodiment.

FIG. 14 is a diagram for explaining an example of a histogram sampling window of the tone correction device according to the fourth embodiment.

FIG. 15 is a diagram showing an example of an extraction histogram of the gradation correction device according to the fourth embodiment.

FIG. 16 is a block diagram of a tone correction device according to a fifth embodiment of the present invention.

FIG. 17 is a block diagram of a histogram memory i / f circuit included in a gradation correction device according to a fifth embodiment of the present invention.

FIG. 18 is an operation timing chart of a histogram memory i / f circuit included in the gradation correction device according to the fifth embodiment of the present invention.

FIG. 19 is a block diagram of a conventional gradation correction device.

FIG. 20 is a characteristic diagram for explaining the operation of each part of the conventional tone correction device.

FIG. 21 is a characteristic diagram for explaining the operation of each part of the conventional tone correction device.

FIG. 22 is a block diagram illustrating a configuration of a conventional tone correction device.

[Explanation of symbols]

1 A / D converter 2, 71, 73 Histogram memory 3, 41, 61, 72, 74, 100 Histogram memory i / f circuit 4 Operation control unit 5 Program ROM 6, 7 Register RAM 10, 12 Correction table memory i / f f circuit 11, 13 correction table memory 14, 15, 16, 22, 25, 28, 31, 57, 8
1, 82, 84 selector 17 DA converter 18 synchronization processing circuit 19 Field counter 20 Feature detection circuit 21, 83 Adder 23 , 24 , 29 , 53 , 55 , 85 Register 26 Pixel counter 27, 30, 54, 56 Comparator 201 Adder 202, 205, 208, 218, 219, 220 , 2
21, 222, 223, 225, 601, 603 Selector 203, 204, 209, 212, 213, 214, 2
15, 216, 217, 604, 605, 606 Register 206 Pixel counter 207, 210, 224, 602 Comparator 301 Maximum value detection circuit 302 Minimum value detection circuit 303 Threshold calculation circuit

Continuation of the front page (56) References JP-A-7-298096 (JP, A) JP-A-3-126377 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5 / 20 H04N 5/202

Claims (10)

(57) [Claims] 1. A gradation correction device for correcting gradation of each screen when a plurality of screens are simultaneously displayed on one screen, wherein the histogram stores a frequency distribution of an amplitude level of a video signal of each screen. A memory and a histogram distribution data are stored in the histogram memory so that the video signal of each screen to which the histogram memory is input is switched at a specific cycle to store the frequency distribution of the amplitude level of the video signal of each screen. A histogram interface circuit that performs write and read control of the histogram memory, and obtains luminance frequency distribution data from the histogram memory via the histogram interface circuit to calculate a cumulative luminance distribution. Control parameters are set so as to have a shape, and the number of luminance An arithmetic control unit that corrects the cloth and creates a correction table for correcting the level of the input luminance signal using the corrected luminance frequency distribution; and a correction table for the video signals of a plurality of screens created by the arithmetic control unit. enter the luminance signal by switching at least a plurality of look-up table memory for storing during the specific period, the plurality of look-up table memory for each video signal for each screen is inputted, the upper <br/> Symbol look An image switching selector for outputting a corrected luminance signal of each image using a correction table in an up table memory. 2. The gradation correcting device according to claim 1, wherein the histogram memory interface circuit is configured to:
The luminance signal is fetched by sequentially switching at a cycle of each field of the video signal or a cycle of a multiple thereof, and control is performed so as to extract a luminance frequency distribution of one video signal from a plurality of video signals displayed on the same screen. A gradation correction device for applying the gradation correction value to the histogram memory. 3. The gradation correction device according to claim 1, wherein the histogram interface circuit includes a plurality of types of frequency distribution extraction units, and switches between the plurality of types of frequency distribution extraction units for each extraction region. A gradation correcting device, comprising: 4. The gradation correction apparatus according to claim 3, wherein the histogram interface circuit switches the plurality of types of frequency distribution extraction sections in synchronization with the switching of the extraction area. Tone correction device. 5. A histogram memory for storing a frequency distribution of amplitude levels of an input video signal; a histogram memory interface circuit for extracting the frequency distribution and writing and reading the histogram memory; A correction expression for correcting the level of the input luminance signal using the data of the luminance frequency distribution extracted from the interface circuit, or an arithmetic control unit for creating a correction table, and a correction expression for the screen created by the arithmetic control unit Or a correction table holding a correction table, wherein the histogram memory interface circuit receives a data storage signal output when the memory at the first address of the histogram memory is full, Reset the memory at the first address Gradation correction device comprising a reset portion for the reset signal to send to said histogram memory, further comprising a data storage signal transmission unit for transmitting the data stored signals in a memory of the second address to. 6. The gradation correction device according to claim 5, wherein the histogram memory interface circuit includes a plurality of types of frequency distribution extraction units, and the reset unit and the data storage signal transmission unit include the plurality of types of frequency distributions. A gradation correction apparatus, wherein the operation is controlled by the operation state of a distribution extraction unit. 7. A gradation correcting device for correcting a gradation of each screen when a plurality of screens are simultaneously displayed on one screen, wherein a video signal of each input screen is switched at a specific cycle, A histogram memory for storing a frequency distribution of the amplitude level of the video signal of each screen; a feature detection circuit for detecting a feature of the amplitude level of the input video signal; control of writing and reading to and from the histogram memory; A histogram interface circuit for controlling input / output of a video signal to a detection circuit; and a correction formula or correction for correcting a level of the input video signal using data of a frequency distribution of the video signal extracted from the histogram interface circuit. An arithmetic control unit for creating a table, and a correction formula or a correction formula for video signals of a plurality of screens created by the arithmetic control unit A plurality of correction table memories for holding a correct table, and each time a video signal of each screen is input, the plurality of correction table memories are switched to input a video signal, and a correction formula or a correction table of the correction table memory is used. And a screen switching selector for outputting a corrected video signal of each screen. The histogram interface circuit extracts a frequency distribution area corresponding to a video signal of one screen from the plurality of screens displayed on the same screen. The histogram interface circuit controls the area corresponding to the video signal of one screen from among the plurality of screens displayed on the same screen as the feature detection area. Wherein the histogram interface circuit includes a plurality of registers, and is detected by the feature detection circuit. A gradation correction device capable of holding the acquired characteristic data for a certain period of time. 8. The gradation correction device according to claim 7, wherein the histogram interface circuit switches the frequency distribution extraction region for each field or at a cycle of a multiple of a field, and switches the feature detection region for each field or a multiple of a field. A gradation correction device characterized in that switching is performed in a cycle of (1). 9. A gradation correcting device for correcting gradation of each screen when a plurality of screens are simultaneously displayed on one screen, wherein a video signal of each input screen is switched at a specific cycle, A histogram memory for storing a frequency distribution of the amplitude level of the video signal of each screen, and a feature of switching the input video signal of each screen at a specific cycle to detect a feature of the amplitude level of the video signal of each screen. A detection circuit; a histogram interface circuit that controls writing and reading to and from the histogram memory and a video signal input and output to and from the feature detection circuit; and data of a frequency distribution of the video signal extracted from the histogram interface circuit. An arithmetic control unit that creates a correction formula or a correction table for correcting the level of the input video signal using A plurality of correction table memories that hold correction formulas or correction tables for the video signals of a plurality of screens created by the unit, and switch the plurality of correction table memories each time a video signal of each screen is input to switch the video signal. A screen switching selector for inputting and outputting a correction video signal of each screen using a correction formula or a correction table of the correction table memory, wherein the histogram interface circuit is provided for selecting a plurality of screens displayed on the same screen. To control a region corresponding to a video signal of one screen to be a frequency distribution extraction region, and the histogram interface circuit converts a video signal of one screen from a plurality of screens displayed on the same screen. The corresponding area is controlled to be a feature detection area, and the histogram interface circuit Gradation correction apparatus characterized by switching as screen of the feature detection area then becomes the frequency distribution extraction region. 10. The gradation correction device according to claim 9, wherein the histogram interface circuit switches the frequency distribution extraction area for each field or at a cycle of a multiple of a field, and switches the feature detection area for each field or a multiple of a field. A gradation correction device characterized in that switching is performed in a cycle of (1).