JP3251463B2 - Method of programming a memory device and its control operation function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory device, and more particularly, to an SDRAM (synchronous memory device).
onous dynamic random access
ss memory) circuit and method for initializing and reprogramming a programmable control operation function of a device to a desired control operation option.

[0002]

2. Description of the Related Art The following prior art describes a 16M × 8 bit SDRAM MT48LC2M8S1.
The MT48LC2M8S1 is internally configured as a dual 1M × 8-bit SDRAM having a built-in synchronization interface and control logic. The dual 1M × 8 bit SDRAM has two banks, each bank having 8 banks.
Memory arrays, each memory array having one row and column electrically intersected in a matrix.
It contains M (1,048,576) bit memory cells. SDRAMs provide a significant advance in the performance of dynamic memories.

[0003] Two major advances in SDRAM are the automatic column address generation, which provides the ability to burst transfer data synchronously at a high data transfer rate and the interleaving between internal banks that hides the precharge time. Function. Interleaving between two open banks increases the likelihood of a "page hit".
Interleaving between open banks coupled to a fast burst mode often allows for "continuous" data flow transfer.

When accessing an SDRAM, a control circuit operates to access one of the internal banks of the memory. Typical synchronous designs provide optimal memory performance for low voltage (typically 3.3V) memory systems. CKE
Except for the (clock enable) signal, all input / output signals are synchronized with the system clock. CL
At the rising edge of the K (system clock) signal, an input trigger for synchronizing the SDRAM is supplied.

[0005] SDRAMs are equipped with many programmable control functions. To activate each programmable control operation function with the desired control operation option (also called control operation mode), first initialize
Registers need to be set. Setting the mode register allows access to the SDRAM.

[0006] Eleven rows by the Active command.
Following input of the address bits (A0-A10), RE
Nine column address bits (A0-A8) are input by the AD / WRITE command to uniquely access each byte. The internal bank selection is performed by a RAS (row address storage) that enables access to the bank so that a read / write operation to the bank can be performed.
be) signal and CAS (column address)
When a strobe signal is input, BA (bankacti)
vate) signal. This bank selection
Also called bank activation. The selected bank is called an active or activated bank.

The SDRAM requires a row access command and a separate precharge command.
When the row of the SDRAM is selected, the bank enters an active state and holds that state. That is, the internally generated RAS * signal remains active, and the selected row remains open until precharged by a precharge command. Throughout this specification, a signal with an asterisk, such as RAS *, represents the inversion of the corresponding signal. The corresponding signal in this example is RAS. While the previous row is still active, inadvertent access to other rows in the same bank is not allowed, destroying data in the memory of the offending bank.

[0008] The SDRAM must be powered on and initialized in a prescribed manner. If the operation is performed in an order other than the specified operation, the startup mode becomes unnecessary and cannot be reproduced. Power supply (VCC and VCCQ) is main logic and D
When supplied simultaneously to the power pins of the Q buffer,
The SDRAM must be delayed by 100 microseconds before the signal is inverted. When the power is turned on, set all inputs to H
It is recommended to keep at the level.

The SDRAM should be considered powered up by the mode register in an unknown state.
At initialization, the signal on the DQ pin is used as an input to the programming circuit. There are programming circuits for each programmable control operation function that program the SDRAM to the desired control operation options in response to the output of the programming circuit and the mode register. Therefore, before executing the operation command, the mode register of the SDARM must be set.

[0010] The mode register is a resident register.
That is, once set, data is latched to its output until reset or until the device is powered down.

FIG. 2 is a part of a related art SDRAM,
Along with the SMRC generated by the master control circuit, address inputs A0-A10 and A
It has a mode register 3 which is programmed by supplying the opcode via BA. The mode register 3 stores the CLK (system clock) when the mode register is enabled by the SMRC.
There are 11 D flip-flop circuits that latch the opcode in the mode register on the rising edge of k). The programming circuit 8 selects a control operation option of each programmable control operation function of the SDRAM.

FIG. 3 shows a control operation option of each programmable control operation function related to an operation code used to generate a desired control operation option. Opcode 9
Is represented by bits M0-M11. The programmable control operation functions include burst length, burst type, and read wait time.
0 is shown. Other programmable control functions are shown in Table 25. The programmable control operation functions shown in Charts 10, 15, and 20 are based on the JEDE
C (joint electron device e)
ngering counsel) standard. Other programmable control operation functions shown in Table 25, except for “test mode entry”, are specific to the vendor and application and have been approved by JEDEC.

The control operation option selected for the read latency function shown in Table 20 is determined by the M4-M6 opcode. The sequential operation option or the interleave operation option of the burst type function shown in FIG. The operation options of the burst length function shown in Table 10 are bits M0-M2
Is determined.

FIG. 4 shows an SDRAM MT48LC2M8S.
1 is a block diagram of the related art, which is published by Micron Technology Inc.
It is also described in RAM Data Book (1993). SMRC is a CS * (chip select) signal, RAS * (row access strobe).
Signal, CAS * (column address st)
probe) and WE (write enable)
e) When the signal is in the idle state, the signal is generated by setting the signal to the L level. It is idle when all internal RAS signals are inactive, usually at H level. S
The MRC is generated by the master control circuit 19.
SMRC, CLK, address input pins A0-A10 and pins
All the opcodes input from the input terminal B A are received by the mode register 21.

The read waiting time is a programmable control operation function defined by an operation code input from the address input pins A4 to A6 together with the SMRC. Address bits A4-A6 define the number of clock cycles, and during a read cycle, the data output will be delayed or offset from the corresponding CAS input. As shown in Table 20 of FIG. 3, the waiting time of 1, 2, or 3 clocks can be set. The read wait time is TCK (clock r
ate) regardless of which clock the data is available on.

The burst type is a programmable control operation function defined by an operation code input from the address input pin A3 together with the SMRC. Address input bit A3 defines which burst type option to invoke, as shown in Table 15 of FIG.

Two types of burst types, a sequential burst type and an interleaved burst type, can be set. Both the sequential burst type and the interleaved burst type support burst lengths of 2, 4, and 8 cycles. In addition, sequential
The burst type supports a full page option.

The burst length is a programmable control operation function defined by an operation code input from the address input pins A0 to A2 together with the SMRC. Address bits 2-0 define the burst length and are shown in FIG.
0 is shown.

The burst length is the length of the continuous data starting from the designated position during read or write access.
It is a flow. 2, 4, 8 burst length options or full page cycles can be programmed.

[0020]

When the mode register of a typical SDRAM is programmed, all of the memory banks need to be inactive,
It takes many clock cycles to reprogram the mode register. For example, at initialization, MT4
If the mode register of the 8LC2M8S1 is programmed for sequential burst, it takes 11 clock cycles to reprogram the mode register for interleaved burst. Related technology MT4
See the timing diagram of FIG. 5 which shows the clock cycles required to reprogram the 8LC2M8S1. A similar problem is encountered when reprogramming another control operation function of the mode register.

The JEDEC-specified standard requires the setting of the order type to be programmed in the mode register. The program register must be reprogrammed each time the sequence type changes. Reprogramming the program registers requires several cycles of overhead. Therefore, changing the sequence type of the program at the time of operation causes a significant loss of time. Therefore, there is a need to minimize the time required to reprogram the mode register, thereby increasing processing speed.

[0022]

SUMMARY OF THE INVENTION In one embodiment, the present invention is a memory device incorporating a master control circuit for receiving a first command and a second command and an initialization / reprogramming circuit. . The master control circuit generates an initialization signal in response to a first command and generates reprogramming in response to a second command. The initialization / reprogramming circuit controls initial programming of the control operation function in response to the initialization signal, and controls reprogramming of the control operation function in response to the reprogramming signal.

In another embodiment, the initialization / reprogramming circuit has a first input node and a second input node, and the potential of the first input node is selected during initial programming of the control operation function. And the potential of the second input node determines the selected control operation option during reprogramming.

The programming circuit of the initialization / reprogramming circuit performs the actual programming of the control operation function. In one embodiment, during initial programming, the input signal to the programming circuit is inverted during reprogramming.

In yet another embodiment, the initialization and reprogramming circuit includes a first information bit receiving a first information bit.
And a second input pin for receiving a second information bit. A latch circuit that latches the first information bit to a latch output node during initial programming;
Upon reprogramming, the second information bit is latched at the latch output node. The multiplexer circuit multiplexes the first information bit and the second information bit to an input node of the latch circuit. The programming circuit programs the control operation function in response to the output of the latch circuit.

The internal control state machine of the master control circuit monitors the command signal,
An active signal is generated in response to the A command, and an idle signal is generated in the absence of the BA command. In at least one embodiment, reprogramming is performed in response to an active signal.

The circuit of the present invention minimizes the time required to reprogram the mode register because the memory device does not need to return to its original state before reprogramming. Except for the command that controls the initial programming, another command controls the reprogramming.

In another embodiment, the present invention programs a first control operation option to a memory device in response to a first command, and stores a second control operation option in a memory device in response to a second command. This is a method of reprogramming the control operation option.

In another embodiment, reprogramming is performed when the BA signal is present.

In another embodiment, a first information bit is latched at the output node of the latch circuit during initial programming, and a second information bit is latched at the latch output node during reprogramming. During initial programming and reprogramming, the selected control operation option is determined from the first information bit and the second information bit value, respectively.

In yet another embodiment, a first programming signal is generated in response to the information bit to determine a control operation option selected during the initial programming and to invert the value of the first programming signal, A second programming signal is generated to determine a selected control operation option selected during reprogramming.

The method of the present invention does not require a memory device to return to its original state before reprogramming. Mode register reprogramming time can be minimized. Except for the command that controls initial programming, another command controls reprogramming. Thus, the method of the present invention increases the processing speed of a memory device.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiments, the electrical functions and connections have been described. Equivalent circuits may be used to perform the described functions without departing from the scope of the invention. Similarly, two connected electronic components can have a component that physically separates the two components. Thus, "connected" is intended to include parts in electrical communication even with parts in between.

According to the present invention, SDRA at startup is
SDRA having a circuit for programming the control operation function into the SDRAM when M is initialized and a circuit for reprogramming the control operation function during the normal operation of the SDRAM
M. Reprogramming is performed using ARC (active
row command) or ABA
When the (active bank activate) signal is present, it is idled during an active cycle. Usually, the ABA signal is generated internally in response to the ARC. In the SDRAM of the present invention, A
The BA signal is generated when the internal RAS * signal is at L level. In this description, the active cycle is
An SDRAM in which there is at least one memory bank in an active state or at least one memory bank is activated by an ABA signal.

FIG. 6 is a simplified block diagram of one SDRAM 30 of the present invention. The SDRAM 30 is a 2M × 8-bit memory containing two memory banks 31 and 31. Each memory bank 31 and 33 has eight memory arrays. Each memory array is
It consists of 1,048,576 bit memory storage cells for recording electronic data. The initialization / reprogramming circuit 35 receives at least two control signals from the master control circuit 37. The master control circuit 37 receives the memory command, generates an internal control signal in response to the memory command, and
Control device behavior. The control signal generated by the master control circuit 37 is received by the initialization / reprogramming circuit 35, controls the initialization and reprogramming of the control operation function, and sets a desired control operation option (control operation mode). The initially selected operation mode depends on the instruction code (opcode) or the potential of at least one of the address input pins A0-A10 and ABA.

In the SDRAM shown in FIG. 6, CKE (cl
All input / output signals are synchronized with the system CLK (clock), except for the ACK enable signal. At the rising edge of CLK, an input trigger is provided to synchronize the SDRAM.

When the SDRAM is initialized, it can be accessed. Each byte has 11 rows
Following input of the address bits (A0-A10), re
It is uniquely accessed by inputting nine column address bits (A0-A8) by the ad / write command. The internal bank selection is controlled by an internal ABA signal generated by the master control circuit 37.
The internal bank selection is a RAS (r) that allows access to the bank to perform a read / write operation to the bank.
When a CAS signal is input, which is performed at the time of inputting an "ow address strobe" signal, an actual read / write access is started. Bank selection is called bank activation. The selected bank is called an active bank.

The SDRAM 30 is reprogrammed when the bank is active or during an actual read / write access. Reprogramming occurs in response to at least two control signals generated at output nodes 38 and 39 of master control circuit 37.

When the control signal of the output node 38 is in the active state, the SMRC (set mode register)
er command) is CS * which becomes L level when the clock is enabled and in the idle state.
(Chip select) signal, RAS * (row
address strobe) signal, CAS * (co
The master control circuit 3 is provided by an external SMRC formed by a signal L. lun address strobe) and a signal WE * (write enable).
7 is generated. When idle, there are no active memory banks and the BA signal goes inactive. When idle, it is initialized in response to SMRC.

There are at least three embodiments of the circuit of FIG. In all three embodiments, the burst type is a control operation function that is initialized and reprogrammed by the circuit and method of the present invention. In all three embodiments, the burst-type operation options are a sequential option and an interleave option. The desired burst type operation option is determined at initialization by the opcode of address bit A3. Sequential burst type and interleave burst type are 2, 4
And bursts of 8 cycles. In addition, the sequential burst type also supports a full page length option.

In all three embodiments, the master
The internal control state of the control circuit 37
The machine monitors the control commands and determines when all memory banks are idle or inactive, and when at least one memory bank is active or the BA signal is active. When all memory banks are inactive, the internal control state machine outputs an idle signal at an output node from the first internal control state machine, and when the BA signal is active. , Internal control state
The machine outputs an active signal from an output node of the second internal control state machine. Circuits that function as internal control state machines are well known to those skilled in the art.

In the first embodiment, the values of the reprogramming are saved. CS * signal, RAS * signal, CAS *
Repr when the signal is at L level and the WE * signal is at H level
The programming command is issued before the read / write cycle. The control operation function is reprog
Reprogrammed in response to the ramming command. During reprogramming, in which the value is retained, when the control operation function is reprogrammed from the first operation option to the second operation option, the SDRAM is reprogrammed.
Operate with the second operation option until reprogrammed by the mming command.

In the second embodiment, the value of reprogramming is not retained. That is, when the control operation function is reprogrammed from the first operation option to the second operation option, the control operation function automatically switches from the second operation option to the first operation option after the current access cycle. Go back. The operation option selected at the time of reprogramming of the second embodiment is valid only during the current access cycle, that is, until another CAS * signal is input. The reprogramming operation is
It lasts only for one burst sequence and is independent of address. If it is desired to maintain the change during a plurality of burst sequences, a reprogramming command, an L-level CAS * signal, a RAS * signal, a CA
The S * signal and H level WE * signal must each be issued before a new column address is issued.

In the third embodiment, an unused address input pin, in this case, the A9 pin receives an operation code during the CAS period. The opcode determines the operation options of the control operation function during reprogramming.

FIGS. 7-11 are detailed views of a portion of the SDRAM shown in FIG. 6 for the embodiment described above. The circuits of FIGS. 7-11 have similar components and functions. Next, these similarities will be described. Common parts are assigned the same numbers in FIGS. Master·
The detailed circuit of the control circuit 37 is a part of the entire circuit of the master control circuit 37 and relates to the circuit of the present invention. Initialization / reprogramming circuit 35
Has 12 D flip-flop circuits D0 to D11 constituting the mode register 51. When the internal control state machine 53 outputs an idle signal from the output node 55 of the first internal control state machine, and when the CKE signal is H
When the level, the CS * signal, the WE * signal, the CAS * signal, and the RAS * signal are at the L level, the master control circuit 37 outputs the output node 38 of the NAND logic gate 59.
Output SMRC. SMRC is an enable signal input to the mode register 51 and enables the D flip-flops D0 to D11. When the D flip-flop is enabled, each address input pin A0
The potentials of -A11 and ABA are latched at the corresponding D flip-flop output nodes in response to the transition of CLK to the H level. In all three embodiments, D
The output of 3 is used in the burst type programming circuit 61 to determine whether the sequential operation option or the interleave operation option is programmed.

In the circuits of FIGS. 7 and 8, the output of D3 is the input to exclusive OR logic gate 63, while
In the circuit of FIG. 9, the output of D3 is directly connected to the input node of the burst type programming circuit 61.
Referring again to FIGS. 7 and 8, the output of exclusive OR logic gate 63 is connected to input node 64 of burst type programming circuit 61. At the time of initialization, the exclusive OR logic gate 63 is enabled, and the output potential of the exclusive OR logic gate 63 is the same as the output potential of D3.

Perhaps the initialization of the SDRAM of FIGS. 7 and 8 is best understood when illustrated. Assuming that the potential of the pin A3 is at the H level, the potential of the H level is D3
And the input node 65 of the exclusive OR logic gate 63. Since the exclusive OR logic gate 63 is enabled by the L-level potential of the input node 66, the potential of the output node 67 of the exclusive OR logic gate 63 is the same as the potential of the input node 65. In the example, the output potential of output node 67 is at H level. The burst type programming circuit programs the SDRAM in an interleaved burst type in response to an H level potential. Conversely, when the potential of the pin A3 is at the L level, the L level potential appears at the output node 67, and the burst type function is set to the sequential burst type by the burst type programming circuit 61.

In the circuit of FIG. 9, the output node of D3 is the input node 6 of the burst type programming circuit 61.
4 is connected directly. The potentials of pins A3 and A9 are multiplexed to the input of D3 so that pin A3 becomes the input of D3 during initialization and pin A9 becomes the input of D3 during reprogramming. Thus, the potential at pin A3 determines the burst function during initialization, and the potential at A9 determines the burst function during reprogramming.

The circuits of FIGS. 7 and 8 have some commonality with respect to the reprogramming of the burst-type function of the present invention. In either case, exclusive OR logic gate 6
The enable signal input to the third input node 66 changes the state at the time of reprogramming. This allows exclusive O
The output potential of R logic gate 63 is inverted to the opposite logic state. When the output potential at output node 67 is inverted, the burst programming circuit responds by programming the reverse operation option to a burst function.
Therefore, if the SDRAM is initialized to a sequential burst, the SDRAM is reprogrammed to an interleaved burst or vice versa. The value of the reprogramming performed by the circuit of FIG. 7 is retained. That is, the SDRAM continues to operate with the reprogrammed burst type function until it is reprogrammed. The values of the reprogramming performed in the circuit of FIG. 8 are not retained. That is, the SDRAM returns to the initial operation option after the current access cycle. In either case, the ITC (internal tagg)
le command) is an exclusive OR logic gate 63
This command changes the state of the enable signal at the input node 66 of the master control circuit 37 and is output from the AND logic gate 75 of the master control circuit 37. In both cases, A
The ND logic gate 75 has an L level CS * signal, RAS
The ITC is generated in response to the * signal, the CAS * signal, the WE * signal, the CKE signal, and the H level active state signal. ITC is an input to the intermediate logic circuit 80,
LK inputs to the exclusive OR logic gate input. L
An external toggle command is configured by a combination of the CS * signal, the RAS * signal, the CAS * signal, the WE * signal, and the CKE signal at the H level. External tog
The gle command generates an ITC in combination with an internally generated active signal.

FIG. 10 is a detailed diagram of the intermediate logic circuit 80 of FIG. CLK and ITC are input to AND logic gate 85. The output of the AND logic gate 85 is an L level S
In response to the MRC, at initialization, output node 90 initially goes low.
Input to a D flip-flop reset to the level potential. The output potential of output node 90 of D flip-flop 87 is connected to input node 66 of the exclusive OR logic gate of FIG.
Connected to The output potential of the output node 90 of the D flip-flop 87 changes as the output potential of the output node 90 of the exclusive OR logic gate changes state when the output of the AND logic gate 85 synchronizes the D flip-flop. The inverted value is inverted by the inverter 95 so that the potential value of the output node 67 of the gate 63 also changes. The potential value of the output node 67 of the exclusive OR logic gate 63 does not change until the external toggle command starts the next reprogramming. Therefore, the value of the reprogramming is retained.

Referring again to FIG. 8, the AND logic gate 100 of the master control circuit 37 is connected to the CAS * RC (CAS registrat) of the intermediate logic gate 80.
(ion command) to the intermediate logic circuit 80. The intermediate logic circuit 80 originally generates a signal obtained from the burst type programming circuit 61 for programming the programmed operation option at the time of initialization to generate C
Responds to AS * RC. CAS * RC is also used for column address for read / write command and latch of WE * state. AND logic gate 100 responds to the CAS * RC signal in response to an active state signal generated within internal control state machine 53 along with an externally controlled CKE, CAS *, RAS * and CS * signals. Generate CKE signal,
The states of the RAS * signal, CS * signal and CAS * signal must be H level, H level, L level and L level, respectively.

FIG. 11 is a detailed diagram of the intermediate logic circuit of FIG. The intermediate logic circuit 80 includes two AND logic gates 105 and 110 to which CLK is input as one input signal, two D flip-flops 115 and 120, a NAND logic gate 125, and a negative NOR logic gate. AND logic gate 105 receives ITC as a second input signal and provides a clock signal to D flip-flop 115. The input node of D flip-flop 115 is connected to a power supply (usually Vcc). The output signal of the D flip-flop 115 is an input signal to the D flip-flop 120. AND logic gate 110 has CAS * RC
As a second input signal, and supplies a clock signal to the D flip-flop 120. The output signal of D flip-flop 120 is the input signal of input node 66 of exclusive OR logic gate 63. D flip-flop 11
5 and 120 are first reset in response to the SMRC,
Enable exclusive OR logic gate 63 for initialization. The output signal of the D flip-flop 120 and the output signal of the AND logic gate 110 are connected to the NAND logic gate 125
This is the input signal to.

Since the toggle command is generated during a burst read or burst write operation, the D flip-flop 115 is used to indicate that the toggle command has been input. D flip-flop 1
Reference numeral 20 denotes a D flip-flop 115 (generated by a toggle command) as an input for determining whether or not to perform a burst type inversion for a subsequent read / write operation.
Use the output of The toggle command uses the following CAS
* Affects only the next read / write operation, as defined by RC. This allows the toggle command to set the burst sequence to a full burst sequence once. The D flip-flop 115 can store the input of the toggle command from the last CAS * RC in the circuit. The D flip-flop 115 sets up a burst type for the next read / write operation during the current operation.

At the time of initialization, D flip-flops 120 and A
The output potential of both ND logic gates 110 is L level, NA
The output potential of ND logic gate 125 is at H level. When an external toggle command is input to the AND logic gate 75 of the master control circuit 37, the ITC is input to one of the inputs of the AND logic gate 105. Next, the output of the AND logic gate 105 goes high when the CLK supplied to the D flip-flop 115 goes high. D flip-flop 115 then
An H level potential is latched for the output. When a clock is supplied to D flip-flop 120, the H-level potential at output node 126 of D flip-flop 120 is transferred to the output of D flip-flop 120, and the output of exclusive OR logic gate 63 is inverted. I do. The burst type programming circuit reprograms the SARAM to the opposite operation option in response to the toggle command. Here, the H-level potential appears at both the input and the output of the NAND logic gate 125, the potential for resetting the D flip-flop 115 becomes L level, and the output node 126 of the D flip-flop 115 becomes L level potential. This state is indicated by "no pending tag
gle "state. The L-level potential of the D flip-flop output node 126 is transferred to the output of the D flip-flop 120 at the next CAS * RC input, inverting the output of the exclusive OR logic gate 63 to the original logic state, and bursting. The type programming circuit 61 programs the SDRAM to an operation state programmed at the time of initialization. SDARM retains the originally programmed operating options until the external toggle command reprograms the burst-type function again. After reprogramming the circuit of FIG. 8, the next CAS * RC input returns the burst-type functional mode to the operating mode programmed at initialization. Therefore, the value of the reprogramming of the burst type function of the SDRAM of FIG. 8 is not retained since it lasts only for one burst operation. However, the circuit can issue a reprogramming command during the execution of the burst operation. This also eliminates interruption of data flow from the SDRAM.

FIG. 12 is a timing chart showing clock cycles necessary for reprogramming the control operation function of the circuit of FIG. 8 during a write cycle.

FIG. 13 is a timing chart showing clock cycles required for reprogramming the control operation function of the circuit of FIG. 8 during a read cycle.

In the circuit shown in FIG. 9, an operation code is stored in the mode register 51 at the time of initialization.
AS * RC is given. The opcode is multiplexed from the external address bits A3 and A9 to the input of D3. As described above, the NAND logic gate 59 includes the SM
The mode register 51 is enabled by RC. Further, the output of NAND logic gate 59 controls multiplexer 149. At the time of initialization, the L level NAND gate output multiplexes the operation code of the external address A3 to the input of D3, and at the time of CAS * RC input, the H level N
The AND gate output changes the operation code of the external address A9 to D.
Multiplex to 3 inputs. SMRC directly enables all D flip-flops except D3. D3 is enabled during initialization when the SMRC is inverted by the inverter 150 connected to the input of the enabled NOR logic gate 155. NOR logic gate 155 applies the H level potential from inverter 150 to D flip-flop D3 at the time of the first SMRC input.
Is converted into an L level potential of an output for enabling. Except during the idle state, the output of NAND logic gate 59 is H
Level, and disables all D flip-flops of the mode register 51 except D3. The H level potential is inverted by the inverter 150 to enable the NOR logic gate 155. At the time of each CAS * RC input, the output potential of AND logic gate 100 is at H level. The enabled NOR logic gate 155 inverts the H level and enables D3 at each CAS * RC input. When CAS * RC is input, A9 opcode is D3
Therefore, the burst type function for each CAS * RC is determined by the value of the opcode of A9. Therefore, the circuit of FIG.
It can be reprogrammed by changing the value of the operation code of A9. The A3 opcode determines the burst type function only at initialization.

FIG. 14 is a simplified block diagram of SDRAM 200 of the present invention. The SDRAM 200 is a 2M × 8-bit memory having one memory bank 210. The memory bank has eight memory arrays. Each memory array consists of 2,097,152 bit memory storage cells for storing electronic data. The initialization / reprogramming circuit 220
At least two internal control signals generated by the control circuit 230 are received. Master control circuit 23
0 receives the memory command and generates an internal control signal, and in response to the memory command,
Control the operation of. The two internal control signals generated by the master control circuit 230 are input to an initialization / reprogramming circuit 220 which controls the initialization and reprogramming of the operation function and sets a desired operation option. The circuits and methods of this embodiment relate specifically to the initialization and reprogramming of burst-type operating functions. The first operation option selected is at least the address input pin A
It depends on the opcode or potential input from one of 0-A10.

In the SDRAM of FIG. 14, all input / output signals except for the CKE signal are synchronized with CLK. C
At the rising edge of LK, an input trigger for synchronizing the SDRAM is provided.

When the SDRAM is initialized, it can be accessed. 11 row addresses by active command
Following input of bits (A0-A11), read / wr
Each column is uniquely accessed by inputting nine column address bits (A0-A8) by the item command. When the CAS * signal is input, the actual read / write
Start access. The memory bank is an L level RA
Accessed in response to the S * signal.

FIG. 15 is a detailed circuit diagram of a part of the SDRAM of FIG. The circuit shown in master control circuit 230 is a part of the entire circuit of master control circuit 230, and is related to the circuit of the present invention. The initialization / reprogramming circuit 220 includes a mode register 250
12 D flip-flops (D0-D11)
It has. When internal control state machine 260 outputs an idle state signal from output node 265 of the internal control state machine, and when CKE signal is at H level and CS *, WE *, CAS * and RAS * signals are at L level When at the level, master control circuit 230 outputs SMRC from output node 270 of NAND logic gate 275. The internal control state machine 260 is the internal control state machine described with respect to the first three embodiments.
It is similar to the state machine 53. SMRC,
This is an enable signal input to the mode register 250 and enables all D flip-flops (D0-D11). When the D flip-flop is enabled, the potential of each address input pin A0-A10 is latched at the output node of the corresponding D flip-flop in response to the transition of the system clock to the H level.

The output signal of D3 is latched at the first input node 285 of the exclusive OR logic gate 290. Exclusive-OR logic gate 290 is configured such that input node 29
5 is enabled by the L-level potential. Therefore, the output signal of D3 is passed to the input node 300 of the burst type programming circuit 305. The burst type programming circuit 305 determines whether the sequential option or the interleave option of the burst type operation function is programmed in response to a signal input from the input node 300.

The intermediate logic circuit 307 includes a D flip-flop 310 and an AND gate 315. At initialization, D
Flip-flop 310 is reset in response to SMRC from output node 270 of NAND gate 270 and provides an exclusive OR logic gate enable signal to input node 295 of exclusive OR logic gate 290.

Unlike the previous three embodiments, which can be reprogrammed at the beginning of the read / write command, the circuit of this embodiment uses the CS * signal when the CKE, CAS * and WE signals are at the H level. And RAS *
An ARC generated when the signal is at L level and an idle state signal at output node 265 of the internal control state machine, in this case an H level is present
Can only be reprogrammed in response to AND gate 31
5 supplies an H level signal to the D flip-flop 310 in response to the ARC generated by the logic gate 316 and the H level CLK. 12 to 14, DQ indicates input / output pins for input / output data, and DQM indicates a control pin called a DQ mask. DQM is used to input a signal for controlling reprogramming of the synchronous DRAM.

When the output signal from AND gate 315 transitions to the H level, a clock is supplied to D flip-flop 310. When the signal applied to the DQM input 320 becomes the input signal to the D flip-flop 310 and is sent to the Q output connected to the input node 295 of the exclusive OR logic gate 290, the control operation function of the SDRAM is reset. Programming.

The signal value on DQM input 320 is externally controlled to reprogram the SDRAM to the desired settings. When the DQM signal is at the L level, the exclusive OR logic gate 290 remains enabled, and the SDRAM operates with the control operation option programmed at initialization. In order to program an operation option that is not selected at the time of initialization of the burst operation type function, the DQM signal must be set to an H level potential when a clock is supplied to the D flip-flop 310. Next, the H level DQM signal input to the input 320 of the D flip-flop 310 is transferred to the Q output and enters the input 295 of the exclusive OR logic gate 290. Exclusive OR logic gate 29
When an H level signal is input to the input 295 of 0, the output potential of the exclusive OR gate is inverted to the opposite logic state. Therefore, the input potential at the input node 300 of the burst type programming circuit 305 is inverted and the burst type programming circuit responds by programming the burst type function to the opposite operation option. Therefore, SDR
When the AM is initialized to the sequential burst type, the DQM signal goes high and the AND gate 31
When the clock is supplied from 5 to the D flip-flop 310, the SDRAM is reprogrammed in an interleaved burst type. When the DQM signal is at the L level, the operation option returns to the option selected at initialization in response to the active ARC.

The actual number of memory banks existing in the SDRAM of the present invention is not limited to the cited example. For example, even though the SDRAM 30 shown in FIG. 6 has two memory banks 31 and 33, the embodiment of the invention described with reference to FIG. 6 has more memory banks or one memory bank. be able to. The SDRAM 200 shown in FIG.
Although only banks, the invention described with respect to FIG. 14 can have multiple memory banks.

[0068]

According to the present invention, CAS * RC or ARC
On input, a means of reprogramming the control function into the memory device, thereby reducing the time previously required to idle the memory device to reinitialize the memory device. As described herein, the description of the present invention relates to the reprogramming of the burst type operation function of the SDRAM.
It is equally applicable to other control functions to reprogram without returning to the idle state of the RAM.
The present invention is also applicable to memory devices other than SDRAM that are initially programmed to a desired control operation function and reprogrammed during normal operation.

Many embodiments of the present invention have shown that the reprogramming circuit and method of the present invention can vary as long as the reprogramming is an actual circuit. It was also found that there are various options that can be set for reprogramming where values are retained and not retained. Therefore, the present invention should be considered limited only by the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram of an SDRAM of the present invention.

FIG. 2 is a block diagram showing a related art mode register and programming circuit.

FIG. 3 is a table showing a bit set value of a mode register for a programmable control operation function of the related art. Each table describes control operation options that can be set for each programmable control operation function, and shows the set values of the mode register necessary for selecting each control operation option.

FIG. 4 is a block diagram of a related art SDRAM.

FIG. 5 is a timing diagram showing clock cycles required for reprogramming a mode register of the related art.

FIG. 6 is a block diagram of an SDRAM of the present invention.

FIG. 7 is a block diagram showing a part of a master control circuit and an initialization / reprogramming circuit according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing a part of a master control circuit and an initialization / reprogramming circuit according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a part of a master control circuit and an initialization / reprogramming circuit according to a third embodiment of the present invention.

FIG. 10 is a detailed diagram of the logic circuit of FIG. 7;

FIG. 11 is a detailed diagram of the logic circuit of FIG. 8;

FIG. 12 is a timing diagram illustrating a clock cycle using the control operation reprogramming function of the circuit of FIG. 8 during a write cycle.

FIG. 13 is a timing diagram illustrating a clock cycle using the control operation reprogramming function of the circuit of FIG. 8 during a read cycle.

FIG. 14 is a block diagram of an SDRAM according to a fourth embodiment of the present invention.

15 is a block diagram showing a part of the master control circuit of FIG. 14 and an initialization / reprogramming circuit of the circuit of FIG. 14;

[Explanation of symbols]

3, 21, 51, 250 Mode register 5 Address bus 7, 19, 37, 230 Master control circuit 8 Programming circuit 9 Opcode 10 Burst length chart 15 Burst chart 15, 17 Bank A memory array 20 Read waiting time Chart 25 Option code chart 30, 200 SDRAM 31, 33, 210 Memory bank 35, 220 Initialization / reprogramming circuit 38, 39, 67, 90, 126, 270 Output node 53, 260 Internal control state machine 55 1 internal control state machine output node 59, 125, 275 NAND logic gate 61, 305 programming circuit 63, 290 exclusive OR logic gate 64, 65, 66, 285, 295, 300 input node 75,85,100,105,110,315,316
AND logic gate 80,307 Intermediate logic circuit 87,115,120,310 D flip-flop 95,150 Inverter 127 Negative NOR logic gate 149 Multiplexer 155 NOR logic gate 265 Internal control state machine output node 320 DQM input

────────────────────────────────────────────────── ─── Continuation of the front page (72) Scott E. Shafer United States, 83706-5280 United States, East Fairbrook Way 301, Boise, Idaho (56) References JP-A-7-93970 (JP, A) JP-A-6-275071 (JP, A) JP-A-6-76567 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/34

Claims (11)

(57) [Claims] 1. A memory device (30) comprising: a) a first command and a second command and a bank switch;
Master control circuit that receives the Tate signal (3
7) The master control circuit (37)
Indicates that the memory banks (31, 33) are in the idle state
When indicated bank state signal that the initialization signal generated in response to the first command, also Memoriba
Link is in the active state.
Generating a reprogramming signal in response to the second command when the tate signal indicates, the initialization signal and the reprogramming signal controlling programming of a control operation function of the memory device (30); b) An initialization / reprogramming circuit (35) for electrically communicating with the master control circuit (37), wherein the initialization / reprogramming circuit (35) comprises:
Controlling an initial programming of the control operation function in response to the initialization signal; and controlling reprogramming of the control operation function in response to the reprogramming signal, the control operation function comprising a plurality of control operation options. Wherein the memory device (30) initially operates according to a first one of the control operation options, and after reprogramming, operates according to a second one of the control operation options. and, c) provided with the master control circuit (37) with the memory bank to be electrically exchanges (31, 33),
It said memory device (30), when said memory banks (31, 33) is in the active state, prior Symbol first
Memory device reprogrammed from the second control operation option to the second control operation option. 2. The memory device according to claim 1, wherein
0) The memory device according to 0), wherein the first command and the second command are different. 3. The memory device (3) according to claim 1,
0), the first command and the second command comprise a plurality of input signals, and at least one of the input signals of the first command corresponds to one of the input signals of the second command. A memory device characterized by being different. 4. The memory device according to claim 1, wherein
In 0), the first command is an external SMRC. 5. The memory device according to claim 1, wherein
0), the second command is CAS * RC (c
column address strobebergis
transition command) and ARC (acti
A memory device selected from a group of commands consisting of (low command). 6. A method for programming a control operation function of a memory device (30) comprising a plurality of memory banks (31, 33), comprising: a) the plurality of memory banks (31, 33) being inactive ; When an external command indicates a programming state,
To have the first operation option of the control operation function.
Programming a memory device (30) ; b) BA (bank) capable of activating at least one of said plurality of memory banks (31, 33)
(c) generating an activate command signal; c) if the BA signal is present and the external command is re-executed;
Memory device (30) to have a second operation option of a control operation function when indicating a programming state;
Method of programming a control operation function of the memory device (30), characterized in that it comprises a step of reprogramming. 7. The memory device according to claim 6, wherein
0) a method of programming a control operation function of: a) generating a control signal that can have a first logic state and a second logic state; b) a first input of a multiplexer circuit (149). Providing a first information bit to a node; c) providing a second information bit to a second input node of the multiplexer circuit (149); d) the first logic of the control signal. In response to a condition, the first information bit is transferred to the multiplexer circuit (14).
9) multiplexing to the output node of e) multiplexing the second information bit to the multiplexer output node in response to the second logic state of the control signal; Latching said first information bit at a latch output node in response to said first logic state of said control signal during a step of programming; and g) said step of re-programming said control signal during said reprogramming step. Latching the second information bit at the latched output node in response to a second logic state.
How to programming the control operation function of 0). 8. The memory device according to claim 7, wherein
0) a method of programming a control operation function, comprising: a) determining the first operation option from a logical state of the first information bit; and b) determining the first operation option from a logical state of the second information bit. Determining an operation option of the second memory device (3).
How to programming the control operation function of 0). 9. The memory device according to claim 6, wherein
0) In the method of programming a control operation function of 0), the step of programming comprises the step of responsive to an information bit appearing on an address pin when all of the plurality of memory banks (31, 33) are inactive, A method of programming a control operation function of a memory device (30), comprising the step of programming (30). 10. The memory device (3) according to claim 9,
0) The method of programming a control operation function of 0), further comprising inverting a signal input to a programming circuit (61) to perform the reprogramming.
How to programming the control operation function of. 11. The memory device according to claim 6, wherein
0) The method of programming a control operation function according to 0), further comprising, after the reprogramming step, resetting the second operation option to the first option. how to programming the control operation function of.