JP3250468B2 - OSD circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OSD (On Screen
n Display) circuit, and particularly to an OSD circuit applicable when a main screen signal is obtained as a digital signal.

[0002]

2. Description of the Related Art Conventionally, this kind of OSD circuit is used for displaying a main screen of a TV or the like on a graphics screen of characters, pictures, figures, or the like.

For example, Japanese Patent Laid-Open Publication No. Hei 5-127039 (hereinafter referred to as Prior Art 1) describes a subcode graphics decoder capable of superimposing or overlaying graphics on a relatively simple TV screen. I have.

FIG. 9 is a simplified block diagram of the sub-code graphics decoder described in the prior art 1. The illustrated sub-code graphics decoder includes a disc player 30, a graphic command interpreter 31, an address calculator 37, and a V-RAM 39.
, A selector 40, a CULT RAM 41, and a TULT
It has a RAM 42, a D / A converter 45, a matrix circuit 47, an encoder 48, a mixer 49, a CRT display 55, a selection switch 56, a coincidence signal generation circuit 57, and a color setting circuit 61. The mixer 49
ATTs 50 and 51 and an inverter 52 are provided.

In this configuration, a graphic screen created by a graphic command also recorded on the disc is superimposed on the main screen recorded on the disc and output.

Prior Art 1 discloses a CLUT RAM 41 and T
It has two look-up tables in the LUT RAM 42, controls the mixer 49 by referring to them, switches the video signal of the main screen and the video signal of the graphics screen, or superimposes by mixing at a certain ratio. Alternatively, an overlay is performed.

Japanese Patent Application Laid-Open No. 2-87886 (hereinafter referred to as Prior Art 2) discloses a pair of a video signal on the main screen side, a first chroma signal whose amplitude is controlled to be constant, and a time on the sub-screen side. A "screen combining circuit" has been disclosed in which a pair of an axis-compressed video signal and a second chroma signal is switched and combined to eliminate unnaturalness due to various video control variables during two-screen combining. . The screen synthesizing circuit disclosed in Prior Art 2 includes an automatic color level control circuit that controls a color level of a signal output from a main screen video signal input terminal through a band-pass filter to create a first macro signal. And an encoder for creating a second chroma signal from the video signal input from the sub-screen video signal input terminal and compressed on the time axis. The screen combining circuit has a screen combining switch for switching and combining a pair of the video signal and the first chroma signal on the main screen and a pair of the compressed video signal and the second chroma signal on the sub-screen. .

Further, in Japanese Patent Application Laid-Open No. 64-57382 (hereinafter referred to as Prior Art 3), different values are set in each of look-up tables (LUTs) storing color data. Thus, a “mask display processing method” has been disclosed in which a normal image portion and a mask portion can be easily distinguished by a difference in color. Prior art 3
, The data of the image memory is 8 bits, and the data of the overlay memory is “1” (mask pattern portion) or “0” (other portions). The selecting means is an inverter. The output of the overlay memory inverted by the inverter is input to the first LUT as a control input, and the output of the overlay memory is input to the second LUT as a direct control input. ing.
The first and second LUTs are selected when the control input is "1", and are not selected when the control input is "0". Therefore, the second LUT is selected in the mask pattern portion,
Otherwise, the first LUT is selected.

[0009]

The above-mentioned OSD circuit of the prior art 1 has the following problems.

The first problem is that the expressive power is poor. The reason is that the method of superimposing the main screen and the graphics screen is merely a superimposition or an overlay with a variable transparency.

A second problem is that the circuit scale becomes very large if various types of expressions can be performed. The reason is that the superimposition processing of the main screen and the graphics screen is performed by switching the signals of both screens or changing the mixing ratio in the state of an analog video signal such as NTSC. This is because it is necessary to synchronize not only the vertical synchronization signal and the horizontal synchronization signal of both screens but also the color subcarriers.
In addition, since superimposition processing that is not so complicated cannot be performed with a video signal such as NTSC, it is once decoded into a signal for each component such as a YCrCb signal or an RGB signal, and after superposition processing for each component, the composite video is again processed. This is because the signal must be encoded.

A third problem is that it is not suitable for video equipment that is being digitized. The reason for this is that, if both the main screen and the graphics screen are converted from digital signals into analog signals and then superimposed, a plurality of D / A converters and encoders are required, which increases the circuit scale. is there.

Accordingly, it is an object of the present invention to provide an OSD circuit capable of expressing various kinds of signals when a main screen signal is obtained as a digital signal.

It is another object of the present invention to provide an OSD circuit which can perform different superposition processes with a single circuit.

Another object of the present invention is to provide an OSD circuit having a small circuit size.

The prior art 2 aims at eliminating unnaturalness at the time of color adjustment or the like in picture-in-picture, and is not related to the object of the present invention. Also,
Prior art 3 is a technical idea that allows a mask pattern portion to be easily distinguished from other image portions, and is different from the present invention in which various types of expressions are possible.

[0017]

In order to solve the above-mentioned problems, the OSD circuit of the present invention superimposes a main screen signal and a graphic screen signal as digital signals.

As the main screen signal, an input vertical synchronizing signal, an input horizontal synchronizing signal, main screen data, and a clock signal are input.

Also, a graphics memory for holding graphics screen data, a rewritable look-up table for superimposing main screen data and graphics screen data, and an external CPU Then, the graphics screen data is written into the graphics memory, and the result of performing the desired superimposition processing on the input data is written into the address corresponding to the input data in the lookup table.

In order to access different addresses of the look-up table for each component, a different superposition process can be performed for each component of main screen data in which each component such as YCrCb is time-division multiplexed. An access control circuit that controls access to the graphics memory and the look-up table from the bit counter and external CPU so as not to interfere with access to the graphics memory and the look-up table from a display system such as a read control circuit. A delay circuit for delaying and outputting the input vertical synchronizing signal and the input horizontal synchronizing signal of the main screen data by the number of clocks required for the screen superimposing process;
It is characterized by having.

[0021]

Since the graphics memory is provided, not only characters but also bitmap information such as figures and pictures can be superimposed on the main screen data.

Since the contents of the superposition processing are determined by the contents of the look-up table, the contents of the look-up table can be rewritten by an external CPU or the like.
The contents of the overlay processing (overlay, mask, monochrome, emphasis, etc.) can be changed without changing the circuit. Also, the distribution of the number of bits in the memory for one dot of graphics memory (how many bits are used for specifying color, how many bits are used for specifying transparency, how many bits are used for mask, etc.) and format (Such as whether to use the RGB format, the pallet code format, or which bits to use for the graphics data format) can be freely changed, so that a single circuit can be used for various types of superposition. Can express and increase the freedom of expression.

By performing the superposition processing using a look-up table, a large number of high-speed adders and multipliers for performing various types of superposition processing by hardware become unnecessary, so that the circuit scale can be reduced. Therefore, cost can be reduced.

By providing a 2-bit counter for treating main screen data in a time-division multiplexed manner using components such as YCrCb and RGB, the bus width of the main screen data can be reduced to 1/2.
Since it can be reduced to 1/3, the memory size of the look-up table can be significantly reduced, and the number and terminals of ICs can be reduced and the circuit board can be downsized. Therefore, cost can be reduced.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an OSD according to an embodiment of the present invention.
1 shows a circuit. The illustrated OSD circuit 100 includes a delay circuit 20.
0, a read control circuit 300, a graphics memory 400, a look-up table (LUT) 500, a 2-bit counter 600, and an access control circuit 700. Also, the OSD circuit 100 has an external CP.
U800 is connected.

The delay circuit 200 is supplied with an input vertical synchronizing signal 110, an input horizontal synchronizing signal 120, and a clock signal 140 for the main screen. The delay circuit 200 delays the input vertical synchronization signal 110 and the input horizontal synchronization signal 120 by the same number of clocks as the number of clocks required for the superimposition processing of the main screen and the graphics screen, and outputs the output vertical synchronization signal 11.
1 and an output horizontal synchronization signal 121. The delay circuit 200 can be composed of shift registers 201 to 208 of the number of stages corresponding to the number of clocks to be delayed.

FIG. 2 shows an example of the configuration of the delay circuit 200 when the delay time is equivalent to four clocks. Delay circuit 20
0 is composed of two shift registers, one is a four-stage shift register composed of four flip-flops (FF) 201 to 204, and the other is composed of four flip-flops (FF) 205 to 208. This is a four-stage shift register. The input vertical synchronization signal 110 is delayed by four clocks by one of the shift registers 201 to 204 and output as an output vertical synchronization signal 111. The input horizontal synchronization signal 120 is delayed by four clocks by the other shift registers 205 to 208 and output as an output horizontal synchronization signal 121.

The delay time can be changed by changing the number of stages of the shift register, that is, the number of flip-flops constituting the shift register. At this time, in general, the number of stages of the shift register for delaying the input vertical synchronization signal 110 is equal to the number of stages of the shift register for delaying the input horizontal synchronization signal 120. However, it is also possible to change the phase difference between the output vertical synchronization signal 111 and the output horizontal synchronization signal 121 by intentionally making them different.

The delay circuit 200 can also be constituted by a FIFO memory. However, the delay circuit 200
Since it is only delayed by at most a few clocks, a shift register is more advantageous in terms of circuit size than a FIFO memory.

The read control circuit 300 is supplied with an input vertical synchronizing signal 110, an input horizontal synchronizing signal 120 and a clock signal 140 for the main screen. Read control circuit 30
0 is the input vertical synchronization signal 110 and the input horizontal synchronization signal 12
In synchronization with 0 and the clock signal 140, a read address 310 of the graphics memory 400, an access permission signal 320, and a reset signal 330 of the 2-bit counter 600 are generated and output.

FIG. 3 shows a configuration example of the read control circuit 300. The read control circuit 300 includes a blanking signal generation circuit 301, a reset signal generation circuit 302, and a counter 303.

The input vertical synchronizing signal 110, the input horizontal synchronizing signal 120 and the clock signal 140 are supplied to the blanking signal generating circuit 301. The blanking signal generation circuit 301 generates a vertical blanking signal indicating a blanking period and a horizontal blanking signal from the input vertical synchronization signal 110 and the input horizontal synchronization signal 120, and performs a logical sum of the two blanking signals, That is, the composite blanking signal is output as the access permission signal 320.

The reset signal generation circuit 302 includes:
An input vertical synchronization signal 110, an input horizontal synchronization signal 120, and a clock signal 140 are supplied. The reset signal generation circuit 302 determines the field of the interlaced main screen from the phase difference between the input vertical synchronizing signal 110 and the input horizontal synchronizing signal 120. At the beginning of the first field, the counter 303 and the 2-bit counter 600 The counter reset signal 330 is generated and output so that is reset.

The counter 303 is a reset signal generating circuit 3
02 is a counter that is reset at the beginning of the first field of the main screen by the counter reset signal 330 output by the counter 02 and counts up by the clock signal 140 up to the beginning of the first field of the next frame of the main screen. The read address 310 for reading the memory 400 is output as a read address.

The graphics memory 400 has a read address 310 output by the read control circuit 300.
And a clock signal 140 which is a data clock of the main screen. The graphics memory 400 outputs the graphics screen data 410 stored at the address specified by the read address 310 in synchronization with the clock signal 140. The graphics memory 400 is connected to the address bus 720 and the data bus 730 of the access control circuit 700 when the graphics memory access control signal 710 of the access control circuit 700 is supplied. The graphics memory 400 includes an external CPU 800 without interrupting display access from the read control circuit 300.
Read / write access from

FIG. 4 shows an example of the configuration of the graphics memory 400. The graphics memory 400 includes a selector 401, a RAM 402, and a flip-flop (FF) 4
03 and a bus transceiver 404.

The selector 401 is connected to the read control circuit 30
A read address 310 output by the access control circuit 700 and an address on the address bus 720 output by the access control circuit 700 are selected based on a graphics memory access control signal 710 output by the access control circuit 700;
The address is given to the RAM 402. Selector 401
Usually selects the read address 310 and sends the
Address bus 7 only when access from 00 is performed
Select the address on 20.

The RAM 402 is a RAM having a required capacity and a data bus width.
The graphics screen data written through “0” is stored. For example, when using 1 byte per pixel on a screen with a resolution of 720 pixels x 480 pixels,
The minimum required RAM capacity of the RAM 402 is 720 × 48
0 × 1 = 345600 bytes.

The flip-flop 403 is connected to the RAM 402
Is a kind of register composed of the same number of flip-flops as the number of bits of the data bus of FIG. The data held in the flip-flop 403 is normally updated every clock of the clock signal 140, but the CPU 800
When the access is performed from, the update is stopped during the period by the graphics memory access control signal 710. Since the access from the CPU 800 is performed during the blanking period based on the access permission signal 320, there is no problem even if the updating of the graphics screen data 410 is stopped.

The bus transceiver 404 is connected to the data bus 7
This is a bidirectional tri-state buffer between the data bus 30 and the data bus of the RAM 402. Bus transceiver 404
Is the graphics memory access control signal 710
This controls the input / output direction and the high impedance state to prevent signal collision. That is, the bus transceiver 404 sets the R
The data bus of the AM 402 and the data bus 730 are connected, and the data bus of the RAM 402 and the data bus 73 are normally connected.
It is controlled to be in a high impedance state in order to disconnect 0.

The look-up table 500 is composed of the main screen data 130, the graphics screen data 410 output from the graphics memory 400, and the 2-bit counter 6.
00 and a clock signal 140 which is a data clock for the main screen. The look-up table 500 uses the main screen data 130, the graphics screen data 410, and the output 610 of the 2-bit counter 600 as read addresses, and calculates the desired superimposition processing result stored at that address into the composite screen data 131. Output as Look-up table 5
00 indicates that the LUT access control signal 740 of the access control circuit 700 is supplied and the access control circuit 70
0 is connected to the address bus 720 and the data bus 730. The lookup table 500 allows read / write access from an external CPU 800 without interfering with display access.

FIG. 5 shows an example of the configuration of the lookup table 500. The lookup table 500 has the same configuration as the graphics memory 400 and performs the same operation. That is, the lookup table 500 includes the selector 501, the RAM 502, and the flip-flop (FF) 5
03 and a bus transceiver 504.
The difference from the graphics memory 400 is that the read address 310 in the graphics memory 400 is different.
In place of the main screen data 130
And the graphics screen data 410 and the output 610 of the 2-bit counter 600 are combined and input as an address. Also, the selector 501, R
The bus width of the AM 502, the flip-flop 503, the bus transceiver 504, and the like are generally different from those of the graphics memory 400.

If it is not necessary to change the superimposition processing by software, R
OM can be used. In that case, the CPU 800
Lookup table 5
00 can be made smaller.

The 2-bit counter 600 is supplied with a main screen data clock (clock signal 140) and a counter reset signal 330 output from the read control circuit 300. The 2-bit counter 600 accesses different addresses of the lookup table 500 for each component in order to perform different superposition processing for each component of main screen data in which components such as YCrCb are time-division multiplexed. Thus, two bits of the read address of the lookup table 500 are generated and output as the output 610 of the two-bit counter 600. More specifically, 2
The bit counter 600 indicates that the main screen data 130 is YCr
In the case of Cb = 4: 2: 2, it is configured as a 2-bit quaternary counter.

The access control circuit 700 is connected to the read control circuit 300, the graphics memory 400, the look-up table 500, and the external CPU 800. The access control circuit 700 does not interrupt access to the graphics memory 400 and the look-up table 500 from the display system for display, and allows the external C
Control is performed based on the access permission signal 320 output from the read control circuit 300 so that the PU 800 can perform read / write access to them.

FIG. 6 shows a configuration example of the access control circuit 700. The access control circuit 700 includes first to third latches 701, 702, 703, and an address decoder 704.
, Access control signal generation circuit 705 and selector 70
6 is comprised.

The first latch 701 is a transparent latch, and the second and third latches are 702 and 70.
Reference numeral 3 denotes a tri-state output transparent latch. The first latch 701 is located between the address bus of the CPU 800 and the address bus 720. Also the second
Latch 702 and third latch 703 are inserted between the data bus of CPU 800 and data bus 730, and
Constitute a bidirectional latch. This is because the transparent state and the high impedance state of the three latches 701 to 703 are determined by the access control signal generation circuit 7.
05.

The address decoder 704 decodes an address to be accessed by the CPU 800, determines whether the address is to access the graphics memory 400 or the look-up table 500, and controls the selector 706 accordingly.

The access control signal generation circuit 705 includes a CP
The CPU 800 sends the graphics memory 40
0 or a control signal for accessing the lookup table 500 is created. If the access permission signal 320 indicates access permission when attempting to access from the CPU 800, the access control signal generation circuit 7
In step 05, the three latches 701 to 703 are controlled to be transparent or high impedance, and are accessed as they are. If the access permission signal 320 indicates that access is prohibited, the access control signal generation circuit 705
Addresses and data are latched in the three latches 701 to 703, and access is performed in place of the CPU 800 when access is permitted. If there is a next access from the CPU 800 before the proxy access ends, the access control signal generation circuit 705 returns a signal indicating that the CPU 800 is in a wait state or an access disable state.

The selector 706 controls the graphics memory 4 generated and output by the access control signal generation circuit 705.
00 or a control signal for accessing the look-up table 500 is switched to either the graphics memory 400 or the look-up table 500 in accordance with the output of the address decoder 704. 71
0 or lookup table access control signal 740
Output as

An externally connected CPU 800 generates graphics screen data and writes it to the graphics memory 400, calculates the desired result of the superposition process and writes it to the lookup table 500, or And performs processing for a user operation of a device in which the OSD circuit according to the present invention is incorporated.

Next, the operation of the OSD circuit according to the embodiment of the present invention shown in FIG. 1 will be described.

FIG. 7 shows an example of the format of the main screen data 130. In FIG. 7, (A) shows the clock signal 1
40 and (B) show the main screen data 130. In the main screen data 130, it is assumed that YCrCb = 4: 2: 2 format data is time-division multiplexed as shown in FIG. 7B. Here, the YCrCb = 4: 2: 2 format means that for the luminance component (Y), one piece of data is written for one dot.
For the color difference components (Cr, Cb), only one data is used for each two dots. Each component includes an input vertical synchronization signal 110 and an input horizontal synchronization signal 1
With reference to 20, it is possible to identify the number of clocks from the reference. For example, in FIG. 7B, the data described as Y _{n + 2} is the data of the Y component of the pixel at the (n + 2) -th dot from the reference, and the data described as Cr _{n + 2} is from the reference ( This is the data of the Cr component of the pixels at the (n + 2) -th and (n + 3) -th dots.

FIG. 8 shows an example of the superposition operation of the OSD circuit 100 shown in FIG. In FIG. 8, (A) shows the clock signal 140, (B) shows the main screen data 130,
(C) shows the graphics screen data 410, (D) shows the output 610 of the 2-bit counter 600, and (E) shows the composite screen data 131. The OSD circuit 100 operates in synchronization with the clock signal 140 of the main screen.

The read control circuit 300 receives the input vertical synchronizing signal 110 and the input horizontal synchronizing signal 12 of the main screen.
Based on 0, a read address 310 of the graphics memory 400 is generated and output so that the first pixel data of the main screen matches the first pixel data of the graphics screen. Also, the 2-bit counter 60
A count reset signal 330 for resetting the 2-bit counter 600 is generated and output so that the value of 0 correctly corresponds to each YCrCb component of the main screen data 130.
Further, the read control circuit 300 includes an external CPU 800
For example, an access permission signal 320 for permitting access to the graphics memory 400 and the lookup table 500 is generated and output in the next clock cycle. The access permission signal 320 is used to read the graphics memory 400 from the read control circuit 300 which is a display system in order to prevent the display of the screen from being disturbed.
Used for arbitration to give priority to reading and writing from 0.

In the 2-bit counter 600, the value of the output 610 of the 2-bit counter 600 and each component of the time-division multiplexed YCrCb of the main screen data 130 are always set in advance by the counter reset signal 330 output from the read control circuit 300. The clock signal 140 is initialized so as to correspond as determined, and the clock signal 140 is counted. In FIG. 8, as shown in FIGS. 8B and 8D, the Cb component corresponds to 0, the subsequent Y component corresponds to 1, the Cr component corresponds to 2, and the subsequent Y component corresponds to 3, It need not be the same as this example. The output 610 of the 2-bit counter 600
Is used as a part of an address for referring to the lookup table 500, and Cb of the main screen data 130 is
By referring to different addresses in the look-up table 500 for each component of YCr, different superposition is performed on each component. Thereby, for example, processing such as monochrome conversion and luminance enhancement can be performed.

The graphics memory 400 uses the read address 310 output by the read control circuit 300 as the address of the RAM 402, and outputs the data stored at that address as graphics screen data 410. As shown in FIG. 8C, unlike the main screen data 130, the graphics screen data 410 is not time-division multiplexed for each component. Therefore, since the period of one pixel is a period of two clocks of the clock signal 140, the graphics screen data is read at the first clock, and the read data is held by the next read flip-flop 403 or latch. The second clock is used when the external CPU 800 does not access the graphics memory 400 through the access control circuit 700, so that the graphics screen can be updated faster than in the case where only the blanking period of the main screen is accessed. .

In this case, the read address 310 used as the address of the RAM 402 and the address bus 720
Is switched according to a graphics memory access control signal 710 output from the access control circuit 700.

The look-up table 500 uses the main screen data 130, the graphics screen data 410, and the output 610 of the 2-bit counter 600 as a memory address, and stores the components of the main screen data 130 and the graphics screen in the address. The result of performing the desired overlay processing operation is calculated and stored in advance in the data 410. When displayed, look-up table 500
Are the main screen data 130 and the graphics screen data 4
The 10 and the output 610 of the 2-bit counter 600 are combined into an address, the content stored at that address is read, held by the flip-flop 503 or a latch, and output as the composite screen data 131. RA is used as a memory for storing the operation result of the superposition processing.
If M502 is used, various superposition processes can be realized by a single circuit by rewriting the contents. Further, by performing calculation and rewriting of the result of the superposition processing by the external CPU 800, a change of the superposition processing can be realized only by software, and a change during operation is also possible. However, as shown in FIG.
Since the period of one pixel corresponds to the period of one clock of the clock signal 140 like the main screen data 130, the access from the external CPU 800 cannot be performed during the display period like the graphics memory 400. Only possible during the blanking period. At that time, as in the case of the graphics memory 400, the main screen data 130, the graphics screen data 410, and the output 61 of the 2-bit counter 600 are used as the addresses of the RAM.
Switching between the address bus 720 and the address bus 720 is performed according to the LUT access control signal 740 output from the access control circuit 700.

The access control circuit 700 controls access from the external CPU 800 to the graphics memory 400 and the lookup table 500 based on the access permission signal 320 output from the read control circuit 300.
Control so as not to disturb the screen by obstructing access for display. The access permission signal 320 indicates whether each of the graphics memory 400 and the look-up table 500 can be accessed in the next clock cycle. When there is a read / write access from the CPU 800 to the graphics memory 400 or the lookup table 500, the access is controlled by the access control circuit 700 by the access permission signal 32.
Based on 0, execute in an accessible clock cycle and return the result to CPU 800. This is CPU80
This is because the clock source (not shown) of 0 is different from the clock signal 140 of the main screen data 130 which is the master clock of the OSD circuit 100, and operates asynchronously with the OSD circuit 100.

The delay circuit 200 receives the input vertical synchronizing signal 11
0 and the input horizontal synchronizing signal 120 are delayed by the number of clocks required for superimposing the main screen and the graphics screen, and the phase relationship between the two synchronizing signals and the screen data is made the same before and after the superimposition. The delayed synchronization signals are output as an output vertical synchronization signal 111 and an output horizontal synchronization signal 121, respectively. For example, in the case of the operation shown in FIG.
Is not required. However, when realizing this, the graphics memory 400 or the lookup table 50 is required.
A very high-speed memory is required for the 0 memory, which is expensive. In order to be able to use an inexpensive and relatively low-speed memory, the processing may be pipelined. In that case, however, a delay of the number of clocks corresponding to the number of stages of the pipeline is inserted. Give a number delay.

The CPU 800 connected to the outside of the OSD circuit 100 not only controls the OSD circuit 100 but also
It can also be used for controlling devices in which the OSD circuit 100 is incorporated. CPU 800 calculates graphics screen data, and includes an attached ROM based on a user operation.
It is generated by some means, such as stored in the memory, and written into the graphics memory 400 through the access control circuit 700. In addition, the CPU 800 calculates a desired result of the superimposition process for all possible values of the main screen data 130 and the graphics screen data 410, and writes the result to the corresponding address of the lookup table 500 through the access control circuit 700.

For example, the main screen data 130 is connected to bits 8 to 8 of the address bus of the look-up table 500 with an 8-bit width, and the graphics screen data 410 is connected to the bits of the address bus of the look-up table 500 with a 6-bit width. 7 to bit 2 and the output 610 of the 2-bit counter 600 is connected to bits 1 to 0 of the address bus of the look-up table 500. The correspondence between the value of the output 610 of the 2-bit counter 600 and each YCrCb component of the main screen data 130 is the same as in FIG. Lookup table 50
The data width of 0 is the same as the data width of the main screen data 130.
Bit. In the superimposition processing, when the graphics screen data 410 is 0, the main screen data 130 at the corresponding position is monochrome. When the graphics screen data 410 is other than 0, the main screen data 13
It is assumed that 0 is output as it is.

In this case, the contents to be written in the look-up table 500 are determined by setting the lower 8 bits of the address of the look-up table 500 to “00000000” or “00”.
The address which becomes "000010", that is, the address referred to when the graphics screen data 410 is 0 and the main screen data 130 is a Cb or Cr component, is 12 addresses.
8, and the other addresses can be realized by using the upper 8 bits of the address, that is, the value of the main screen data 130 when the address is referred to.

[0066]

The present invention has the following effects. The first effect is that the expressive power is high. The reason is that various types of superposition processing can be performed.

A second effect is that various types of screen superimposition processing can be performed with a relatively simple circuit. The reason is that, for all possible values of the main screen data and the graphics screen data, the calculation of the superposition processing is performed in advance by software by the CPU, and the result is stored in a look-up table, and when the display is performed, the main screen is displayed. This is because hardware such as an arithmetic unit such as an adder and a multiplier is not required because the superposition processing is executed by referring to the look-up table using data, graphics screen data, and the like as addresses. Further, since the superposition processing can be changed by changing the value stored in the look-up table, a single circuit can be used for a plurality of superposition processing by rewriting at any time by the CPU or the like.

The third effect is that the capacity of the lookup table can be reduced. The reason is that the data width of the main screen data is reduced from 前 to の before the time division multiplexing by handling the components such as YCbCr of the main screen data by time division multiplexing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an OSD circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a delay circuit used in the OSD circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a read control circuit used in the OSD circuit shown in FIG.

FIG. 4 is a block diagram showing a configuration of a graphics memory used in the OSD circuit shown in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a look-up table (LUT) used in the OSD circuit shown in FIG.

FIG. 6 is a block diagram showing a configuration of an access control circuit used in the OSD circuit shown in FIG.

FIG. 7 is a timing chart showing an example of a format of main screen data supplied to the OSD circuit shown in FIG.

8 is a timing chart showing an example of an operation of superimposing main screen data and graphics screen data in the OSD circuit shown in FIG.

FIG. 9 is JP-A-5-127639 (prior art 1).
2 is a simplified block diagram showing a sub-code graphics decoder described in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 OSD circuit 110 input vertical synchronization signal 111 output vertical synchronization signal 120 input horizontal synchronization signal 121 output horizontal synchronization signal 130 main screen data 131 composite screen data 140 clock signal 200 delay circuit 300 read control circuit 310 read address 320 access permission signal 330 counter Reset signal 400 Graphics memory 410 Graphics screen data 500 Look-up table (LUT) 600 2-bit counter 610 2-bit counter output 700 Access control circuit 710 Address bus 730 LUT access control signal 800 CPU

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 5/377 H04N 9/74 H04N 5/278 G09G 5/00 555P 9/74 5/36 520N (58) Fields surveyed (Int. .Cl. ⁷ , DB name) H04N 5/45 G09G 5/00 G09G 5/00 510 G09G 5/06 G09G 5/18 G09G 5/377 H04N 5/278 H04N 9/74

Claims (7)

(57) [Claims] 1. A graphics screen data (410)
Memory means for storing and rewritable graphics
(400);Each component of main screen data time-division multiplexed for each component
Counter circuit (60) that outputs a value corresponding to
0) and; Said Main screen data (130) and the graphics screen
For all possible combinations of values with data
The result of the calculation of the desired overlay processing is
The surface data is stored as an address,
Main screen data and the graphics screen dataAnd said
The output of the counter circuitWith the address as the address
Lookup table means (500) for obtaining; input of the main screen data; input of vertical synchronization signal (110);
The horizontal synchronizing signal (120) and the clock signal (140)
Based on the read address of the graphics memory means.
A dress (310), an access permission signal (320),
The components of the main screen data and thecounterOutput value ofWhenIs positive
The aboveCounter circuitReset
Read to output the counter reset signal (330)
Control means (300); for receiving the access permission signal,
Access between the memory means and the look-up table means
Access control means (700) for controlling the input vertical synchronizing signal and the input horizontal synchronizing signal,
The overlap between the main screen data and the graphics screen data
Delay by the number of clocks required for joining processing and output
Delay means for outputting a vertical synchronization signal and an output horizontal synchronization signal
An OSD circuit comprising: (200); 2. The OSD circuit according to claim 1, wherein the graphics screen data is a character, a picture, a graphic, or the like. 3. The OS according to claim 1, wherein the plurality of components include a luminance component Y and two color difference components Cr and Cb.
D circuit. 4. The OSD of claim 1, wherein said plurality of components comprises a red component R, a green component G, and a blue component B.
circuit. 5. The OSD circuit according to claim 1, wherein said access control means controls said graphics memory means and said look-up table means with a display system prior to an external access. 6. The OSD circuit according to claim 1, wherein said look-up table means uses a RAM for storage. 7. The OSD circuit according to claim 1, wherein said look-up table means uses a ROM for storage.