JP3240367B2 - Active matrix type liquid crystal image display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display.

[0002]

2. Description of the Related Art A conventional technique for an active matrix type liquid crystal image display device will be described with reference to FIG. In this device, a plurality of data signal lines y1 to ym and a plurality of scanning signal lines x1 to xn are arranged in a matrix. The scanning driver 8 supplies a scanning signal to each of the scanning signal wirings x1 to xn to drive them. The data driver 9 supplies a video signal as a display data signal to each of the data signal lines y1 to ym to drive them. The plurality of data signal lines y1 to ym and the plurality of scanning signal lines x1 to xn are arranged on a panel A, which is a liquid crystal image display unit in which a plurality of pixels are arranged in a matrix.

A pixel transistor 10 (hereinafter, simply referred to as a transistor 10) which is turned on in response to an active scanning signal applied to a gate electrode is provided at each of the intersections of these signal lines. Each of the gate electrodes of each transistor 10 is individually connected to the corresponding scanning signal wiring x1 to xn. Each source electrode of each transistor 10 is individually connected to the corresponding data signal wiring y1 to ym.

Each of the drain electrodes of each transistor 10 is individually connected to a pixel electrode in a corresponding pixel 12. Each pixel 12 is composed of a pixel electrode, a counter electrode that is a transparent electrode, and a liquid crystal portion sandwiched between these two electrodes. The counter electrode of each pixel 12 is driven by a common signal COM commonly supplied from a counter electrode driving circuit 13 (hereinafter simply referred to as a driving circuit) via a counter bus line 11. A liquid crystal material for display is sealed in the liquid crystal portion sandwiched between each pixel electrode and the counter electrode in each pixel 12. Each of these pixels 12
Among them, P1 and P2 are typically denoted by different reference numerals for the sake of description, and the pixels P1 and P2 are arranged at positions where the data signal wiring y1 intersects with the scanning signal wirings x1 and x2, respectively. ing.

[0005] As shown in FIG.
The control circuit 7 supplies an inverted signal FRP that is inverted every horizontal cycle (1H). The inversion signal FRP is the driving circuit 1
3. After the AC adjustment and DC adjustment within 3, the common signal C
Output as OM. The common signal COM is a pulse alternating current in which the DC signal is inverted to a potential lower than the DC DC level by AC and a potential higher by AC than the DC DC level every horizontal period.

FIG. 13 is a diagram showing a timing at which a display video signal is written to the pixel 12 together with a scanning signal. FIG. 13A shows a data signal line y from the data driver 9.
13 shows a waveform of a video signal supplied to the counter 1, and FIG. 13B shows a waveform of a common signal COM supplied from the drive circuit 13 to the counter electrode in the pixel 12 via the bus line 11. The video signal and the common signal COM are 1
The polarity is inverted every H. FIGS. 13C to 13F respectively show scanning signal wirings x1, x2, x
, Xn supplied to the scanning signals x1, x, respectively.
2, x3,..., Xn. FIG. 13G shows the voltage difference between the source and drain electrodes of the transistor 10 in P1 of the pixel 12 in FIG. 11 by oblique lines.

FIG. 13g will be briefly described. During the first 1H, a video signal is supplied as a display data signal from the data signal wiring y1 to the source electrode of the transistor 10 corresponding to the pixel P1. In the first half TH1 of this 1H, the high level, that is, the active scanning signal x1 of FIG. 13C is supplied to the gate electrode of the transistor 10 via the scanning signal wiring x1. As a result, the transistor 10 corresponding to the pixel P1 is turned on. Therefore, in the first half period TH1, the liquid crystal portion in the pixel P1 in which the pixel electrode is connected to the drain electrode of the transistor 10 serves as a liquid crystal capacitor from the data signal line y1. A video signal is written.

In the second half TH1 of 1H, the level of the scanning signal x1 supplied to the scanning signal wiring x1 becomes low level, that is, non-active, so that the transistor 10 corresponding to the pixel P1 is turned off and the transistor 10 has high impedance. The potential of the pixel electrode is maintained at the level of the first half period Tl. The transistor 10 is also OFF after the period TH3 in the next 1H. In this case, the pixel P1
The potential of the common signal COM applied to the opposite electrode is 1H
Therefore, the potential of the pixel electrode of the pixel P1 varies with the same amplitude potential as the potential of the common signal COM. This is the lower half of the waveform shown by the dotted line in FIG. 13g. The waveform of the lower half dotted line also corresponds to the waveform of the drain potential in the transistor 10.

The upper half waveform shown by the solid line in FIG. 13g is the video signal on the data signal line y1, that is, the potential of the source electrode of the transistor 10.
Is the potential difference between the waveforms of the dotted line and the solid line, that is, the total amplitude of the video signal and the common signal COM, which is shown by oblique lines in FIG. 13G.

As described above, the scanning signal x1 is active at a high level during the first half period TH1 in this example and the transistor 10 becomes 0N in the first half period TH1. However, the scanning signal x1 remains at the low level during one vertical period thereafter. Since the transistor 10 is in the non-active state, the above-described maximum applied voltage time between the source electrode and the drain electrode during the OFF period of the transistor 10 is applied over a considerably long period as compared with the ON period. .

The above is an outline of the operation of a general active matrix type liquid crystal image display device. In addition to the same type of image display device, there is a field sequential color type liquid crystal image display device. Next, a liquid crystal image display device using this field sequential color system will be described.

A large screen in a liquid crystal image display device is of a projection type. With this projection type, a large screen can be obtained relatively easily by irradiating a liquid crystal display with light and projecting it on a screen. . As a method of colorization, the projection light is divided into red, green, and blue, which is called a simultaneous additive color mixture, and is divided into 1 for each.
There are a method of using a liquid crystal display device for each sheet, and a method of using one liquid crystal display device, which is called juxtaposed additive color mixture, and providing red, green, and blue pixels in one of the liquid crystal display devices as in the direct-view type.

However, the former is expensive, while high resolution is obtained, and the latter is disadvantageous in that it is inexpensive but cannot obtain resolution. As a solution to this problem, one pixel is red,
A field sequential color system in which green and blue are displayed in a time-division manner is exemplified. In this field sequential color system, 1
The same high-definition as the simultaneous additive color mixing can be obtained with a single liquid crystal display device, and the size can be reduced.
For example, in order to display images corresponding to red, green, and blue within 16 msec, the time to be relaxed is 5 to 5.
6 msec. As a result, the field sequential color method requires at least three times the speed of the transistor and a liquid crystal material with a high response speed as compared with the simultaneous addition and color mixing method which is a normal method.

A twisted nematic (TN: Tw) used in a conventional active matrix liquid crystal image display device.
isted Nematic) mode response is approximately 10 msec
Therefore, it is difficult to realize the optical conversion mode of the π-cell as a high-speed response liquid crystal material, which is about one to two orders of magnitude faster than such a twisted nematic mode, and is very advantageous in terms of viewing angle characteristics. There is.

The π cell mode has a structure in which the pretilt angle is oriented in a plane-symmetric relationship with respect to the center plane between the substrates.
The orientation state is spray orientation when no potential is applied between the substrates, and then transitions to bend orientation when a potential is applied. Further, when a potential is applied, the liquid crystal molecules in the bend alignment are oriented perpendicular to the substrate, and light is transmitted.

In the liquid crystal image display device, in the above two states in the bend alignment, light is transmitted when a voltage of the bend alignment is applied by providing a polarizer on both sides and operating the direction of the polarizer. Alternatively, the display is performed by preventing transmission. The following two techniques are disclosed as the driving method in the π cell mode.

That is, Japanese Patent Application Laid-Open No. 61-116329 describes a method of controlling liquid crystals by forming active switching elements in a matrix for driving π cells. Also, in Japanese Patent Application Laid-Open No. 61-128227, a liquid crystal panel (π cell) that does not correspond to display information has a.
A description is given of performing a high-speed response by applying an ON voltage of lmsec or more and 50 msec or less.

As a method of driving a high-speed liquid crystal, the applicant of the present invention has disclosed in Japanese Patent Application No. 5-320335 a drive voltage supply section in a liquid crystal display device, and the drive voltage supply section is provided with a predetermined voltage of the liquid crystal with respect to irradiation light. Before applying a signal voltage as an applied voltage for obtaining transmittance or reflectance, a first preliminary voltage having an absolute value larger than at least the signal voltage is applied to the pixel, and further, after applying the first preliminary voltage, the signal is applied. A method of improving the response speed of the liquid crystal by applying a second preliminary voltage whose absolute value is smaller than the voltage is proposed.

[0019]

As described above, when a liquid crystal other than twisted nematic is used, special driving is performed before applying a display signal to the liquid crystal. However, a high level voltage must be supplied from the data driver. For this reason, it is necessary to increase the withstand voltage of the transistor constituting the data driver. This causes an increase in the area of the data driver due to the increase in the size of the transistor, and further increases the so-called frame and the cost of the peripheral portion of the liquid crystal image display screen. Was.

For this reason, for example, Japanese Patent Application No. 5-320335
Describes an example in which a counter electrode wired in a stripe pattern is used as a means for applying a voltage.However, since the counter electrode is wired in a stripe so as to be parallel to the scanning signal wiring, the wiring impedance is reduced. Deterioration has led to a decrease in display quality such as contrast image quality. Also,
The arrangement in a stripe shape causes a decrease in aperture ratio, that is, an increase in an area that cannot be used for transmitting light to the liquid crystal, and there is a problem that it is difficult to design a high aperture ratio.

In addition, in the π-cell mode driving method described in Japanese Patent Application Laid-Open No. 61-128227, it is necessary to maintain the bend alignment in the liquid crystal when a low voltage period is long in display information. There is a problem that the orientation returns to the initial spray orientation because the period during which no voltage is applied becomes long.

[0022]

In the active matrix type liquid crystal image display device of the present invention, a plurality of data signal lines for supplying data signals for display and a plurality of scanning signal lines for supplying scanning signals are provided. Arranged in a matrix, at the intersection of these wirings, one terminal side electrode of the three-terminal type active element is connected to the data signal wiring, and the driving terminal side electrode of the active element is connected to the scanning signal wiring. A pixel electrode forming a pixel is connected to the other terminal side electrode, the pixel includes a liquid crystal portion between the pixel electrode and a counter electrode, and a common signal is applied to the counter electrode from a counter electrode driving circuit. commonly supplied, the counter electrode driving circuit, a common signal to be supplied to the counter electrode during the period affects the image is not at least 2
The counter electrode driving circuit is configured to simultaneously supply the scanning signals during the period, and to supply the scanning signals during the period , the counter electrode driving circuit does not affect the image.
Obtain a predetermined transmittance or reflectance of the liquid crystal for the irradiation light
Before applying the signal voltage as the applied voltage,
Voltage that is greater in absolute value than the voltage at the time of signal voltage application.
By applying pressure, at least the signal voltage
When the first preliminary voltage having a large absolute value is applied to the pixel,
Before the signal voltage is applied and the first preliminary voltage
After the application, a second preset having an absolute value smaller than the signal voltage is performed.
The above-described problem is solved by being characterized in that the configuration is such that a reserve voltage is applied .

The value of the first preliminary voltage is preferably
The transition of the data driver that drives the data signal wiring
This is a value higher than the star withstand voltage .

The counter electrode driving circuit includes at least a control
An input circuit to which a signal is input, and an output section of the input circuit
Between the land and two resistors connected in series with each other
An automatic amplitude adjustment circuit comprising a plurality of sets;
Signals from this automatic amplitude adjustment circuit
Are input, and the control signal
Switch means for selectively outputting one of them;
Connected to the switch means to supply a common signal to the opposite electrode.
And a DC adjustment circuit.

Preferably, the counter electrode driving circuit has a small
At least the power generator and its common gate
P-channel MOS field-effect transistor supplied
Consisting of N-channel MOS field-effect transistors
A CMOS circuit and a power supply according to a signal from a control circuit.
A high-level signal supplied from the generation device to the CMOS circuit.
A first switch for selecting a bell power level, and a control circuit
From the power generation device in response to a signal from the CMOS circuit.
Select the low-level power level supplied to the road
A second switch, and the power supply responsive to the input of the control signal.
The high-level signal supplied from the source generator to the CMOS circuit.
Potential between the mid-level power supply and low-level power supply, or CMO
A third switch for selecting one of the outputs of the S circuit.
And is composed of

Preferably, the liquid crystal in the liquid crystal section is:
A liquid crystal having a bend alignment and a spray alignment, wherein an initial voltage is applied to a liquid crystal portion between the pixel electrode and the counter electrode during a predetermined initial period to perform display, and a liquid crystal in the liquid crystal portion is applied. At least one operation of changing the applied voltage to a voltage lower than the initial voltage during a rest period having a predetermined time width.
Repeat at least twice.

More preferably, the pause period is 1 ms or more and 3 seconds or less.

Preferably, the application of the initial voltage is performed by the counter electrode driving circuit.

More preferably, the operation during the idle period is
This is performed by changing the voltage applied to the counter electrode.

More preferably, the operation during the idle period is
This is performed by changing the voltage applied to the pixel electrode.

In the active matrix type liquid crystal image display device of the present invention, the potential of the counter electrode is made normal during the initial period of supply of the display data signal to the data signal wiring, at most within a half horizontal period, Then, the above-described problem is solved by a configuration in which the potential of the counter electrode is brought closer to the potential level in the direction in which no voltage is applied to the liquid crystal at the polarity of the data signal of the data signal wiring.

Preferably, the counter electrode driving circuit includes an amplitude adjusting circuit capable of adjusting the amplitude of the common signal to at least two or more amplitudes.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIG. First, a liquid crystal driving method involves applying a voltage higher than a signal voltage to be displayed as a first preliminary voltage, and then applying a voltage lower than the signal voltage as a second preliminary voltage, so that a liquid crystal during subsequent display is displayed. There is a driving method for improving the response speed of the above, but the first embodiment of the present invention will be described based on this driving method.

In FIG. 1, the same reference numerals are given to the same portions as those of the conventional liquid crystal image display device, and the portions corresponding to the same reference numerals are the same as those of the conventional liquid crystal image display device, and the detailed description thereof will be omitted. 1 is a counter electrode drive circuit,
The opposing electrode drive circuit 1 is basically composed of an input circuit 2, an automatic amplitude adjustment circuit 3, and a DC adjustment circuit 4. The inversion signal FRP is supplied to the input circuit 2 from the control circuit 7 via the bus line 6. The automatic amplitude adjustment circuit 3 is connected to the input circuit 2 and receives control signals A and B from the control circuit 7 via the control signal bus line 5. The potential of the common signal COM output to the counter electrode bus line 11, that is, the pixel, depends on the input timing of the control signals A and B from the control circuit 7, which will be described later, and the amplitude level automatically set by the automatic amplitude adjustment circuit 3. The potential of the opposing electrode constituting 12 can be set arbitrarily.
The DC adjustment circuit 4 is connected to the automatic amplitude adjustment circuit 3 and supplies the common signal COM to the common electrode bus line 11.

The details of the counter electrode driving circuit 1 shown in FIG. 1 will be described with reference to FIGS. FIG. 3A shows the waveform of the inverted signal FRP supplied from the control circuit 7 to the input circuit 2 in the automatic amplitude adjustment circuit 3. The inverted signal FRP is a signal whose amplitude is inverted to “1” and “0” every one vertical cycle (one field). The inverted signal FRP input to the input circuit 2 has an input resistance Rs
The signal is amplified by a constant determined by the feedback resistance Rf and is supplied to the automatic amplitude adjustment circuit 3.

Here, the automatic amplitude adjustment circuit 3 includes three amplitude adjustment circuits 31, 32, and 33. The control signal bus line 5 from the control circuit 7 is composed of two bus lines, a bus line 5A for the control signal A and a bus line 5B for the control signal B. Each bus line 5A, 5B
Are the terminals SWl and SW in the analog switch 20, respectively.
2 while the amplitude adjustment circuits 31, 32 and 33 are connected to the input terminal IN of the analog switch 20 respectively.
I, IN2 and IN3 are individually connected.

Each of the amplitude adjusting circuits 31, 32, and 33 includes two resistors R1, R2; R3, R4; R5, which are connected in series with each other between the output section of the input circuit 2 and the ground.
R6, and the common connection of the resistors is connected to the input terminals IN1, IN2, IN3 of the analog switch 20, respectively. With this connection configuration, the amplitude level of the inverted signal FRP output from the input circuit 2 can be individually determined by appropriately selecting the constants of the resistance values of the two resistors connected in series. Here, the amplitude adjustment circuit 3
The amplitude level of 1 is set to VH, the amplitude level of the amplitude adjustment circuit 32 is set to 0, and the amplitude level of the amplitude adjustment circuit 33 is set to 1/2 VH.
And The truth table of the analog switch 20 is as shown in Table 1 below.

[0038]

[Table 1]

Referring to Table 1, A and B are control signals, and when A = 0 and B = 0, the amplitude adjustment circuit 3
1 is selected and the terminal IN of the analog switch 20 is selected.
1 and output from the terminal OUT, A = 0, B = 1
In this case, the output of the amplitude adjustment circuit 32 is selected and applied to the terminal IN2 of the analog switch 20 and output from the terminal OUT. When A = 1 and B = 0, the output of any of the amplitude adjustment circuits is not selected and the terminal Not output from OUT. A =
When 1, B = 1, the output of the amplitude adjustment circuit 33 is selected and given to the terminal IN3 of the analog switch 20 and the terminal O
Output from UT. The inverted signal FRP output from these terminals OUT is DC-adjusted by the DC adjustment circuit 4 and supplied to the common electrode bus line 11 as a common signal COM. Therefore, when the control signals A and B having the waveforms shown in FIGS. 3B and 3C are input, the input IN1, that is, the amplitude level VH of the amplitude adjustment circuit 31 is used during the period in FIG.
Similarly, the amplitude level 0 of the amplitude adjustment circuit 32 is selected during the period, and the amplitude level ・ · VH of the amplitude adjustment circuit 33 is selected during the period. Thus, the common signal COM from the counter electrode driving circuit 1 has a waveform shown in FIG. 3D.

The inverted signal FRP supplied to the automatic amplitude adjusting circuit 3 through the input circuit 2 has a signal waveform whose amplitude level is inverted to "1" and "0" for each field as shown in FIG. The waveform of the signal COM is the inverted signal FR.
According to the waveform of P, the waveform has a waveform whose amplitude is inverted every field. The period in one field period indicates a display period, and the scanning bus lines x1 to xn are timings to turn on the pixel transistors 10 in order from the scanning bus line x1 in the uppermost stage. The period is a period irrelevant to display, and may be a blanking period of a video signal or may be arbitrarily created. The data signal for display is not limited to a video signal and may be another data signal.

Next, the state of the video signal applied to the other electrode of the liquid crystal, that is, the pixel electrode, will be described with reference to FIG. FIG. 4A shows the waveform of the common signal COM of FIG. 3D. FIG. 4B shows a waveform of a video signal applied from the data driver 9 to the data signal line y1.
FIG. 3C shows the waveforms of the scanning signals x1 to xn applied to the scanning signal wirings x1 to xn from the scanning driver 8 (they are the same as those of the scanning signal wirings for the sake of explanation). Here, the video signal indicates a signal supplied from the data driver 9. The common signal COM and the common signal COM are determined depending on whether the data driver 9 performs sampling and holding in the data driver 9 or in the liquid crystal display panel A. Although the polarity of the video signal is opposite to that of the video signal, an example of the signal held in the liquid crystal display panel A is shown here for easy understanding. The period in FIG. 4 indicates the same period as in FIG.
The period is a period of the first preliminary voltage Vp1 (= VH) which is a voltage higher than the display voltage Von (= １ ／ · VH) level. The period is a period in which the voltage applied to the liquid crystal is the display voltage Von.
This is a period of the second preliminary voltage Vp2 (= 0), which is a lower voltage. Here, the second preliminary voltage Vp2 is set to the 0 level.

Since the liquid crystal cell constituting the liquid crystal display does not respond optically sufficiently when only the display voltage Von is applied,
Before applying a signal voltage for obtaining a predetermined transmittance or reflectance to the liquid crystal cell, a first preliminary voltage Vp1 having an absolute value larger than at least the signal voltage Von is applied. The period in which the second preliminary voltage Vp2 whose absolute value is smaller than at least the display voltage Von is provided during the period in which the display voltage Von is applied.

Further, the application period of the first preliminary voltage Vp1 and the application period of the second preliminary voltage Vp2 need to be shorter than the application period of the display voltage Von. The liquid crystal used here is d × Δn> λ / 2 or 2d × Δn>
λ / 2 (where d × Δn is the retardation due to the displacement of the liquid crystal molecules, that is, the ordinary light component due to the birefringence effect of the light possessed by the liquid crystal molecules when the irradiation light for display passes through the liquid crystal layer once. The difference in the light path of the liquid crystal cell from the extraordinary light component is shown.

D is the thickness of the liquid crystal cell, Δn is the difference between the refractive index of ordinary light and the refractive index of extraordinary light due to the refractive index anisotropy of the liquid crystal, and λ is a liquid crystal satisfying the irradiation light wavelength. Before the display is performed, a first preliminary voltage Vp1 for changing the molecular orientation to the simple mode 0 is always applied, and the first preliminary voltage Vp1 is further applied.
, The liquid crystal molecules are relaxed by the second preliminary voltage Vp2 lower than the voltage at which the voltage becomes the primary peak, and then the display is performed by the applied display voltage Von.

Here, the mode 0 means that the voltage applied to the liquid crystal cell is plotted on the horizontal axis and the light transmittance is maximized when the light transmittance is maximized when the light transmittance is plotted on the vertical axis. At this time, the transmittance becomes the minimum at the highest applied voltage side, and the primary peak means that the voltage is gradually reduced from the voltage at which this optical characteristic becomes mode 0. At the very beginning, that is, the point at which the light transmittance is maximized.

Here, the voltage applied to the liquid crystal cell is
Since the potential difference between the potential of the pixel electrode and the potential of the counter electrode facing the pixel electrode (common potential) is obtained, the video signal on the pixel electrode side during the period is obtained by subtracting the common signal potential VH at the desired first preliminary voltage Vp1. Value. This is video H for convenience of explanation. The period is the second preliminary voltage Vp2
Is set to the 0 level, so that the video signal is set to the 0 level. Therefore, in the first preliminary voltage period, if the potential on the common signal side applied to the counter electrode is set to a sufficiently high voltage VH, the video H applied to the pixel electrode on the opposite side may have a correspondingly lower voltage. Will be.

Thus, by setting the potential to be equal to or lower than the withstand voltage of the data driver 9, the driving of the data driver 9 and the scanning driver 8 can be performed at or below the withstand voltage regardless of the application of the first preliminary voltage Vp1. The period is a period that does not affect the display, and the scanning signals x1 to x1 illustrated in FIG.
xn, the pixel transistors 1
0, all the scanning bus lines x1 to
The first preliminary voltage Vp1 and the second preliminary voltage Vp2 can be applied to the counter electrode side of the liquid crystal forming each of the pixels xn.

As described above, a high voltage can be applied to the liquid crystal in the pixel 12 without exceeding the withstand voltage of each of the data driver 9 and the scanning driver 8, so that the liquid crystal can be driven with a high-speed response and the data driver can be driven. 9
In addition, the scanning driver 8 can be driven at a low voltage. In addition, the size of the pixel transistor 10 can be reduced and the operation speed can be increased, and the circuit can be simplified.
This reduction in transistor size has a large ripple effect in the sense of not only improving the aperture ratio but also facilitating the design of a large high definition liquid crystal panel or an ultra high definition liquid crystal panel. This pixel transistor as a three-terminal active element can be a thin film transistor (TFT) or a bulk transistor (MOS).
FET).

FIG. 4 does not limit the timing of each of the scanning signals x1 to xn in the period. Naturally, the period of the scanning signals x1 to xn is completed in a shorter time than the period shown in FIG. It does n’t matter
It is needless to say that the present invention can be applied to the following field sequential color system.

A method of performing the above-described driving in a field sequential color system will be described with reference to FIG. 1 field is 1 /
It is divided into three fields of three fields each and assigned to red (R), green (G) and blue (B) colors. Each of the first preliminary voltage period and the second preliminary voltage period selects a period that does not affect the display like the waveform of the common signal COM shown in FIG. 5A, and during that period, all the lines of the scanning signal are in FIG. Are turned on all at once by the scanning signals x1 to xn shown in FIG. Also, the scanning signal x in the display period
The scan from 1 to xn may use the rest of the period or a short period. Here, FIG.
5 and the scanning signals x1 to xn shown in FIG. In this way, the display can be switched for each screen (also referred to as surface scanning), flicker and the like can be suppressed, and optimal display can be realized. As described above, in the driving requiring high-speed driving such as the field sequential color method and the surface scanning, the response speed of the liquid crystal and the speeding up of the driver are required, so that the data driver 9 and the scanning driver 8 can be driven at low voltage. This actual driving is particularly effective.

Next, another example of the method of generating the common signal COM voltage will be described. The configuration is not limited to the automatic amplitude adjustment circuit 3 shown in FIG. 2, but may be another configuration shown in FIG. 14 in FIG. 6 is Pch
Is a CMOS circuit composed of a MOS field-effect transistor and a N-channel MOS field-effect transistor, and an inverted signal FRP is commonly supplied from a control circuit to a common gate electrode of the transistors. Reference numeral 15 denotes two levels, that is, VH and 1 as high-level power supply levels for the CMOS circuit 14 supplied from the power supply generation device 17 in response to the input of the control signal A from the control circuit.
/ 2 · VH, a switch 15 ′ is a CMOS circuit 1 supplied from the power supply generator 17 in response to the input of the control signal A from the control circuit.
4 is a switch for selecting one of two levels, that is, 1 VH and -1 / 2.VH, as the level of the low-level power supply with respect to 4. A switch for selecting either the intermediate potential between the high-level power supply and the low-level power supply supplied from the generation device 17 to the CMOS circuit 14 or the output of the CMOS circuit 14.

Here, an example is shown in which the power supply potential is generated by one of the power supply generation devices 17, but devices for separately generating the potentials may be separately provided. The control signals A and B have binary levels of “0” and “1” as described above, and the control signals A and B
5 and 15 'are opened and closed, and an output of the common signal COM waveform similar to the timing shown in FIG.

A driving method performed by driving the counter electrode is described in Japanese Patent Application Laid-Open No. 1-2479. That is, according to this publication, the horizontal period is divided into a plurality of periods, the counter electrode is set to a normal voltage in the last divided period, and the voltage applied to the pixel in this period is set higher than the voltage in the other divided periods. Techniques are disclosed. This technique is to reduce the maximum application time between the source electrode and the drain electrode of the pixel transistor to reduce the leak current, and has a different purpose from the embodiment of the present invention. is there. Further, since the applied voltage is maximized by using the last period of the horizontal period, the purpose is different from that of the present invention in that respect. Also,
In the embodiment of the present invention, a pixel transistor is used as a three-terminal type active element. One terminal of the active element is used as a source electrode of the transistor, and the other terminal is used as a drain electrode of the transistor. The driving electrode is a gate electrode.

Next, a second embodiment of the present invention will be described with reference to FIGS. 7, 8 and 9. The second embodiment is an example of a liquid crystal image display device using a liquid crystal having a spray (spread) orientation and a bend (curved) orientation as a liquid crystal of a pixel, in which the orientation state is changed. Liquid crystal molecules are optically, dielectrically, and magnetically anisotropic in a direction parallel to the long axis and in a direction perpendicular to the long axis, and are deformed by the application of an external electric or magnetic field. It has the property of restoring the original orientation by removing the field. FIG. 7 shows a state of the liquid crystal molecules 31 sandwiched between the two electrodes 30. FIG. 7a shows the electrodes 30, 30 in spray orientation.
This is the first initial state in which no voltage is applied in between.

In this initial state, spray orientation can be taken by rubbing the polymer film or the like. FIG. 7b shows FIG.
3 shows a state in which a voltage 32 required for transition from the spray orientation to the bend orientation is applied between the electrodes 30 and 30. FIG. 7C shows a bend orientation which is an orientation when a voltage 32 is further applied from the bend orientation state of FIG. 7A. The image display device of the present invention performs display using the orientations in the states of FIGS. 7B and 7C as ON and OFF, respectively. In order to perform the display of ON and OFF, it is necessary to change from the initial state of the spray orientation in FIG. 7A to the bend orientation in the state of FIG. 7B. A method is known in which a high voltage is applied for 5 to 6 seconds to change the orientation from spray orientation to bend orientation. However, since the transition is insufficient by itself, in order to improve the transition, an operation of setting the applied voltage to a voltage lower than the initial voltage within a predetermined time width (the time is referred to as a pause period) is one. It can be improved by repeating at least twice. The rest period should preferably be at least lmsec and up to 3 seconds. The operation during the idle period can be performed by setting the potential state between the electrodes 30 facing each other to a potential lower than the initial voltage. The state of this potential may be a method of applying a lower potential to the data signal wiring. Alternatively, it can be performed by a method of applying a voltage from a counter electrode.

Next, a method of driving the above-mentioned idle period by driving the counter electrode will be described with reference to FIG. The configuration of the liquid crystal display device and the counter electrode drive circuit are the same as those in FIGS. 1 and 2 according to the first embodiment. In FIG. 2, the amplitude adjustment levels of the amplitude adjustment circuits 31 and 32 in the automatic amplitude adjustment circuit 3 are set to VH and 0 as in the first embodiment, and the amplitude of the analog switch 6 connected to the amplitude adjustment circuit 33 is changed. The input IN3 is left open. Since the potential level 0 is selected during the idle period and the potential level VH is set during the idle period based on the timings of the control signals A and B shown in FIGS. 9C and 9D and the truth table of Table 1, the common waveform of FIG. A signal can be obtained. Here, the voltage applied to the liquid crystal is a voltage difference between the voltage applied to the counter electrode and the voltage of the video signal having the waveform of FIG. 9a applied to the pixel electrode. That is, if the potential VH of the common signal is set to a sufficiently high potential during a period other than the rest period, the video signal of the opposing pixel electrode can be set to a correspondingly lower potential. As a result, the data driver 9 and the scanning driver 8 can be driven at a low voltage, so that the transistor size of the drivers 8 and 9 can be reduced and the response speed can be increased, and the configuration of the drivers 8 and 9 can be simplified. Can be achieved.

The above-described driving is performed not only in the π cell mode but also in other modes, for example, OCB (Optically Compatible
It can also be applied to driving in the ensated bend mode.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In the above, a special electric potential is applied from the counter electrode side so as not to increase the withstand voltage of the data driver other than the twisted nematic liquid crystal, but this method is also applicable to a display using the twisted nematic liquid crystal. . In a liquid crystal display device using, for example, a p-Si TFT (thin film transistor using polycrystalline silicon) as a pixel transistor, the OFF current of the TFT is generally larger than that of a-Si TFT (thin film transistor using amorphous silicon).
Sometimes it is necessary to suppress the potential applied to the pixel transistor to a low level.

The case where this operation is performed from the counter electrode side will be described below. The configuration of the liquid crystal image display device described here is the same as that of FIG. FIG. 10A shows a data signal line y1.
3 shows the waveform of the video signal. FIG. 10B shows the waveform of the common signal COM, and FIG. 10C shows the waveforms of the scanning signals x1 to xn from the uppermost scanning signal wiring x1 to the lowermost scanning signal wiring xn. VB in FIG. 10a indicates an intermediate potential of the video signal. Here, the scanning signals x1 to x1
xn is applied to the gate of the pixel transistor to turn on the transistor and activate it. However, it is not necessary to activate the transistor for all periods during one horizontal period (1H). Any time can be used as long as the potential for display can be written to the capacitor. This is the time until the scanning signals x1 to xn fall. Here, the scanning signal falls in the first half of 1H. Further, FIG.
As shown in FIG. 10, at the beginning of the display signal transfer period to the data signal wiring, at most a half horizontal period (the period T
1, T2), the potential of the common signal COM is set to a normal potential, and the remaining time (T3) approaches the potential level in the direction in which no voltage is applied to the liquid crystal at the polarity of the data signal of the data signal wiring. Here, the potential is made equal to the video signal of the data signal line y1 in FIG. 10A. Thus, the potential between the drain and source electrodes of the transistor of the pixel P1 is as shown by the waveform in FIG. 10D. The waveform will be described in detail below.

Looking at the pixel electrode potential of the pixel P1 (corresponding to the potential on the drain electrode side of the pixel transistor), the video signal level of the data signal line y1 is obtained during the high level period of the scanning signal line xl. After that, it is the OFF period,
Since the pixel transistor is turned off, the pixel electrode potential fluctuates according to the counter electrode potential (common signal COM). Thus, the pixel electrode potential of the pixel P1 is as shown by the dotted line in FIG. 10D. The potential on the source electrode side of the pixel transistor is the video signal potential of the data signal line y1, which is the same as that of FIG. 10A and is indicated by the solid line in FIG. 10D. From this, the source of the transistor of the pixel P1
The potential difference in the OFF period between the two electrodes of the drain is the potential difference between the waveform of the dotted line and the waveform of the solid line. Therefore, the period during which the maximum voltage is applied during the OFF period of the transistor is T1,
Only the period indicated by the diagonal line of the period T2 is shown in FIG.
Can be reduced as compared with the shaded period shown by. The ON period of the transistor of the pixel P1 is only the ON period shown in the figure during one screen scan (one vertical period), and the rest is the OFF period. Therefore, it is necessary to reduce the maximum potential application period when the transistor is OFF. Is very effective not only for reducing the off-state current but also for preventing deterioration of the transistor.

Compared with the conventional example shown in FIG. 12, the period during which the low potential is applied increases, but the low potential does not affect the deterioration by selecting a level at which the OFF breakdown voltage of the transistor does not deteriorate. be able to.

Each of the above embodiments shows a basic configuration, and it is needless to say that this configuration can be appropriately changed as needed.

[0063]

According to the present invention, low-voltage driving of a DEC driver can be realized for driving a liquid crystal, particularly for driving a liquid crystal with a high speed response. It can be simplified. Further, since the maximum applied voltage period between the source and drain electrodes in the OFF period of the pixel transistor is shortened, the leak current is reduced, so that the display quality can be improved and the deterioration of the pixel transistor can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an active matrix type liquid crystal image display device according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a counter electrode driving circuit.

FIG. 3 is a waveform chart for explaining the operation of the counter electrode drive circuit of FIG. 2;

FIG. 4 is a waveform chart for explaining the operation of the device of FIG. 1;

FIG. 5 is a waveform chart for explaining generation of a first preliminary voltage and a second preliminary voltage.

FIG. 6 is a diagram showing a modification of the counter electrode drive circuit.

FIG. 7 is a diagram illustrating a configuration of a pixel for explaining a voltage applied to an electrode when the liquid crystal of the pixel is changed from a spray alignment to a bend alignment.

8 is a waveform diagram of a voltage applied to the liquid crystal in FIG.

FIG. 9 is a waveform diagram when a voltage is applied to liquid crystal using a counter electrode driving circuit.

FIG. 10 is a waveform chart for explaining the operation of the liquid crystal image display device according to another embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional liquid crystal image display device.

FIG. 12 is a waveform diagram of an inverted signal and a common signal in a conventional device.

FIG. 13 is a waveform chart for explaining the operation of the conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter electrode drive circuit 2 Input circuit 3 Automatic amplitude adjustment circuit 7 Control circuit 8 Scan driver 9 Data driver 10 Pixel transistor 12 Pixel y1 to yn Data signal wiring x1 to xn Scan signal wiring

Continuation of the front page (56) References JP-A-5-16430 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G02F 1/133 550 G09G 3/36

Claims (11)

(57) [Claims] 1. A plurality of data signal lines for supplying data signals for display and a plurality of scanning signal lines for supplying scanning signals are arranged in a matrix. One terminal side electrode of the terminal type active element, a drive terminal side electrode of the active element is connected to the scanning signal wiring, and a pixel electrode forming a pixel is connected to the other terminal side electrode of the active element. is an active matrix type liquid crystal image display device common signal from the counter electrode driving circuit is commonly supplied to are those containing liquid portion and the counter electrode between the pixel electrode and the counter electrode, wherein Counter electrode
The drive circuit applies a voltage to the counter electrode during a period that does not affect the image.
Supply at least two levels of common signal
And simultaneously activates the scanning signals during the period.
In the active matrix type liquid crystal display device , the counter electrode drive circuit has a period during which the image is not affected.
The predetermined transmittance of the liquid crystal to the irradiation light for display or
Before applying the signal voltage as the applied voltage to obtain the reflectance
Absolutely higher than the voltage at the time of signal voltage application as a common signal.
By applying a voltage having a large value, at least the
A first preliminary voltage having an absolute value larger than the signal voltage is applied to the pixel.
And before the signal voltage is applied and the first
After applying the preliminary voltage, its absolute value is smaller than the signal voltage.
An active matrix type liquid crystal image display device , wherein a second preliminary voltage is applied . 2. The method according to claim 1 , wherein the value of the first preliminary voltage is the data signal.
Of the data driver that drives the signal wiring
2. The accelerator according to claim 1, wherein
Active matrix type liquid crystal image display device. 3. The counter electrode driving circuit according to claim 1, wherein
An input circuit to which a control signal is input, and an output unit of the input circuit.
Two resistors connected in series to ground
Automatic amplitude adjustment circuit comprising a plurality of sets of
Connected to the automatic amplitude adjustment circuit.
Signals are input and the plurality of signals are
Switch means for selectively outputting one of
Connected to switch means to supply common signal to counter electrode
And a DC adjustment circuit that
The active matrix type liquid according to claim 1 or 2,
Crystal image display device. 4. The counter electrode driving circuit according to claim 1, wherein at least
An inverted signal is supplied to the source generator and its common gate
Pch MOS field effect transistor and Nch M
CMOS circuit composed of OS field-effect transistors
Path and the power generation device according to a signal from the control circuit.
From the high level power supply supplied to the CMOS circuit.
A first switch for selecting a level, and a signal from a control circuit.
Signal from the power generation device to the CMOS circuit.
Second level for selecting the level of the low level power supplied
A power supply generating circuit in response to a switch and a control signal input;
The high-level power supply supplied to the CMOS circuit from the device;
Potential between CMOS and low level power supply or CMOS circuit
A third switch to select one of the outputs
3. The method according to claim 1, wherein
An active matrix type liquid crystal image display device as described in the above. 5. The liquid crystal in the liquid crystal section is a liquid crystal having a bend alignment and a spray alignment, and a liquid crystal between the pixel electrode and the counter electrode is provided during a predetermined initial fixed period for performing display. At least one operation of applying an initial voltage to change liquid crystal molecules in the liquid crystal portion from the spray alignment to the bend alignment, and thereafter reducing the applied voltage to a voltage lower than the initial voltage during a pause period having a predetermined time width. 5. The active matrix type liquid crystal image display device according to claim 1, wherein the display is repeated at least twice. 6. The active matrix type liquid crystal image display device according to claim 5, wherein said pause period is 1 ms or more and 3 seconds or less. 7. The active matrix liquid crystal image display device according to claim 5, wherein the application of the initial voltage is performed by the counter electrode driving circuit. 8. The active matrix type liquid crystal image display device according to claim 5, wherein the operation during the idle period is performed by changing a voltage applied to the counter electrode. 9. The active matrix liquid crystal display device according to claim 5, wherein the operation during the idle period is performed by changing a voltage applied to the pixel electrode. 10. A plurality of data signal lines for supplying data signals for display and a plurality of scanning signal lines for supplying scanning signals are arranged in a matrix. The drive terminal side electrode of the active element is connected to one terminal side electrode of the terminal type active element to the scanning signal wiring, and the pixel electrode forming a pixel is connected to the other terminal side electrode of the active element, and the pixel is An active matrix liquid crystal image display device including a liquid crystal portion between a pixel electrode and a counter electrode, wherein a common signal is commonly supplied to the counter electrode from a counter electrode driving circuit. Early in the supply of data signals,
The potential of the counter electrode is assumed to be normal for at most a half horizontal period, and thereafter, the potential of the counter electrode is brought closer to a potential level in a direction in which no voltage is applied to the liquid crystal at the polarity of the data signal of the data signal wiring. Characteristic active matrix liquid crystal image display device. 11. The counter electrode drive circuit according to claim 1, further comprising an amplitude adjustment circuit capable of adjusting the amplitude of said common signal to at least two amplitudes.
The active matrix type liquid crystal image display device according to any one of the above.