JP3239437B2 - Horizontal sync signal detection circuit - Google Patents

Horizontal sync signal detection circuit

Info

Publication number
JP3239437B2
JP3239437B2 JP10967492A JP10967492A JP3239437B2 JP 3239437 B2 JP3239437 B2 JP 3239437B2 JP 10967492 A JP10967492 A JP 10967492A JP 10967492 A JP10967492 A JP 10967492A JP 3239437 B2 JP3239437 B2 JP 3239437B2
Authority
JP
Japan
Prior art keywords
circuit
signal
horizontal
output
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10967492A
Other languages
Japanese (ja)
Other versions
JPH05308585A (en
Inventor
喜孝 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP10967492A priority Critical patent/JP3239437B2/en
Publication of JPH05308585A publication Critical patent/JPH05308585A/en
Application granted granted Critical
Publication of JP3239437B2 publication Critical patent/JP3239437B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、テレビ信号やビデオ信
号の検出回路を含むテレビ受信機に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver including a circuit for detecting television signals and video signals.

【0002】[0002]

【従来の技術】近年、テレビ受信機は、自動選局機能や
ノイズ画面消去機能(ブルーバック機能)を動作させな
いためにテレビ信号やビデオ信号の有無を検出する水平
同期信号検出回路が不可欠となってきている。従来は、
水平同期信号検出回路として水平AFC回路がロック状
態か非ロック状態かで判定する方法が用いられている。
以下、図面を参照しながら従来の水平同期信号検出回路
の一例について説明する。 図2において、1は水平同
期信号、2は水平AFC回路、3は水平発振回路、4は
AND回路、5は積分回路、6は電圧比較回路である。
2. Description of the Related Art In recent years, a horizontal synchronizing signal detecting circuit for detecting the presence or absence of a television signal or a video signal is indispensable in a television receiver in order to prevent the automatic channel selection function and the noise screen erasing function (blue back function) from operating. Is coming. conventionally,
A method for determining whether the horizontal AFC circuit is locked or unlocked is used as a horizontal synchronization signal detection circuit.
Hereinafter, an example of a conventional horizontal synchronization signal detection circuit will be described with reference to the drawings. In FIG. 2, 1 is a horizontal synchronizing signal, 2 is a horizontal AFC circuit, 3 is a horizontal oscillation circuit, 4 is an AND circuit, 5 is an integration circuit, and 6 is a voltage comparison circuit.

【0003】以上のように構成された水平同期信号検出
回路について、以下その動作を説明する。
[0003] The operation of the horizontal synchronizing signal detecting circuit configured as described above will be described below.

【0004】水平同期信号が有る時には、水平AFC回
路はロック状態となって、水平発振回路信号は水平同期
信号と同位相の信号となり、水平同期信号との論理積を
積分した電圧は電圧比較回路の基準値よりも高くなり、
水平同期信号有りと判定する。水平同期信号が無い時に
は、ノイズと水平発振回路信号の論理積となり、積分し
た電圧は電圧比較回路の基準値よりも低くなり、水平同
期信号無しと判定して、ビデオ回路の入力をブルーバッ
ク信号へ切り換える。
When there is a horizontal synchronizing signal, the horizontal AFC circuit is in a locked state, the horizontal oscillation circuit signal becomes a signal having the same phase as the horizontal synchronizing signal, and the voltage obtained by integrating the logical product with the horizontal synchronizing signal is a voltage comparing circuit. Higher than the reference value of
It is determined that there is a horizontal synchronization signal. When there is no horizontal synchronizing signal, the logical product of the noise and the horizontal oscillation circuit signal is obtained, and the integrated voltage becomes lower than the reference value of the voltage comparison circuit. Switch to.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前記の
ような構成では、テレビ受信機にビデオ再生機を接続し
て、再生状態での早送りをした時に生じる水平同期信号
の一部欠落が、水平AFC回路の引き込み周波数範囲を
逸脱するために、論理積を積分した電圧が低下し、電圧
比較回路の基準値よりも低くなることで、水平同期信号
無しと判定して、ブルーバック表示となり、再生画像が
見えない場合があるといった問題点を有していた。
However, in the above-described configuration, the horizontal AFC is partially lost when a video player is connected to a television receiver and fast-forwarding is performed in a playback state. In order to deviate from the pull-in frequency range of the circuit, the voltage obtained by integrating the logical product decreases and becomes lower than the reference value of the voltage comparison circuit. There was a problem that there was a case where it could not be seen.

【0006】本発明は、前記従来の問題点を解決するも
ので、再生状態での早送りをしても水平同期信号有りと
判定する水平同期信号検出回路を提供することを目的と
する。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a horizontal synchronizing signal detecting circuit for judging that there is a horizontal synchronizing signal even when fast-forwarding in a reproducing state.

【0007】[0007]

【課題を解決するための手段】この目的を達成するため
に、本発明の水平同期信号検出回路は、水平同期信号
入力される水平AFC回路と、前記水平AFC回路によ
り前記入力水平同期信号と発振周波数が同一位相になる
ように制御される水平発振回路と、前記水平発振回路か
ら出力される水平発振信号と前記入力水平同期信号との
論理積を演算し前記入力水平同期信号と同一位相の信号
が出力されるAND回路と、前記AND回路からの出力
信号を積分する第1の積分回路と、前記第1の積分回路
から出力される電圧を基準電圧と比較して検出信号を出
力する電圧比較回路と、前記入力水平同期信号を積分す
る第2の積分回路と、前記電圧比較回路から出力される
検出信号と前記第2の積分回路から出力される出力信号
の論理和を演算するOR回路とを備えた構成により、信
号の一部が欠落して入力される水平同期信号に対する前
記第2の積分回路から出力される積分信号が前記OR回
路のしきい値よりも高くなるように前記第2の積分回路
の時定数を設定し、入力水平同期信号の欠落により前記
電圧比較回路から出力される検出信号の電圧が水平同期
信号の存在を示す所定の電圧レベルより低くなっても前
記第2の積分回路から水平同期信号の存在を示す所定レ
ベルの電圧が前記OR回路に供給され、前記OR回路か
ら入力水平同期信号有りの正しい判定信号が出力される
ようにしたことを特徴とするものである。
Means for Solving the Problems To this end, the horizontal synchronizing signal detecting circuit of the present invention, the horizontal synchronizing signal
The input horizontal AFC circuit and the horizontal AFC circuit
The input horizontal synchronization signal and the oscillation frequency have the same phase
Controlled by the horizontal oscillation circuit and the horizontal oscillation circuit
Between the horizontal oscillation signal output from the
Calculates the logical product and outputs the same phase as the input horizontal synchronization signal
And an output from the AND circuit
A first integration circuit for integrating a signal, and the first integration circuit
The output signal is compared with the reference voltage to output a detection signal.
A voltage comparison circuit for integrating the input horizontal synchronizing signal.
Output from the second integrating circuit and the voltage comparing circuit.
A detection signal and an output signal output from the second integration circuit
And an OR circuit for calculating the logical sum of
Before the horizontal sync signal that is input with part of the signal missing
The integration signal output from the second integration circuit is the OR signal.
The second integrating circuit so as to be higher than the threshold value of the road.
The time constant of
The voltage of the detection signal output from the voltage comparison circuit is synchronized horizontally.
Even before it falls below a predetermined voltage level indicating the presence of a signal
A predetermined signal indicating the presence of the horizontal synchronizing signal is output from the second integrating circuit.
A bell voltage is supplied to the OR circuit.
Outputs the correct judgment signal with input horizontal sync signal
It is characterized by doing so.

【0008】[0008]

【作用】前記構成によって、再生状態での早送りをした
時に、水平同期信号の一部欠落があっても、水平同期信
号を積分した信号がOR回路のしきい値よりも高くなる
ように積分時定数を設定することで、論理和はHIGH
となり、水平同期信号有りと判定できる。
With the above arrangement, even if a horizontal synchronizing signal is partially lost during fast-forwarding in the reproducing state, the integration time is adjusted so that the signal obtained by integrating the horizontal synchronizing signal becomes higher than the threshold value of the OR circuit. By setting a constant, the logical sum is HIGH
And it can be determined that there is a horizontal synchronization signal.

【0009】[0009]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。
An embodiment of the present invention will be described below with reference to the drawings.

【0010】図1は、本発明の一実施例の水平同期信号
検出回路である。尚、図1において図2に示した従来例
と同様の構成については、同符号を付して、その詳細な
説明は省略する。
FIG. 1 shows a horizontal synchronizing signal detecting circuit according to an embodiment of the present invention. In FIG. 1, the same components as those in the conventional example shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0011】本実施例は、電圧比較回路の出力信号と水
平同期信号を積分した信号の論理和を付加した構成にお
いて従来例との違いを有するものである。
The present embodiment differs from the conventional example in the configuration in which the logical sum of the output signal of the voltage comparison circuit and the signal obtained by integrating the horizontal synchronizing signal is added.

【0012】以上のように構成された水平同期信号検出
回路について説明する。再生状態での早送りをした時
に、水平同期信号の一部欠落があっても、水平同期信号
を積分した信号がOR回路のしきい値よりも高くなるよ
うに積分時定数を設定することで、論理和はHIGHと
なり、水平同期信号有りと判定できるので、再生画像を
見ることができる。
The horizontal synchronizing signal detecting circuit configured as described above will be described. By setting the integration time constant so that the signal obtained by integrating the horizontal synchronizing signal becomes higher than the threshold value of the OR circuit, even if the horizontal synchronizing signal is partially lost when fast-forwarding in the playback state. The logical sum becomes HIGH, and it can be determined that there is a horizontal synchronization signal, so that the reproduced image can be viewed.

【0013】[0013]

【発明の効果】以上のように本発明は、水平同期信号と
水平AFCかいろで制御した水平発振回路信号の論理積
を積分して電圧比較した信号と、前記水平同期信号を積
分した信号の論理和から、水平同期信号の有無を判定す
ることによって、テレビ受信機にビデオ再生機を接続し
て、再生状態での早送りをしても水平同期信号有りと判
定して、再生画像を見ることができる。
As described above, according to the present invention, the signal obtained by integrating the logical product of the horizontal synchronizing signal and the horizontal oscillation circuit signal controlled by the horizontal AFC circuit and comparing the voltage is compared with the signal obtained by integrating the horizontal synchronizing signal. By judging the presence or absence of a horizontal synchronizing signal from the logical sum, a video player is connected to the television receiver, and it is judged that there is a horizontal synchronizing signal even when fast-forwarding in the playback state, and the reproduced image is viewed. Can be.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における水平同期信号検出回
FIG. 1 is a horizontal synchronization signal detection circuit according to an embodiment of the present invention.

【図2】従来例の水平同期信号検出回路FIG. 2 is a conventional horizontal synchronization signal detection circuit.

【符号の説明】[Explanation of symbols]

1 水平同期信号 2 水平AFC回路 3 水平発振回路 4 AND回路 5、7 積分回路 6 電圧比較回路 8 OR回路 DESCRIPTION OF SYMBOLS 1 Horizontal synchronizing signal 2 Horizontal AFC circuit 3 Horizontal oscillation circuit 4 AND circuit 5, 7 Integration circuit 6 Voltage comparison circuit 8 OR circuit

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 水平同期信号が入力される水平AFC回
路と、前記水平AFC回路により前記入力水平同期信号
と発振周波数が同一位相になるように制御される水平発
振回路と、前記水平発振回路から出力される水平発振信
号と前記入力水平同期信号との論理積を演算し前記入力
水平同期信号と同一位相の信号が出力されるAND回路
と、前記AND回路からの出力信号を積分する第1の積
分回路と、前記第1の積分回路から出力される電圧を基
準電圧と比較して検出信号を出力する電圧比較回路と、
前記入力水平同期信号を積分する第2の積分回路と、前
記電圧比較回路から出力される検出信号と前記第2の積
分回路から出力される出力信号の論理和を演算するOR
回路とを備え、信号の一部が欠落して入力される水平同
期信号に対する前記第2の積分回路から出力される積分
信号が前記OR回路のしきい値よりも高くなるように前
記第2の積分回路の時定数を設定し、入力水平同期信号
の欠落により前記電圧比較回路から出力される検出信号
の電圧が水平同期信号の存在を示す所定の電圧レベルよ
り低くなっても前記第2の積分回路から水平同期信号の
存在を示す所定レベルの電圧が前記OR回路に供給さ
れ、前記OR回路から入力水平同期信号有りの正しい判
定信号が出力されるようにしたことを特徴とする水平同
期信号検出回路。
1. A horizontal AFC circuit to which a horizontal synchronization signal is input.
And the input horizontal synchronization signal by the horizontal AFC circuit.
And horizontal oscillation controlled so that the oscillation frequency is the same
Oscillation circuit, and a horizontal oscillation signal output from the horizontal oscillation circuit.
Signal and the input horizontal synchronizing signal, and
AND circuit for outputting a signal having the same phase as the horizontal synchronization signal
And a first product for integrating an output signal from the AND circuit
A dividing circuit and a voltage output from the first integrating circuit.
A voltage comparison circuit that outputs a detection signal by comparing with a reference voltage;
A second integration circuit for integrating the input horizontal synchronization signal;
A detection signal output from the voltage comparison circuit and the second product
OR for calculating the logical sum of the output signals output from the branch circuit
Circuit and a horizontal
Integral output from the second integration circuit for the period signal
So that the signal is higher than the threshold value of the OR circuit.
The time constant of the second integration circuit is set, and the input horizontal synchronization signal is set.
Detection signal output from the voltage comparison circuit due to lack of
Is higher than a predetermined voltage level indicating the presence of the horizontal sync signal.
The horizontal synchronizing signal from the second integrating circuit.
A voltage of a predetermined level indicating the presence is supplied to the OR circuit.
From the OR circuit to determine whether there is an input horizontal synchronization signal.
A horizontal synchronizing signal detection circuit wherein a constant signal is output .
JP10967492A 1992-04-28 1992-04-28 Horizontal sync signal detection circuit Expired - Fee Related JP3239437B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10967492A JP3239437B2 (en) 1992-04-28 1992-04-28 Horizontal sync signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10967492A JP3239437B2 (en) 1992-04-28 1992-04-28 Horizontal sync signal detection circuit

Publications (2)

Publication Number Publication Date
JPH05308585A JPH05308585A (en) 1993-11-19
JP3239437B2 true JP3239437B2 (en) 2001-12-17

Family

ID=14516307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10967492A Expired - Fee Related JP3239437B2 (en) 1992-04-28 1992-04-28 Horizontal sync signal detection circuit

Country Status (1)

Country Link
JP (1) JP3239437B2 (en)

Also Published As

Publication number Publication date
JPH05308585A (en) 1993-11-19

Similar Documents

Publication Publication Date Title
US4688082A (en) Multi-system television receiver
JPH1198422A (en) Video signal discrimination circuit
US5339113A (en) Motion-and nonstandard-adaptive three-dimensional YC separating circuit for NTSC signal
JP3239437B2 (en) Horizontal sync signal detection circuit
JP3024913B2 (en) Synchronous signal processing circuit
US4999707A (en) Synchronizing signal separating circuit separating synchronizing signal from a composite video signal
JP3456712B2 (en) Composite video signal detection circuit
EP0298488B1 (en) Video signal processing circuit for VTR signal
US5917550A (en) Clock signal generator for composite video signal
JPS59221087A (en) Automatic discriminating system of sound multiplex mode of vtr
KR0113153Y1 (en) Stored image display apparatus of video vision system during co-signal
EP0479610B1 (en) Television receiver
CA2013532C (en) Synchronizing signal separating circuit
JPH0720251B2 (en) Image synthesizer
JP4663134B2 (en) A / D conversion apparatus and method for analog video signal
CA1262281A (en) Multi-system television receiver
JPS6059793B2 (en) Video recording and playback device
US20030081148A1 (en) Method and device for detecting the parity of successive fields of an interlaced video signal
JP3296637B2 (en) Sync separation circuit
JP3865015B2 (en) Image display device
JP2876610B2 (en) Color signal processing circuit
JP3785632B2 (en) Signal processing circuit
JPH0414541B2 (en)
KR100216913B1 (en) Video level controlling apparatus by discriminating scanning mode of tv
JPH082085B2 (en) Synchronization detection device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees