JP3237374B2 - Digital signal recording device, digital signal reproducing device, and digital signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording apparatus for encoding and recording a digital signal in a solid-state memory, and a digital signal reproducing apparatus for reproducing a signal recorded by the recording apparatus.

[0002]

2. Description of the Related Art In recent years, a digital signal recording / reproducing apparatus using a solid-state memory as a recording medium is expected as a next-generation recording / reproducing apparatus. However, at present, the solid-state memory has a very high unit cost per byte as compared with other recording media such as a magnetic tape, a magnetic disk, and an optical disk, which hinders the practical use of a digital signal recording / reproducing apparatus. Signal compression technology
Although this is an effective means for effectively utilizing a solid-state memory and for putting a digital signal recording / reproducing apparatus into practical use, there is a trade-off problem that increasing the compression rate while reducing the recording quality.

Therefore, various solutions have been conventionally proposed. For example, as a conventional example closest to the present invention,
There are the following. The encoding bit rate is made variable, and when the memory capacity is sufficient, the digital signal is encoded at a high bit rate and recorded in the solid-state memory. Next, when the remaining capacity of the solid-state memory decreases, data recorded at a high bit rate is read from the solid-state memory, and the bit rate is reduced by a compression algorithm different from the original one, and the encoding is performed again, and the solid-state memory is re-encoded. An empty area is secured in the solid-state memory by recording.
By repeating this series of processes, the contradictory problem of recording quality and long time is dealt with (for example, see Japanese Patent Application Laid-Open No. Hei 2-305053).

[0004]

However, in the above-mentioned conventional example, in order to secure an empty area in the solid-state memory, data recorded at a high bit rate is read from the solid-state memory, and a low-level data different from the initial state is read. The bit rate has to be reduced and re-encoded again by the bit rate compression algorithm, which has a problem that the load on hardware is large and the efficiency is low. Further, there is a problem that an unused area is generated in the solid-state memory depending on the amount of data, and the memory of the solid-state memory cannot be effectively used.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a digital signal recording apparatus and a digital signal reproducing apparatus capable of efficiently extending a recording time while maintaining recording quality as much as possible. I do. It is another object of the present invention to provide a digital signal recording device and a digital signal reproducing device for effectively utilizing a solid-state memory.

[0006]

In order to achieve this object, a digital signal recording apparatus according to a first aspect of the present invention comprises an encoder for encoding an input digital signal into first code data; A decoder for decoding the encoded data into the original digital signal, and a time required for encoding the input digital signal by the encoder and for decoding the encoded data into the original digital signal by the decoder A delay unit for delaying the input digital signal by an amount, a subtractor for outputting a difference signal between the output signal of the decoder and the output signal of the delay unit as second code data, and the first code data. A solid-state memory having a data storage area for storing the second code data, an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data; De While the writable area exists in the data storage area, the first code data and the second code data are stored in the data storage area. If the writable area of the data storage area becomes insufficient, A part or all of the second code data stored in the data storage area is discarded, and the first code data is stored in an area where the discarded data is stored. In the auxiliary information storage area.

A digital signal reproducing apparatus according to a second aspect of the present invention includes a data storage area storing code data recorded by the digital signal recording apparatus according to the first aspect of the present invention, an attribute of the data storage area, A solid-state memory having an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; and a first memory stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. Are read out sequentially, and if the second code data is present in the data storage area, the read controller also reads the second code data, and the read controller reads the second code data. A decoder for decoding the first code data, and an adder for outputting a sum signal of the output signal of the decoder and the second code data.

A digital signal recording apparatus according to a third aspect of the present invention provides a first encoder for encoding an input digital signal into first code data, and decoding the first code data into an original digital signal. A first decoder for encoding, and a process of encoding the input digital signal by the first encoder and decoding the encoded data to an original digital signal by the first decoder. A delay unit that delays an input digital signal by a time, a subtractor that outputs a difference signal between an output signal of the first decoder and an output signal of the delay unit as second code data, and the subtractor A second encoder for encoding the output signal of the second code data as third code data, a data storage area for storing the first code data and the third code data, Attributes and attributes of the stored data A solid-state memory having an auxiliary information storage area for storing auxiliary information, and the first code data and the third code data being stored in the data storage area while a writable area exists in the data storage area. When the writable area of the data storage area becomes insufficient, a part or all of the third code data stored in the data storage area is discarded, and the discarded data is stored. And a write controller that stores the first code data in the area where the writing has been performed, and stores the auxiliary information in the auxiliary information storage area.

A digital signal reproducing apparatus according to a fourth aspect of the present invention includes a data storage area storing code data recorded by the digital signal recording apparatus according to the third aspect of the present invention, an attribute of the data storage area, A solid-state memory having an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; and a first memory stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. Are read out sequentially, and if the third code data is present in the data storage area, the read controller also reads the third code data, and the read controller reads the third code data. A first decoder that decodes the first code data, a second decoder that decodes the third code data read by the reading controller, and a first decoder that decodes the third code data. The decoder An output signal is obtained by an adder which outputs a sum signal between the output signal of said second decoder.

The digital signal recording / reproducing apparatus of the present invention comprises the digital signal recording apparatus of the first aspect and the digital signal reproducing apparatus of the second aspect, or the digital signal recording apparatus of the third aspect and the fourth aspect. In the digital signal reproducing apparatus according to the invention, the decoder is shared.

[0011]

According to the present invention, when there is a free area in the memory according to the above-described configuration, in addition to the normal compressed and encoded data,
The data lost due to the compression encoding is also stored in the memory, and at the time of reproduction, the data lost due to the compression encoding is added to the normal decoded data, so that reproduction with higher quality than normal compression encoding is performed. A signal is obtained. Further, even when the memory has a shortage of free space, a part or all of the data stored in the past and lost by the compression coding is discarded while the normal compression-coded data is retained, and the free space in the memory is discarded. , And the recording process is continued, so that a reproduced signal having at least the quality of ordinary compression encoding can be obtained.

By doing so, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. Further, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used.

Further, the digital signal recording / reproducing apparatus of the present invention comprises the digital signal recording apparatus of the first aspect and the digital signal reproducing apparatus of the second aspect, or the digital signal recording apparatus of the third aspect and the fourth aspect. In the digital signal reproducing apparatus according to the invention, the decoder is commonly used, and the circuit configuration can be simplified.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the digital signal recording apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital signal recording apparatus according to a first embodiment of the present invention. FIG.
, 11 is an encoder that compresses and encodes, for example, a 16-bit input digital signal into first encoded data.
Is a decoder that decodes the first coded data into the original digital signal. 13 is a coder that encodes the input digital signal by the coder 11 and further decodes the coded data into the decoder 12.
A delay unit for delaying the input digital signal by a time required for decoding the original digital signal into a digital signal, and a second code for converting a difference signal between the output signal of the decoder 12 and the output signal of the delay unit 13 into a second code A subtractor 15 for outputting as data includes a data storage area for storing the first code data and the second code data, an attribute of the data storage area, and an attribute of the stored data. The solid-state memory 16 having an auxiliary information storage area for storing auxiliary information shown therein, the solid-state memory 16 includes, while a writable area exists in the data storage area,
The first code data and the second code data are stored in the data storage area, and when the writable area of the data storage area becomes insufficient, the second code data stored in the data storage area is stored. A part or all of the code data is discarded, the first code data is stored in an area where the discarded data is stored, and the auxiliary information is
This is a write controller that stores the auxiliary information in the auxiliary information storage area. Here, the encoder 11 performs PCM, ADPCM, C
Any conventional encoder such as an ELP may be used. In addition, the decoder 12 includes the encoder 11
Is a decoder corresponding to. Here, it is assumed that the data storage area is a memory having a storage capacity of 8 bits per address. The solid-state memory 15 uses a nonvolatile memory, but the present invention is not limited to such a nonvolatile memory. this is,
This is common to all the descriptions given in the solid-state memories of the following embodiments.

FIG. 2 is a diagram showing the state of the data storage area when the recording process is completed before the data storage area of the solid-state memory 15 becomes full.

FIG. 3 is a diagram showing a state of the auxiliary information storage area when the recording process is completed before the data storage area of the solid-state memory 15 becomes full.

FIG. 4 is a diagram showing a state of the data storage area when the data storage area of the solid-state memory 15 is in the memory full state, and after the recording processing is continued for a while, the recording processing is completed.

FIG. 5 is a diagram showing a state of the auxiliary information storage area when the data storage area of the solid-state memory 15 is in the memory full state, and after the recording processing has been continued for a while, the recording processing is completed.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIGS.

In FIG. 1, first, an input digital signal having 16 bits in each sample is compression-coded by a coder 11 into 4 bits for each sample, and first code data is output. The decoder 12 decodes the first code data output from the encoder 11 into an original digital signal.
The delay unit 13 delays the input digital signal by the time T required for the compression encoding and decoding. Subtractor 14
Then, a difference signal between the output signal of the decoder 12 and the output signal of the delay unit 13 is output as second code data. Here, it is assumed that the amplitude of the difference signal is a signal that can be expressed by 8 bits. While the write controller 16 has a free area in the data storage area in the solid-state memory 15,
The first code data and the second code data are stored in a data storage area in the solid-state memory 15.

Here, since the first code data is 4 bits per sample, the code data of 2 samples is arranged in 8 bits and stored at one address, and the second code data is 1 sample. 8 bits per
It shall be stored at one address for each sample. The first code data is sequentially stored in the data storage area from the address number 000000 to the address number 0FFFF, and the second code data is sequentially stored in the data storage area from the address number 10000 to the address number 2FFFF. Shall be done. This is because if the data storage area has only 30000 addresses, for example,
Since the first code data is a signal of 4 bits per sample and the second code data is a signal of 8 bits per sample, the area where the second code data is stored is the first code data. This is because the required area is twice as large as the area where the data is stored.

By performing such a writing process, until the data storage area of the solid-state memory 15 becomes full,
FIG. 2 shows the state of the data storage area when the recording process is completed. In FIG. 2, D1 (t) represents the first code data at time t, and D2 (t) represents the second code data at time t. FIG. 3 shows a state of the auxiliary information storage area in such a case. Here, the storage area of the first code data is the address 0000.
0 to address 0FFFF, the storage area of the second code data is allocated from address 10000 to address 2FFFF, the first code data is 4 bits per sample, and the second code data The data is 8 bits per sample and the first
Code data from address 000000 to address 04
000, indicating that the second code data is stored from address 10000 to address 18000.

If the recording process is not completed before the data storage area of the solid-state memory 15 becomes full, the write controller 16 stores only the first code data in the solid-state memory 15. Store in the area.
At this time, the first code data is sequentially stored in the data storage area from the address number 10000 to the address number 2FFFF. As a result, address number 1
The second code data stored in the area from 0000 to the address number 2FFFF is gradually discarded, and the first code data is stored in the discarded area. After that, the recording time can be extended.

FIG. 4 is a diagram showing a state of the data storage area when data is recorded even after the data storage area of the solid-state memory 15 has reached the memory full state by performing such a writing process. In FIG. 4, D1 (t) represents the first code data at time t, and D2 (t) represents the second code data at time t. In this example, since the first code data is stored up to the address 14000, of the second code data stored in the past, the address 100
It is shown that the data stored at the address 14000 from 00 is discarded. Also, in such a case,
FIG. 5 shows the state of the auxiliary information storage area. Here, the storage area of the first code data is the address 000
00 to address 0FFFF,
The storage area for the second code data is allocated from address 10000 to address 2FFFF, and the first code data is 4 bits per sample.
Is 8 bits per sample, and the first code data is from address 000000 to address 1
The second code data is stored up to 4000.
Since the data is stored from the address 14001 to the address 2FFFF, of the second code data, the data stored from the address 10000 to the address 14000 is discarded and rewritten with the first code data. You can see that it was done.

As described above, according to the present embodiment, the encoder for encoding the input digital signal into the first code data and the decoding for decoding the first code data into the original digital signal A delay unit that encodes an input digital signal with the encoder and further delays the input digital signal by a time required for a process of decoding the encoded data into an original digital signal with the decoder. A subtractor for outputting a difference signal between the output signal of the decoder and the output signal of the delay unit as second code data, and data for storing the first code data and the second code data A solid-state memory having a storage area and an auxiliary information storage area for storing auxiliary information indicating an attribute of the data storage area and an attribute of the stored data, and a writable area in the data storage area, Serial first code data and the second
Is stored in the data storage area, and if the writable area of the data storage area is insufficient, a part or all of the second code data stored in the data storage area is discarded. A write controller that stores the first code data in the area where the discarded data is stored, and stores the auxiliary information in the auxiliary information storage area, and a free area exists in the memory. At the time, normal compressed encoded data (the first encoded data)
In addition, since the data (the second code data) lost by the compression encoding is also stored in the memory, a recording process of higher quality than the normal compression encoding can be performed. Also, even if there is not enough free space in the memory, a part of the data stored in the past that is lost by the compression coding is discarded while retaining the normal compressed and coded data, and the free space is left in the memory. Since the recording process is secured and the recording process is continued, at least the recording process of the quality of normal compression encoding can be performed.

As described above, according to the present invention, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. In addition, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used.

FIG. 6 is a block diagram showing a configuration of a digital signal reproducing apparatus according to a second embodiment of the present invention. FIG.
, 21 stores a data storage area in which code data recorded as in the first embodiment is stored, an attribute of the data storage area, and auxiliary information indicating an attribute of the stored data. A solid-state memory 22 having an auxiliary information storage area and a first code data stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area; Are read sequentially, and if the second code data is present in the data storage area, the read controller 23 also reads the second code data. The read controller 23 reads the second code data. A decoder 24 for decoding the first code data is an adder for outputting a sum signal of the output signal of the decoder 23 and the second code data. Here, the decoder 23
This is the same as the decoder 12 in the first embodiment.

The operation of the digital signal reproducing apparatus configured as described above will be described below with reference to FIGS. 6, 3 and 5.

In FIG. 6, first, the reading controller 22
Reads the attribute of the data storage area and the auxiliary information indicating the attribute of the stored data from the auxiliary information storage area of the solid-state memory 21. For example, the auxiliary information as shown in FIG. 3 is read. Here, the storage area for the first code data is allocated from address 00000 to address 0FFFF, and the storage area for the second code data is allocated from address 10000 to address 2FFFF. Is 4 bits per sample, the second code data is 8 bits per sample, the first code data is stored from address 000000 to address 04000, and the second code data is , From the address 10000 to the address 18000, the first code data and the second code data are stored for all times from the recording start time to the recording end time. You can see that. Therefore, the reading controller 22 sequentially reads the first code data and the second code data stored in the data storage area, and reads the first code data and the second code data.
To the decoder 23, and the second code data to the adder 24. Here, the timing at which the second encoded data is transmitted is delayed by that time in consideration of the time required for the decoding process by the decoder 23 and transmitted. The decoder 23 receives the read first code data and decodes it into the original digital signal. The adder 24 generates a reproduction signal by performing an addition process on the output signal of the decoder 23 and the read second code data.

The auxiliary information shown in FIG.
This is the case where the recording process is completed before the data storage area of the memory becomes full.
If the recording process is not completed before the data storage area becomes full, the auxiliary information as shown in FIG. 5 is stored in the auxiliary information storage area. In FIG. 5, the storage area of the first code data is address 00
000 to address 0FFFF, and the storage area for the second code data is at address 1000
0 to address 2FFFF, the first code data is 4 bits per sample,
The second code data is 8 bits per sample, the first code data is stored from address 000000 to address 14000, and the second code data is stored from address 14001 to address 2FFFF. Of the second code data, the address 10000 to the address 1400
It can be seen that the data stored up to 0 has been discarded. Based on this, the read controller 22 sequentially reads the first code data and the second code data stored in the data storage area, and sends the first code data to the decoder 23. , The second code data to the adder 24
To send to. Since the second code data is an 8-bit code, the fact that the data stored from address 10000 to address 14000 has been discarded means that the data from the start of recording to the 4000th sample has been discarded. Therefore, the second code data is
Reading is started from the 4001st sample. here,
The timing at which the second code data is sent is determined by the decoder 2
3. In consideration of the time required for the decoding process, the transmission is delayed by the time. The decoder 23 receives the read first code data and decodes it into the original digital signal. The adder 24 generates a reproduction signal by performing an addition process on the output signal of the decoder 23 and the read second code data.

As described above, according to this embodiment, the code data recorded as in the first embodiment is stored.
A solid-state memory having a data storage area, an auxiliary information storage area for storing an attribute of the data storage area and an auxiliary information indicating an attribute of the stored data, and a memory based on the auxiliary information stored in the auxiliary information storage area. Reading control for sequentially reading out the first code data stored in the data storage area, and also reading out the second code data if the second code data exists in the data storage area. Decoder, a decoder for decoding the first code data read by the read controller, and an addition for outputting a sum signal of an output signal of the decoder and the second code data. From the solid-state memory in which, in addition to the normal compressed encoded data (the first encoded data), data (the second encoded data) lost by the compression encoding is also stored in the memory. , It reads the encoded data of the ordinary,
Since normal decoded data is obtained, data lost due to the compression encoding is also read out, and the data is added, so that a reproduced signal with higher quality than ordinary compression encoding can be obtained. Even if the recording time is long and only normal compressed and encoded data exists in the data storage area, at least,
A reproduction signal having the quality of normal compression encoding is obtained.

FIG. 7 is a block diagram showing the configuration of a digital signal recording apparatus according to a third embodiment of the present invention. FIG.
, 31 is a first encoder for compressing and encoding a 16-bit input digital signal into first code data, 32
Is a first decoder for decoding the first coded data into the original digital signal, 33 encodes the input digital signal by the first coder 31 and further converts the coded data to the first digital data.
A delay unit 34 for delaying the input digital signal by the time required for the decoding of the original digital signal by the decoder 32, the output signal of the first decoder 32 and the output of the delay unit 33 A subtractor that outputs a difference signal from the signal as second code data; 35, a second encoder that encodes an output signal of the subtractor 34 as third code data;
A data storage area for storing the first code data and the third code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data. The solid-state memory 37 has a writable area in the data storage area.
The first code data and the third code data are stored in the data storage area, and when the writable area of the data storage area becomes insufficient, the third code data stored in the data storage area is stored. A write controller for discarding a part or all of the code data of the above, storing the first code data in the area where the discarded data is stored, and storing the auxiliary information in the auxiliary information storage area. is there. Here, the first encoder 31 is configured to perform PCM, ADPCM, C
Any conventional encoder such as an ELP may be used. Also, the first decoder 32
This is a decoder corresponding to the first encoder 31. Here, it is assumed that the data storage area is a memory having a storage capacity of 8 bits per address.

FIG. 8 is a diagram showing a state of the data storage area when the recording process is completed before the data storage area of the solid-state memory 36 becomes full.

FIG. 9 is a diagram showing the state of the auxiliary information storage area when the recording process is completed before the data storage area of the solid-state memory 36 becomes full.

FIG. 10 is a diagram showing the state of the data storage area when the data storage area of the solid-state memory 36 is full and the recording process has been continued for a while, and then the recording process has been completed.

FIG. 11 is a diagram showing the state of the auxiliary information storage area when the data storage area of the solid-state memory 36 has reached the memory full state and the recording processing has continued for a while, and then the recording processing has been completed.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIGS.

In FIG. 7, first, for example, an input digital signal of 16 bits for each sample is compression-encoded by the first encoder 31 into 4 bits for each sample. The first decoder 32 decodes the first encoded data output from the first encoder 31 into an original digital signal. In the delay unit 33, the time T required for the compression encoding and decoding is calculated.
Only the input digital signal is delayed. The subtractor 34 outputs a difference signal between the output signal of the first decoder 32 and the output signal of the delay unit 33 as second code data. The second encoder 35 compression-encodes the difference signal into two bits for each sample. The write controller 37 stores the first code data and the third code data in the data storage area in the solid-state memory 36 while the data storage area in the solid-state memory 36 has a free area. .

Here, since the first code data is 4 bits per sample, the code data of 2 samples is arranged in 8 bits and stored in one address, and the third code data is 1 sample. 2 bits per
It is assumed that the code data of the sample is arranged in 8 bits and stored at one address. The first code data is sequentially stored in the data storage area from the address number 000000 to the address number 1FFFF, and the third code data is stored in the data storage area at the address number 20000.
From the address 2FFFF. If the data storage area has only 30000 addresses, the first code data is a signal of 4 bits per sample, and the third code data is
This is because, since each sample is a 2-bit signal, the area in which the first code data is stored needs to be twice as large as the area in which the third code data is stored.

By performing such a writing process, until the data storage area of the solid-state memory 36 becomes full memory,
FIG. 8 is a diagram showing a state of the data storage area when the recording process is completed. In FIG. 8, D1 (t) represents first code data at time t, and D3 (t) represents third code data at time t. FIG. 9 shows a state of the auxiliary information storage area in such a case. Here, the storage area of the first code data is the address 0000.
0 to address 1FFFF, the storage area of the third code data is allocated from address 20000 to address 2FFFF, the first code data is 4 bits per sample, and the third code data The data is 2 bits per sample and the first
Code data from address 000000 to address 08
000, indicating that the third code data is stored from address 20,000 to address 24000. If the recording process is not completed before the data storage area of the solid-state memory 36 becomes full, the write controller 37 stores only the first code data in the data storage area of the solid-state memory 36. I will do it. At this time, the first code data is converted from address number 20000 of the data storage area to address number 2
The data is sequentially stored in the area of FFFF. by this,
The third code data stored in the area from the address number 20000 to the address number 2FFFF is gradually discarded, and the first code data is stored in the discarded area. After that, the recording time can be extended.

FIG. 10 shows the state of the data storage area in the case where data is recorded even after the data storage area of the solid-state memory 36 has reached the memory full state by performing such a write process. In FIG. 10, D1 (t) is the time t
, And D3 (t) represents the third code data at time t. In this example, since the first code data is stored up to the address 24000, of the third code data stored in the past, the address 2 is stored.
It is shown that what has been stored from 0000 to address 24000 has been discarded. FIG. 11 shows the state of the auxiliary information storage area in such a case. Here, the storage area for the first code data is allocated from address 00000 to address 1FFFF, and the storage area for the third code data is address 20
000 to address 2FFFF, the first code data is 4 bits per sample, the third code data is 2 bits per sample, and the first code data is from address 000000 The third code data is stored from address 24001 to address 2FFFF.
Since the third code data is stored from address 20000 to address 24
It can be seen that the data stored up to 000 has been discarded.

As described above, according to the present embodiment, the first encoder that encodes the input digital signal into the first code data, and decodes the first code data into the original digital signal And a time required for encoding the input digital signal by the first encoder and decoding the encoded data to the original digital signal by the first decoder. A delay unit that delays the input digital signal by an amount corresponding to the input signal; a subtractor that outputs a difference signal between the output signal of the first decoder and the output signal of the delay unit as second code data; A second encoder for encoding the output signal as third code data, a data storage area for storing the first code data and the third code data, and an attribute of the data storage area And auxiliary information indicating attributes of the stored data. The first code data and the third code data are stored in the data storage area while the data storage area has a solid-state memory having an auxiliary information storage area for storing data. If the writable area of the data storage area is insufficient,
A part or all of the third code data stored in the data storage area is discarded, and the first code data is stored in an area where the discarded data is stored. In the auxiliary information storage area, and when there is a free area in the memory, normal compression encoded data (the first code data)
In addition, since data lost by the compression encoding (the second code data) is also compression-encoded and stored in the memory, higher quality recording processing can be performed than ordinary compression encoding. Further, even when the free space in the memory is insufficient, the data which has been stored in the past and which is lost by the normal compression encoding and which has been compressed and encoded while retaining the normal compression encoded data (the third data described above). A part of the code data) is discarded, a free area is secured in the memory, and the recording process is continued, so that at least the recording process of the normal compression encoding quality can be performed. Further, since the data lost by the normal compression encoding is compression-encoded, the recording process can be performed for a longer time than the case shown in the first embodiment.

As described above, according to this embodiment, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. In addition, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used.

FIG. 12 is a block diagram showing the configuration of a digital signal reproducing apparatus according to the fourth embodiment of the present invention. In FIG. 12, reference numeral 41 denotes a data storage area in which code data recorded as in the third embodiment is stored, an attribute of the data storage area, and auxiliary information indicating an attribute of the stored data. The solid-state memory 42 having the auxiliary information storage area to be stored and similar to the third embodiment, the first solid-state memory 42 stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. A read controller for sequentially reading the code data, and if the third code data is present in the data storage area, a read controller for reading the third code data. A first decoder that decodes the first code data thus obtained,
44 is a second decoder for decoding the third code data read by the reading controller, 45 is a first decoder
Is an adder that outputs a sum signal of the output signal of the decoder 43 and the output signal of the second decoder 44. Here, the first
Is the same as the first decoder 32 in the third embodiment.

The operation of the digital signal reproducing apparatus configured as described above will be described below with reference to FIGS. 12, 9 and 11.

In FIG. 12, first, the reading controller 4
2 reads, from the auxiliary information storage area of the solid-state memory 41, auxiliary information indicating the attribute of the data storage area and the attribute of the stored data. For example, the auxiliary information as shown in FIG. 9 is read. Here, the storage area of the first code data is from address 00000 to address 1FFFF
, The storage area for the third code data is allocated from address 20000 to address 2FFFF, the first code data is 4 bits per sample, and the third code data is 1 bit. Since it is 2 bits per sample, the first code data is stored from address 00000 to address 08000, and the third code data is stored from address 20000 to address 24000. It can be seen that the first code data and the third code data are stored for all times from the recording start time to the recording end time. Therefore, the reading controller 42 sequentially reads the first code data and the third code data stored in the data storage area, and reads the first code data and the third code data.
Is transmitted to the first decoder 43, and the third code data is transmitted to the second decoder 44.

Here, the timing at which the third code data is transmitted is determined in consideration of the time required for the decoding process by the first decoder 43 and the time required for the decoding process by the second decoder 44. , Delay (or advance) by the time difference
Send out. The first decoder 43 receives the read first code data and decodes it into the original digital signal. In the second decoder 44, the read third
Receiving the coded data of
To the encoded data of. The adder 45 performs a process of adding the output signal of the first decoder 43 and the output signal of the second decoder 44 to generate a reproduced signal.

The auxiliary information shown in FIG.
In this case, the recording process has been completed before the data storage area of the solid state memory 41 becomes full.
If the recording process has not been completed before the data storage area becomes full, the auxiliary information as shown in FIG. 11 is stored in the auxiliary information storage area.
In FIG. 11, the storage area of the first code data is allocated from address 00000 to address 1FFFF, and the storage area of the third code data is address 200.
00 to address 2FFFF,
The first code data is 4 bits per sample, the third code data is 2 bits per sample, and the first code data is stored from address 000000 to address 24000. 3 indicates that the code data is stored from the address 24001 to the address 2FFFF. Therefore, of the third code data, from the address 20000 to the address 2400
It can be seen that the data stored up to 0 has been discarded. Based on this, the reading controller 42 sequentially reads out the first code data and the third code data stored in the data storage area, and reads the first code data into the first decoder 43. And the third code data is transmitted to the second
To the decoder 44. Since the third code data is a 2-bit code, the fact that the data stored from address 20,000 to address 24000 is discarded means that the data from the start of recording to the 4 × 4000th sample is discarded. The third
Is read from the 4 × 4001 sample. Here, the timing at which the third code data is transmitted is determined by considering the time required for the decoding process in the first decoder 43 and the time required for the decoding process in the second decoder 44. Delay (or advance) the difference
Send out. The first decoder 43 receives the read first code data and decodes it into the original digital signal. In the second decoder 44, the read third
Receiving the coded data of
To the encoded data of. The adder 45 performs a process of adding the output signal of the first decoder 43 and the output signal of the second decoder 44 to generate a reproduced signal.

As described above, according to the present embodiment, the code data recorded as in the third embodiment is stored.
A solid-state memory having a data storage area, an attribute of the data storage area, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; Reading control means for sequentially reading the first code data stored in the data storage area, and also reading the third code data if the third code data exists in the data storage area. Device, a first decoder for decoding the first code data read by the read controller, and a decoder for decoding the third code data read by the read controller And a second decoder that outputs a sum signal of the output signal of the first decoder and the output signal of the second decoder. (The first
In addition to the compressed data, the data lost due to the compression encoding is also read out from the solid-state memory in which ordinary compressed encoded data is read out to obtain ordinary decoded data, and the compressed encoded data is obtained. Since the data (third code data) obtained by encoding the data lost due to the above is also read, and it is decoded and added, a reproduced signal having higher quality than ordinary compression encoding can be obtained. Even if the recording time is long and only normal compression coded data is present in the data storage area, at least a reproduction signal of the normal compression coded quality can be obtained.

FIG. 13 is a block diagram showing the configuration of a digital signal recording / reproducing apparatus according to the fifth embodiment of the present invention. In FIG. 13, reference numeral 51 denotes a first encoder for compressing and encoding, for example, a 16-bit input digital signal into first code data, and 52 a first encoder for decoding the first code data into an original digital signal. The first decoder 53 encodes the input digital signal with the first encoder 51 and further converts the encoded data into the original digital signal with the first decoder 52 in a time required for processing. A delayer that delays the input digital signal only by a delay, a subtractor that outputs a difference signal between the output signal of the first decoder 52 and the output signal of the delay unit 53 as second code data, A data storage area for storing the first code data and the second code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data. Solid state memory, 6 stores the first code data and the second code data in the data storage area while the writable area exists in the data storage area, and the writable area of the data storage area is insufficient. In this case, part or all of the second code data stored in the data storage area is discarded, and the first code data is stored in the area where the discarded data is stored. And a write controller for storing the auxiliary information in the auxiliary information storage area, based on the auxiliary information stored in the auxiliary information storage area, the first code data stored in the data storage area. Is read out sequentially, and if the second code data is present in the data storage area, the read controller 58 also reads out the second code data. The output signal of the encoder 51 is sent to the first decoder 52, and at the time of read processing, the first code data stored in the solid-state memory 55 read by the read controller 57 is converted to the first code data. A multiplexer 59 that sends the signal to the decoder 52 of the first decoder 52 is an adder that outputs a sum signal of the output signal of the first decoder 52 and the second code data. Here, the first encoder 51
Any conventional encoder such as PCM, ADPCM, CELP, etc. may be used. Also,
The first decoder 52 is a decoder corresponding to the first encoder 51. Here, it is assumed that the data storage area is a memory having a storage capacity of 8 bits per address.

The operation of the digital signal recording / reproducing apparatus configured as described above will be described below with reference to FIG.

In FIG. 13, first, at the time of the recording process,
The input digital signal for every 16 bits of each sample is the first digital signal.
Are compressed and encoded into 4 bits for each sample by the encoder 51. The multiplexer 58 controls the first
Of the encoder 51 is sent to the first decoder 52. The first decoder 52 outputs from the multiplexer 58
The first coded data output from the first coder 51 is received and decoded into an original digital signal. In the delay unit 53,
The input digital signal is delayed by the time T required for the compression encoding and decoding. The subtractor 54 outputs a difference signal between the output signal of the first decoder 52 and the output signal of the delay unit 53 as second code data. Hereinafter, the operation of the write controller 56 is the same as the operation in the first embodiment already described.

Next, at the time of reproduction processing, the reading controller 57
Reads the attribute of the data storage area and the auxiliary information indicating the attribute of the stored data from the auxiliary information storage area of the solid-state memory 55, and stores the first information stored in the data storage area of the solid-state memory 55 based on the read information. And the second code data. This operation is the same as the operation in the second embodiment. Multiplexer 58
Sends the first code data read by the reading controller 57 to the first decoder 52 at the time of reproduction processing. The first decoder 52 includes a multiplexer 58
Receives the first coded data from the base station and decodes it into the original digital signal. The adder 59 performs a process of adding the output signal of the first decoder 52 and the read second code data to generate a reproduced signal.

As described above, according to the present embodiment, the first encoder that encodes the input digital signal into the first code data, and decodes the first code data into the original digital signal And a time required for encoding the input digital signal by the first encoder and decoding the encoded data to the original digital signal by the first decoder. A delay unit for delaying the input digital signal by an amount, a subtractor for outputting a difference signal between an output signal of the first decoder and an output signal of the delay unit as second code data, Having a data storage area for storing the first code data and the second code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data. Memory and the above data storage area While writable area is present,
The first code data and the second code data are stored in the data storage area, and when the writable area of the data storage area becomes insufficient, the second code data stored in the data storage area is stored. A write controller for discarding part or all of the code data of the above, storing the first code data in an area where the discarded data is stored, and storing the auxiliary information in the auxiliary information storage area. The first code data stored in the data storage area is sequentially read out based on the auxiliary information stored in the auxiliary information storage area, and if the second code data exists in the data storage area, A reading controller that also reads out the second encoded data, and outputs the output signal of the first encoder to the first decoder at the time of recording processing, and outputs the output signal of the first encoder at the time of recording processing. The first of the code data stored in the solid-state memory read by the controller Heading first
And a sum signal of the output signal of the first encoder and the second code data stored in the solid-state memory read by the reading controller. An output adder, and when there is a free area in the memory, in addition to the normal compressed encoded data (the first code data), data lost by the compression encoding (the second code) Data) is also stored in the memory, so that higher quality recording / reproducing processing can be performed than normal compression encoding. In addition, even if the memory has insufficient free space, a part of the data stored in the past that is lost due to the compression coding is discarded and the free space is secured in the memory, while the normal compression coded data is retained. Then, since the recording process is continued, at least the recording / reproducing process of the normal compression encoding quality can be performed.

As described above, according to the present invention, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. Further, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used. Moreover, at the time of recording processing, the output signal of the first encoder is sent to the first decoder, and at the time of reproduction processing, the output signal is stored in the solid-state memory read by the reading controller. The first code data is converted to the first code data.
Since the multiplexer for transmitting the data to the decoder is provided, the first decoder can be shared between the recording process and the reproducing process, and the circuit scale can be reduced.

FIG. 14 is a block diagram showing the configuration of a digital signal recording / reproducing apparatus according to the sixth embodiment of the present invention. In FIG. 14, reference numeral 61 denotes a first encoder that compresses and encodes, for example, a 16-bit input digital signal into first code data, and 62 denotes a first encoder that decodes the first code data into an original digital signal. The first decoder 63 encodes the input digital signal by the first encoder 61, and decodes the encoded data into the original digital signal by the first decoder 62 for the time required for processing. A delayer for delaying the input digital signal only by a delay; a subtractor for outputting a difference signal between an output signal of the first decoder and an output signal of the delayer as second code data; A second encoder 65 for encoding the output signal of the encoder 64 as third code data, a data storage area for storing the first code data and the third code data, Attributes of data storage area and its storage The solid-state memory 66 includes an auxiliary information storage area for storing auxiliary information indicating the attribute of the data, and the first code data and the third code data while the writable area exists in the data storage area. Code data is stored in the data storage area, and if the writable area of the data storage area becomes insufficient, a part or all of the third code data stored in the data storage area is discarded. A write controller that stores the first code data in the area where the discarded data is stored, and stores the auxiliary information in the auxiliary information storage area; The first information stored in the data storage area based on the auxiliary information
Is read out sequentially, and if the third code data is present in the data storage area, the read controller 68 also reads out the third code data. The output signal of the encoder 51 is sent to the first decoder 52, and at the time of read processing, the first code data stored in the solid-state memory 65 read by the read controller 67 is converted to the first code data. The multiplexer 611 that sends the data to the decoder 62 of the first decoder 611 is a second decoder that decodes the third code data read by the read controller 67, and the decoder 69 that is the first decoder 62 Is an adder that outputs a sum signal of the output signal of the second decoder 611 and the output signal of the second decoder 611. Here, the first encoder 61 uses PCM, ADP
Any conventional encoder such as CM, CELP, etc. may be used. The first decoder 62 is a decoder corresponding to the first encoder 61. Here, it is assumed that the data storage area is a memory having a storage capacity of 8 bits per address.

The operation of the digital signal recording / reproducing apparatus configured as described above will be described below with reference to FIG.

In FIG. 14, first, at the time of recording processing,
The 16-bit input digital signal for each sample is
The first encoder 61 compression-encodes each sample into 4 bits. At the time of recording processing, the multiplexer 68
The output of the first encoder 61 is sent to the first decoder 62. The first decoder 62 receives the first encoded data output from the first encoder 61 from the multiplexer 68, and decodes the first encoded data into the original digital signal. The delay unit 63 delays the input digital signal by the time T required for the compression encoding and decoding. The subtractor 64 outputs a difference signal between the output signal of the first decoder 62 and the output signal of the delay unit 63 as second code data. The second encoder 610 compression-encodes the difference signal into 2 bits for each sample. Hereinafter, the operation of the write controller 66 is the same as the operation in the third embodiment.

Next, at the time of reproduction processing, the reading controller 67
Reads the attribute of the data storage area and the auxiliary information indicating the attribute of the stored data from the auxiliary information storage area of the solid-state memory 65, and stores the first information stored in the data storage area of the solid-state memory 65 based on the read-out information. And the third code data. This operation is the same as the operation in the fourth embodiment already described. The multiplexer 68 sends the first code data read by the read controller 67 to the first decoder 62 during the reproduction process. The first decoder 62 receives the first encoded data from the multiplexer 68 and decodes the first encoded data into the original digital signal. The second decoder 611 receives the read third code data and decodes the read third code data into the second code data. The adder 69 performs a process of adding the output signal of the first decoder 62 and the output signal of the second decoder 611 to generate a reproduced signal.

As described above, according to the present embodiment, the first encoder that encodes the input digital signal into the first code data, and decodes the first code data into the original digital signal A first decoder for encoding, and a process for encoding an input digital signal with the first encoder and further decoding the encoded data into an original digital signal with the first decoder. A delay unit for delaying an input digital signal by a required time, a subtractor for outputting a difference signal between an output signal of the first decoder and an output signal of the delay unit, and an output of the subtractor A second encoding of the signal as third encoded data
, A data storage area for storing the first code data and the third code data, and auxiliary information indicating the attribute of the data storage area and the attribute of the stored data. While the solid-state memory having the auxiliary information storage area to be stored and the writable area in the data storage area, the first code data and the third code data are stored in the data storage area, If the writable area of the data storage area is insufficient, a part or all of the third code data stored in the data storage area is discarded, and the area where the discarded data is stored is discarded. A write controller for storing the first code data and storing the auxiliary information in the auxiliary information storage area; and the data controller based on the auxiliary information stored in the auxiliary information storage area. A reading controller for sequentially reading the first code data stored in the data storage area, and also reading the third code data if the third code data exists in the data storage area; At the time of recording processing, the output signal of the first encoder is sent to the first decoder, and at the time of reading processing, the output signal stored in the solid-state memory read by the reading controller is read. A multiplexer for transmitting the first code data to the first decoder; a second decoder for decoding the third code data read by the read controller; And an adder that outputs a sum signal of the output signal of the second decoder and the output signal of the second decoder. When there is an empty area in the memory, the normal compression encoded data (the above Compression coding in addition to the first code data) Thus the data to be lost gradually stored in the memory by the compression encoding (the second code data), high-quality recording and reproduction processing of perform than conventional compression coding. Further, even when the free space in the memory is insufficient, the data (the second code data) stored in the past and lost by the normal compression coding while maintaining the normal compression coded data is compressed and coded. A part of the data (the third code data) is discarded, an empty area is secured in the memory, and the recording process is continued, so that at least the recording and reproducing process of the normal compression encoding quality can be performed. Further, since data lost by the first compression encoding is compression-encoded, recording processing for a longer time than that shown in the fifth embodiment can be performed.

As described above, according to this embodiment, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. Further, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used. Moreover, at the time of recording processing, the output signal of the first encoder is sent to the first decoder, and at the time of reproduction processing, the output signal is stored in the solid-state memory read by the reading controller. Since the multiplexer for transmitting the first code data to the first decoder is provided, the first decoder can be shared between the recording process and the reproduction process.

FIG. 15 is a block diagram showing the configuration of a digital signal recording / reproducing apparatus according to the seventh embodiment of the present invention. In FIG. 15, reference numeral 71 denotes a first code for compressing and encoding, for example, a 16-bit input digital signal into first code data.
The first encoder 72 decodes the first encoded data into the original digital signal. The first encoder 73 encodes the input digital signal with the first encoder 71 and further encodes the input digital signal. A delay unit 74 for delaying the input digital signal by the time required for decoding the encoded data into the original digital signal by the first decoder 72, an output signal of the first decoder 71, A subtractor 75 for outputting a difference signal from the output signal of the delay unit 73 as second code data; 75 a data storage area for storing the first code data and the second code data; The solid-state memory 76 has an attribute of a data storage area and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data. Code data and the second The code data stored in the data storage area, if the writable area of the data storage area is insufficient, stored in the data storage area,
A write operation for discarding part or all of the second code data, storing the first code data in the area where the discarded data is stored, and storing the auxiliary information in the auxiliary information storage area A controller configured to sequentially read the first code data stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area;
If the second code data is present in the data storage area, the read controller 78 for reading out the second code data also performs the first encoder 71 during the recording process.
Is output to the first decoder 72, and at the time of reading processing, the first code data stored in the solid-state memory 75 read by the reading controller 77 is converted to the first decoder 72. A multiplexer 79 for sending the signal to the adder 72 is an adder for outputting a sum signal of the output signal of the first decoder 72 and the second code data. The above is the one shown in the fifth embodiment. Is similar to This embodiment is different from the fifth embodiment in that the lines shown by the broken lines in FIG. 15 are connected to each other by a detachable connector.

The operation of the digital signal recording / reproducing apparatus according to the present embodiment is the same as the operation according to the fifth embodiment already described, and the description is omitted. Generally, in the encoding and decoding of digital signals, the scale of hardware for performing decoding is smaller than the scale of hardware for performing encoding. Therefore, if the connector as described above is provided, only the part necessary for the decoding process can be carried in a compact form when only the decoding process is performed.

As described above, in this embodiment, FIG.
, The solid-state memory 75, the read controller 77, the first decoder 72, and the multiplexer 78
In the case where only the decoding process is performed by connecting the portion constituted by the adder 79 and the other portion with an optional detachable connector, the portion necessary for the decoding process is used. Only can be carried in a compact form.

FIG. 16 is a block diagram showing the configuration of a digital signal recording / reproducing apparatus according to the eighth embodiment of the present invention. In FIG. 16, reference numeral 81 denotes a first encoder that compresses and encodes, for example, a 16-bit input digital signal into first encoded data, and 82 denotes a first encoder that decodes the first encoded data into an original digital signal. The first decoder 83 encodes the input digital signal by the first encoder 81 and the time required for decoding the encoded data into the original digital signal by the first decoder 82. A delay unit 84 for delaying the input digital signal only by a delay, a subtractor 84 for outputting a difference signal between the output signal of the first decoder 82 and the output signal of the delay unit 83 as second code data, and a subtractor 810 for subtraction. A second encoder 85 for encoding the output signal of the encoder 84 as third code data, a data storage area for storing the first code data and the third code data, Data storage area attributes and their storage The solid-state memory 86 has an auxiliary information storage area for storing auxiliary information indicating the attribute of the data, and the first code data and the third code data while the writable area exists in the data storage area. Code data is stored in the data storage area, and if the writable area of the data storage area becomes insufficient, a part or all of the third code data stored in the data storage area is discarded. A write controller that stores the first code data in the area where the discarded data is stored and stores the auxiliary information in the auxiliary information storage area; The first information stored in the data storage area based on the auxiliary information
Is read out sequentially, and if the third code data is present in the data storage area, the read controller 88 also reads out the third code data. The output signal of the encoder 81 is sent to the first decoder 82, and at the time of reading processing, the first code data stored in the solid-state memory 85 read by the reading controller 87 is converted to the first code data. , A multiplexer 811 for transmitting the third code data read by the read controller 87, and a multiplexer 89 for transmitting the third code data to the first decoder 82. This is an adder that outputs a sum signal of the output signal of the second decoder 811 and the output signal of the second decoder 811. The above is the same as that shown in the sixth embodiment. This embodiment is different from the sixth embodiment in that the lines shown by the broken lines in FIG. 16 are connected by an optional detachable connector.

The operation of the digital signal recording / reproducing apparatus according to the present embodiment is the same as the operation according to the above-described sixth embodiment, and a description thereof will be omitted. Generally, in the encoding and decoding of digital signals, the scale of hardware for performing decoding is smaller than the scale of hardware for performing encoding. Therefore, if the connector as described above is provided, only the part necessary for the decoding process can be carried in a compact form when only the decoding process is performed.

As described above, in this embodiment, FIG.
, The solid-state memory 85, the read controller 87, the first decoder 82, and the second decoder 81
1, the multiplexer 88 and the adder 89, and the other parts are connected by an optional detachable connector to perform only the decoding process. Only the parts necessary for processing can be carried in a compact form.

FIG. 17 is a diagram showing a basic configuration of an encoder and a decoder in a general CELP system (code excitation type linear prediction system). The encoder of this system includes a decoder, a delay unit 93 for adjusting the phase of an output signal of the decoder and an input signal, an output signal of the delay unit 93, and an output signal of the decoder. And a subtractor 94 for obtaining a difference signal. That is, the processing of the excitation vector codebook 121 in the encoder in FIG.
Is similar to the processing of the excitation vector codebook 107 and the processing of the synthesis filter 106 in the decoder, and incorporates a subtractor for calculating the difference between the output signal of the synthesis filter and the input signal after the phase adjustment. Will be. C
Generally, not only the ELP method but also an analysis-synthesis method encoder (MPC method, LD-CELP method, VSELP method, etc.) and a predictive encoding method encoder (ADPCM method, etc.)
A decoder, a delay unit for adjusting the phase of the output signal of the decoder and the input signal, a subtractor for obtaining a difference signal between the output signal of the delay unit and the output signal of the decoder; (See, for example, "Handbook of Digital Signal Processing, ed. By the Institute of Electronics, Information and Communication Engineers, pp. 338-346, December 1993").

FIG. 18 is a block diagram showing the configuration of a digital signal recording apparatus according to the ninth embodiment of the present invention. In FIG. 18, reference numeral 91 denotes a first encoder which compresses and encodes, for example, a 16-bit input digital signal into first code data, which is a CELP encoder shown in FIG.
Reference numeral 92 denotes a first decoder configured by excitation vector codebook processing and synthesis filter processing in the CELP compression encoding process, which is built in the first encoder 91. , 93 are the first decoder 92, which is built in the first encoder 91.
A delay unit 94 for matching the phase of the output signal of the first encoder 91 with the output signal of the first decoder 92, which is built in the first encoder 91. A subtractor for obtaining a difference signal from the signal as second code data; 95, a second encoder for coding the output signal of the subtractor 94 as third code data; 96, a first code data A solid-state memory having a data storage area for storing data and the third code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data; Stores the first code data and the third code data in the data storage area while the writable area exists in the data storage area, and the writable area of the data storage area becomes insufficient. If the above Stored in over data storage area,
A part or all of the third code data is discarded, the first code data is stored in an area where the discarded data is stored, and the auxiliary information is stored in the auxiliary information storage area. Write controller.

FIG. 19 is a diagram showing a state of the data storage area when the recording process is completed before the data storage area of the solid-state memory 96 becomes full.

FIG. 20 is a diagram showing the state of the auxiliary information storage area when the recording process is completed before the data storage area of the solid-state memory 96 becomes full.

FIG. 21 is a diagram showing the state of the data storage area when the data storage area of the solid-state memory 96 is full and the recording process has been continued for a while, and then the recording process has been completed.

FIG. 22 is a diagram showing the state of the auxiliary information storage area when the data storage area of the solid-state memory 96 is full and the recording processing is continued for a while, and then the recording processing is completed.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 18, first, one sample is set for each sample.
The 6-bit input digital signal is supplied to a first encoder 91.
Is compressed and encoded as first code data at a bit rate of 8 kb / s. At this time, at the same time, the output signal of the subtractor 94 (the second signal) for obtaining the difference signal between the output signal of the first decoder 92 and the output signal of the delay unit 93, which is generated in the process of encoding by the encoder 91, Is encoded by the second encoder 95 as third encoded data at a bit rate of 16 kb / s. The write controller 97 stores the first code data and the third code data in the data storage area in the solid-state memory 96 as long as there is a free area in the data storage area in the solid-state memory 96. . Here, the first code data is from the address number 000000 to the address number 0FF of the data storage area.
The third code data is sequentially stored in the FF area, and the third code data is sequentially stored in the data storage area from the address number 10000 to the address number 2FFFF.
If the data storage area has only 30000 addresses, the first code data is 8 kp / s bit rate coded data, and the third code data is 16 kp / s.
Since the encoded data has a bit rate of p / s, the third
Is required twice as large as the area in which the first code data is stored.

By performing such a writing process, until the data storage area of the solid-state memory 96 becomes full memory,
FIG. 19 shows the state of the data storage area when the recording process is completed. FIG. 20 shows a state of the auxiliary information storage area in such a case. Here, the storage area of the first code data is allocated from address 00000 to address 0FFFF, and the storage area of the third code data is from address 10000 to address 2
Up to FFFF, the first code data is compression-coded at a bit rate of 8 kb / s, and the third code data is compression-coded at a bit rate of 16 kb / s. The first code data is stored from address 00000 to address 04000, and the third code data is stored at address 100
This indicates that the data is stored from 00 to the address 18000. If the recording process is not completed before the data storage area of the solid-state memory 96 becomes full, the write controller 97 stores only the first code data in the data storage area of the solid-state memory 96. I will do it. At this time, the first code data is sequentially stored in the data storage area from the address number 10000 to the address number 2FFFF. As a result, the third code data stored in the area from the address number 10000 to the address number 2FFFF is gradually discarded, and the first code data is stored in the discarded area. Even after the memory becomes full, the recording time can be extended.

FIG. 21 is a diagram showing a state of the data storage area when data is recorded even after the data storage area of the solid-state memory 96 has reached the memory full state by performing such a writing process. FIG. 22 shows a state of the auxiliary information storage area in such a case. Here, the storage area of the first code data is allocated from address 00000 to address 0FFFF, and the storage area of the third code data is from address 10000 to address 2
FFFF are allocated, the first code data is compression-coded at a bit rate of 8 kb / s, and the third code data is compression-coded at a bit rate of 16 kb / s. The first code data is stored from address 00000 to address 14000, and the third code data is stored at address 140
01 to address 2FFFF, and therefore, of the third code data, address 1
It can be seen that the data stored from 0000 to address 14000 has been discarded.

As described above, according to the present embodiment, the first encoder of the analysis / synthesis method for encoding the input digital signal into the first code data and the first code data of the first code data are converted to the original digital data. An output signal of the first decoder, an output signal of the first decoder, and an input signal, which are built in the first encoder of the analysis and synthesis method, which decodes the signal. An output signal of a subtractor incorporated in the first encoder for obtaining a difference signal from an output signal of a delay unit incorporated in the first encoder for adjusting the phase of the signal A second encoder for encoding (second code data) as third code data, a data storage area for storing the first code data and the third code data, Stores attributes of the data storage area and auxiliary information indicating the attributes of the stored data A solid-state memory having an auxiliary information storage area and a writable area in the data storage area, the first code data and the third code data are stored in the data storage area; If the writable area of the data storage area is insufficient, a part or all of the third code data stored in the data storage area is discarded, and the area where the discarded data is stored is discarded. A write controller for storing the first encoded data and storing the auxiliary information in the auxiliary information storage area, and when there is a free area in the memory, the normal compressed encoded data (the first compressed Code data), the data (the second code data) lost by the compression encoding is also compression-encoded and stored in the memory, so that the quality is higher than that of the normal compression encoding. Recording processing can be performed. Also, even when the memory space is insufficient, the normal compression-encoded data is retained, and a part of the data stored in the past that has been compressed and encoded for the data lost by the normal compression-encoding is discarded. Then, since a free area is secured in the memory and the recording process is continued, at least the recording process of the quality of the normal compression encoding can be performed.

As described above, according to this embodiment, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. In addition, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used.

FIG. 23 is a block diagram showing a configuration of a digital signal reproducing apparatus according to the tenth embodiment of the present invention.
In FIG. 23, reference numeral 101 denotes a data storage area in which code data recorded as in the ninth embodiment is stored;
The solid-state memory 102 having the attribute of the data storage area and the auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data, similar to the ninth embodiment, is stored in the auxiliary information storage area. The first code data stored in the data storage area is sequentially read out based on the obtained auxiliary information, and if the third code data exists in the data storage area, the third code data is read out. Is a reading controller for decoding the first code data read by the reading controller 102, and 104 is a reading controller for the analysis / synthesis method. A second decoder 105 for decoding the third code data read at 102 is a sum of an output signal of the first decoder 103 and an output signal of the second decoder 104. With an adder that outputs a signal That. Here, the first decoder 10
Reference numeral 3 is the same as the first decoder 92 built in the first encoder 91 in the ninth embodiment described above.

The operation of the digital signal reproducing apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 23, first, the reading controller 1
In step 02, the auxiliary information indicating the attribute of the data storage area and the attribute of the stored data is read from the auxiliary information storage area of the solid-state memory 101. For example, the auxiliary information as shown in FIG. 20 is read. Here, the storage area of the first code data is from address 00000 to address 0F.
FFF is allocated, and the storage area of the third code data is from address 10000 to address 2FFFF.
And the first code data is 8 kb.
/ S compression-coded at a bit rate of / s, the third code data is compression-coded at a bit rate of 16 kb / s, and the first code data is from an address 000000 to an address 04000. Since the third code data is stored from address 10000 to address 18000, the first code data is stored for all times from the recording start time to the recording end time. It can be seen that the code data and the third code data are stored. Therefore, the reading controller 102 sequentially reads the first code data and the third code data stored in the data storage area,
Sending the first coded data to the first decoder 103;
The third coded data is sent to the second decoder 104. Here, the timing at which the third encoded data is transmitted is determined by considering the time required for the decoding process by the first decoder 103 and the time required for the decoding process by the second decoder 104. The data is transmitted after being delayed (or advanced) by the difference. The first decoder 103 receives the read first code data and decodes it into an original digital signal. The second decoder 104 receives the read third code data and decodes it into the second code data in the ninth embodiment. The adder 105 performs a process of adding the output signal of the first decoder 103 and the output signal of the second decoder 104 to generate a reproduced signal.

The auxiliary information shown in FIG.
By the time the data storage area 01 becomes full memory,
In the case where the recording process is completed, if the recording process is not completed before the data storage area of the solid-state memory 101 becomes full, the auxiliary information as shown in FIG. It is stored in the auxiliary information storage area. In FIG. 22, the storage area of the first code data is
Addresses from 00000 to address 0FFFF are allocated, a storage area for the third code data is allocated from addresses 10000 to 2FFFF, and the first code data is compression-coded at a bit rate of 8 kb / s. The third code data is compression-coded at a bit rate of 16 kb / s, and the first code data is stored from address 000000 to address 14000. Code data is from address 14001 to address 2FFF
F of the third code data from address 10000 to address 1 of the third code data.
It can be seen that the data stored up to 4000 has been discarded. Based on that, the reading controller 102
Reads out the first code data and the third code data stored in the data storage area sequentially, sends the first code data to the first decoder 103, and outputs the third code data. To the second decoder 104. Since the third code data is coded at a bit rate of 16 kb / s, the auxiliary information indicates that the data stored from address 10000 to address 14000 has been discarded. Based on the information, the time of the discarded data is calculated, and the third code data is not read at that time. Here, the timing at which the third encoded data is transmitted is determined by considering the time required for the decoding process by the first decoder 103 and the time required for the decoding process by the second decoder 104. The data is transmitted after being delayed (or advanced) by the difference. The first decoder 103 receives the read first code data and decodes it into an original digital signal. The second decoder 104 receives the read third code data and decodes it into the second code data in the ninth embodiment. The adder 105 performs an addition process on the output signal of the first decoder 103 and the output signal of the second decoder 104,
Generate a playback signal.

As described above, according to this embodiment, the code data recorded as in the first embodiment is stored.
A solid-state memory having a data storage area, an attribute of the data storage area, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; Reading control means for sequentially reading the first code data stored in the data storage area, and also reading the third code data if the third code data exists in the data storage area. Device, a first decoder for decoding the first code data read by the read controller, and a decoder for decoding the third code data read by the read controller And a second decoder that outputs a sum signal of the output signal of the first decoder and the output signal of the second decoder. (The first
In addition to the normal compressed data, solid-state memory in which data lost by the compression encoding is also compressed and stored is read to obtain ordinary decoded data, and the compressed code is obtained. Also, data obtained by compression-encoding data that has been lost due to encoding is read, decoded, and added, so that a reproduced signal with higher quality than ordinary compression-encoding can be obtained. Even if the recording time is long and only normal compression coded data is present in the data storage area, at least a reproduction signal of the normal compression coded quality can be obtained.

FIG. 24 is a block diagram showing the configuration of a digital signal recording apparatus according to the eleventh embodiment of the present invention.
In FIG. 24, reference numeral 111 denotes a first encoder that compresses and encodes, for example, a 16-bit input digital signal into first code data, and 112 denotes a first encoder that decodes the first code data into an original digital signal. The first decoder 113 encodes the input digital signal by the first encoder 111 and further decodes the encoded data into the original digital signal by the first decoder 112. A delay unit 114 for delaying the input digital signal only by the first decoder 112
The difference signal between the output signal of
A second encoder for encoding the output signal of the subtractor 114 as third code data, and a subtractor 116 for encoding the output signal of the subtractor 114 as third code data. The solid-state memory 117 includes a data storage area for storing data and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data. While the writable area exists, the first code data and the third code data are stored in the data storage area. If the writable area of the data storage area becomes insufficient, the data storage A part or all of the third code data stored in the area is discarded, and the first code data is stored in the area where the discarded data is stored. The information is a write controller for storing in the auxiliary information storage area. Here, the first encoder 111 is a variable bit rate encoder that adaptively changes the encoding bit rate according to the properties of the input digital signal. Also, the second encoder 115 outputs the second
Is a variable bit rate encoder that adaptively changes the encoding bit rate according to the nature of the encoded data.

FIG. 25 is a diagram showing the state of the data storage area when the recording process is completed before the data storage area of the solid-state memory 116 becomes full.

FIG. 26 is a diagram showing the state of the auxiliary information storage area when the recording process is completed before the data storage area of the solid-state memory 116 becomes full.

FIG. 27 is a diagram showing the state of the data storage area when the data storage area of the solid-state memory 116 has reached the memory full state and the recording processing has continued for a while, and then the recording processing has been completed.

FIG. 28 is a diagram showing the state of the auxiliary information storage area when the data storage area of the solid-state memory 116 has reached the memory full state and the recording processing has continued for a while, and then the recording processing has been completed.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
8 will be described.

In FIG. 24, first, one sample is set for each sample.
The 6-bit input digital signal is supplied to the first encoder 11
1, the data is compression-coded as first code data at a variable bit rate. The first decoder 112 decodes the first coded data output from the first coder 111 into an original digital signal. The delay unit 113 delays the input digital signal by a time T required for the compression encoding and decoding. In the subtractor 114, the first decoder 112
The difference signal between the output signal of
Is output as code data of. Second encoder 115
Compresses and encodes the difference signal as third code data at a variable bit rate. The write controller 117 stores the first code data and the third code data in the data storage area in the solid-state memory 116 while the data storage area in the solid-state memory 116 has a free area. . Here, the first code data is sequentially stored in the direction from the address number 000000 to the address number 30000 of the data storage area, and the third code data is stored from the address number 30000 to the address number 000000 of the data storage area.
Are stored sequentially in the direction of. This is the first
Since both the first code data and the third code data are code data encoded at a variable bit rate, the ratio between the first code data and the third code data is stored in the memory. Can not be determined in advance,
This is because a memory area cannot be allocated to each of them at a specific ratio in advance.

FIG. 25 is a diagram showing a state of the data storage area when the recording processing is completed until the data storage area of the solid-state memory 116 is in a memory full state by performing such a write processing. FIG. 26 shows a state of the auxiliary information storage area in such a case. Here, the first code data is stored from address 00000 to address 18000, and the third code data is stored from address 2FFFF to address 20000. Here, the determination as to whether the data storage area is in the memory full state can be made by comparing the total amount of the stored code data with the memory capacity, or the current write address of the first code data and the current write address. The third code data may be detected by detecting a difference from the write address of the third code data.
If the recording process is not completed before the data storage area of the solid-state memory 116 becomes full, the write controller 117 continues to store only the first code data in the data storage area in the solid-state memory 116. Are sequentially stored in the method of the address number 30000. As a result, the third code data already stored in the area in the direction of the address number 30000 is gradually discarded, and the first code data is stored in the discarded area. The recording time can be extended even after the state has been reached.

FIG. 27 shows the state of the data storage area in the case where data is recorded even after the data storage area of the solid-state memory 116 has reached the memory full state by performing such a writing process. In this example, since the first code data is stored up to the address 24000, of the third code data, the address 2FFFF to the address 240
Those other than those stored in 01 are discarded. FIG. 28 shows a state of the auxiliary information storage area in such a case. Here, the first code data is stored from address 00000 to address 24000, and the third code data is stored at address 2FF.
Since it indicates that data is stored from the FF to the address 24001, it can be seen that, of the third code data, data other than the above-mentioned data has been discarded.

As described above, according to the present embodiment, the first encoder for encoding the input digital signal into the first code data, and the first encoder for decoding the first code data into the original digital signal A first decoder that encodes the input digital signal with the first encoder, and further encodes the encoded data with the first encoder.
And a delay unit for delaying the input digital signal by the time required for decoding to the original digital signal by the decoder, and a difference between the output signal of the first decoder and the output signal of the delay unit. A subtractor for outputting a signal as second code data; a second encoder for coding an output signal of the subtracter as third code data; a first code data and the third code A solid-state memory having a data storage area for storing data, an attribute of the data storage area, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; and writing to the data storage area. While the available area exists, the first code data and the third code data are stored in the data storage area. If the writable area of the data storage area becomes insufficient,
A part or all of the third code data stored in the data storage area is discarded, and the first code data is stored in an area where the discarded data is stored. And a write controller for storing the first code data in the data storage area of a continuous address space from address A to address B. From the address A of the storage area to the address B, the third code data is stored from the address B to the address A of the data storage area, and the free space is stored in the data storage area. Is lost, the writing process of the third code data is stopped,
By storing the first code data in the direction of the address B successively, when there is a free area in the memory, the first code data is stored in addition to the normal compressed coded data (the first code data). Since data lost by compression encoding (the second code data) is also compression-encoded and stored in the memory, higher quality recording processing can be performed than normal compression encoding. Further, even when the free space in the memory is insufficient, while the normal compression-encoded data is held, the data stored in the past and lost by the normal compression-encoding and compressed and encoded (the third data described above). A part of the code data) is discarded, a free area is secured in the memory, and the recording process is continued, so that the recording process of at least normal compression encoding quality can be performed.

As described above, according to this embodiment, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. In addition, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used. In addition, if a data storage method such as the write controller is adopted, data management (particularly the third method) can be performed even on data encoded at a variable bit rate.
(Code data discarding process) can be easily performed.

[0097]

As described above, the digital signal recording apparatus according to the first aspect of the present invention comprises an encoder for encoding an input digital signal into first encoded data, and an encoder for converting the first encoded data into an original digital signal. And a decoder that decodes the input digital signal by the encoder, and further delays the input digital signal by a time required for a process of encoding the input digital signal by the encoder and decoding the encoded data to the original digital signal by the decoder. A delay unit that outputs a difference signal between an output signal of the decoder and an output signal of the delay unit as second code data;
Having a data storage area for storing the first code data and the second code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data. While the memory and the writable area exist in the data storage area, the first code data and the second code data are stored in the data storage area, and the writable area of the data storage area is insufficient. If it has been stored in the data storage area,
A write operation for discarding a part or all of the second code data, storing the first code data in an area where the discarded data is stored, and storing the auxiliary information in the auxiliary information storage area When there is a free area in the memory, a normal compressed and coded data (the first
In addition, the data (the second code data) lost by the compression encoding is also stored in the memory in addition to the compression encoding, so that a higher quality recording process than the normal compression encoding can be performed. Also, even if there is not enough free space in the memory, a part of the data stored in the past that is lost by the compression coding is discarded while retaining the normal compressed and coded data, and the free space is left in the memory. Since the recording process is secured and the recording process is continued, at least the recording process of the quality of normal compression encoding can be performed.

As described above, according to the present invention, it is possible to efficiently extend the recording time while maintaining the recording quality as much as possible. In addition, since the data is effectively stored in the solid-state memory while maintaining the recording quality as much as possible, the memory of the solid-state memory can be effectively used.

Further, a digital signal reproducing apparatus according to a second aspect of the present invention includes a data storage area storing code data recorded by the digital signal recording apparatus according to the first aspect of the present invention, an attribute of the data storage area, A solid-state memory having an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; and a first memory stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. Are read out sequentially, and if the second code data is present in the data storage area, the read controller also reads the second code data, and the read controller reads the second code data. A decoder that decodes the first encoded data, and an adder that outputs a sum signal of the output signal of the decoder and the second encoded data. Up In addition to the first encoded data), the normal compressed encoded data is read out from the solid-state memory in which the data lost by the compression encoding (the second encoded data) is also stored in the memory. Since the decoded data is obtained, the data lost by the compression encoding is also read, and the data is added, so that a reproduced signal having higher quality than that of the normal compression encoding can be obtained. If the recording time is long,
Even if only normal compression-encoded data exists in the data storage area, it is possible to obtain a reproduction signal of at least normal compression-encoding quality.

Further, a digital signal recording apparatus according to a third aspect of the present invention includes a first encoder for encoding an input digital signal into first code data, and decoding the first code data into an original digital signal. A first decoder for encoding, and a process of encoding the input digital signal by the first encoder and decoding the encoded data to an original digital signal by the first decoder. A delay unit that delays an input digital signal by a time, a subtractor that outputs a difference signal between an output signal of the first decoder and an output signal of the delay unit as second code data, and the subtractor A second encoder for encoding the output signal of the third as the third code data, a data storage area for storing the first code data and the third code data, Attributes and attributes of the stored data A solid-state memory having an auxiliary information storage area for storing auxiliary information, and the first code data and the third code data are stored in the data storage area while a writable area exists in the data storage area. If the writable area of the data storage area becomes insufficient, a part or all of the third code data stored in the data storage area is discarded, and the discarded data is stored. A write controller for storing the first encoded data in the area where the data has been stored, and for storing the auxiliary information in the auxiliary information storage area. In addition to the (first code data), data (the second code data) lost by the compression coding is also compression-coded and stored in the memory. It can be carried out high-quality recording process than the reduction. Further, even when the free space in the memory is insufficient, the data which has been stored in the past and which is lost by the normal compression encoding and which has been compressed and encoded while retaining the normal compression encoded data (the third data described above). A part of the code data) is discarded, a free area is secured in the memory, and the recording process is continued, so that at least the recording process of the normal compression encoding quality can be performed. Further, since the data lost by the normal compression encoding is compression-encoded, the recording process can be performed for a longer time than in the first aspect.

A digital signal reproducing apparatus according to a fourth aspect of the present invention includes a data storage area storing code data recorded by the digital signal recording apparatus according to the third aspect of the present invention, an attribute of the data storage area, A solid-state memory having an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; and a first memory stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. Are sequentially read, and if the third code data is present in the data storage area, the read controller also reads the third code data, and the read controller reads the third code data. A first decoder that decodes the first code data, a second decoder that decodes the third code data read by the reading controller, and a first decoder that decodes the third code data. The decoder An adder that outputs a sum signal of the output signal and the output signal of the second decoder, and in addition to the normal compressed encoded data (the first encoded data), The normal compressed and encoded data is read out from the solid-state memory in which the lost data is also stored in a compressed state, and the normal decoded data is obtained. Is read out, decoded, and added, so that a reproduced signal having higher quality than that of normal compression encoding can be obtained. Even if the recording time is long and only normal compression coded data is present in the data storage area, it is possible to obtain a reproduction signal of at least normal compression coded quality.

The digital signal recording / reproducing apparatus of the present invention comprises the digital signal recording apparatus of the first aspect and the digital signal reproducing apparatus of the second aspect, or the digital signal recording apparatus of the third aspect and the fourth aspect. By sharing the decoder in the digital signal reproducing apparatus according to the invention, the circuit scale can be reduced.

Further, in the digital signal recording / reproducing apparatus of the present invention, when only the decoding processing is performed by connecting the digital signal recording / reproducing apparatus with an optional detachable connector,
Only the parts necessary for the decoding process can be carried in a compact form.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal recording device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a state of a data storage area when a recording process is completed before the data storage area becomes a memory full state;

FIG. 3 is a diagram showing a state of an auxiliary information storage area when a recording process is completed before the data storage area becomes a memory full state;

FIG. 4 is a diagram showing the state of the data storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 5 is a diagram showing the state of the auxiliary information storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 6 is a block diagram showing a configuration of a digital signal reproducing device according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a digital signal recording device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a state of the data storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 9 is a diagram showing a state of the auxiliary information storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 10 is a diagram showing a state of the data storage area when the data storage area is in a memory full state and the recording processing is continued for a while, and then the recording processing is completed.

FIG. 11 is a diagram showing the state of the auxiliary information storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 12 is a block diagram showing a configuration of a digital signal reproducing device according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a digital signal recording / reproducing apparatus according to a fifth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a digital signal recording / reproducing apparatus according to a sixth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a digital signal recording / reproducing apparatus according to a seventh embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a digital signal recording / reproducing apparatus according to an eighth embodiment of the present invention.

FIG. 17 is a diagram illustrating a basic configuration of an encoder and a decoder in a general CELP scheme (code-excited linear prediction scheme).

FIG. 18 is a block diagram showing a configuration of a digital signal recording device according to a ninth embodiment of the present invention.

FIG. 19 is a diagram showing a state of the data storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 20 is a diagram showing a state of the auxiliary information storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 21 is a diagram illustrating a state of the data storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 22 is a diagram showing the state of the auxiliary information storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 23 is a block diagram showing a configuration of a digital signal reproducing device according to a tenth embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of a digital signal recording device according to an eleventh embodiment of the present invention.

FIG. 25 is a diagram showing a state of the data storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 26 is a diagram showing a state of the auxiliary information storage area when the recording process is completed before the data storage area becomes full of memory.

FIG. 27 is a diagram showing the state of the data storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

FIG. 28 is a diagram showing the state of the auxiliary information storage area when the recording processing is completed after the data storage area has reached the memory full state and the recording processing has continued for a while;

[Explanation of symbols]

11, 31, 51, 61, 71, 81, 91, 111
First encoder 12, 23, 32, 43, 52, 62, 72, 82, 9
2, 103, 112 First decoder 13, 33, 53, 63, 73, 83, 93, 113
Delay device 14, 34, 54, 64, 74, 84, 94, 114
Subtractors 35, 610, 810, 95, 115 Second encoders 16, 37, 56, 66, 76, 86, 97, 117
Write controller 44, 611, 811, 104 Second decoder 24, 45, 59, 69, 79, 89, 105 Adder 22, 42, 57, 67, 77, 87, 102 Read controller 15, 21, 36, 41, 55, 65, 75, 85, 9
6, 101, 116 solid-state memory 58, 68, 78, 88 multiplexer

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masayuki Misaki 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Tsuneo Tanaka 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. JP-A-2-305053 (JP, A) JP-A-61-190198 (JP, A) JP-A-62-231299 (JP, A) JP-A-5-233000 (JP, A) JP-A-5-324000 (JP, A) JP-A-6-243696 (JP, A) JP-A-5-28791 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G10L 19/00

Claims (15)

(57) [Claims] An encoder for encoding an input digital signal into first encoded data; a decoder for decoding the first encoded data into an original digital signal; A delay unit that encodes a signal and delays the input digital signal by a time T (T ≧ 0) required for a process of decoding the encoded data into an original digital signal by the decoder; A subtractor for outputting a difference signal between the output signal of the delay unit and the output signal of the delay unit as second code data, a data storage area for storing the first code data and the second code data, A solid state memory having an auxiliary information storage area for storing auxiliary information indicating an attribute of the data storage area and an attribute of the stored data;
While the writable area exists in the data storage area, the first code data and the second code data are stored in the data storage area. If the writable area of the data storage area is insufficient, Discarding a part or all of the second code data stored in the data storage area, storing the first code data in the area where the discarded data is stored, A write controller for storing information in the auxiliary information storage area. 2. A reproducing apparatus for reproducing a digital signal recorded by the digital signal recording apparatus according to claim 1,
When the first code data stored in the data storage area is sequentially read based on the auxiliary information stored in the auxiliary information storage area, and the second code data exists in the data storage area Is a read controller that also reads the second code data, a decoder that decodes the first code data read by the read controller, an output signal of the decoder, A digital signal reproducing device comprising: an adder that outputs a sum signal with second code data. 3. A first encoder for encoding an input digital signal into first code data, a first decoder for decoding said first code data into an original digital signal, First
The input digital signal is encoded by the encoder (1), and the input digital signal is delayed by a time (T ≧ 0) required for processing for decoding the encoded data into the original digital signal by the first decoder. A delay unit that outputs a difference signal between the output signal of the first decoder and the output signal of the delay unit; and a delay unit that encodes the output signal of the subtractor as third code data. 2 encoder, a data storage area for storing the first code data and the third code data, and auxiliary information indicating the attribute of the data storage area and the attribute of the stored data. While the solid-state memory having the auxiliary information storage area to be stored and the writable area in the data storage area exist, the first code data and the third code data are stored in the data storage area. Data case If the writable area of the area is insufficient, a part or all of the third code data stored in the data storage area is discarded, and the third code data is stored in the area where the discarded data is stored. A digital signal recording device, comprising: a write controller that stores the first code data and stores the auxiliary information in the auxiliary information storage area. 4. A reproducing apparatus for reproducing a digital signal recorded by the digital signal recording apparatus according to claim 3,
When the first code data stored in the data storage area is sequentially read based on the auxiliary information stored in the auxiliary information storage area, and the third code data exists in the data storage area Is a read controller that also reads the third code data, a first decoder that decodes the first code data read by the read controller, and a read controller that reads the first code data. A second decoder for decoding the read third code data, and a sum signal of an output signal of the first decoder and an output signal of the second decoder. A digital signal reproducing device comprising an adder. 5. A first encoder for encoding an input digital signal into first code data, a first decoder for decoding said first code data into an original digital signal, First
The input digital signal is encoded by the encoder (1), and the input digital signal is delayed by a time (T ≧ 0) required for processing for decoding the encoded data into the original digital signal by the first decoder. A delay unit that outputs a difference signal between the output signal of the first decoder and the output signal of the delay unit as second code data; a delay unit that outputs the first code data and the second code data; A solid-state memory having a data storage area for storing code data, and an auxiliary information storage area for storing an attribute of the data storage area and auxiliary information indicating an attribute of the stored data; While the writable area exists, the first code data and the second code data are stored in the data storage area. If the writable area of the data storage area is insufficient, the data is stored in the data storage area. A part or all of the second code data stored in the data storage area is discarded, the first code data is stored in the area where the discarded data is stored, and the auxiliary information is stored. The first code data stored in the data storage area is sequentially read based on the write controller stored in the auxiliary information storage area and the auxiliary information stored in the auxiliary information storage area. A reading controller that also reads the second code data when the code data exists in the data storage area;
At the time of recording processing, the output signal of the first encoder is sent to the first decoder, and at the time of reading processing, the first signal stored in the solid-state memory read by the reading controller is read. , A multiplexer for sending the encoded data to the first decoder, an output signal of the first encoder, and a second signal stored in the solid-state memory read by the reading controller. A digital signal recording / reproducing apparatus, comprising: an adder for outputting a sum signal with code data. 6. A first encoder for encoding an input digital signal into first code data, a first decoder for decoding the first code data into an original digital signal, First
The input digital signal is encoded by the encoder (1), and the input digital signal is delayed by a time (T ≧ 0) required for processing for decoding the encoded data into the original digital signal by the first decoder. A delay unit that outputs a difference signal between the output signal of the first decoder and the output signal of the delay unit; and a delay unit that encodes the output signal of the subtractor as third code data. 2 encoder, a data storage area for storing the first code data and the third code data, and auxiliary information indicating the attribute of the data storage area and the attribute of the stored data. While the solid-state memory having the auxiliary information storage area to be stored and the writable area in the data storage area exist, the first code data and the third code data are stored in the data storage area. Data case If the writable area of the area is insufficient, a part or all of the third code data stored in the data storage area is discarded, and the third code data is stored in the area where the discarded data is stored. 1, a write controller for storing the code data of No. 1 and storing the auxiliary information in the auxiliary information storage area, and a first controller stored in the data storage area based on the auxiliary information stored in the auxiliary information storage area. And a reading controller for sequentially reading out the third code data when the third code data is present in the data storage area, and the first encoder for recording processing. Is output to the first decoder, and at the time of reading processing, the first signal stored in the solid-state memory read by the reading controller is read out.
And a multiplexer for sending the encoded data of the third decoder to the first decoder, and the third decoder read by the read controller.
A second decoder for decoding the encoded data of
A digital signal recording / reproducing apparatus, comprising: an adder that outputs a sum signal of the output signal of the decoder and the output signal of the second decoder. 7. A part constituted by the solid-state memory, the read controller, the first decoder, the multiplexer and the adder, and the other parts are detachable by connectors. The digital signal recording / reproducing apparatus according to claim 5, wherein 8. A part constituted by the solid-state memory, the read controller, the first decoder, the second decoder, the multiplexer and the adder, and the other parts are detachably connected by connectors. 7. The digital signal recording / reproducing device according to claim 6, wherein the digital signal recording / reproducing device is enabled. 9. The apparatus according to claim 1, wherein said first encoder is an encoder of an analysis-synthesis system or a predictive encoding system including said first decoder, said delay unit and said subtractor. The digital signal recording device according to claim 1 or 3, wherein 10. The method according to claim 1, wherein said first encoder is an encoder of an analysis and synthesis system or a predictive encoding system incorporating said first decoder, said delay unit and said subtractor. The digital signal recording / reproducing apparatus according to any one of claims 5, 6, 7, and 8. 11. The digital signal recording apparatus according to claim 1, wherein said solid-state memory is a detachable nonvolatile memory. 12. The digital signal reproducing apparatus according to claim 2, wherein said solid-state memory is a removable nonvolatile memory. 13. The digital signal recording according to claim 5, wherein said solid-state memory is a detachable nonvolatile memory. Playback device. 14. The write controller stores the first code data in the data storage area of a continuous address space from address A to address B in the direction from address A to address B in the data storage area. When the second code data or the third code data is stored in the data storage area in the direction from address B to address A, and when the data storage area runs out of free space. And stopping the writing process of the second code data or the third code data, and storing the first code data in the address B direction. The digital signal recording device according to any one of claims 9 to 11. 15. The write controller stores the first code data in a data storage area of a continuous address space from address A to address B in a direction from address A to address B in the data storage area. When the second code data or the third code data is stored in the data storage area in the direction from address B to address A, and when the data storage area runs out of free space. The writing process of the second code data or the third code data is stopped, and the first code data is successively stored in the address B direction. The digital signal recording / reproducing apparatus according to any one of claims 6, 7, 8, 10, and 13.