JP3224946B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a logic circuit and a memory are mounted on the same chip, such as a single-chip microcomputer (microcomputer). The present invention relates to a memory content test circuit for testing contents stored in a memory at the time of acceptance inspection or the like on a user side and outputting the result to the outside.

[0002]

2. Description of the Related Art Various methods have been proposed to protect memory contents from unauthorized reading such as dead copy. One of the methods is to prevent the contents stored in a memory from being output to the outside ( Output is prohibited). When the method of prohibiting output as described above is employed, a party who can know the memory contents can perform a test of whether or not the memory contents are correct (for example, whether or not the memory contents match the user's specification). A memory content test circuit is provided.

[0003] Such a memory content test circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-40836, a single-chip memory.
As disclosed in the microcomputer, while maintaining the confidentiality without outputting the memory contents to the outside, input expected value data corresponding to each address of the memory from the outside, compare with the memory data and match It is desirable to output the result of the mismatch.

In the above-mentioned Japanese Patent Application Laid-Open No. 5-40836,
Two embodiments are disclosed for testing a user program stored in a one-time PROM (programmable read-only memory that can be written only once).

In the first embodiment, address data and expected value data are sequentially changed from the start address to the end address of the user program and input from the outside, and a determination signal is output in synchronization with the input timing of the expected value data. Is determined, the user program is determined for each address.

In a second embodiment, an address decoder for decoding a start address and an end address of a block area to be tested by a user program is provided, and all addresses between the start address and the end address are provided. The address is compared with the memory data and the expected value data, and a result indicating whether or not all the addresses match is output to the outside.

An advantage of the second embodiment described above is that a person who attempts an illegal read can set the expected value data for each address for all addresses between the start address and the end address of the block area to be tested. If a computer is used to generate the combination, it takes a lot of years even if a computer is used, and in practice, illegal reading is almost impossible.

However, when the user program is divided into a number of block areas and the above-described test is performed for each block area, an address decoder is used to decode the start address and end address of each block area. Must be provided, and the number of address decoders used increases, leading to an increase in chip size. Such a problem becomes particularly noticeable as the capacity of the memory to be tested increases.

[0009]

As described above, the conventional memory contents test circuit is used to test the contents of the mounted memory by dividing the contents of the mounted memory into a plurality of block areas.
There has been a problem that the number of address decoders used for decoding a specific address such as a test start address and a test end address for each block area increases, resulting in an increase in chip size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to carry out a test while keeping the confidentiality of the mounted memory without outputting it to the outside. Even when a test is divided into a plurality of block areas, an address decoder for decoding a specific address such as a test start address and a test end address for each block area is provided for each block area.
It is an object of the present invention to provide a semiconductor integrated circuit having a memory content test circuit which does not need to be provided.

[0011]

A semiconductor integrated circuit according to the present invention is divided into a plurality of block areas for storing data.
In the test mode of the ROM, an address signal specifying the address of the ROM and expected value data corresponding to the address are input from the outside in the test mode of the ROM, and the expected value is read without outputting the read data of the ROM to the outside. A memory content test circuit for outputting a match / mismatch determination result to the outside in comparison with data, wherein the memory content test circuit is configured to output the RO signal in response to the address signal.
Data read from M and synchronized with the address signal
And compares it with predetermined expected value data that is sequentially input.
A data comparison circuit for determining whether or not the
Address signal for designating consecutive addresses of a predetermined number of sequential
There a continuous address input determination circuit determines whether the input, based on the matching determination output of the decision output and the data comparing circuit of the continuous address input judging circuit, depending on the communication <br/> connection address A continuous data match determination circuit that determines whether or not all data corresponding to the data read from the ROM and the sequentially input expected value data match each other and outputs a determination signal ; Having the above consecutive addresses
The input determination circuit is configured to determine a predetermined upper bit of the address signal.
First detection for detecting that the signal of the number of bits does not change
Circuit and a predetermined number of lower bits of the address signal
For each of a plurality of block areas of the ROM based on the signal of
Start address and end address for each block area
A second detection circuit for detecting the continuous data match.
A determination circuit configured to detect a detection output of the first detection circuit;
Of the start address for each block area in the detection circuit
The detection output and the match judgment output of the data comparison circuit are input.
A first logic circuit to be applied and an output of the first logic circuit
A third detection circuit for detecting that the
In the detection circuit of No. 2, the end address of each block area is
When detected, the detection output of the third detection circuit is
And a second logic circuit that outputs the signal as a determination signal .

[0012]

In the ROM test mode, an address signal designating a predetermined number of consecutive addresses of the ROM is sequentially input from the outside to the address bus, and expected value data corresponding to each address is externally synchronized in synchronization with the change of the address signal. Second
Are sequentially input to the data bus. And the first from ROM
It is possible to sequentially compare the data read sequentially to the data bus with the expected value data without outputting the data to the outside, and output the result of judging whether all the data at consecutive addresses match or not to the outside It has become.

Therefore, the contents of the ROM (eg, a user program) are divided into a plurality of block areas in units of a predetermined number of continuous words, and a test is performed for each block area.
By repeating this test for all the block areas, it becomes possible to execute the test for all the contents of the ROM.

In this case, even when the capacity of the ROM is increased, the test can be performed by repeatedly using the same test circuit. Therefore, in the conventional example, the start address and the end address of each block area are decoded. As compared with the case where a large number of address decoders are required to perform the operation, the increase in the chip size is small.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of a single-chip microcomputer according to a first embodiment of the present invention.

In this microcomputer, 1 is a CPU (Central Processing Unit), 2 is a ROM for storing program data or table data, and 3 is an address signal / data signal transfer connected to the CPU 1 and the ROM 2. An internal bus (address / data bus), 4 is a peripheral circuit, and 5 is an address / data terminal group.

The ROM 2 has a capacity of 4K bits (= 16 bits × 256) capable of storing, for example, 256 words of 16-bit words, and specifies 256 address spaces by an 8-bit address signal. It is possible.

The memory content test circuit 10 includes the ROM
In the test mode 2, an address signal for designating a predetermined number of consecutive addresses of the ROM and expected value data corresponding to the addresses are sequentially inputted from the outside.
The data sequentially read from M2 are sequentially compared with the expected value data without being output to the outside, and a determination result as to whether or not all the data at the continuous addresses match is output to the outside. , For example, as described below.

That is, the memory content test circuit 10 comprises:
An address bus 11 to which an address signal is externally input via an address terminal group 11a; a plurality of control signal lines 12 to which a plurality of control signals are externally input via a control signal terminal group 12a; A first data bus from which the ROM 2 is controlled by a control signal on a line 12 to read ROM data in accordance with an address signal on the address bus 11; The second data bus 14 to which data is input, the data on the first data bus 13 and the second
A data comparison circuit 15 which compares the data on the data bus 14 and generates a data match determination signal when the data matches.
, A continuous address input determination circuit 16 and a continuous data match determination circuit 17.

The continuous address input determining circuit 16 determines whether or not an address signal for sequentially specifying a predetermined number of consecutive addresses among the addresses of the ROM 2 is sequentially input from the outside to the address bus 11, and determines whether or not the continuous address input is performed. , A continuous address input determination signal is output.

Based on the output signal of the continuous address input determination circuit 16 and the output signal of the data comparison circuit 15, the continuous data match determination circuit 17 responds to the continuous address sequentially input to the address bus 11 according to the serial address. It is determined whether or not the corresponding data of the data sequentially read out to the first data bus 13 and the expected value data sequentially input to the second data bus all match. It outputs a data match determination signal.

In the memory content test circuit 10, in the test mode of the ROM 2, an address signal designating a predetermined number of consecutive addresses of the ROM 2 is sequentially input from the outside to the address bus 11, and each address signal is synchronized with the change of the address signal. Expected value data corresponding to the address is sequentially input from the outside to the second data bus 14, and the data sequentially read from the ROM 2 to the first data bus 13 is sequentially compared with the expected value data. Can be output to the outside as a result of determination as to whether or not all match.

Accordingly, the contents of the ROM 2 are divided into a plurality of block areas in units of continuous 16 words, for example, and a test is performed for each block area. Testing can be performed for all of them.

In this case, even if the capacity of the ROM 2 becomes large, the test can be performed by repeatedly using the same test circuit. In the conventional example, the start address and the end address of each block area are decoded. As compared with the case where a large number of address decoders are required to perform the operation, the increase in the chip size is small.

FIG. 2 shows a specific example of the continuous address input determination circuit 16 and the continuous data coincidence determination circuit 17 shown in FIG. Continuous address input judgment circuit 16
Comprises a first detection circuit 21 for detecting that, for example, the upper 4 bits of the address signal do not change after being reset after receiving the first control clock signal; A second detection circuit 22 for detecting that the lower 4 bits have continuously changed from "0000" to "1111", for example.

The second detection circuit 22 is a 4-bit binary counter that counts a second control clock signal given each time the address signal changes after resetting in response to the first control clock signal. Circuit 221
And a matching circuit 222 for detecting whether or not the 4-bit output of the counter circuit 221 matches the lower 4 bits of the address signal. This matching circuit 222
The four exclusive OR gates 223 to which the two sets of 4-bit signals are input, and the four exclusive OR gates 223, respectively.
And a NOR gate 224 to which each of the 23 outputs is inputted.

The continuous data coincidence judgment circuit 17 detects the detection output of the first detection circuit 21 and the second detection circuit 2
The logic circuit is configured to output both the continuous data coincidence determination signal upon detecting that both the two detection outputs are generated and the data coincidence determination signal of the data comparison circuit 15 does not change.

That is, the detection output of the first detection circuit 21, the detection output of the second detection circuit 22, and the data comparison circuit 15
And a third detection circuit 24 for detecting that the output of the first AND gate 23 does not change, and a 4-bit output of the counter circuit 221. A fourth detection circuit 25 for detecting that all are "1", and a fourth detection circuit 2
5 and the output of the third detection circuit 24. The second AND gate 26 receives the output of the second AND gate 26, and outputs the output of the second AND gate 26 to the outside via the continuous data match determination output terminal 27. Output.

Next, the operation of the memory content test circuit 10 of FIGS. 1 and 2 will be described in detail with reference to the timing chart of FIG. In ROM test mode,
First, after a first control clock signal and a second control clock signal are input to the control signal line 12 from the outside, an 8-bit address signal is input to the address bus 11 from the outside. ROM
Start address of the area (in this example, the lower 4
An address whose bits are all "0" is allocated. ) Is specified, and predetermined expected value data is input to the second data bus 14 from the outside.

The first control clock signal causes the first
Is reset to output the "H" level, the third detection circuit 24 is also reset and outputs the "H" level, and the counter circuit 221 is reset to change the 4-bit output to "0000". . As a result, the 4-bit output “0000” of the counter circuit 221 matches the lower 4 bits “0000” of the address signal, and the “H” level is output from the matching circuit 222. In this case, the data in the ROM 2 is read onto the first data bus 13 according to the address signal, and the data comparison circuit 15
Compares the data on the first data bus 13 with the expected value data on the second data bus 14, and generates an "H" level data match determination signal when they match. As a result, all three inputs of the first AND gate 23 go to the “H” level, and the output of the first AND gate 23 goes to the “H” level. However, the third detection circuit 24 outputs the “H” level input. Maintain the "H" level output state without responding.

Thereafter, the lower 4 bits of the address signal are controlled so as to continuously change by 16 addresses from "0000" to "1111", and predetermined expected value data is synchronized with the change of the address signal. Is entered.

In this case, the counter circuit 221 counts the second control clock signal input in synchronization with the change of the address signal, and outputs the lower 4 bits of the address signal “000”.
Since the 4-bit output of the counter circuit 221 changes continuously from "0000" to "1111" in synchronization with the continuous change from "0" to "1111", the matching circuit 22
2 maintains the "H" level output state.

Further, the data comparison circuit 15 sends a signal from the ROM 2 to the first data bus 1 in response to a change in the address signal.
3 is sequentially compared with the expected value data sequentially input to the second data bus 14 in synchronization with the change of the address signal.
Maintain the level output state.

While the lower 4 bits of the address signal continuously change from "0000" to "1111" as described above, the upper 4 bits of the address signal do not change. By detecting this state, the "H" level output state is maintained.

Then, the state where the lower 4 bits of the address signal become "1111" (4 in the counter circuit 221).
When the fourth detection circuit 25 detects that the bit outputs are all set to “1”, the output becomes “H” level,
Both inputs of the second AND gate 26 become "H" level, and the output of the second AND gate 26 becomes "H" level.

This output indicates that the upper 4 bits of the address signal are constant and the lower 4 bits are from "0000" to "1111".
This is a continuous data match determination output indicating that all of the ROM read data for 16 addresses and the expected value data at each address, which change continuously until the end, all match.

According to the memory contents test circuit 10 of the above embodiment, the contents of the ROM 2 (for example, a user program)
Is divided into 16 block areas in units of continuous 16 words, and the above-described processing is repeated for each block area, so that the contents of the ROM 2 are maintained while the confidentiality is maintained without outputting the contents of the ROM 2 to the outside. Can be tested for all of

In this case, even when the capacity of the ROM 2 is increased, the test can be performed by repeatedly using the same memory content test circuit 10, so that
In the conventional example, a large number of address decoders are required to decode the start address and the end address of each block area, respectively, but the increase in the chip size can be reduced.

Here, consider the case where an attempt is made to illegally read the contents of the ROM 2. The 16 bits forming one word have 64K (= 2 ¹⁶ ) combinations, and 256 forming continuous 16 words specified by continuous changes (16 patterns) of lower 4 bits of an 8-bit address signal.
The bits have (2 ¹⁶ ) ¹⁶ = 2 ³² = 1.16 × 10 ⁷⁷ combinations.

Therefore, it is necessary to input 1.16 × 10 ⁷⁷ kinds of word data at the maximum when attempting illegal reading.
If μs is required, it would take 3.67 × 10 ⁶³ years, which makes illegal reading impossible.

In the above-described embodiment, the continuous address input determination circuit 16 is provided with a first detection circuit 21 for detecting that a predetermined upper bit of the address signal does not change, and the content of the lower bit of the address signal is continuous. And a second detection circuit 22 for detecting that the number of changes has been changed a predetermined number of times. Therefore, it is possible to easily determine continuous address input in units of a memory area that is an integral number of the number of addresses in the ROM 2.

Further, the second detection circuit 22 detects that a plurality of lower bits of the address signal have continuously changed from the state of all "0" to the state of all "1". A binary counter circuit 221 that counts a control clock signal given for each signal change;
This can be realized by a simple circuit configuration using the matching circuit 222 for detecting whether or not the output bit of the binary counter circuit 221 matches the lower bit of the address signal. Further, by detecting that all the output bits of the binary counter circuit 221 have become "1", it is possible to easily detect that the input of a predetermined continuous address has been completed.

FIG. 4 shows the block configuration of the single-chip microcomputer of FIG. 1 in more detail. 1 is CP
U, 2 a ROM, 3 an internal bus for transferring address signals and data signals connected to the CPU and the ROM,
4 is a peripheral circuit, 5 is an address / data terminal group, and 10a is a memory content test circuit.

Reference numeral 41 denotes the CPU 1 according to the normal operation mode of the single-chip microcomputer / test mode of the ROM.
A first multiplexer circuit for switching the address signal output from the controller / address signal input to the address bus 11 and supplying the switched address signal to the ROM 2.

Reference numeral 42 denotes a second multiplexer circuit that switches between the control signal output from the CPU 1 and the control signal input to the control signal line 12 according to the normal operation mode / test mode of the ROM and supplies the control signal to the ROM 2. .

Reference numeral 43 denotes an input buffer circuit with an enable control function inserted into the intermediate portion of the internal bus 3 so that data can be input from the address / data terminal group 5 when data is input in the normal operation mode. In the test mode of the ROM, it is controlled by an enable control signal TEST / READ so as to be in a non-operating state.

Reference numeral 44 denotes a state connected in parallel with the input buffer circuit 41 so that data can be output to the address / data terminal group 5 during data output in the normal operation mode.
This is an output buffer circuit with an enable control function that is controlled by an enable control signal TEST / WRITE so as to be in an inactive state in the M test mode.

The input buffer circuit 43 and the output buffer circuit 44 are connected to the internal bus 3 in the ROM test mode.
Is divided into the ROM 2 side and the address / data terminal group 5 side, so that expected value data can be input from the outside without outputting the ROM read data to the outside. Thus, a portion of the internal bus 3 closer to the ROM 2 than the input buffer circuit 43 / output buffer circuit 44 also serves as the first data bus 13 and has a higher address / address than the input buffer circuit 43 / output buffer circuit 44. The portion on the data terminal group 5 side also serves as the second data bus 14.

As described above, in the single-chip microcomputer of FIG. 4 having a configuration corresponding to the normal operation mode of the single-chip microcomputer / the test mode of the ROM, the ROM test mode is also described with reference to FIG. Since such an operation is performed, the above-described effects can be obtained.

[0050]

As described above, according to the memory contents test circuit mounted on the semiconductor integrated circuit of the present invention, a predetermined number of consecutive addresses are stored in predetermined address areas of a ROM mounted on the same chip. Without outputting the ROM data to the outside, it compares with the expected value data corresponding to each address,
It is possible to output a determination result as to whether or not data matches with all addresses to the outside.

Therefore, the test can be performed while maintaining the confidentiality of the ROM contents. Even when the test is performed by dividing the contents of the ROM into a number of block areas, the test start address and the test end address for each block area are tested. It is no longer necessary to provide an address decoder for decoding a specific address for each block area , and the increase in chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a single-chip microcomputer according to a first embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a specific example of a continuous address input determination circuit and a continuous data match determination circuit in FIG. 1;

FIG. 3 is a timing chart showing an operation example of the memory content test circuit of FIGS. 1 and 2;

FIG. 4 is a block diagram showing the configuration of the single-chip microcomputer of FIG. 1 in further detail;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... ROM, 3 ... Internal bus (address / data bus), 5 ... Address / data terminal group, 10a ... Memory content test circuit, 11a ... Address terminal group, 11 ...
Address bus, 12a: control signal terminal group, 12: control signal line, 13: first data bus, 14: second data bus, 15: data comparison circuit, 16: continuous address input determination circuit, 17: continuous data Match determination circuit, 41: first multiplexer circuit, 42: second multiplexer circuit, 43: input buffer circuit, 44: output buffer circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI G11C 29/00 673 G11C 29/00 673B (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/16 G06F 12 / 14 G06F 15/78 G11C 17/00 G11C 29/00

Claims (4)

(57) [Claims] 1. A plurality of blocks for storing data
A ROM divided into regions, and a ROM externally provided in a test mode of the ROM.
And an expected value data corresponding to the address are input, and the readout data of the ROM is compared with the expected value data without outputting the readout data to the outside, and the result of the match / mismatch determination is output to the outside. A memory content test circuit that reads data from the ROM in response to the address signal.
Data and sequentially input in synchronization with the address signal
Compares with expected value data and determines whether they match
A data comparator circuit for the address signals for sequentially specifying the consecutive addresses predetermined number of a continuous address input determination circuit determines whether the input of the ROM, determines an output and the data of the continuous address input judging circuit
Based on the matching determination output over data comparator circuit, the data read from the ROM in response to the continuous address
And a continuous data match determining circuit corresponding data together with the expected value data are sequentially inputted outputs a determination signal by determining whether or not all consistent, the continuous address input judging circuit, the address signal The signal of the predetermined number of upper bits of
A first detection circuit for detecting that the address signal does not change, and a signal having a predetermined number of lower bits of the address signal.
Based on the start address for each of the plurality of block areas of the ROM,
Detects the end address of each dress and each block area
A second detection circuit, wherein the continuous data coincidence determination circuit includes a detection output of the first detection circuit and a detection output of the second detection circuit.
Detection and output of the start address for each block area
And a first input to which a match determination output of the data comparison circuit is input.
And the output of the first logic circuit does not change.
A third detection circuit, and an end address for each of the block areas in the second detection circuit.
When less is detected, the detection output of the third detection circuit
And a second logic circuit that outputs as the determination signal
The semiconductor integrated circuit according to claim Rukoto. Wherein said second sensing circuit, said predetermined number of bits of the signal of the lower bits are all of the address signals by detecting the state of "0" to detecting the start address, the state of all "1" 2. The semiconductor integrated circuit according to claim 1, wherein the end address is detected by detecting the end address . 3. A binary counter circuit for counting a second control clock signal provided every time the address signal changes after resetting upon receiving a first control clock signal. 2. The semiconductor integrated circuit according to claim 1, comprising: 4. The circuit according to claim 1, wherein said first and second logic circuits are
2. The gate according to claim 1, wherein the gate is a gate.
A semiconductor integrated circuit as described in the above.