JP3214430B2 - Block coding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an orthogonal transform coding method for an image, and more particularly to orthogonal transform coding of a macroblock.

[0002]

2. Description of the Related Art FIG. 12 is a diagram showing one screen of an image having an interlaced structure for explaining a conventional macro block. In the figure, reference numeral 50 denotes a screen having an interlaced structure. Reference numeral 51 denotes a first field that forms the interlace structure, and 52 denotes a second field that also forms the interlace structure. 53 is m pixels in the horizontal direction,
This block is composed of 2n pixels (m and n are natural numbers) in the vertical direction. An image having such an interlace structure is obtained by first displaying information of the first field on a screen,
An image for one screen is displayed by displaying the information of the second field between the first fields.

FIG. 13 shows an example of the configuration of a conventional macroblock consisting of two blocks in both the horizontal and vertical directions. FIG. 13A shows a 4: 4: 4 format, and FIG.
Shows a 4: 2: 2 format, and (c) shows a 4: 2: 0 format.

[0004] An image signal is composed of several signal components. For example, assuming that there are three channel signal components, FIG. 13A shows a case where each channel is constituted by red, green, and blue signal components.
FIGS. 13B and 13C show a case where the signal components of three channels are composed of luminance and color difference signals of two channels. A case in which the ratio of the number of pixels of each signal component is 1: 1: 1 is called a 4: 4: 4 format. The ratio of the number of pixels of each signal component is 2:
The case of a 1: 1 configuration is called a 4: 2: 2 format. Furthermore, the ratio of the number of pixels of each signal component is 4:
The case of a 1: 1 format is called a 4: 2: 0 format.

The macro block shown here is, for example,
It may be composed of the pixel value of the current frame or the difference value between the current frame and the previous frame. Whether to send the pixel value of the current frame or the difference value between the current frame and the previous frame is determined as appropriate by the system.As a typical example, when sending the first image, In many cases, the pixel value of the current frame representing the entire image is encoded, and thereafter, the difference value between the current frame and the previous frame is encoded to reduce the amount of information to be transmitted.

In each of FIGS. 13 (a), 13 (b) and 13 (c), orthogonal transformation is performed in blocks of m pixels in the horizontal direction and 2n pixels in the vertical direction (m and n are natural numbers). For a signal having a concept of a field, such as an image having an interlaced structure as shown in FIG. 12, in order to increase the coding efficiency, two upper and lower blocks are paired in accordance with the magnitude of the motion to reconstruct the block. Is going.

FIG. 14 shows an example of the structure of two blocks above and below for a signal having the concept of a field in FIG. 13, that is, a signal excluding Cb and Cr in FIG. 13C. FIG. 3A shows a frame block, and FIG.
Indicates a field block. In the drawing, solid arrows indicate the first field, and broken lines indicate the second field. In the conventional macroblock orthogonal transform coding method, a frame block in which fields are mixed as shown in FIG. 14A or a field block in which fields are separated as shown in FIG. 61, the second field block 62), and the orthogonal transformation is performed on the reconstructed block. Therefore, all blocks have the same size of m pixels in the horizontal direction and 2n pixels in the vertical direction. Processing is in progress. Thereafter, quantization is performed on the orthogonal transform coefficients, and the order of the numbers (# 1, # 2, # 3) shown in FIG.
...).
Here, when m = 8 and n = 4, for example, the configuration of a macroblock in MPEG2 is obtained, and orthogonal transform coding is performed in block units of the same size.

[0008]

In the conventional encoding method, the pixel value of the current frame is encoded, and after transmitting, the difference value between the next current frame and the previous frame is continuously transmitted. Therefore, when the decoding of the pixel value of the current frame transmitted first fails, there is a problem that all the signals of the difference values between the current frame and the previous frame which are continuously transmitted later are wasted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and when encoding and transmitting a current pixel value and a difference value, it is not necessary to encode and transmit the encoded pixel value and transmit it efficiently. It is an object of the present invention to obtain a block coding scheme capable of performing encoded transmission.

[0010]

In order to solve the above problems SUMMARY OF THE INVENTION, macro block coding scheme according to the present invention, the
Interlay having one field and second field
Image information having an image structure, and storing the stored image information.
Information consisting of only the image signals of the first field.
And a pixel signal of the first field
A plurality of differential signals from the pixel signals of the second field
Divided into two types of blocks, the second block,
When encoding the first and second blocks of
Encoding of the first block and encoding of the second block
Is performed alternately for each macroblock.

In the block decoding method according to the present invention,
When encoding two blocks, the first block encodes the pixels of the first field, and the second block encodes the difference signal between the first field and the second field. Therefore, the pixel signal of the first field can always be sent, and the transmission amount can be reduced simultaneously by sending the difference signal of the second field and the first field.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration example of a macroblock orthogonal transform coding scheme according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a macroblock orthogonal transform coding circuit. 2 is a frame storage circuit. Reference numeral 3 denotes a block orthogonal transform encoding circuit for orthogonally transform-encoding a block composed of m pixels in the horizontal direction and 2n pixels in the vertical direction (m and n are natural numbers). Reference numeral 4 denotes a sub-block consisting of only a first field consisting of m pixels in the horizontal direction and n pixels in the vertical direction and a sub-block consisting of only a second field consisting of m pixels in the horizontal direction and n pixels in the vertical direction. This is a sub-block orthogonal transform coding circuit that performs orthogonal transform coding on one sub-block. Reference numeral 5 denotes a switching circuit that switches and operates the block orthogonal transform encoding circuit 3 and the sub-block orthogonal transform encoding circuit 4. 6
Is an input line for inputting image information and storing it in the frame storage circuit 2. 7 is a block orthogonal transform coding circuit 3
Alternatively, it is an output line for outputting encoded data encoded by the sub-block orthogonal transform encoding circuit 4.

Next, the operation of the macroblock orthogonal transform coding circuit 1 shown in FIG. 1 will be described separately for the case of transmitting a frame block and the case of transmitting a field block. FIGS. 2 and 3 show an example of transmitting a frame block. FIGS. 4 and 5 show an example of transmitting a field block.

FIG. 2 specifically illustrates the operation of the block orthogonal transform coding circuit 3 and shows an example of the configuration of a macroblock when coding a frame block according to the present invention. FIG. 4 is a diagram showing a mode in which orthogonal transform coding is performed in a horizontal direction and a vertical direction. The macroblock shown here is composed of, for example, the pixel value of the current frame or the difference value between the current frame and the previous frame. FIG. 3A shows a macroblock configuration in the 4: 4: 4 format, FIG. 3B shows a macroblock configuration in the 4: 2: 2 format, and FIG. 3C shows a 4: 2: 4 format.
This figure shows a macro block configuration in the 0 format, and a portion surrounded by a frame in the figure corresponds to a block.

FIG. 3 shows the structure of the block shown in FIG. 2. In FIG. 3, solid arrows indicate the first field, and broken arrows indicate the second field. Orthogonal transform coding is performed on the block configured as described above in accordance with the order of the numbers (# 1, # 2, # 3,...) Shown in FIG.

FIG. 4 is a diagram for particularly explaining the operation of the sub-block orthogonal transform coding circuit 4, and shows an example of the configuration of a macroblock when coding a field block in the present invention. FIG. 3 is a diagram illustrating a mode in which each block includes two blocks in the horizontal direction and two blocks in the vertical direction in a mode in which orthogonal transform coding is performed for each of two sub-blocks. The macroblock shown here is composed of, for example, the pixel value of the current frame or the difference value between the current frame and the previous frame.
FIG. 4B shows the macro block configuration in the 4: 2: 2 format, and FIG. 4C shows the macro block configuration in the 4: 2: 0 format. It is shown. A portion surrounded by a frame in the drawing corresponds to a sub-block.

FIG. 5 shows an example of the configuration of the block shown in FIG. 4. In FIG. 5, a solid arrow indicates a first field, and a broken arrow indicates a second field. For example, in FIG. 4, "A" corresponds to data of the first field, and "B" corresponds to data of the second field. For the sub-blocks configured in this way, for example, the order of the numbers shown in FIG. 4 (# 1A, # 1B, # 2A, # 2B, # 3A, # 3B
Perform orthogonal transform coding in ()

The frame storage circuit 2 stores the image information input from the input line 6 on a frame basis. The image information stored in the frame storage circuit 2 may be the pixel value of the current frame or the current frame. And the difference value of the previous frame. Whether the pixel value of the current frame or the difference value between the current frame and the previous frame is stored is determined by another system provided before the input line 6, and the frame storage circuit 2 is aware of which is stored. The image information is stored without performing. Similarly, the block orthogonal transform coding circuit 3 and the sub-block orthogonal transform coding circuit 4 recognize whether the value stored in the frame storage circuit 2 is the pixel value of the current frame or the difference value between the current frame and the previous frame. Encode without encoding.

The switching circuit 5 operates to operate the block orthogonal transform encoding circuit 3 when encoding a frame block, and to operate the sub-block orthogonal transform encoding circuit 4 when encoding a field block. . Whether to encode either the frame block or the field block is determined by a request given from the outside, and the switching circuit 5 performs the switching operation based on the request from the outside or the identification signal from the outside. Do.

As described above, in this embodiment, in an image having an interlaced structure composed of several signal components, m pixels in the horizontal direction are displayed on a screen of one frame in which the first and second fields are combined. , Vertical direction 2n
A mode in which blocks composed of pixels (m and n are natural numbers) are used as blocks, and orthogonal transform coding is performed for each block;
Each block is divided into two sub-blocks, a sub-block consisting of only a first field consisting of m pixels in the horizontal direction and n pixels in the vertical direction, and a sub-block consisting of only a second field consisting of m pixels in the horizontal direction and n pixels in the vertical direction. Divided into sub-blocks, and has a mode of performing orthogonal transform coding for each sub-block, and for a macro block obtained by collecting a plurality of blocks from each signal component, performing coding in order of signal importance. I do.

Embodiment 2 FIG. In the first embodiment, the case where the switching circuit 5 performs the orthogonal transform coding by adaptively switching between the block orthogonal transform coding circuit 3 and the sub-block orthogonal transform coding circuit 4 has been described. May be provided only in the block orthogonal transform encoding circuit 3. On the other hand, in a system that encodes only the field blocks, the system may include only the sub-block orthogonal transform encoding circuit 4.

Embodiment 3 FIG. FIGS. 6, 7, and 8 are diagrams for explaining the block coding schemes according to the second and third inventions. In FIG. 6, reference numeral 11 denotes an encoding apparatus having the block encoding scheme described in the first embodiment,
Reference numeral 2 denotes a decoding device, and reference numeral 13 denotes an additional unit that generates an additional block with respect to the macroblock encoded by the encoding device 11. Reference numeral 14 denotes a thinning unit that deletes one or more blocks from the macroblock encoded by the encoding device 11. In FIG. 6A,
The adding unit 13 exists in the encoding device 11, and in FIG. 6B, the adding unit exists in the decoding device. Also, in FIG. 6C, the thinning means exists in the encoding device,
In FIG. 6D, the thinning means 14 exists in the decoding device.

Next, FIG. 7 is a diagram showing a case where the image information is composed of signal components of three channels, for example, red, green and blue. FIG. 7B shows that the encoded data of blocks # 9, # 10, # 11, and # 12 are converted to the format shown in FIG. Furthermore, it is shown that the format shown in FIG. 7C can be converted to the format shown in FIG. 7C by thinning out the encoded data of the blocks # 7 and # 8 from the format shown in FIG. Thus, as shown in FIG.
In the case of encoding in the image of 2: 2 format from # 1 to # 8, an image of 4: 2: 2 can be obtained as before, and # 7 and # 8 are thinned out by # 1 from # 1 by thinning means. When encoding is performed up to # 6, a 4: 2: 0 image as shown in FIG. 2C can be obtained. On the contrary, FIG.
The format shown in FIG. 7B can be generated by generating encoded data of new blocks # 7 and # 8 by performing an interpolation process, a filtering process, or the like on (c). is there. FIG. 7 (b)
In the same manner, the additional means performs interpolation processing or filtering processing on the format of FIG.
It is possible to convert to the format of (a). Next, FIG. 8 shows a case where the signal component is a signal component of three channels and is composed of luminance and a color difference signal of two channels. From FIG. 8A to FIG. FIG. 6 is a diagram showing that format conversion can be performed by thinning means by thinning out encoded data of a block. For example, in a 4: 2: 2 format image as shown in FIG. 8B, when encoding is performed from # 1A to # 8B, a 4: 2: 2 image can be obtained as in the related art. Thinning out # 7A to # 8B by
When encoding is performed from A to # 6B, a 4: 2: 0 image as shown in FIG. 8C can be obtained. Similarly, FIG.
The format can be converted by adding encoded data of a new block by the adding means from (c) to (a).

As described above, this embodiment is a signal sequence composed of three channel components, for example, red, green, and blue, and is a signal sequence in which the ratio of the number of pixels of each component is 1: 1: 1. : In the 4: 4 format image, the coding mode described in the first embodiment is used, and a predetermined block order is assigned to a macroblock in which a plurality of blocks are collected from each signal component at a ratio of 1: 1: 1. Thus, it is characterized in that coded data of one or a plurality of blocks is thinned out and scalably coded.

A signal sequence composed of three channel components, for example, luminance and two channel color difference signals,
The above embodiment is applied to a 4: 2: 2 format image in which the number of pixels in the horizontal direction of the chrominance signal is halved in comparison with the luminance signal and the ratio of the number of pixels of each component is 2: 1: 1. In the coding mode described in 1, the macro data obtained by collecting a plurality of blocks from each signal component at a ratio of 2: 1: 1 is encoded data of one or more blocks in a predetermined block order. Scalable encoding by thinning out or adding.

A signal sequence composed of three channel components, for example, luminance and two channel color difference signals,
The number of pixels in the horizontal and vertical directions of the chrominance signal is halved in comparison with the luminance signal, and the ratio of the number of pixels of each component is reduced to 4: 1: 1.
In the 4: 2: 0 format image configured as follows, the image has the encoding mode described in the first embodiment,
Encoding scalable by adding encoded data of one or more blocks in a predetermined block order to a macroblock in which a plurality of blocks are collected at a ratio of 4: 1: 1 from each signal component. It is characterized by.

Embodiment 4 In the third embodiment, the case where encoded data of a block is added between three formats of 4: 4: 4 format, 4: 2: 2 format and 4: 2: 0 format, or code of a block is added. Although the case where the coded data is thinned has been described, the coded data of the block for conversion into another format may be added or thinned.

Embodiment 5 In the third embodiment, when the thinning-out unit thins out the coded data of the block, regardless of the case where the block is simply deleted, information from a plurality of blocks is extracted to form one block. It may be a method. For example, when the block of # 5 and # 7 is changed to the block of # 5, it is not limited to the case of simply deleting # 7. The case of creating the # 5 block may be used.

Embodiment 6 FIG. FIG. 9 is a diagram showing an embodiment of the block encoding system according to the fourth invention.
In the figure, reference numeral 21 denotes a block encoding circuit. Reference numeral 22 denotes a first field orthogonal transform encoding circuit for orthogonally transform encoding the first field. Reference numeral 30 denotes a pixel encoding circuit in the first field orthogonal transform encoding circuit 22. Reference numeral 23 denotes a second field orthogonal transform coding circuit that performs orthogonal transform coding on the second field. 31 is the first field and the second
This is a differential signal generation circuit that generates a differential signal of a field. Reference numeral 32 denotes a differential signal encoding circuit that encodes the generated differential signal.

FIGS. 10 and 11 show an example of the configuration of a block for explaining the operation of the block encoding circuit shown in FIG. 9. In FIG. 10, solid arrows indicate the first field, and broken arrows indicate the first field. It shows the second field. The diagram shown in FIG. 10 has the same configuration as the field block of FIG. 14B described in the conventional example, but in FIG. 10, the block having a solid arrow is the first block.
The pixel value of the field is used as data as it is, and a block having a broken arrow has data as a difference value between the pixel value of the first field and the pixel value of the second field indicated by a solid line. FIG. 11 shows a block configuration similar to that of FIG. 5 described in the first embodiment. In FIG. 11, blocks having solid arrows indicate data using pixel values of the first field as they are, A block having an arrow has a difference value between the pixel value of the first field and the pixel value of the second field indicated by a solid line as data. For the block configured as described above, for example, the pixel value as it is in the part A shown in FIG. 4 is used as data, and the difference value from the part A is used as the data in the part B as shown in FIG. (For example, # 1
A, # 1B, # 2A, # 2B, # 3A, # 3B ...
..) Perform orthogonal transform coding.

As described above, in FIG. 10, in a block composed of m pixels in the horizontal direction and 2n pixels in the vertical direction (m and n are natural numbers), only the first field composed of m pixels in the horizontal direction and 2n pixels in the vertical direction is used. The first block is composed of a first block and the second block is composed of only a second field composed of m pixels in the horizontal direction and 2n pixels in the vertical direction.
When orthogonal transform coding is performed for each block using two blocks, for the first block, the pixels themselves are subjected to orthogonal transform coding, and for the second block, the difference signal between the first block and the first block is calculated. The orthogonal transform coding is performed.

In FIG. 11, in a block composed of m pixels in the horizontal direction and 2n pixels in the vertical direction (m and n are natural numbers), each block is composed of only a first field composed of m pixels in the horizontal direction and n pixels in the vertical direction. First composed
Is divided into two sub-blocks, i.e., a second sub-block consisting of only a second field consisting of m pixels in the horizontal direction and n pixels in the vertical direction, and performing orthogonal transform coding for each sub-block. For the first sub-block, orthogonal transform coding of the pixel itself is performed, and for the second sub-block, orthogonal transform coding of a difference signal from the first sub-block is performed.

[0033]

As described above, according to the present invention, when encoding is performed, one field is always decoded from the pixel value by using a part of the encoded data as the pixel value and the difference value. In addition to this, there is an effect that data can be compressed by the difference value.

[Brief description of the drawings]

FIG. 1 is a diagram showing a macroblock orthogonal transform coding system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a macroblock according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a block configuration of a macro block configuration example according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of a macroblock configuration according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a block configuration of a macro block configuration example according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a configuration example of an adding unit and a thinning unit according to the embodiment of the present invention.

FIG. 7 is a diagram for explaining format conversion in one embodiment of the present invention.

FIG. 8 is a diagram for explaining format conversion in one embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration example of a block encoding circuit according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating a block configuration of a macro block configuration example according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a block configuration of a macro block configuration example according to an embodiment of the present invention;

FIG. 12 is a diagram showing an image having an interlaced structure for explaining a conventional macroblock.

FIG. 13 is a diagram showing an example of a conventional macro block configuration.

FIG. 14 is a diagram showing an example of a conventional block configuration.

[Explanation of symbols]

1 macroblock orthogonal transform coding circuit, 2 frame storage circuit, 3 block orthogonal transform coding circuit, 4 sub-block orthogonal transform coding circuit, 5 switching circuit, 6
Input line, 7 output line, 11 encoding device, 12 decoding device, 13 adding means, 14 decimation means, 21 block encoding circuit, 22 first field orthogonal transform encoding circuit, 23, second field orthogonal transform encoding Circuit, 30
Pixel encoding circuit, 31 difference signal generation circuit, 32 difference signal encoding circuit, 50 images forming an interlaced structure, 51 first field, 52 second field.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-1688 (JP, A) JP-A-1-219773 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 7/32

Claims (1)

(57) [Claims] An image information having an interlace structure having a first field and a second field is stored, and the stored image information is stored in the first field for each macro block .
And one or more first blocks consisting only of the image signals of the first field and the pixel signals of the first field and the second block.
Two types of blocks of one or the second block of multi <br/> number consists difference signal between the pixel signal of the field, the code of the macro blocks of said one or more first and second blocks when performing the reduction, the a first field coding block, fees of the second block
Between the first and second blocks.
Block coding scheme, characterized in that it is carried out in the each other.