JP3211830B2 - CMOS level shifter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a contract no. 33615-88 awarded by the Air Force Department.
-Made under government support under C-1825. The government has certain rights in the invention.

FIELD OF THE INVENTION The present invention relates to logic circuits, and more particularly, to complementary metal oxide semiconductor (CMOS) level shifter circuit configurations.

BACKGROUND OF THE INVENTION Many logic, memory, and timing configurations require communication between functional blocks that require different drive voltages. Voltage level shifters provide an interface where the voltage levels available at the output of one block do not meet the voltage level requirements of the interconnected blocks.

U.S. Pat. No. 4,618,785 (H. van Tran) discloses a CM including an n-channel level shifter and a differential sense amplifier.
An OS differential sense amplifier is disclosed. This level shifter uses only n-channel transistors and loses its threshold voltage when providing an output high ("1") signal. This sense amplifier uses a complementary MOS transistor and can perform a level shift function. It cannot provide an output voltage level lower than the same low voltage level associated with the level shifter having an output coupled to the input of the differential sense amplifier.

The design of voltage level shifters is well known in the art, but often has special operating conditions and device characteristics that result in poor operation of known circuits. For example, flat panel displays (eg, liquid crystal displays) often require special interface circuits due to the discharge of transistors having very large time constants. If the circuit is formed on a glass panel using thin film technology, the characteristics of the thin film device (eg, a field effect transistor) are not as accurately defined as the production type device. In such devices, proper operation must be ensured over a wide range of conditions and a wide range of device parameters.

There is a need for a voltage level shifter circuit that is adapted to operate with widely varying device characteristics and is suitable for implantation using CMOS thin film transistors on the glass of a liquid crystal display.

SUMMARY OF THE INVENTION In one aspect, the present invention comprises first and second p-channel field effect transistors and third and fourth n-channel field effect transistors.
-Is directed to a voltage level shifting circuit configuration including a channel field effect transistor and inversion means.
Each of the transistors has a respective gate and a first output. The inverting means has an input coupled to the gate of the first transistor, directly coupled to the input terminal of the circuit configuration, and an output coupled to the gate of the second transistor. An output terminal of the circuit configuration is coupled to a node to which the first outputs of the second and fourth transistors are coupled, the node having a capacitance. First outputs of the first and third transistors are coupled to gates of the third and fourth transistors.

In a typical embodiment, the second outputs of the first and second transistors are coupled to a positive voltage source (eg, + 15V) and the second outputs of the third and fourth transistors are connected to a negative It is coupled to a voltage source (eg, -5V). The inverting means is an inverter having a supply voltage terminal coupled between + 15V and 0V. The input signal voltage levels applied to the input terminals of this circuit configuration are logic "1" (high) and "0" (low) voltage levels of + 15V and 0V, respectively. The voltages generated at the output terminals of this circuit configuration are logic "1" and "0" voltage levels of + 15V and -5V, respectively.

The level shift circuitry of the present invention takes into account changes in threshold voltage that exists with metal oxide semiconductor (MOS) transistors formed on glass surfaces (eg, liquid crystal displays) using thin film technology. Can also work perfectly within acceptable limits.

Viewed from another aspect, the present invention comprises a pair of voltage buses, first and second MOS transistors of one conductivity type,
And a level shifter circuit including MOS transistors of the third and fourth opposite conductivity types. Each transistor has a gate for controlling conductivity.
The first and third transistors are connected in series between the voltage buses, and the second and fourth transistors are connected in series between the voltage buses. The node between the first and third transistors is connected to the gates of the third and fourth transistors. An input signal having one of the first and second levels is applied directly to the gate of the first transistor, and an inversion of the input signal is applied to the gate of the third transistor. A node between the second and fourth transistors is coupled to one of the voltage buses through one of the second and fourth transistors in response to the first level of the input signal, and the second level of the input signal is provided. Connected to another one of the voltage buses through the other one of the second and fourth transistors. The node between the second and fourth transistors has a capacitance.

The present invention will be better understood from the following detailed description, taken in conjunction with the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of one level shifter circuit according to the prior art.

FIG. 2 is a schematic block diagram of another level shifter circuit according to the prior art.

FIG. 3 is a schematic block diagram of a level shifter circuit according to one embodiment of the present invention.

FIG. 4 is a schematic block diagram of a level shifter circuit according to another embodiment of the present invention.

DETAILED DESCRIPTION Referring to FIG. 1, one level shifter circuit 10 according to the prior art is shown. The level shifter circuit 10
Including input terminal (VIN) 26, supply voltage terminals 32, 34 and 36, output terminal (VOUT) 42, inverters 12, 14 and 16, p-channel MOS transistors 18 and 20, and n-channel MOS transistors 22 and 24. It is a thing.
Input terminal 26 is coupled to the input of inverter 12. The output of inverter 12 is connected to the input of inverter 14 and the gate of p-channel MOS transistor 18 via node 28. The output of the inverter 14 is connected to the gate of the p-channel MOS transistor 20 via the node 30. p-channel MOS transistors 18 and 20
And the first supply voltage terminals of the inverters 12, 14 and 16 are connected at a supply voltage terminal 32 to a positive voltage source + Vdd. The drains of transistors 22 and 24,
And the second supply voltage terminal of the inverter 16 is connected to the negative voltage source -Vss2 and the supply voltage terminal 34. The second supply terminals of the inverters 12 and 14 are connected to a reference voltage source Vss1.
And supply voltage terminal 36. Transistor 18
Is connected to the drain of transistor 22 and the gate of transistor 24 via node 38.
The drain of transistor 20 is connected via node 40 to the drain of transistor 24 and to the input of inverter 16. The output of the inverter 16 is connected to an output terminal (VOUT) 42.

Typically, a logical 0 (low, "0") and a logical 1
A binary signal with a (high, “1”) state is applied to VIN (pin 2
6) is applied. Positive supply voltage at terminal 32 + Vdd
Is, for example, + 15V. The negative supply voltage -Vss2 at the terminal 34 is, for example, -5V. The reference supply voltage Vss1 at the terminal 36 is, for example, 0 V (ground). The input signal applied to terminal 26 has a high ("1") level of + 15V and a low ("0") level of 0V (earth). Therefore, the terminal
The input signal applied to 26 has logic levels of 0V and + 15V. As is well known in the art, an inverter produces a logic one in response to a logic zero at its input and a logic zero in response to a logic one at its input. The inverters 12 and 14 are connected between + 15V and Vss1, which is, for example, 0V (ground). Thus, a "0" from inverters 12 and 14 has a 0V level, and a "1" from inverters 12 and 14 has a + 15V level. Inverter 16 is connected between supply voltages + Vdd and -Vss2. “0” from the inverter 16 is −Vss2
The voltage level, and the "1" from it, has a + Vdd voltage level.

When the voltage level applied to terminal 26 is 0V, the input "0" level, node 28 at the output of inverter 12 shifts to "1", for example, + 15V. The input of inverter 14 and the gate of transistor 18 are at the "1" level of + 15V. Inverter 14 generates a "0" at node 30, which enables transistor 20 (bias on). The current through transistor 20 pulls node 40 up in voltage to + Vdd. Transistor 18 is disabled (biased off, turned off) by the "1" level at its gate (node 28) and becomes non-conductive. Node 40 is
When charged to + Vdd, transistor 22 is enabled, discharging node 38 to -Vss2. this is,
Disabling transistor 24, which allows the voltage at node 40 to continue to rise, allowing it to reach a voltage level of + Vdd. Since the voltage of the node 40 is "1" (+15 V) at this time, the output voltage of the circuit 10 at the terminal 42 is "0" (-Vss2 which is -5 V).

When input "1" is applied to terminal 26, node 28 is "0" and transistor 18 is enabled and conducting. Output of inverter 14, node 30 and transistor
The voltage at the gate of 20 is a "1", which disables transistor 20 (turns off, biases off). When transistor 18 conducts, it
Charges 38 toward + Vdd, which enables transistor 24 to begin conducting. Conduction through transistor 24 pulls node 40 down (discharges) to -Vss2 in voltage. The voltage of -Vss2 on node 40 disables transistor 22. This allows transistor 18 to be enabled to continue charging node 38 to + Vdd, which keeps transistor 24 enabled. The voltage of −Vss2 obtained on the node 40 is inverted by the inverter 16 and output on the terminal 42 as “1” (+ Vd
d voltage).

The circuit of FIG. 1 provides the desired voltage level as long as the transistor characteristics properly meet the requirements of the circuit. However, under certain circumstances, transistors having relatively poor characteristics must be used, and the level shifter circuit 10 may not function. For example, thin film field effect transistors (eg, MOS transistors) on glass substrates (eg, liquid crystal displays) are required for optical displays and sensing devices. Such a transistor is shown in FIG.
Exhibit poor characteristics that may impair the operation of the circuit of FIG. p
The threshold voltage of the channel transistor 18 is n-
Consider the operation of level shifter 10 when it is significantly higher than the threshold voltage of channel transistor 22. If the input voltage applied to the input terminal 26 is
At Vss2, when node 40 goes from + Vdd to + 15V when node 40 is at + Vdd, transistor 20 is turned off by the high voltage level at node 30. If the threshold of p-channel transistor 18 is significantly higher than the threshold of n-channel transistor 22, when both are enabled and conducting, the p-channel transistor
The drain-source resistance of 18 can be significantly higher than the drain-source resistance of n-channel transistor 22. Thus, p-channel transistor 18 cannot raise (pull) the voltage at node 38 sufficiently high that n-channel transistor 24 is enabled and turned on. This leaves node 40 essentially at + 15V, so the output on terminal 42 is -V
ss2 (−5V). Thus, when + Vdd is applied to the input, the circuit 10 which should have an output voltage level of + Vdd,
ss2 output level
It will not function as a shifter.

Referring to FIG. 2, another prior art level shifter circuit
100 is shown. The level shifter 100 includes n-channel MOS transistors 106, 108, 110 and 112. Each of the transistors has a gate, a drain, and a source. The first input terminal VIN is connected to transistor 1
06 and the terminal 114. A second input terminal VIN 'is connected to the gate of transistor 108 and terminal 116.
Is bound to. VIN 'accepts a logical inversion of the signal applied to VIN. The output terminal VOUT is connected to the transistor 108
, The drain of transistor 112 and terminal 118. The first power supply terminal is a transistor 10
6 and 108 are coupled to a power supply having drains, terminal 120 and voltage + Vdd. Transistors 110 and 1
Twelve sources are both coupled to terminal 122 and to a power supply having a voltage level of -Vss2. The input signal voltage level of the signal applied to VIN and VIN 'is "1" of + Vdd.
The voltage level and the "0" voltage level of Vss1 (not shown), where Vss1 is more positive than -Vss2 and not more positive than + Vdd. The source of transistor 106 and the drain of transistor 110 are connected to transistors 110 and 11
2 and to the terminal 122. In one illustrative embodiment of circuit 100, + Vdd = + 15V, Vss1 = 0V (ground) and Vss2 = -5V. The input signals applied to input terminals 114 and 116 have a "1" logic level of + 15V and a "0" logic level of 0V. The "1" applied to the input terminal 114 enables (bias on) the transistor 106, creating a current path from + Vdd to -Vss2 through the transistor 106 and transistor 110. This causes an attempt to raise the voltage at terminal 122, enable transistor 112, turn on transistor 112, and reduce the voltage at terminal 118 (VOUT) to -Vss2. At this time, the voltage of the terminal 116 is the logical input “0”, 0V
It is. This weakly enables transistor 108 because its gate can be negative by -Vss2 in voltage. As transistor 108
Attempts to pull the voltage at terminal 118 toward + Vdd. Thus, transistor 112 is strongly biased on and transistor 108 is weakly biased on, and the voltage at output terminal 118 typically approaches -Vss2, logic output "0".

Input "0" (0V) applied to input terminal (VIN) 114
Biases transistor 106 weakly on, and + Vd through transistor 106 and transistor 110
Establish a current flow from d to -Vss2. This biases transistor 112 weakly on, which then attempts to pull the voltage at terminal 118 to -Vss2. At the same time, transistor 108 is biased on strongly by input "1" applied to terminal 116. Thus, a current path from + Vdd is created via transistors 108 and 112. Since the transistor 108 is strongly biased on, the voltage obtained at the output terminal 118 is + Vd
d, approaching logic output "1". The maximum level of the logical output "1" is obtained by subtracting the threshold voltage of the transistor 108 from + Vdd. Thus, the difference between the output voltage logic levels of circuit 100 may be smaller than the difference between + Vdd and -Vss2.

Referring now to FIG. 3, there is shown a level shifter circuit 200 according to the present invention. The level shifter circuit 200 has p
-Channel field effect transistors 206 and 208, n-
Channel field effect transistors 210 and 212 and an inverter 202 are included. Each of the transistors is typically a MOS transistor having a gate, a drain, and a source. The input terminal (VIN) is connected to the input of the inverter 202, the gate of the transistor 206, and the terminal 214.
Is bound to. Output terminal (VOUT) is transistor 20
8 and 212 are coupled to the drain and terminal 218.
The first power supply terminal of the inverter 202 is connected to the transistor 2
Sources 06 and 208 are coupled to a power supply having terminals 220 and a voltage level of + Vdd. Inverter 202
Is coupled to terminal 224 and a power supply having a voltage level of Vss1. Transistor
The sources of 210 and 212 are both coupled to a power supply having terminals 222 and a voltage level of -Vss2. here
Vss1 is not more positive than + Vdd but more positive than -Vss2. The output of inverter 202 is coupled to the gate of transistor 208 and terminal 216. The drains of transistors 206 and 210 are coupled to the gates of transistors 210 and 212 and terminal 204.

In one specific example of circuit 200, + Vdd = + 15V, Vss1 = 0
V (earth) and Vss2 = -5V. The input signal applied to the VIN terminal has a "1" logic level of + 15V and a "0" logic level of 0V. A logic input “1” applied to input terminal 214 disables (bias off) transistor 206. This is transistor 21
Disable 0 so that no current flows through it. This disables transistor 212. The output of inverter 202 (terminal 216) is a logical input “0” (0V), which enables transistor 208. Thus, the output terminal (VOUT) 218 is at + Vdd
(+ 15V) voltage level, a wide range up to logic output "1". If the input signal applied to the input terminal (VIN) 214 is input "0" (0V, Vss1), the transistor 206 is enabled and the transistor 208 is disabled. This provides a current path from + Vdd through transistors 206 and 210,
A voltage builds up at terminal 204, which enables transistor 212, which in turn conducts. Parasitic or load capacitance coupled to terminal 218 (both not shown)
, The initial current flow through the enabled transistor 212 is essentially the same as that flowing through the transistors 206 and 210. Thus, the output terminal (VOUT) 218 discharges through the enabled transistor 212 over a wide range up to the voltage level of -Vss2 (-5V) and the logic output "0". Transistor 212
Stops conduction when terminal 218 reaches -Vss2. Accordingly, input signals having logic levels from 0 to + 15V are level shifted in circuit 200 to output signal levels of -5V and + 15V, respectively. Thus, the output signal level has a potential difference equal to the total difference between + Vdd and -Vss2.

Unlike the level shifter circuit 10 of FIG. 1, the level shifter circuit 200 of FIG. 3 does not rely on matching the threshold voltages of the p-channel and n-channel transistors. Thus, the circuit operation of the level shift circuit 200 is independent of device threshold differences that can occur when using transistors having poor characteristics. Referring now to FIG. 4, a level shifter circuit 400 according to the present invention
It is shown. The level shifter circuit 400 is essentially the same as the level shifter circuit 200 of FIG. 3, except for the addition of a second input inverter 404 and an output buffer inverter 406 (shown in dashed boxes). All parts and terminals of the inverter circuit 400 are the level shifter circuit 200 of FIG.
The same components and terminals have the same reference numbers.

Buffer inverter 406 includes p-channel transistor 408 and n-channel transistor 410
It is included. The gates of transistors 408 and 410 are coupled to terminal 218. Transistors 408 and 41
The zero source is coupled to power supply terminals 220 and 222, respectively. The drains of transistors 408 and 410
Terminal 4 that plays the role of the output (VOUT) of inverter circuit 400
Combined with 12. Buffer inverter 406 is used to provide increased current drive capability to level shifter circuit 400. It introduces some inversion into the output signal generated at terminal 412, so that the additional inversion provided by inverter 404 produces an output signal waveform essentially identical to that generated by circuit 200 of FIG. Needed for. Inverter 404 has an input coupled to input terminal 402 of inverter circuit 400, and has an input coupled to inverter 202, and an output coupled to terminal 214.

Inverters 404 and 202 each include a CMOS inversion stage, typically having the same type as inverter 406.

It should be understood that the specific embodiments described herein are merely illustrative of the spirit and scope of the present invention. Improvements can be readily made by one skilled in the art, consistent with the principles of the present invention.

Claims (10)

(57) [Claims] 1. A voltage level shifting circuit configuration for shifting a voltage level, each of which comprises first and second p-channel field effect transistors having a gate and a first output, each of which comprises: A third and fourth n-channel field effect transistor having a gate and a first output, a circuit configuration input terminal directly coupled to the gate of the first transistor, the second and fourth transistors Connected to provide a potential difference equal to the difference between the first and second power supply voltages, the circuit configured output terminal having at least one of a parasitic capacitance and a load capacitance. And inverting means for inverting a signal applied to an input, said inverting means comprising an input coupled to said circuit configuration input terminal and said second transistor. A first inverter having an output coupled to the gate of the first transistor, wherein a first output of the first transistor is a first output of the third transistor, and a first output of the third and fourth transistors. A voltage level shifting circuit arrangement, coupled to a gate, wherein each of said field effect transistors is a thin film field effect transistor formed on a non-semiconductor substrate. 2. The semiconductor device according to claim 1, wherein said first inverter comprises: a fifth p-channel field effect transistor;
The n-channel field effect transistor of
And each of the sixth transistors has a gate and a first
Wherein the gates of the fifth and sixth transistors are coupled to an input terminal of the circuit configuration, and a first output of the fifth and sixth transistors is an output of the first inverter. 3. The voltage level shifting circuit configuration of claim 1, wherein the voltage level shifting circuit configuration is coupled to: 3. A first power supply terminal coupled to a second output of the first and second transistors, and a second power supply coupled to a second output of the third and fourth transistors. And a third power supply terminal, wherein the fifth and sixth transistors each have a second output, the second output of the fifth transistor being the first power supply. 3. The voltage level shifting circuitry of claim 2, wherein the voltage level shifting circuit configuration is coupled to a supply terminal, and wherein a second output of the sixth transistor is coupled to the third power supply terminal. 4. The first, second, and third power supply terminals are adapted to couple to first, second, and third power supplies, respectively, and the first, second, and third power supply terminals are coupled to the first, second, and third power supply terminals, respectively. 4. The voltage level shifting circuit configuration of claim 3, wherein the voltage of the power supply is more positive than the voltage of the third power supply which is more positive than the voltage of the second power supply. 5. The circuit of claim 1, further comprising a second inverter having an input and an output, wherein the input is coupled to a connection of a first output of the second and fourth transistors, and the output is an output terminal of the circuit configuration. 5. The voltage level shifting circuit configuration of claim 4, wherein the second inverter is coupled to receive power from the first and second power supply terminals. 6. The second inverter comprises a series combination of a p-channel field effect transistor and an n-channel field effect transistor, wherein the p-channel and n-channel field effect transistors are connected in series.
The drain of the channel transistor is coupled to the output of the second inverter, the p-channel and the n-
6. The voltage level shifting circuit configuration of claim 5, wherein both gates of the channel transistors are coupled to an input of a corresponding second inverter. 7. The voltage level shifting circuit configuration of claim 6, wherein all said transistors are MOS transistors. 8. A semiconductor device comprising: a pair of voltage buses; a first and a second p-channel MOS transistor; and a third and a fourth n-channel MOS transistor, each transistor having a gate for controlling conduction of the transistor. And wherein the first and third transistors are connected in series between the pair of voltage buses, the second and fourth transistors are connected in series between the pair of voltage buses, The node between the first and third transistors is connected to the third transistor.
And means connected to the gate of the fourth transistor for applying an input signal having one of the first and second levels directly to the gate of the first transistor, and inverting the input signal to the second transistor. Means for applying to the gates of said transistors, said means comprising only one inverter for inverting said input signal, between said second and fourth transistors, said means being responsive to said first level input signal. Coupled to one of the voltage buses through one of the second and fourth transistors and coupled to the other of the voltage buses through the other of the second and fourth transistors in response to the second level input signal. A node for providing an output signal level having a potential difference equal to the difference between the pair of voltage buses, the node having at least one of a parasitic capacitance and a load capacitance, A level shifter circuit, wherein each of the field effect transistors is a thin film field effect transistor formed on a non-semiconductor substrate. 9. The operation of the circuit, wherein the first level input signal is essentially a voltage applied to a first one of the voltage buses, and wherein the second level input signal is Is a positive voltage due to the voltage being applied to the second one of the voltage buses. 10. A semiconductor device comprising a first and a second p-channel field effect transistor each having a gate, a source and a drain, and a third having each a gate, a source and a drain.
And a fourth n-channel field effect transistor, wherein the first and third transistors are first and second
First connection means for connecting in series between the power supply terminals of the first and second power supply terminals, and a second connection means for connecting the second and fourth transistors in series between the first and second power supply terminals. Means for applying a binary, logic level, complementary input signal to the gates of the first and second transistors, the means being directly connected to a circuit input terminal. And a single inverter having an input connected directly to the gate of the second p-channel field effect transistor, the gate of the first p-channel field effect transistor being connected to the circuit. An output signal that is directly connected to an input terminal and that takes out an output from the second connection means between the second and fourth transistors and has a potential difference equal to the difference between the first and second power supply voltages; A means for providing a bell, the means having at least one of a parasitic capacitance and a load capacitance, wherein the circuit node in the first connection means between the first and third transistors comprises: Means for connecting to control the voltage at the gates of third and fourth transistors, each of the field effect transistors being a thin film field effect transistor formed on a non-semiconductor substrate, -Shifting circuit.