JP3210292B2 - Ferroelectric memory device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, and more particularly to a ferroelectric memory suitable for a 1T-1C type memory in which one memory cell is formed by using one transistor and one ferroelectric capacitor. The present invention relates to an apparatus and a driving method thereof.

[0002]

2. Description of the Related Art A ferroelectric capacitor in which a ferroelectric substance is arranged between a pair of electrodes exhibits polarization according to an applied voltage. The characteristic of the amount of polarization versus the applied voltage shows hysteresis, and residual polarization remains even when the applied voltage is set to zero.

[0003] When remanent polarization according to information is formed, a nonvolatile memory can be formed with a ferroelectric capacitor. A field effect transistor can be used to read the polarization of the ferroelectric capacitor. For example, one electrode of a ferroelectric capacitor is connected to an insulated gate electrode of an insulated gate field effect transistor, and on / off of the transistor is controlled according to polarization.

At present, a 2T-2C type ferroelectric random access memory (FeRAM) using two transistors and two capacitors per memory cell is 64k.
Even bits have been commercialized. However, a 1T-1C FeRAM using one transistor and one capacitor per memory cell is still in the research stage for practical use.

FIGS. 8A to 8C show a conventional ferroelectric memory. As shown in FIG. 8A, a floating gate electrode 53 of polycrystalline silicon or the like is formed on the surface of a p-type silicon substrate 51 via a gate oxide film 52. A ferroelectric layer 54 is formed on the floating gate electrode 53, and a control gate electrode 55 is further formed thereon. The above stack is patterned to form a gate electrode. A source region 61 and a drain region 62 are formed by adding an n-type impurity to both sides of the gate electrode by ion implantation or the like.

A positive voltage + V is applied to control gate electrode 55.
It is assumed that this voltage is removed after the voltage is applied. By applying a voltage of + V, the ferroelectric layer 54 is polarized as shown in the figure.
This polarization remains even after the voltage applied to the control gate electrode 55 is removed. Due to the remanent polarization, the floating gate electrode 53 is positively charged, and n
Induce channel 60. Therefore, the source 61 and the drain 62 are electrically connected by the n-channel 60.

As shown in FIG. 8B, after applying a negative voltage -V to the control gate electrode 55, this voltage is removed. The application of -V polarizes the ferroelectric layer 54 to the opposite polarity. Polarization remains even after the voltage applied to the control gate electrode 55 is removed. Therefore, the floating gate electrode 53 is negatively charged, and extinguishes the channel on the surface of the p-type silicon substrate 51. Therefore, the source 61 and the drain 6
The two are electrically separated.

In this manner, the ferroelectric layer 54 is applied by the voltage applied to the control gate electrode 55 to the substrate 51.
Can be controlled to record information in a nonvolatile manner.

In the ferroelectric memory shown in FIGS. 8A and 8B, a capacitor C2 having a gate oxide film 52 as a capacitor dielectric layer and a capacitor C1 having a ferroelectric layer 54 as a capacitor dielectric layer. Is a circuit type connected in series. The dielectric constant of the ferroelectric layer 54 is
, The capacitance of the capacitor C1 tends to be larger than the capacitance of the capacitor C2.

As shown in FIG. 8C, when a voltage V is applied between the substrate 51 and the control gate electrode 55, the voltage V1 applied to the ferroelectric capacitor C1 is applied to the capacitor C2 connected in series. It becomes smaller than the applied voltage V2.

The hysteresis characteristic of the ferroelectric capacitor is as follows:
When 1 is required, the voltage to be applied to the control gate electrode 55 is V1 + V2, and a large voltage is required.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a ferroelectric memory in which information can be written with a small voltage.

Another object of the present invention is to provide a ferroelectric memory having a novel structure.

Another object of the present invention is to provide a simple structure of 1T-
An object of the present invention is to provide a 1C type ferroelectric memory device.

Another object of the present invention is to provide a ferroelectric memory device capable of performing a write operation with only two lines, a word line and a bit line.

Still another object of the present invention is to provide a novel driving method of a 1T-1C type ferroelectric memory device.

[0017]

According to one aspect of the present invention, a semiconductor substrate, a gate insulating film formed on a surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, An insulated gate field effect transistor having a pair of source / drain regions formed on the surface of the semiconductor substrate on both sides of the gate electrode; an insulating film formed on the surface of the semiconductor substrate so as to cover the gate electrode;
A ferroelectric film formed on the insulating film, and a pair of capacitor electrodes formed to face each other on the ferroelectric film, wherein one of the pair of capacitor electrodes and the gate electrode are electrically connected to each other. And a pair of capacitor electrodes connected to the ferroelectric memory.

By forming a pair of electrodes opposed to and in contact with the ferroelectric layer to form a ferroelectric capacitor, a ferroelectric capacitor having a desired capacitance can be produced.
By arranging one electrode of the ferroelectric capacitor over the gate electrode, the stray capacitance of the capacitor electrode can be reduced.

According to another aspect of the present invention, there is provided an insulated gate field effect transistor having a source, a drain and an insulated gate, and a pair of capacitor electrodes disposed on one surface of the ferroelectric layer, A ferroelectric memory device including a memory cell having a ferroelectric capacitor connected between the drain and the insulated gate is provided.

By coupling the insulated gate and the drain of the insulated gate field effect transistor with a ferroelectric capacitor, a diode-connected field effect transistor is formed. Due to the remanent polarization of the ferroelectric capacitor,
The rising potential (threshold) of the diode-connected field effect transistor is controlled.

The polarization of the ferroelectric capacitor can be controlled according to the voltage applied between the source and the drain.

According to another aspect of the present invention, a plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel so as to intersect with the plurality of bit lines, and A ferroelectric memory cell connected to each intersection of a bit line and the word line, wherein each ferroelectric memory cell has a source, a drain, an insulated gate field effect transistor having an insulated gate, the drain and the insulated gate. A method for driving a ferroelectric memory device having a ferroelectric memory cell having a ferroelectric capacitor connected between the gate and a gate, comprising the steps of: (a) grounding a selected word line to ground; Applying a first reference potential to a word line and all bit lines, and writing first information in all ferroelectric memory cells connected to the selected word line; and (b) selecting the selected word line. Connect to The ground potential and the first reference potential are continuously supplied to the ferroelectric memory cells to which the first information is to be written among the ferroelectric memory cells thus written, and the other bit lines are supplied with the first potential smaller than the first reference potential. The first information is supplied only to the selected ferroelectric memory cell by supplying a third reference potential lower than the first reference potential and higher than the second reference potential to the second reference potential and the other word lines. Writing process,
(C) setting the potential of the bit line and the potential of a word line other than the selected word line to the same as in step (b), and setting the potential of the selected word line to be higher than the first reference potential;
And the second information is written to the ferroelectric memory cells to which the first information has not been written in the step (b) among the ferroelectric memory cells connected to the selected word line. And a method of driving the ferroelectric memory device.

After the first information is once written to a plurality of memory cells connected to the same word line, the first information is written again to the memory cell to which the first information is to be written, and the second information is written to the memory cell to which the first information is to be written. By writing the second information in the cell to be written, a writing method that is resistant to write disturb is provided.

According to still another aspect of the present invention, a semiconductor substrate, an insulated gate electrode formed on the semiconductor substrate, and a source region formed on the surface of the semiconductor substrate on both sides of the insulated gate electrode. A drain region, a first insulating layer formed on the surface of the semiconductor substrate so as to form the same surface surrounding the insulated gate electrode, an opening groove penetrating the first insulating layer and reaching the drain, A ferroelectric memory device comprising: a bit line filling the opening groove to form the same surface as the insulating layer; and a ferroelectric layer formed on the same surface covering the insulated gate electrode and the bit line. Is provided.

By forming an insulated gate electrode, a first insulating layer, and a bit line on the same surface and forming a ferroelectric layer on the same surface, a ferroelectric memory cell which is easy to miniaturize and has stable characteristics. Can be provided.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the ferroelectric memory shown in FIGS. 8A and 8B, a gate oxide film, a floating gate electrode, a ferroelectric layer and a control gate electrode are laminated and patterned into the same shape. Therefore, the capacitance of the ferroelectric capacitor tends to be larger than the capacitance formed by the floating gate electrode and the substrate. If the capacity of the ferroelectric capacitor is to be reduced, the thickness of the ferroelectric layer becomes unusually large, which involves difficulties in the manufacturing process.

Further, the configuration in which the ferroelectric layer is interposed between the floating gate electrode and the control gate electrode is characterized in that the interface between the floating gate electrode and the ferroelectric layer and the interface between the ferroelectric layer and the control gate electrode are formed. The properties of the interface between the two tended to differ, and it was not easy to obtain stable performance.

The present inventor proposes disposing a pair of electrodes in parallel on one surface of a ferroelectric layer and forming a ferroelectric capacitor between these electrodes. By adjusting the thickness of the ferroelectric layer and the distance between the electrodes, the capacitance of the ferroelectric capacitor can be set almost freely.

FIGS. 4 (A), 4 (B), 5 (A), 5 (B)
FIG. 3 is a diagram for explaining a preliminary experiment performed by the present inventors.

FIGS. 4A and 4B are a cross-sectional view and a plan view schematically showing the structure of the prepared sample. FIG.
(A) shows a cross-sectional configuration of a sample. Silicon substrate 21
A silicon oxide film 28 having a thickness of 350 nm is formed on the surface, and SrBi ₂ Ta ₂ O having a thickness of 200 nm is formed thereon.
₉ (SBT) Ferroelectric layer 29 was laminated. Ferroelectric layer 2
A pair of electrodes 31, 32 on the surface of 9 at intervals of 0.1 μm.
Were arranged in parallel.

FIG. 4B shows a plane pattern of the electrodes 31 and 32. The electrodes 31 and 32 have parallel electrode portions facing each other with a gap of 0.1 μm over a length of 200 μm, and a pad P for applying a voltage from substantially the center of each.
1, P2 has been pulled out. In the figure, the length l of the parallel electrodes is 200 μm, and the distance g between them is 0.1 μm.
m. The electrodes 31 and 32 were formed of a platinum film.

The dielectric constant of the SBT film depends on the method of preparation, but is about 200, which is significantly higher than the dielectric constant of air. Therefore, the capacitance of the ferroelectric capacitor formed between the electrodes 31 and 32 is almost determined by the dielectric constant and thickness of the ferroelectric layer 29, the distance between the electrodes 31 and 32, and the opposing length.

FIGS. 5A and 5B show FIGS.
5 is a graph showing characteristics of the sample shown in FIG. FIG. 5A shows a structure in which an oxide film 28, a ferroelectric layer 29, and electrodes 31 and 32 are stacked on a silicon substrate 21.
3 is an X-ray diffraction pattern showing what crystallinity a ferroelectric layer has. The horizontal axis indicates the X-ray diffraction angle 2θ in unit degree, and the vertical axis indicates the diffraction intensity on an arbitrary scale.

In the figure, the peaks other than the (100) plane diffraction peak of the silicon substrate and the (111) plane diffraction peak of the Pt electrode correspond to the SBT diffraction peak. From this result, it can be seen that the SBT layer formed on the silicon oxide film is well crystallized as a ferroelectric layer.

FIG. 5B shows the hysteresis characteristics of the samples shown in FIGS. 4A and 4B. The horizontal axis represents the applied voltage between the counter electrodes in units of V, and the vertical axis represents the accumulated charge in units of pC.
Indicated by The amount of charge when the applied voltage V = 0 indicates the magnitude of the remanent polarization. From the measured values shown in the figure, the remanent polarization is 0.5 p.
C, the remanent polarization per 1 μm is 2.5 f
C / μm.

In order to induce a channel on the semiconductor surface of the MOS transistor, a charge density of about 0.1 μC / cm ² may be provided. The gate area of the MOS transistor assuming 1 [mu] m ^2, given a charge density of 0.1 C / cm ^2, a charge amount of about 1 × 10 ^{-1 5} C. From the above-mentioned remanent polarization of 2.5 fC / μm, the required facing length of the capacitor electrode is about 0.4 μm. Such a dimension of the capacitor electrode is a dimension that does not hinder the fabrication of a highly integrated ferroelectric memory.

In the above-described sample, the interval between the capacitor counter electrodes is set to 0.1 μm. However, various changes may be made such as widening the interval and increasing the opposing length for ease of the manufacturing process. That will be obvious to those skilled in the art.

In the sample structure shown in FIG. 4A, by reducing the thickness of the ferroelectric layer 29, even if the polarization of the ferroelectric layer occurs with sufficient strength, the capacitance of the ferroelectric capacitor can be reduced. Is easily limited to a desired value. Further, it becomes easy to set the drive voltage to a desired value by selecting the electrode interval and the like.

FIGS. 1A and 1B schematically show the structure of a ferroelectric memory according to an embodiment of the present invention. FIG. 1 (A)
1 schematically shows a cross-sectional configuration of a ferroelectric memory, and FIG.
(B) shows the equivalent circuit.

In FIG. 1A, a field oxide film 2 is formed on a surface of, for example, a p-type silicon substrate 1 by a known LOCOS technique. A gate oxide film 3 having a thickness of, for example, 10 nm is formed on the surface of the active region surrounded by the field oxide film 2, and a gate electrode 4 of polycrystalline silicon is formed thereon, for example, having a thickness of 200 nm. N-type impurities are ion-implanted into both sides of the gate electrode 4 to form a pair of source / drain regions 5 and 6.

Incidentally, if necessary, a side spacer such as a silicon oxide film may be formed on the side wall of the gate electrode 4 and further ion implantation may be performed. In addition, wiring for the source / drain regions 5 and 6 can be formed.

Thereafter, a silicon oxide film 8 covering the gate electrode 4 is formed by chemical vapor deposition (CVD) or the like.
The surface of the silicon oxide film 8 is preferably flattened. On the surface of the silicon oxide film 8, SBT, Pb (Zr,
Ti) A ferroelectric layer 9 such as O ₃ (PZT) is formed. The ferroelectric layer 9 is, for example, an SBT layer having a thickness of 200 nm. Counter electrode 1 of Pt or the like on the surface of ferroelectric layer 9
1 and 12 are formed. At this time, it is preferable to form a via hole that penetrates through the ferroelectric layer 9 and the insulating layer 8 and reaches a part of the gate electrode 4 so that the electrode 11 is in electrical contact with the gate electrode 4.

Further, by arranging the electrode 11 and the gate electrode 4 so as to overlap in the substrate surface direction, the floating capacitance of the electrode 11 can be reduced.

FIG. 1B shows an equivalent circuit of the ferroelectric memory thus formed. A ferroelectric capacitor _CF is connected to a gate electrode G of a MOS transistor T having a source S, a drain D and a gate G. The source S and the drain D are the first bit line B1 and the second bit line B1, respectively.
Connected to the bit line B2, the other electrode of the ferroelectric capacitor C _f is connected to the word line W.

The recorded information can be known by checking the conduction between the pair of bit lines B1 and B2. Further, by applying a voltage equal to or more than a certain value between the bit lines B1, B2 and the word line W, the ferroelectric capacitor C _f
Information can be written to the

Hereinafter, a manufacturing process of the ferroelectric memory shown in FIG. 1 will be described with reference to FIGS. 2 (AV) to 3 (CP). 2 (AV) to 3 (CP), (AV),
(BV) and (CV) show cross-sectional views, respectively, and (A)
(P), (BP), and (CP) show plan views, respectively.

As shown in FIGS. 2 (AV) and (AP), p
Field oxide film 2 is formed on the surface of the active silicon substrate 1 by LOCOS, and then a thickness of 10 n
m gate oxide film 3 is formed by thermal oxidation. About 200 n thick on the surfaces of the field oxide film 2 and the gate oxide film 3
m of polycrystalline silicon layer 4 is formed, for example, by chemical vapor deposition (CV).
D). This polycrystalline silicon layer 4 is an n-type region doped with an n-type impurity.

The polycrystalline silicon layer 4 is patterned by photolithography using a resist pattern to form a gate electrode 4 extending from the gate oxide film 3 onto the field oxide film 2. Using the gate electrode 4 as a mask, n
An n-type source / drain region is formed by ion implantation of a type impurity (see FIG. 1A). The ion implantation is performed from a substantially vertical direction using, for example, As ions under the conditions of an acceleration energy of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

As shown in FIGS. 2B and 2B, a silicon oxide film 8 is formed by CVD so as to cover the gate electrode 4. After forming the silicon oxide film 8, the surface is flattened by chemical mechanical polishing (CMP). The CMP is performed using, for example, a trade name SC112 of Rodale.

As shown in FIGS. 2C and 2C, an SBT layer 9 having a thickness of, for example, 200 nm is formed on the surface of the silicon oxide film 8 whose surface is flattened. The SBT layer can be formed by, for example, a sol-gel method. A mixed alkoxide solution as a starting material is spin-coated on the substrate surface, and dried at a temperature of 250 ° C. This step is repeated four times, and then crystallization annealing is performed at a temperature of 800 ° C. for 30 minutes in an O ₂ atmosphere.

A resist pattern is formed on the surface of the ferroelectric layer 9, and the ferroelectric layer is patterned by, for example, reactive ion etching (RIE) using a mixed gas of CF ₄ and Ar to form a ferroelectric layer of the capacitor. Create layer 9.

As shown in FIGS. 3 (AV) and (AP), a silicon oxide film 10 is formed by CVD so as to cover the ferroelectric layer 9. A resist pattern is formed on the surface of the silicon oxide film 10, and a via hole VH reaching the gate electrode 4 is formed. Thereafter, the resist pattern is removed.

As shown in FIGS. 3 (BV) and 3 (BP), the silicon oxide film 10 is further removed by CVD. At this time, it is inevitable that the silicon oxide film 8 is slightly etched together with the etching of the silicon oxide film 10. However, by selecting the thickness of the silicon oxide film 10 to be small, the shape of the silicon oxide film 8 can be substantially reduced. It can be kept unchanged.

As shown in FIGS. 3 (CV) and 3 (CP), a Ti layer 12a is formed on the substrate surface on which the via holes VH are formed.
The counter electrodes 11, 12 of the capacitor are formed by forming and patterning an aluminum wiring layer composed of a laminate of the TiN layer 12b and the Al layer 12c. Ti layer 12
a serves to improve the adhesion, and the TiN layer 12b functions as a barrier layer for preventing solid phase diffusion of Al and Si.

As shown in FIG. 3C, the ferroelectric layer 9
Part electrodes 11 and 12 on the surface of the faces constitute a ferroelectric capacitor C _f.

Although the case where the capacitor dielectric layer is formed by SBT has been described, other ferroelectrics can be used. For example, PZT may be used instead of SBT. PZT has an even higher dielectric constant than SBT. The ferroelectric material forming the ferroelectric layer preferably has a dielectric constant 10 times or more that of the insulating layer (the dielectric constant of silicon oxide is approximately 4 in the case of silicon oxide) disposed thereunder. In order to make almost only the ferroelectric layer a capacitor dielectric layer, the distance between the counter electrodes 11 and 12 should be 3 times the thickness of the ferroelectric layer 9.
It is preferable to set it to twice or less. When electrically separating the ferroelectric capacitor from the underlying semiconductor device structure,
The thickness of the insulator layer 8 is preferably at least 10 nm even at the thinnest part.

In the above embodiment, the upper part of the MOS transistor was covered with the insulator layer 8 and the ferroelectric layer 9, and the counter electrodes 11 and 12 were provided on the ferroelectric layer 9. Counter electrode 1
1 and 12 need to be formed on the surface of the ferroelectric layer 9, but need not be provided on the upper surface of the ferroelectric layer 9.

FIG. 6 is a sectional view showing a structure of a ferroelectric memory according to another embodiment of the present invention. In this embodiment, similarly to the embodiment shown in FIG. 1, after forming a field oxide film 2 on the surface of a silicon substrate 1, a gate insulating film 3 and a gate electrode 4 are formed in an active region surrounded by a feed oxide film 2. ,
A MOS transistor having a source region 5 and a drain region 6 is formed, and an insulating layer 8 is provided so as to cover the surface. Counter electrodes 11, 12 are provided on the surface of the insulating layer 8,
The surfaces of the counter electrodes 11 and 12 and the surface of the insulating layer 8 are coplanar.

In such a configuration, for example, a part of the insulating layer 8 is formed first, the opposing electrodes 11 and 12 are formed on the surface thereof, and the remaining part of the insulating layer 8 is covered so as to cover the opposing electrodes 11 and 12. The portion can be formed by forming a film and performing a planarization process.

The ferroelectric layer 9 is formed so as to cover the surfaces of the opposing electrodes 11 and 12 and the insulating layer 8. In this way, a ferroelectric memory having the counter electrodes 11 and 12 embedded in the insulator layer 8 is obtained as shown in FIG.

FIG. 7 is a circuit diagram of a ferroelectric memory device constituted by using a ferroelectric memory as shown in FIGS. Bit lines BLm, BLm +
.. Are arranged, and word lines WL are arranged in the horizontal direction in FIG.
, WLn + 1,... are provided in plurality. Further, a plurality of source lines SLn, SLn + 1,... Are provided in the horizontal direction in the figure.

The bit line BL is connected to a bit line control circuit BLC
And to the sense circuit SC. Word line WL is connected to word line control circuit WLC.
Source line SL is connected to source line control circuit SLC.

The bit line control circuit BLC, word line control circuit WLC, and source line control circuit SLC control the potentials of the bit line BL, word line WL, and source line SL, respectively. The sense circuit SC detects a current flowing through the bit line BL.

Various changes may be made to the ferroelectric memory of FIGS. 1A and 6. For example, another insulated gate field effect transistor may be used instead of the MOS transistor. A ferroelectric material other than SBT and PZT may be used as the ferroelectric material. A conductive material other than Pt may be used for the electrode of the ferroelectric capacitor. Various other changes are possible. The circuit format of the memory cell is not limited to that shown in FIG.

FIGS. 9A to 9D show a novel memory cell according to an embodiment of the present invention. 9A shows a circuit format of one memory cell, FIGS. 9B and 9C are graphs showing a write operation and a read operation, and FIG. 9D is a graph showing a read current. .

In FIG. 9A, an insulated gate field effect transistor T has an insulated gate G, a source S, and a drain D. Between the insulated gate G and the drain D,
The ferroelectric capacitor _Cf is connected. Thus, a diode-connected insulated gate field effect transistor is formed.

Further, a capacitance C _gs is connected between the insulated gate G and the source S. This capacitance C _gs can be formed by the capacitance between the insulated gate and the source formed between the insulated gate G and the source S of the transistor T without externally attaching a capacitor. When a voltage is applied between the source S and the drain D, the ferroelectric capacitor C
Coupling ratio R that determines the voltage component applied to _f
= C _gs / (C _gs + C _f ) is preferably 0.2 or more. The drain D is connected to the bit line BL, and the source S
Are connected to a word line WL.

Hereinafter, it is assumed that the insulated gate field effect transistor T is an n-channel transistor. When a voltage V is applied between the source S and the drain D, this voltage can be considered to be divided by two capacitors C _gs and C _f . The voltage applied to the ferroelectric capacitor _Cf is defined as _Vf .

[0069] Figure 9 (B) is a graph showing the polarization P versus the applied voltage V _f of the ferroelectric capacitor C _f. A hysteresis curve indicated by a broken line shows a hysteresis characteristic in a case where polarization is caused until saturation occurs. A hysteresis curve indicated by a solid line indicates a hysteresis characteristic used for a memory operation. The three straight lines C _gs · (V−V _f ) are load straight lines when the capacitor C _gs is used as a load.
This shows a case where voltages V = + Vcc, 0, and -Vcc are applied between the drains D. Once + Vcc is applied, even if the applied voltage V is returned to "0", the residual polarization of "1" remains, and once -Vcc is applied, the applied voltage V is changed to "0".
, The residual polarization representing "0" remains.

FIG. 9C is a graph showing read characteristics. As shown in FIG. 9 (B), the ferroelectric capacitor C _f and residual polarization occurs. At the time of memory reading, a voltage + Vr smaller than the writing voltage + Vcc
Is applied. In a state where reading voltage + Vr is applied, the intensity if the dielectric capacitor C _f is "0", strong polarization of the ferroelectric capacitor C _f is changed to "0", "1" is long if positive polarization Increases further. The conductivity of the insulated gate field effect transistor T changes according to the difference in the amount of polarization, and the stored information can be read.

FIG. 9D shows a change in the read current. The horizontal axis indicates the applied voltage V, and the vertical axis indicates the current I flowing through the insulated gate field effect transistor T. When the written information is "1", a channel is generated due to the remanent polarization, and the current I increases as soon as the voltage V is increased.

On the other hand, when the written information is “0”, the current I does not immediately flow even when the voltage V is applied.
When the applied voltage V is the read voltage Vr, the flowing current is weak. Thus, the current I flowing through the transistor T depends on whether the written information is “1” or “0”.
Varies significantly. Information can be read by detecting the difference between the currents. In writing, it is preferable that the applied voltage be pulsed to suppress power consumption.

FIGS. 10A and 10B show the configuration and operation of the memory cell array. FIG. 10A is a block diagram illustrating a configuration of a memory cell array, and FIG. 10B is a graph illustrating voltages applied to word lines WL and bit lines BL. The actual applied voltage has a pulse waveform, but is shown as a DC waveform for simplicity.

In FIG. 10A, a plurality of bit lines B
L are arranged in parallel in the vertical direction in the figure. The plurality of word lines WL are arranged in parallel in the horizontal direction in the figure so as to intersect with the bit lines BL. Bit line BL and word line W
The memory cell MC shown in FIG. 9A is connected to each intersection of L. The bit line BL is a bit line control circuit BL
C and supplied with a bit line control signal. The bit line BL is connected to the sense circuit SC at the bottom in the figure, and a current flowing through the bit line is detected. Word line WL
Are connected to a word line control circuit WLC and supplied with a word line control signal.

At the time of reading, between the bit line BL and the word line WL connected to the memory cell to be read, FIG.
By applying a read voltage Vr as shown in (D) and applying a smaller voltage to other memory cells, information of a desired memory cell can be read.

FIG. 10B shows a signal waveform at the time of writing. The upper part of the figure shows the signal waveform applied to the word line WL, and the lower part shows the signal waveform applied to the bit line BL. The word line WL has a signal waveform of ground potential 0, reference potential Vcc.
And 4 levels including 2 Vcc / 3 and 4 Vcc / 3. The signal waveform of the bit line BL has reference potentials Vcc and Vc
It is two levels of c / 3.

It is assumed that one word line is selected and desired information is written to a memory cell connected to the word line. Time region IIIA indicates the selected state of the word line. The potential of the selected word line is set to the ground potential “0”, and the non-selected word lines are set to the reference potential Vcc. All bit lines BL are set to the reference potential Vcc.

FIG. 11A shows a word line selection state.
The ground potential “0” is applied only to the selected word line WL, and the reference potential Vc is applied to the other word lines and bit lines.
c is given. Therefore, voltage + Vcc is applied to all memory cells connected to the selected word line. With this applied voltage, “1” is written to all the memory cells connected to the selected word line.

In FIG. 10B, the time domain IIIA
From time region IIIB to the time region IIIB, the potential of the unselected word line WL is lower than the reference potential Vcc by 2 Vcc / while the potential of the selected word line WL is kept at the ground potential.
Changed to 3. Further, “1” is set in the bit line BL.
Are kept at the reference potential Vcc, and the potentials of the other bit lines are changed to Vcc / 3.

FIG. 11B shows a state in the time domain IIIB. + Vcc is continuously applied to the memory cell to which "1" is to be written, while + Vcc is applied to the other memory cells.
A potential of Vcc / 3 or -Vcc / 3 is applied. By applying such a voltage, "1" is surely written to the memory cell to which "1" is to be written, while
Other memory cell states are not significantly affected.

In FIG. 10B, the time domain IIIB
, The potential of the selected word line is changed from the ground potential to 4 Vcc / 3. The potential of the unselected word line does not change. Also, the bit line BL
Is maintained in the same manner as in the time domain IIIB.

FIG. 11C shows a state in the time domain IIIC. The potential of the selected word line changes from "0" to 4 Vcc
By changing to // 3, -Vcc is applied to memory cells other than those to which "1" is to be written (memory cells to which "0" is to be written) among the memory cells connected to the selected word line. And "0" is written.
Other memory cells include + Vcc / 3 or -Vcc
Only a potential of / 3 is applied.

By executing such a writing method, a writing characteristic with a large disturbance resistance can be obtained. Further, the writing of “1” and the writing of “0” can be performed only by changing the potential of the selected word line WL, so that the circuit configuration can be simplified.

FIGS. 12A and 12B show a configuration of a memory cell suitable for realizing the above-described circuit format. FIG.
12A shows a cross-sectional view, and FIG. 12B shows a top view. A cross section along XII A-XII A in FIG. 12B corresponds to the cross section in FIG.

On the surface of the p-type silicon substrate 1, a well-known L
A field oxide film 2 is formed by OCOS. A pair of insulated gate field effect transistors are formed in each active region surrounded by the field oxide film 2.

As an insulated gate field effect transistor, for example, a MOS transistor is used. After a gate oxide film 3 is formed in each active region, a pair of gate electrodes 4 is formed thereon with a polycrystalline silicon layer. On the gate electrode 4, a bottom electrode 18 having properties suitable for an electrode of a ferroelectric capacitor is formed. In the configuration shown, the gate electrode 4 and the bottom electrode 18 constitute a gate electrode structure.

Using the gate electrode structure as a mask, ion implantation for forming the source region 5 and the drain region 6 is performed. Here, in order to increase the coupling ratio R by increasing the gate-source capacitance C _gs , ion implantation is divided into two stages, and the source region 5 and the drain region 6 are formed by separate ion implantation.

For example, a region where a drain region is to be formed is masked with a resist mask or the like, and As ions are implanted while rotating the substrate under the conditions of an incident angle of 60 degrees, an acceleration energy of 60 keV, and a dose of 1 × 10 ¹⁵ cm ^−2. I do. By setting the incident angle to 60 degrees, the implanted As ions are distributed below the gate electrode. Therefore, the capacitance C _gs is positively formed between the source region 5 and the gate electrode 4 to be formed.

The source region is masked with a resist mask or the like.
Exposing the region where the drain region is to be formed,
Acceleration energy 30 keV from a direct direction, dose 1 × 10
^Fifteencm ^-2As ions are implanted under the following conditions. This ion injection
As a result, a pair of drain regions 6 are formed. ion
Since the injection direction is vertical, the drain region 6 is slightly gated.
Extends below the contact electrode 4 but projects on the substrate surface.
Time, the amount by which the drain region 6 overlaps with the gate electrode
(Area) is that the source region 5 overlaps the gate electrode.
It becomes significantly smaller than the amount (area). Therefore, the source
・ Gate-to-gate capacitance is larger than drain-to-gate capacitance
No.

An insulating film 17 is once formed on the substrate surface, and an opening reaching drain region 6 is formed. A bit line 19 also serving as a drain electrode is formed in this opening. The bit line 19 also serves as a bottom electrode of the ferroelectric capacitor. Bottom electrode 18 on insulating gate electrode, insulating layer 1
7. The surface of the bit line 19 is polished to form a flat same surface, and the ferroelectric layer 20 is formed thereon. Ferroelectric layer 2
Since 0 is formed on a flat surface, its characteristics are easily stabilized. After forming the ferroelectric film 20, unnecessary portions thereof are removed as necessary.

The insulating layer 21 covers the ferroelectric layer 20.
Is formed. An opening penetrating through the insulating layers 21 and 17 is formed until reaching the source region 5, and a word line 22 electrically connected to the source region 5 is formed.

As shown in FIG. 12B, a word line 22 extends in the horizontal direction in the figure, and a ferroelectric layer 20 extends below it. The bit line 19 extends below the ferroelectric layer 20 in the vertical direction in the figure. The contact hole 23 is connected to the word line 2
2 shows a contact region between the semiconductor device 2 and the source region 5. Also, 1
An area corresponding to one memory cell MC is indicated by a broken line.

The manufacturing process for manufacturing the memory cell as shown in FIGS. 12A and 12B will be described with reference to FIGS.
This will be described with reference to FIG.

As shown in FIG. 13A, after a field oxide film is formed on the surface of a p-type silicon substrate 1, a gate oxide film 3 is formed to a thickness of about 10 nm, and a polycrystalline silicon layer is formed thereon. Deposit about 200 nm. The gate electrode 4 is formed by patterning the polycrystalline silicon layer. Using the gate electrode 4 and, if necessary, a resist pattern as a mask, ion implantation for forming the source region 5 and the drain region 6 is performed.

In order to increase the amount of overlap between the gate electrode 4 and the source region 5, ion implantation into the source region 5 is performed at an incident angle of 60 degrees and an acceleration energy of 60 ke.
V and a dose of 1 × 10 ¹⁵ cm ⁻² are implanted by implanting As ions. The ion implantation for forming the drain region 6 is performed under the conditions of an acceleration energy of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² from the vertical direction. It may be performed by implanting As ions.

As shown in FIG. 13B, the gate electrode 4
A silicon oxide film 17a is formed by CVD so as to cover. After forming the silicon oxide film 17a, the surface is flattened by chemical mechanical polishing (CMP).

As shown in FIG. 13C, an opening exposing the source region 5 and the drain region 6 is formed in the silicon oxide film 1.
7a, a polycrystalline silicon layer 30 is deposited on the surface of the substrate by CVD, and the opening is filled back.

As shown in FIG. 13D, the gate electrode 4 is exposed by performing CMP again from the front side. On the surface after the CMP, polycrystalline silicon plugs 30a and 30b connected to the gate electrode 4, the silicon oxide layer 17a, the source 5, and the drain 6 form the same plane.

As shown in FIG. 14A, a lower electrode 18a formed of a TiN / Ti laminate and a main electrode 18b formed of Pt are formed on the same surface of the substrate. In the lower electrode 18a, the Ti layer is a layer for improving adhesion, and the TiN layer functions as a diffusion barrier layer. The Pt main electrode layer 18b forms an electrode having excellent contact characteristics with the ferroelectric.

As shown in FIG. 14B, the electrode layer 18
By forming a resist pattern on the lamination of a and 18b and patterning the electrode layer, a bottom electrode 18A connected to the gate electrode 4 and a bottom electrode 18B connected to the drain region are formed. This patterning can be performed, for example, by reactive ion etching (RIE) using a mixed gas of CF ₄ and Ar.

After patterning the electrodes 18A and 18B,
A silicon oxide layer 17b is deposited by CVD to completely cover the bottom electrode.

As shown in FIG. 14C, the CM
By performing P, a flat surface where the bottom electrodes 18A and 18B are exposed is formed.

As shown in FIG. 15A, a 200 nm-thick SrBi ₂ Ta ₂ O film is formed on the formed flat surface.
_{9 An} (SBT) layer 20 is formed. The SBT layer can be formed by, for example, a sol-gel method. First, a mixed alkoxide solution as a starting material is spin-coated, and the temperature is 25 ° C.
Dry at 0 ° C. This coating-drying step is repeated four times to obtain a coating film having a desired thickness. Next, crystallization annealing treatment is performed for 30 minutes at a temperature of 800 ° C. in an O ₂ atmosphere.

By such steps, an SBT layer having excellent ferroelectric properties can be obtained. After forming the SBT layer 20,
Forming a resist pattern on the surface of the SBT layer 20;
The patterning of the T layer 20 is performed. This patterning
For example, it can be performed by reactive ion etching (RIE) using a mixed gas of CF ₄ and Ar. After the patterning of the ferroelectric layer 20, a silicon oxide film 21 is deposited over the surface thereof by CVD.

As shown in FIG. 15B, an opening is formed through the silicon oxide films 21 and 17b by photolithography, and the surface of the plug 30a connected to the source region 5 is exposed. In this opening, the opening is backfilled by depositing a polycrystalline silicon layer by CVD,
A flat surface is formed by performing the same CMP as in FIG. A source extraction electrode 31 is formed in the opening.

As shown in FIG. 15C, a laminated wiring layer including a lower wiring layer 32a and a main wiring layer 32b is formed on a flat surface. By patterning the laminated wiring layer,
A word line 32 is formed. The lower wiring layer 32a
Is formed of, for example, a laminate of TiN / Ti, and the main wiring layer 3
2b is formed of Al or an Al alloy.

According to such a manufacturing process, since important constituent elements are formed on a flat surface, stable characteristics can be easily obtained. Further, since the ferroelectric capacitor is formed on the MOS transistor structure, the occupied area per memory cell can be reduced.

In the configuration shown in FIG. 12A, electrodes are arranged on the lower surface of the ferroelectric layer to form a ferroelectric capacitor. The ferroelectric capacitor can also be formed by arranging electrodes on the upper surface of the ferroelectric layer.

FIGS. 16A and 16B show a configuration of a memory cell according to another embodiment of the present invention. This memory cell is
Counter electrodes 18 and 19 are formed on the upper surface of the ferroelectric layer 20 and have the same function as the memory cell shown in FIG. A silicon oxide layer 21 is formed on the surfaces of the counter electrodes 18 and 19, and an opening 23 reaching the source region 5.
Are formed. The electrode 18 is connected to the gate electrode 4 by a conductive plug 25 formed at a position not shown, and the electrode 19 is connected to the drain region 6 by a plug 26 formed at a position not shown. The other points are the same as the structure illustrated in FIG.

FIG. 16B is a top view of the memory cell shown in FIG. A cross section along the dashed-dotted line XVI A-XVI A corresponds to the cross section in FIG. The region indicated by the cross hatch indicates the region where the contact hole exists.

FIGS. 17 (AV) to (DP) and FIG. 18 (A)
V) to (CP) are a cross-sectional view and a plan view for describing a process for manufacturing the memory cell shown in FIGS. 16A and 16B. The drawing attached with V is a sectional view, and the drawing attached with P is a plan view.

As shown in FIG. 17 (AP), a feed oxide film 2 is formed on the surface of a p-type silicon substrate 1 to define an active region.

As shown in FIG. 17A, a gate oxide film 3 is formed on the active region by thermal oxidation to a thickness of about 10 nm, and a polycrystalline silicon layer 4 is deposited thereon to a thickness of about 200 nm. The polycrystalline silicon layer is patterned to form a gate electrode 4 extending from the gate oxide film onto the feed oxide film. Using the gate electrode 4 as a mask, ion implantation for forming the source region 5 and the drain region 6 is performed.

In order to increase the amount of overlap between the gate electrode 4 and the source region 5, ion implantation into the source region 5 is performed at an incident angle of 60 degrees and an acceleration energy of 30 ke.
The ion implantation of As is performed under the conditions of V and a dose of 1 × 10 ¹⁵ cm ⁻² . The ion implantation for forming the drain region 6 may be performed by implanting As from the vertical direction under the conditions of an acceleration energy of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

As shown in FIGS. 17 (BV) and (BP),
A silicon oxide film 17 is deposited by CVD so as to cover the gate electrode 4. After depositing the silicon oxide film 17,
The surface is flattened by CMP.

As shown in FIGS. 17 (CV) and (CP),
An SBT layer 20 having a thickness of, for example, 200 nm is formed on the surface of silicon oxide film 17 having a flattened surface. SBT
The layer 20 can be formed by, for example, a sol-gel method. The deposited SBT layer 20 is etched with a mixed gas of CF ₄ and Ar to pattern the SBT layer 20.

Next, a Pt layer is formed by sputtering,
The opposite electrodes 18 and 19 are formed by patterning by etching with a mixed gas of CF ₄ and Ar.

As shown in FIGS. 17 (DV) and (DP),
CV so as to cover the SBT layer 20 and the counter electrodes 18 and 19.
D forms a silicon oxide film 21. A resist pattern is formed on the silicon oxide film 21 and the counter electrode 1 is formed.
Contact holes to 8 and 19 and contact holes reaching the gate electrode and drain regions are formed.

As shown in FIGS. 18 (AV) and (AP),
Ti layer, TiN on the substrate surface with contact holes
The wiring layers 27 and 28 are formed by forming and patterning a wiring layer composed of a layer and an Al layer. Wiring layer 28
Becomes a bit line. Note that the Ti layer is an electrode layer useful for improving adhesion, and the TiN layer functions as a diffusion barrier.

As shown in FIGS. 18 (BV) and (BP),
A silicon oxide layer 29 is deposited by CVD so as to cover the substrate surface, and a contact hole 30 reaching the source region 5 is formed.

As shown in FIGS. 18 (CV) and (CP),
A wiring layer 31 composed of a Ti layer, a TiN layer, and an Al layer is formed and patterned to form a word line.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0123]

As described above, according to the present invention,
A ferroelectric memory in which a ferroelectric capacitor has a desired small capacitance is provided. When the capacitance of the ferroelectric capacitor is made smaller than that of the insulated gate electrode,
The main part of the applied voltage can be applied to the ferroelectric capacitor.

Since the counter electrode of the ferroelectric capacitor is formed on the same surface of the ferroelectric layer, the characteristics of the ferroelectric capacitor can be easily stabilized. The patterning process of the counter electrode can be simplified.

A ferroelectric memory device having a simple configuration is provided. Although only one transistor is used per memory cell, a method of driving a ferroelectric memory device having high resistance to disturbance during writing is provided.

[Brief description of the drawings]

FIG. 1 is a sectional view and an equivalent circuit diagram showing a ferroelectric memory according to an embodiment of the present invention.

FIGS. 2A and 2B are a cross-sectional view and a plan view for explaining a manufacturing process of the ferroelectric capacitor shown in FIG.

3A and 3B are a cross-sectional view and a plan view for explaining a manufacturing process of the ferroelectric capacitor shown in FIG.

4A and 4B are a cross-sectional view and a plan view for explaining a preliminary experiment performed by the present inventors.

FIG. 5 is a graph showing characteristics of the sample shown in FIG.

FIG. 6 is a sectional view showing a ferroelectric memory according to another embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of the ferroelectric memory device.

FIG. 8 is a sectional view and an equivalent circuit diagram for explaining a ferroelectric memory according to the related art.

FIG. 9 is a circuit diagram showing a memory cell according to an embodiment of the present invention and a graph showing characteristics.

FIG. 10 is a circuit diagram and a signal waveform diagram showing a circuit format of a memory cell array according to an embodiment of the present invention.

FIG. 11 is a schematic plan view showing how the memory cell array operates according to the signal waveforms shown in FIG. 2 (B).

FIG. 12 is a sectional view and a plan view showing a configuration of a ferroelectric memory device according to an embodiment of the present invention.

13 is a cross-sectional view for explaining a manufacturing process for manufacturing the ferroelectric memory device of FIG.

14 is a cross-sectional view for explaining a manufacturing process for manufacturing the ferroelectric memory device of FIG.

15 is a cross-sectional view for explaining a manufacturing process for manufacturing the ferroelectric memory device of FIG.

FIG. 16 is a sectional view and a plan view showing a configuration of a ferroelectric memory device according to an embodiment of the present invention.

17A and 17B are a cross-sectional view and a plan view for explaining a manufacturing process for manufacturing the ferroelectric memory device of FIG.

18A and 18B are a cross-sectional view and a plan view for explaining a manufacturing process for manufacturing the ferroelectric memory device of FIG.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5, 6 source / drain region 8 insulating layer 9 ferroelectric layer 11, 12 counter electrode (of ferroelectric capacitor) C _f ferroelectric capacitor B bit line W Word line T Insulated gate field effect transistor G Insulated gate S Source D Drain C _f Ferroelectric capacitor C _gs Source-gate capacitance BL Bit line WL Word line 17 Insulating layer 18 Bottom electrode 18A, 18B Bottom electrode 19 Bit line Reference Signs List 20 ferroelectric layer 21 insulating layer 22 word line 30a, 30b plug 31 plug 32 word wiring layer

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Enge 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-9-82905 (JP, A) JP-A-6-119773 (JP, A) JP-A-11-176958 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/105 H01L 21/822 H01L 27/04

Claims (16)

(57) [Claims] A semiconductor substrate; a gate insulating film formed on the surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; and a gate electrode formed on both sides of the gate electrode on the surface of the semiconductor substrate. An insulated gate field effect transistor having a pair of source / drain regions; an insulating film covering the gate electrode and formed on the surface of the semiconductor substrate; and a ferroelectric film formed on the insulating film. A ferroelectric film having a pair of capacitor electrodes formed on the ferroelectric film so as to face each other, the pair of capacitor electrodes being electrically connected to one of the pair of capacitor electrodes and the gate electrode; Dielectric memory device. 2. The ferroelectric memory device according to claim 1, wherein an interval between the pair of capacitor electrodes has a value not more than three times a thickness of the ferroelectric film. 3. The ferroelectric memory device according to claim 1, wherein one of said pair of capacitor electrodes is disposed above said gate electrode. 4. The ferroelectric memory device according to claim 1, wherein said insulating film has a thickness of 10 nm or more. 5. The pair of capacitor electrodes are buried in the insulating film to form a common surface with the insulating film,
5. The ferroelectric memory device according to claim 1, wherein said ferroelectric film covers said pair of capacitor electrodes and said insulating film. 6. The ferroelectric memory device according to claim 1, wherein the other of said pair of capacitor electrodes is electrically connected to one of said pair of source / drain regions. 7. An insulated gate field effect transistor having a source, a drain, and an insulated gate, and a pair of capacitor electrodes disposed on one surface of a ferroelectric layer, wherein the drain and the insulated gate are connected to each other. A ferroelectric memory device comprising a memory cell having a ferroelectric capacitor connected therebetween. 8. A plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel so as to intersect with the plurality of bit lines, and an intersection of the bit line and the word line , Wherein each ferroelectric memory cell includes an insulated gate field effect transistor having a source, a drain, and an insulated gate, and a ferroelectric memory cell disposed on one surface of the ferroelectric layer. A ferroelectric memory device comprising: a ferroelectric memory cell having a pair of capacitor electrodes and having a ferroelectric capacitor connected between the drain and the insulated gate. 9. The ferroelectric memory device according to claim 8, wherein the insulated gate field effect transistor has a larger source-insulated gate capacitance than a drain-insulated gate capacitance. 10. The ferroelectric memory according to claim 9, wherein the insulated gate field effect transistor has a larger overlap area between the insulated gate and the source than an overlap area between the insulated gate and the drain. apparatus. 11. When the capacitance of the ferroelectric capacitor is C _f and the capacitance between the source and the insulated gate is C _gs , a coupling ratio R = C _gs / (C _gs + C _f ) is 0.2 or more. The ferroelectric memory device according to claim 8, wherein: 12. An operation connected to the word line and the bit line, the operation of applying a positive potential to the bit line with respect to the potential of the word line to write first information in the ferroelectric capacitor. 12. A control circuit capable of executing an operation of applying a negative potential to the bit line with respect to the potential of the word line and writing second information to the ferroelectric capacitor. A ferroelectric memory device according to any one of claims 1 to 3. 13. A plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel so as to intersect with the plurality of bit lines, and each of the bit lines and the word lines A ferroelectric memory cell connected to the intersection, wherein each ferroelectric memory cell is connected between the drain and the insulated gate, an insulated gate field effect transistor having a source, a drain, and an insulated gate. A method for driving a ferroelectric memory device having a ferroelectric memory cell having a ferroelectric capacitor, comprising the steps of: (a) grounding a selected word line and connecting other word lines and all bit lines Applying a first reference potential to write first information into all ferroelectric memory cells connected to the selected word line; and (b) ferroelectric memory connected to the selected word line. The ground potential and the first reference potential are continuously supplied to the ferroelectric memory cell to which the first information is to be written, and the second reference potential smaller than the first reference potential is supplied to the other bit lines. (C) supplying a third reference potential lower than the first reference potential and higher than the second reference potential to the word line to write the first information only in the selected ferroelectric memory cell; The potential of the bit line and the potential of the word lines other than the selected word line are the same as in step (b), and the potential of the selected word line is higher than the first reference potential.
And the second information is written to the ferroelectric memory cells to which the first information has not been written in the step (b) among the ferroelectric memory cells connected to the selected word line. And a method for driving a ferroelectric memory device. 14. When the first reference potential is Vcc, the second, third, and fourth reference potentials are about Vcc / 3, about 2
14. The driving method of a ferroelectric memory device according to claim 13, wherein Vcc / 3 is about 4 Vcc / 3. 15. A semiconductor substrate, an insulated gate electrode formed on the semiconductor substrate, a source region and a drain region formed on a surface of the semiconductor substrate on both sides of the insulated gate electrode, A first insulating layer formed on the surface of the semiconductor substrate so as to surround and form the same surface; an opening groove penetrating the first insulating layer to reach the drain; and the insulating layer filling the opening groove. A ferroelectric memory device comprising: a bit line forming the same plane as the above; and a ferroelectric layer formed on the same plane covering the insulated gate electrode and the bit line. 16. A second insulating layer formed on the semiconductor substrate so as to cover the ferroelectric layer, an opening reaching the source region through the second insulating layer and the first insulating layer, The ferroelectric memory device according to claim 15, further comprising a word line filling the opening and crossing the bit line and extending on the second insulating layer.