JP3210236B2 - Pattern generator for IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
More particularly, the present invention relates to a pattern generator for an IC test apparatus that generates pattern data serving as a reference of a test signal applied to an IC to be measured.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or a part of the IC product in each process of a manufacturing department and an inspection department and to inspect its electrical characteristics. There is. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus gives predetermined test pattern data to the IC to be measured, reads data output from the IC to be measured in response thereto, and outputs whether there is no problem in the basic operation and function of the IC to be measured. The analysis is performed based on the data, and the inspection regarding the electrical characteristics is performed. The tests in the IC test apparatus are roughly classified into a direct current test (DC measurement test) and a function test (FC measurement test). In the DC test, a predetermined voltage or current is applied from the DC measuring means to the input / output terminal of the IC under test to check whether there is any defect in the basic operation of the IC under test. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the IC under test from the pattern generating means, and the output data of the IC under test is read. It is to check whether or not.

FIG. 2 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test apparatus is roughly divided into a tester section 50 and an IC mounting apparatus 70. The tester unit 50 includes a control unit 51, a DC measurement unit 52, a timing generation unit 5
3. It comprises a pattern generating means 54, a pin control means 55, a pin electronics 56, a fail memory 57 and an input / output switching means 58. In the actual tester section 50,
There are various other components, but only necessary parts are shown in this specification. The tester unit 50 and the IC mounting device 70 are connected by a signal line composed of a plurality of (m) coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the coaxial cables is associated with each other by a relay matrix (not shown), and transmission of various signals is performed between a predetermined terminal and the coaxial cable. This signal line is physically connected to the IC mounting device 70.
Of the same number as the total number m of input / output terminals.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted on a socket. The input / output terminal of the IC 71 to be measured and the input / output terminal of the IC mounting device 70 are connected in one-to-one correspondence. For example, if the IC 71 to be measured having 28 input / output terminals is 1
In the case of the IC mounting device 70 capable of mounting zero ICs, a total of 28
It has zero input / output terminals. At present, some of those on the market have 1024 input / output terminals. The control means 51 controls the entire IC test apparatus,
It performs operations and management, and has a microprocessor configuration. Therefore, although not shown, it has a ROM for storing a system program, a RAM for storing various data, and the like. Further, the control means 51 includes a DC
The measuring means 52, the timing generating means 53, the pattern generating means 54, the pin control means 55 and the fail memory 57 are connected via buses (data bus, address bus, control bus) 65 and respective internal registers. The control means 51 converts the DC test data into the DC measurement data 52
A signal for starting a function test is sent to the timing generator 53, data for generating a test pattern is sent to the pattern generator 54, and expected value data and the like are sent to the pin controller 55.
Respectively. In addition, the control means 51 outputs various data to respective components via a bus. In particular, the control means 51 has internal registers (hereinafter referred to as "pin registers") corresponding to pins for storing data relating to each input / output terminal, the number of which corresponds to the number of input / output terminals, and writes data therein. Thus, data relating to the input / output terminals is transferred to each component. Further, the control unit 51 reads out the test results (fail data and DC data) from the fail memory 57 and the DC measurement unit 52, performs various data processing and the like, analyzes the test data, and determines the quality of the IC.

[0005] The DC measurement means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting device 70 based on the data. DC
The measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result into an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data indicating the test result written in the internal register of the DC measuring means 52 is read by the control means 51 via the bus 65 and analyzed there. Thus, the DC test is performed. DC measurement means 5
2 are reference voltages VIH, VIL, VO for the driver 63 and the comparator 64 of the pin electronics 56.
H and VOL are output.

The timing generation means 53 outputs a predetermined clock to the pin control means 55, and the data selector 59,
It controls the operation speed and the like of the formatter 60, the I / O formatter 61, and the comparator logic circuit 62. Therefore, the test signal P2 output from the formatter 60 to the pin electronics 56 and the I / O formatter 61
The output timing of the switching signal P6 output to the input / output switching unit 58 is also controlled according to the high-speed operation clock CLK from the timing generation unit 53. The pattern generating means 54 inputs test pattern generation data and the like from the control means 51 and outputs pattern data based on the data to the data selector 59 of the pin control means 55.

The pin control means 55 includes a data selector 59,
It comprises a formatter 60, an I / O formatter 61 and a comparator logic circuit 62. The data selector 59 is composed of a memory storing various test signal creation data (address data / write data) P1, switching signal creation data P5 and expected value data P4, and stores the pattern data from the pattern generation means 54. Input as an address, and test signal creation data P corresponding to the address.
1 and the switching signal creation data P5 are output to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62.

The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) P1 from the data selector 59 to create a predetermined applied waveform. Then, it is used as a test signal P2 in the timing
The signal is output to the driver 63 of the pin electronics 56 in synchronization with the timing signal (the rate signal RATE or the edge signal EDGE). Like the formatter 60, the I / O formatter 61 has a multi-stage configuration of flip-flop circuits and logic circuits.
The switching signal generation data P5 is processed to generate a predetermined application waveform, and the waveform is output to the input / output switching unit 58 as a switching signal P6 in synchronization with the timing signal from the timing generation unit 53.

The comparator logic circuit 62 includes read data P3 from the comparator 64 of the pin electronics 56 and expected value data P4 from the data selector 59.
And outputs the result of the determination to the fail memory 57 as fail data FD. The pin electronics 56 includes a plurality of drivers 63 and comparators 64.
Consists of One driver 63 and one comparator 64 are provided for each input / output terminal of the IC mounting device 70, and one of them is connected via the input / output switching means 58. The input / output switching means 58 is provided with a switching signal P5 from the I / O formatter 61.
The connection state between one of the driver 63 and the comparator 64 and the input / output terminal of the IC mounting device 70 is switched in accordance with. That is, the IC mounting device 7
When the number of input / output terminals of 0 is m, the number of drivers 63, comparators 64, and input / output switching means 58 is m. However, when measuring a memory IC, etc.,
Since a comparator is not required for an address terminal, a chip select terminal, or the like, the number of comparators and input / output switching means may be small.

The driver 63 is connected to input / output terminals of the IC mounting device 70, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the IC 71 to be measured via the input / output switching means 58. ,
The test signal P from the formatter 60 of the pin control means 55
A signal of high level “1” or low level “0” corresponding to 2 is applied, and a desired test pattern is written to the IC under test 71. The comparator 64 inputs a signal output from the data output terminal of the IC 71 to be measured via the input / output switching means 58, compares it with the reference voltages VOH, VOL at the timing of the strobe signal from the control means 51, and The comparison result is output to the comparator logic circuit 62 as read data P3 of high level “1” or low level “0”.

The fail memory 57 stores the fail data FD output from the comparator logic circuit 62, and is constituted by a RAM which has the same storage capacity as the IC 71 to be measured and which can be read and written at any time. The fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 70. For example, if the total number of input / output terminals of the IC mounting device 70 is 280, and 160 of them are data output terminals, the fail memory 57 stores data of the same number or more than this number of data output terminals. It is composed of a memory having an input terminal. The fail data FD stored in the fail memory 57 is read out by the control means 51, transferred to a data processing memory (not shown), and analyzed. The function test is performed in this manner.

FIG. 3 is a block diagram showing a schematic configuration of the pattern generating means 54 of FIG. Pattern generating means 54
Is composed of a sequence control memory (SQM) 31, a pattern memory address generator 32, and a pattern memory 9. The sequence control memory 31
Only sequence instructions related to sequence control, such as an instruction (JMP) for instructing a jump to a specified address, an instruction (RPT) for instructing a repetition of a specified number of times, and an instruction (STOP) for instructing a stop, are stored. This sequence instruction is composed of an operation code and an operand. For example, a jump instruction that jumps the pattern memory address to "b" when the pattern memory address becomes "a" is represented as "JMP b, a, sb". Here, the operand "a" indicates the execution address of the jump instruction, "b" indicates the jump destination address of the jump instruction, and "sb" indicates the jump sequence memory address in the sequence control memory 31. The pattern memory address generator 32 generates a pattern memory address according to a sequence command from the sequence control memory 31 in accordance with an operation clock CLK from the timing generator 53. That is,
The pattern memory address generator 32 has a built-in program counter for counting the operation clock, and increments or decrements the built-in program counter until the execution address in the sequence instruction is reached, and when the value of the built-in program counter reaches the execution address. To execute the instruction. For example, when the sequence instruction is “JMP b, a, sb” as described above, the pattern memory address generator 32 sets the jump instruction when the value of the built-in program counter reaches the execution address “a”. Execute As a result, at the next timing, the pattern memory address becomes the jump address “b”, and a new sequence instruction is read from the sequence control memory 31 at a position corresponding to the jump address “sb”. The pattern memory 9 stores the pattern data PD stored at a position corresponding to the pattern memory address from the pattern memory address generator 32.
Is output.

[0013]

As described above, the pattern memory address generator 3 of the conventional pattern generating means 54 is used.
2 is the operation clock CL from the timing generation means 53
Since the operation is performed according to K, the higher the operation clock CLK is, the higher the operation speed of the pattern generation unit 54 can be. However, the conventional pattern generating means 54 accesses the sequence control memory 31 according to the pattern memory address output from the pattern memory address generator 32, and controls the counting operation of the built-in program counter again according to the accessed sequence command. Due to the adoption of the feedback method, the operation speed of the pattern generating means 54 is limited by the access speed of the sequence control memory 31, and it is difficult to achieve a speed higher than the access speed of the sequence control memory 31. Had the problem that

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a pattern generating apparatus capable of generating pattern data at high speed at a speed higher than the operating speed of the pattern generating means, that is, the access speed of the sequence control memory. The purpose is to provide.

[0015]

A pattern generator of an IC test apparatus according to the present invention stores a plurality of sequence instructions, and in response to an input of a sequence memory address, stores the sequence instruction stored in the sequence memory address. A sequence control memory to be output, and the sequence command output from the sequence control memory, and a first operation clock until a count value reaches a sequence memory address at which the sequence command is to be executed. And outputs the count value of the first internal counter to the sequence control memory as the sequence memory address. The count value of the first internal counter reaches the sequence memory address at which the sequence instruction is to be executed. At the time A sequence memory address generating means for executing a sequence instruction to control the count value of the first internal counter; and a sequence instruction sequentially output from the sequence control memory in synchronization with the first operation clock. Instruction holding means for storing a plurality of sequence instructions in parallel and outputting the stored sequence instructions in parallel, and selection for selectively outputting the sequence instructions output in parallel from the instruction holding means in the order of storage Means for inputting the sequence command through the selecting means, and until the count value reaches a pattern memory address at which the sequence command is to be executed, a second operation clock faster than the first operation clock is used. 2, and outputs the count value as a pattern memory address. A pattern for controlling the count value of the second built-in counter by executing the sequence command when the count value of the built-in counter reaches the pattern memory address at which the sequence command being input is to be executed via the selection means. Memory address generating means; and selection instructing means for instructing the selecting means to select a next sequence instruction when the count value of the second program counter reaches a pattern memory address at which the sequence instruction is to be executed. It is provided with.

The sequence control memory inputs the count value output from the first built-in counter in the sequence memory address generating means as a sequence memory address, and outputs a sequence command corresponding to the address. The sequence memory address generating means controls the count operation of the first built-in counter according to a sequence command output from the sequence control memory. The instruction holding means sequentially stores the sequence instructions sequentially output from the sequence control memory at a timing synchronized with the low-speed operation clock (first operation clock) in the output order, and stores the stored sequence instructions in parallel. Output. The selection means selectively outputs the sequence instructions output in parallel from the instruction holding means in the order of storage. Therefore, the sequence instruction stored first in the instruction holding means is first selected by the selection means and output to the pattern memory address generation means. The pattern memory address generating means controls the counting operation of the second built-in counter in accordance with the sequence command selected by the selecting means, and supplies the count value to the pattern memory as a pattern memory address. The second internal counter is a high-speed operation clock (second operation clock)
Count. When the count value from the second built-in counter in the pattern memory address generating means (that is, the pattern memory address) matches the pattern memory address at which the sequence instruction is to be executed, the selection instructing means sends the next sequence instruction to the selecting means. Instruct the user to select That is, the selecting means outputs the sequence command stored in the command holding means storing the next sequence command to the pattern memory generating means in accordance with the instruction from the selection instructing means. As a result, the sequence memory address is fed back to the sequence control memory as in the related art, and it is not necessary to access the memory with the fed back address. Instructions can be easily accessed, and pattern data can be generated at a speed higher than the access speed limit of the sequence control memory.

[0017]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a pattern generator of an IC test apparatus according to the present invention. Sequence control memory (SQM) 1
Is a command (JM
P) or an instruction (RP
T) and instructions related to sequence control such as an instruction to stop (STOP) (hereinafter referred to as “sequence instruction”)
And outputs a sequence command corresponding to the read address from the sequence memory address generator 2 to the sequence memory address generator 2 and the multiplexer 3. This sequence instruction is composed of an operation code and an operand. For example, in the case of a jump instruction in which the pattern memory address jumps to "b" when the pattern memory address becomes "a", "J
MP b, a, sb, sa ". Here, the operand “a” indicates the execution pattern memory address of the jump instruction, and “b” indicates the jump pattern memory address of the jump instruction. “S a ” indicates the execution sequence memory address of the jump instruction in the sequence control memory 1, and “s b ” indicates the jump sequence memory address of the jump instruction in the sequence control memory 1. That is, in this embodiment, an operand indicating the execution sequence memory address in the sequence control memory 1 is additionally stored in the sequence instruction.

The sequence memory address generator 2 generates a read address (sequence memory address) of the sequence control memory 1 in accordance with a sequence command from the sequence control memory 1 in synchronization with the low-speed operation clock CLKL from the timing generating means 53. This is fed back to the sequence control memory 1. That is, the sequence memory address generator 2 has a built-in program counter for counting the low-speed operation clock CLKL, and increments or decrements the program counter until the value of the built-in program counter reaches the execution sequence memory address in the sequence instruction. When the value of the built-in program counter reaches the execution sequence memory address, the sequence instruction is executed. For example, when the sequence instruction is “JMP b, a, sb, sa” as described above, the sequence memory address generator 2 sets the jump instruction when the value of the built-in program counter reaches “sa”. Execute As a result, at the next timing, the sequence memory address becomes the jump destination address “s
b ”, a new sequence command is read from the jump destination address“ sb ”of the sequence control memory 1 and output to the sequence memory address generator 2 and the multiplexer 3.

The write counter 6 is a cyclic 3-bit counter that counts the low-speed operation clock CLKL from the timing generator 53, and outputs the count value to the selection control terminal S of the multiplexer 3. The flip-flop circuits 41 to 48 are for temporarily storing sequence commands from the sequence control memory 1, and are capable of storing eight sequence commands. The multiplexer 3 has a selection control terminal S
The flip-flop circuits 41 to 48 are sequentially selected in accordance with the 3-bit count value from the write counter 6 being input to the circuit. Therefore, any one of the flip-flop circuits 41 to 48 selected by the multiplexer 3
Finally, a sequence command from the sequence control memory 1 is written. The read counter 7 is a cyclic 3-bit counter that counts the coincidence signal from the comparison determination circuit 10, and outputs the count value to the selection control terminal S of the multiplexer 5. The comparison / decision circuit 10 includes a pattern memory address output from the pattern memory address generator 8 and an execution pattern memory address in a sequence instruction output from any one of the flip-flop circuits 41 to 48 selected by the multiplexer 5. And outputs a match signal to the reading counter 7 when the two match. Multiplexer 5
Selects one of the flip-flop circuits 41 to 48 in order according to the 3-bit count value from the read counter 7 being input to the selection control terminal S, and executes the sequence instruction stored therein. Output to the pattern memory address generator 8. The low-speed operation clock CLKL supplied to the sequence memory address generator 2 and the write counter 6 is masked when the count value of the write counter 6 becomes smaller than the count value of the read counter 7 by one. The data is not supplied to the sequence memory address generator 2 and the write counter 6. That is, when the sequence command from the sequence control memory 1 is stored in all the flip-flop circuits 41 to 48, at that time,
The operations of the sequence memory address generator 2 and the write counter 6 are stopped. As mentioned above,
Multiplexer 3, flip-flop circuits 41-48,
The multiplexer 5, the write counter 6, and the read counter 7 sequentially store eight sequence instructions output from the sequence control memory 1, and output the sequence instructions to the pattern memory address generator 8 in the order in which they are stored. (First-In First
-Out) It operates as a circuit.

The pattern memory address generator 8 generates a pattern memory address of the pattern memory 9 in synchronization with the high-speed operation clock CLKH from the timing generator 53 in accordance with a sequence command from the multiplexer 5. That is, the pattern memory address generator 8 has a built-in program counter for counting the high-speed operation clock CLKH, and increments or decrements the built-in program counter until the execution pattern memory address in the sequence instruction is reached. When the execution pattern memory address is reached, the sequence instruction is executed. For example, if the sequence instruction is “JMP b,
In the case of "a, sb, sa", the pattern memory address generator 8 executes the jump instruction when the value of the built-in program counter reaches the execution pattern memory address "a", and executes the pattern memory at the next timing. The address is set to the jump address “b”. Note that the operand related to the sequence memory address in the sequence instruction is ignored in the processing of the pattern memory address generator 8. The pattern memory 9 outputs the pattern data PD stored at a position corresponding to the pattern memory address sequentially output from the pattern memory address generator 8 in synchronization with the high-speed operation clock CLKH. Thus, the pattern memory address generator 8 can sequentially output the pattern data at the speed of the high-speed operation clock CLKH.

In the above embodiment, the case where the number of flip-flop circuits is eight has been described. However, this is merely an example, and it is needless to say that two, four, sixteen, or the like may be used. Absent. In this case, the write counter and the read counter may be a 1-bit counter, a 2-bit counter, and a 4-bit counter.

[0022]

According to the pattern generator of the IC test apparatus of the present invention, there is an effect that pattern data can be generated at a speed higher than the access speed limit of the sequence control memory.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a pattern generator of an IC test apparatus according to the present invention.

FIG. 2 is a block diagram illustrating an overall configuration of an IC test apparatus.

FIG. 3 is a diagram showing a schematic configuration of a conventional pattern generator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sequence control memory, 2 ... Sequence memory address generator, 3, 5 ... Multiplexer, 41-
48 flip-flop circuit, 6 write counter, 7 read counter, 8 pattern memory address generator, 9 pattern memory

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/3183

Claims (3)

(57) [Claims] 1. A sequence control memory for storing a plurality of sequence instructions and outputting a sequence instruction stored in the sequence memory address in response to an input of a sequence memory address, and the sequence output from the sequence control memory A first operation clock is counted by a first internal counter until a count value reaches a sequence memory address at which the sequence instruction is to be executed, and the count value of the first internal counter is stored in the sequence memory. The sequence command is output to the sequence control memory as an address, and when the count value of the first built-in counter reaches a sequence memory address at which the sequence command is to be executed, the sequence command is executed to count the first built-in counter. The value A sequence memory address generating means for controlling, and a plurality of sequence instructions sequentially output from the sequence control memory in synchronization with the first operation clock are stored in the output order, and the stored sequence instructions are stored in parallel. An instruction holding unit for outputting, a selection unit for selectively outputting the sequence instructions output in parallel from the instruction holding unit in a stored order, and inputting the sequence instruction via the selection unit; Until the count value reaches a pattern memory address where the sequence instruction is to be executed, a second operation clock faster than the first operation clock is counted by a second internal counter, and the count value is used as a pattern memory address. And outputs the count value of the second internal counter via the selection means. A pattern memory address generating means for controlling the count value of the second internal counter by executing the sequence instruction when the pattern memory address at which the sequence instruction is to be executed is reached; A selection instruction means for instructing said selection means to select a next sequence instruction when a pattern memory address at which said sequence instruction is to be executed is reached.
Pattern generator for test equipment. 2. A sequence control memory for storing a plurality of sequence instructions and outputting a sequence instruction stored in the sequence memory address in response to an input of a sequence memory address, the sequence output from the sequence control memory A first operation clock is counted by a first internal counter until a count value reaches a sequence memory address at which the sequence instruction is to be executed, and the count value of the first internal counter is stored in the sequence memory. The sequence command is output to the sequence control memory as an address, and when the count value of the first built-in counter reaches a sequence memory address at which the sequence command is to be executed, the sequence command is executed to count the first built-in counter. The value Sequence memory address generating means for controlling, a first counting means for counting the first operation clock and outputting the count value, a plurality of instruction holding means for separately holding and outputting the sequence instruction, First selecting means for sequentially selecting the instruction holding means based on the count value from the first counting means and storing the sequence instruction from the sequence control memory in the selected instruction holding means; And outputs the count value.
Counting means, and sequentially selecting the instruction holding means based on the count value from the second counting means, and outputting the sequence instruction held in the selected instruction holding means.
The sequence command is input via the second selection device, and the second command is faster than the first operation clock until the count value reaches a pattern memory address at which the sequence command is to be executed. Operation clock is counted by a second internal counter, the count value is output as a pattern memory address, and the count value of the second internal counter executes the sequence instruction being input via the second selecting means. A pattern memory address generating means for controlling the count value of the second internal counter by executing the sequence instruction when the pattern memory address to be reached is reached; and transmitting the count value of the second internal counter and the sequence instruction. Compare with the pattern memory address to be executed,
A pattern determination device for an IC test device, comprising: comparison determination means for outputting the match signal to the second counting means when both match. 3. The method according to claim 1, wherein the supply of the first operation clock to the sequence memory address generating means is stopped when the instruction holding means holds a number of sequence instructions that can be held. The pattern generator of the IC test apparatus according to claim 1 or 2, wherein