JP3203031B2 - Video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera having a solid-state image pickup device (CCD), and more particularly to a video camera capable of generating a so-called strobe image by electrical processing.

[0002]

2. Description of the Related Art In recent years, stationary video tape recorders have been developed.
In the (VTR), various special reproduction modes can be realized. One of them is a strobe afterimage generation mode as shown in FIG. In the example of FIG. 8, the motion of the pendulum is generated as a strobe image, and a plurality of afterimages from the past to the present are discretely displayed at a time interval in one screen.

On the other hand, in a video camera, particularly a camera-integrated VTR in which a VTR is integrated, there is a strong demand for downsizing of the device, and simplification of the circuit configuration has priority over diversification of functions. Also, in a video camera, there is a request to create a video signal of a predetermined format after removing noise included in an image pickup signal. For this purpose, for example, a cyclic digital noise reduction circuit using a field memory is provided. (See Nikkan Kogyo Shimbun, "Digital Signal Processing of Images", pp. 115-118).

Therefore, in a video camera, a large-scale memory and a control circuit for generating a strobe afterimage are required in addition to the field memory for noise reduction in order to realize a strobe afterimage generation mode. The camera had not been put to practical use.

It is an object of the present invention to provide a video camera capable of realizing various modes such as a strobe image generation mode with a simple circuit configuration.

[0006]

Accordingly, in the present invention, the cyclic digital noise reduction circuit is used for generating a strobe image, and the circuit configuration is simplified.

[0007] Video camera according to the present invention, as shown in FIG. 1, the output of the solid-state imaging device into a digital image signal, a video camera to create a video signal of a predetermined format based on the image pickup signal, the solid-state imaging Timing circuit (15) for issuing a charge read control signal to element (1)
A for converting the output of the solid-state imaging device into a digital imaging signal
A / D converter (3), a signal obtained by multiplying a digital imaging signal output from the A / D converter (3) by a first coefficient K of 1 or less,
A cyclic digital noise reduction circuit () for adding a signal obtained by multiplying the digital imaging signal read from the field memory (10) by a second coefficient (1-K) and storing the addition result in the field memory (10) 9), a coefficient generating circuit (8) for generating the first and second coefficients and supplying the coefficient to the noise reduction circuit (9), and writing and reading to and from the field memory (10) of the noise reduction circuit (9). A field memory control circuit (11) for controlling, a camera signal processing circuit for creating and outputting a video signal of a predetermined format based on an output signal of the noise reduction circuit (9),
Before Symbol timing circuit (15), and a system control means for variably setting the operation of the coefficient generation circuit (8) and the field memory control circuit (11), said field memory control circuit (11)
Is the first field period every two or more predetermined fields
Between the first coefficient K and a predetermined decimal value k (0 <k <
Set to 1) and write to the field memory (10)
Reading and reading, and during the remaining field period
To set the first coefficient K to 0,
The reading for the memory (10) is performed.

[0008]

In this embodiment, the mode selection signal includes a signal for selecting a normal mode, a noise reduction mode, and a strobe afterimage generation mode .

In the noise reduction mode (FIG. 4), the first coefficient K is set to an arbitrary fractional value k (0 <k <1) by the coefficient generation circuit 8 only in one of the odd field and even field fields. In the other field period, the first coefficient K is switched to 0 and set. In the one field period, signal reading and writing to the field memory (10) are performed simultaneously, and in the other field period, signal writing to the field memory (10) is not performed. , Only signal reading is performed.
As a result, the cyclic digital noise reduction circuit (9)
As a result, a noise reduction process based on only the digital imaging signal in the one field period is performed, and an output signal of the circuit is sent to a camera signal processing circuit.

In the strobe image persistence image generation mode (FIG. 6), the cycle T of a plurality of field periods is
And the first coefficient K for the first field period in the cycle T
Is an arbitrary decimal value k (0 <k <1), and the first coefficient K is switched to 0 during the remaining field period in the cycle.
In the first field period, a field memory is used.
Signal reading and writing are performed simultaneously for (10),
In the remaining field period, a field memory (10)
No signal is written to, but only a signal is read. As a result, the output signal of the cyclic digital noise reduction circuit (9) changes in the cycle T of the plurality of field periods, and the output signal of each cycle T includes the second coefficient (1- K) will be included, and a strobe afterimage will be generated.

[0011]

According to the video camera of the present invention, since the recursive digital noise reduction circuit is used not only for the original noise reduction function but also for generating a strobe image or the like , the circuit configuration is complicated. Instead, a special mode such as a strobe afterimage generation mode is realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, the video camera is provided with a CCD (1) provided with a well-known color filter (not shown) as an imaging device, and the output of the CCD (1) is supplied to a noise removal circuit (2). After noise removal processing by correlated double sampling is performed, the signal is converted into a digital signal via an A / D converter (3).

The output signal (CCD output signal) of the A / D converter (3) is a digital noise reduction circuit (9) which is a cyclic filter in the time axis direction, and a vertical interpolation processing circuit (a camera signal processing circuit). 12) and camera process circuit (1
3), the video signal (R
It is output as a GB signal or a luminance signal and a color difference signal.

The cyclic digital noise reduction circuit (9) is supplied with a pair of a first coefficient K and a second coefficient (1-K) from a coefficient generation circuit (8).

The writing and reading of the field memory 10 constituting the digital noise reduction circuit 9 are controlled by a field memory control circuit 11.
The CCD (1) is driven by a charge reading control signal from the timing circuit (15).

[0016] The microcomputer (14) that Nikki by Tsukasa system control of the entire video camera, together with the mode selection signal is supplied from outside, is supplied field identification signal from the timing circuit (15), in response thereto, micro The computer (14) sends a coefficient selection signal to the coefficient generation circuit (8) and sends an exposure time control signal to the timing circuit (15). Further, a write mode setting signal is sent to the field memory control circuit (11), and an interpolation coefficient is sent to the vertical interpolation processing circuit (12). Further, an electronic shutter signal is sent to the CCD (1) as needed.

The digital noise reduction circuit (9)
A first multiplier multiplies the CCD output signal from the A / D converter (3) by a first multiplier.
(5), a read signal from the field memory (10) is connected to a second multiplier (6), and further, both multipliers (5)
The output of (6) is connected to the adder (7), and the weighted average circuit (4)
Is composed. The first multiplier (5) includes a coefficient generation circuit
The first coefficient K is supplied from (8), and the second multiplier (6)
The second coefficient (1-K) is supplied from the coefficient generation circuit (8),
By adding the two multiplication results in the adder (7), C
A weighted average of the CD output signal and the field memory output signal by the coefficients K and (1-K) is calculated.

The weighted averaged signal is processed by a vertical interpolation processing circuit.
At the same time as being output to (12), it is written to the field memory (10), and the signal in the field memory (10) is read in the next field. As a result, the CCD output signal of an arbitrary field is first multiplied by K and output to the vertical interpolation processing circuit (12), and after the next field, every time the signal circulates through the loop including the field memory (10). To (1-K)
It is multiplied and output to the vertical interpolation processing circuit (12).

In the current standard television system, interlaced scanning is performed, and the signal output from the CCD is also an interlaced signal.
In the (en) field and the odd (odd) field, signals on the same line cannot be obtained. Therefore, if the weighted averaging process is performed between an odd field and an even field in a cycle of one field, the image may be blurred.

Therefore, in the present embodiment, in a special mode such as a digital noise reduction mode or a strobe image persistence image generation mode, an arbitrary coefficient K is given in an odd (or even) field, and a coefficient K is given in an even (or odd) field. When the value is set to 0, the weighted average processing is always performed on the odd (or even) field. In this case, the signal of the even (or odd) field is artificially generated from the signal of the odd (or even) field by interpolation.

FIG. 7 shows the principle of generating new odd field signals and even field signals by interpolating the odd field signals output from the CCD. At this time, it is possible to adopt a method in which the original odd field is used as it is as an odd field and only the even field is newly generated from the original odd field, but in this case, the vertical resolution of the even field is extremely reduced. I do.

Therefore, in this embodiment, the output of the weighted averaging circuit (4) in FIG. 1 is set to 0.2 in the odd field in order to obtain a good frame image by adjusting the resolution level in the odd field and the even field. In the case of an even field, an interpolation coefficient of 0.75 is given to the vertical interpolation processing circuit 12 in the case of an even field (see FIGS. 3 to 6). Produces two signals. For this purpose, the microcomputer (14) of FIG. 1 takes in the field identification signal from the timing circuit (15), identifies the even / odd number of the field, and converts the interpolation coefficient according to the field into a vertical interpolation processing circuit (12). ).

According to the apparatus shown in FIG. 1, a normal mode which is a normal use mode, a long exposure mode for controlling the charge accumulation time of the CCD, and two digital noise reduction modes for performing weighted averaging in the time direction are provided. A total of five modes, ie, a strobe afterimage generation mode, can be set, and a mode selection signal created based on a user's selection operation is sent to the microcomputer (14), thereby performing mode selection. Hereinafter, the circuit operation in each mode will be described.

Normal Mode In the normal mode, as shown in FIG. 2, a charge readout pulse is sent to the CCD every field, and the CCD output is taken out. Also, by fixing the coefficient K of the weighted average circuit to 1, the CCD output signal is sent to the vertical interpolation processing circuit as it is. At this time, writing and reading of data to and from the field memory are not performed. The interpolation coefficient sent to the vertical interpolation circuit is set to 0, and no vertical interpolation processing is performed.

As a result, the fields O1, E1, O2, E2, O3, E3,... Output from the CCD are output from the weighted averaging circuit as they are.

Long time exposure mode In the long time exposure mode, by setting the charge read cycle T to 6 fields as shown in FIG. 3, signals accumulated for a 6 field period are taken out from the CCD at a cycle of 6 fields. During a field period for extracting an output signal from the CCD, the coefficient K of the weighted averaging circuit is set to 1, and as a result, the CCD output signal is directly written into the field memory and sent to the vertical interpolation circuit at the same time. During the period of 5 fields during which no output signal is taken out from the CCD, the signal read out from the field memory is sent to the vertical interpolation circuit as it is by only reading out the signal from the field memory and setting the coefficient K of the weighted average circuit to 0. .

Thus, for example, the field number O3
During the period from E5 to E5, the CCD output signal accumulated during the previous period from the field number E0 to E2 is added to the CCD output signal at the field number O3, and the addition result is output to the vertical interpolation circuit.

As a result, an image in which six fields overlap is generated while being updated every six field periods.

First noise reduction mode In this mode, as shown in FIG. 4, an output signal is taken out of the CCD every field, an arbitrary decimal value k is given to the coefficient K of the weighted averaging circuit at an odd field, and the CCD output signal and the field memory The weighted average value of the output signal is sent to the vertical interpolation circuit, and at the same time, the weighted average value is written to the field memory.
In the case of an even field, only reading from the field memory is performed, and by setting the coefficient of the weighted averaging circuit to 0, the read signal from the field memory is sent to the vertical interpolation circuit as it is.

As a result, the signal sent to the vertical interpolation circuit in each odd field is continuously output to the subsequent even fields, and a noise reduction effect by weighted averaging is obtained. In particular, the noise reduction effect for still images is large.

Second noise reduction mode In the first noise reduction mode, each field,
Although the CCD output signal is taken out, in the second noise reduction mode, as shown in FIG. 5, charge readout is performed every other field, and the signal accumulated for two field periods is taken out from the CCD at a cycle of two fields. is there.

In this mode, since the S / N ratio is improved by accumulating charges for two field periods in the CCD, a greater noise reduction effect can be obtained in synergy with the noise reduction effect of the weighted average circuit. .

In the strobe afterimage generation mode, in the strobe afterimage generation mode, the CCD output signal is extracted every field as shown in FIG. 6, while the coefficient K of the weighted averaging circuit is changed in the first field every six field periods T.
The coefficient K is set to an arbitrary decimal value k, and the coefficient K is set to 0 for the remaining five field periods. In the first field period, writing and reading to and from the field memory are performed, and in the remaining five fields, only reading of signals from the field memory is performed.

Thus, for example, the field number O4
In the period from to E6, a signal obtained by multiplying the weighted average circuit output A of the previous six field periods by (1-K) and a signal obtained by multiplying the CCD output signal of the field number O4 by K are added, and the addition result B Is output to the vertical interpolation circuit. Further, during the next field number O7 to E9, the previous 6
A signal obtained by multiplying the weighted average circuit output B in the field period by (1−K) and a signal obtained by multiplying the CCD output signal of the field number O7 by K are added, and the addition result C is output to the vertical interpolation circuit.

As a result, on each screen generated while being updated every six field periods T, as shown in FIG. 8, a plurality of previously generated images are discretely displayed as afterimages.
These plural afterimages become thinner as going back in the past.

In this embodiment, as shown in FIG. 1, an electronic shutter signal is transmitted from the microcomputer (14) to the CCD (1) at a field cycle (FIG. 8) to enhance the strobe effect for each afterimage. ing.

According to the video camera of the present invention, as described above, by controlling the field memory constituting the digital noise reduction circuit and variably setting the coefficient K of the weighted averaging circuit, a plurality of mode settings including a strobe afterimage generation mode are performed. Is possible.

The description of the above embodiments is for the purpose of illustrating the present invention and should not be construed as limiting the invention described in the appended claims or reducing the scope thereof. Further, the configuration of each part of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made within the technical scope described in the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video camera according to the present invention.

FIG. 2 is a timing chart illustrating an operation in a normal mode.

FIG. 3 is a timing chart illustrating an operation in a long exposure mode.

FIG. 4 is a timing chart illustrating an operation in a first noise reduction mode.

FIG. 5 is a timing chart illustrating an operation in a second noise reduction mode.

FIG. 6 is a timing chart illustrating an operation in a strobe afterimage generation mode.

FIG. 7 is a diagram illustrating the principle of vertical interpolation.

FIG. 8 is a diagram illustrating an example of a strobe afterimage.

[Explanation of symbols]

 (1) CCD (3) A / D converter (4) Weighted average circuit (8) Coefficient generation circuit (9) Digital noise reduction circuit (10) Field memory (11) Field memory control circuit (14) Microcomputer

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masao Takuma 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Toru Yamamoto 2-18-3 Keihanhondori, Moriguchi-shi, Osaka (72) Inventor Seiji Kawakami 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Tohru 2--18-18 Keihanhondori, Moriguchi-shi, Osaka JP-A-2-228884 (JP, A) JP-A-2-162970 (JP, A) JP-A-1-290380 (JP, A) JP-A-58-200676 (JP) , A) JP-A-5-91396 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/22-5/257

Claims (1)

(57) [Claims] 1. A video camera for converting an output of a solid-state imaging device into a digital imaging signal and generating a video signal of a predetermined format based on the imaging signal, wherein a charge reading control signal is transmitted to the solid-state imaging device (1). A timing circuit (15), an A / D converter (3) for converting the output of the solid-state imaging device into a digital imaging signal, and an A / D converter
A signal obtained by multiplying the digital imaging signal output from (3) by a first coefficient K of 1 or less, and a signal obtained by multiplying the digital imaging signal read from the field memory (10) by a second coefficient (1-K) And a cyclic digital noise reduction circuit (9) for storing the addition result in a field memory (10).
A coefficient generation circuit (8) for generating and supplying the first and second coefficients to a noise reduction circuit (9), and a field memory for controlling writing and reading of a field memory (10) of the noise reduction circuit (9) Control circuit (11)
If, based on said output signal of the noise reduction circuit (9), a camera signal processing circuit configured to create a video signal of a predetermined format, before Symbol timing circuit (15), the coefficient generation circuit (8) and the field memory control System control means for variably setting the operation of the circuit (11) , wherein the system control means is provided for every two or more predetermined fields.
In the first field period, the first coefficient K is determined.
Set a fixed decimal value k (0 <k <1)
Write to and read from the memory (10), and
The first coefficient K is set to 0 in the other field period
A video camera for reading data from the field memory (10) .