JP3200485B2 - Communication method and communication device using ISDN - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method and a communication apparatus using ISDN (Integrated Services Digital Communication Network).

[0002]

2. Description of the Related Art The prior art is disclosed in Japanese Patent Laid-Open No. 2-7752.
This is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-95 "Compound terminal device for ISDN".
A conventional technique will be described with reference to FIG.

[0003] The ISDN 101 is an ISDN composite terminal 10.
2 is an exchange network for exchanging information between the ISDN 2 and the ISDN composite terminal 103. In the ISDN composite terminal 103, the layer 1 interface 131 matches electrical and physical conditions for connecting the terminal to the switching network. That is, connection conditions in the seven physical layers of the open system interconnection (OSI) are prepared. The Bch synchronization data generator 137 generates B channel synchronization data to be transmitted to synchronize the data strings of the B1 channel and the B2 channel. The Bch transmission unit 133 transmits the B channel data and the B channel synchronization data obtained from the Bch synchronization data generation unit to the other communication terminal via the layer 1 interface 131. Bch data receiving unit 134
Receives the B channel data transmitted from the composite terminal 102 via the layer 1 interface 131.
The synchronization algorithm storage unit 138 stores a synchronization algorithm for correcting the data strings so as to synchronize the data strings of the B1 and B2 channels.

Next, the operation of the above conventional configuration will be described. First, a transmission data sequence is transmitted from the Bch data transmission unit (not shown) of the ISDN composite terminal 102 via the ISDN 101. The ISDN composite terminal 103 checks the order of the data string received via the layer 1 interface 131, and corrects the data string for synchronizing the data strings of the next B1 channel and B2 channel. Specifically, the correction data is obtained by delaying each data of the B2 channel received by the Bch data synchronization unit 135 by n data. In order to perform this data string correction, a synchronization algorithm is stored in the synchronization algorithm storage unit 138, and the Bch data synchronization unit 135 is stored.
Then, using the synchronization algorithm, the data strings of the subsequent B1 channel and B2 channel are synchronized.

[0005]

However, in the above-mentioned conventional example, only the case where one line is used is disclosed. Two B channels having a transmission speed of 64 kbps and a D channel having a transmission speed of 16 kbps are disclosed. In the case of the ISDN composite terminal having the basic interface of No. 1, communication exceeding 128 kbps could not be performed even if two B channels were used simultaneously. Therefore, when transmitting an enormous amount of image data such as high-resolution image data using the basic interface, there is a problem that the time required for the transmission becomes extremely long.

An object of the present invention is to provide a communication device and a communication method for performing data communication using more than two B channels using a plurality of lines.

[0007]

SUMMARY OF THE INVENTION A communication apparatus using an ISDN according to the present invention is an ISDN communication apparatus having a plurality of communication channels.
By connecting multiple wires, transmission and reception of data carrying
These are divided into multiple communication channels of multiple ISDN lines.
A communication device using ISDN , wherein
Provided corresponding to the ISDN line,
Line interface means for interfacing
And calls on a plurality of communication channels of the plurality of ISDN lines.
When the connection is completed, synchronization establishment data is sent.
Data transmitting means and receiving from the synchronization establishment data transmitting means.
The received synchronization establishment data is divided and
The data to be transmitted is sequentially transmitted to each of the line interface means.
Data dividing means, and a plurality of each of the plurality of ISDN lines.
The synchronization establishment data provided corresponding to the communication channel;
Receive the synchronization establishment data reception signal
Synchronization establishment data receiving means, and the plurality of line interfaces
And provided from the ISDN line.
A plurality of data storage means for storing received data;
A plurality of data storage means and a plurality of the synchronization establishment data reception means;
Communication establishment means for receiving the synchronization establishment data.
When a signal is detected, the corresponding data storage means is
Request to start data storage, and
Multiple data storage inputs / outputs controlling the data output from the means
Force control means and all of the plurality of synchronization establishment data receiving means.
Recognizes that the synchronization establishment data reception signal has been output.
Is stored in the plurality of data storage units.
The plurality of data storage inputs / outputs to output data.
Control means for controlling the control means, and the plurality of data storages
Input the data output from the
A switch to switch and output these data in accordance with the imaging signal
Replacement output means, depending on the speed of the data carrying the predetermined information.
Signal stored in the plurality of data storage means.
Output from the switching output means in a predetermined order.
The switching timing signal to be supplied to the switching output means.
And a time slot generating means for supplying the time slot .

[0008] Further, the communication method using ISDN of the present invention provides a method for connecting a plurality of ISDN lines having a plurality of communication channels.
The transmission and reception of data carrying the predetermined information
A communication method using the ISDN performed using a plurality of communication channels of the ISDN line simultaneously, on the transmitting side, the
For each of a plurality of ISDN lines,
Interface with a plurality of ISDN lines
Synchronization is established when the call connection is completed on multiple communication channels
Transmitting data to each communication channel of the plurality of ISDN lines;
And then divide the data carrying the predetermined information
The communication channel of each of the plurality of ISDN lines is
To the receiving side, and on the receiving side, the plurality of I
In correspondence with each of the SDN lines,
Each of the plurality of ISDN lines.
A plurality of communication channels receive the synchronization establishment data
And send a synchronization establishment data reception signal respectively.
The received data carrying the divided predetermined information is
A plurality of communication channels of the plurality of ISDN lines.
The synchronization establishment data reception signals corresponding to all the channels are detected.
Then, depending on the speed of the data carrying the predetermined information,
Before splitting stored for each of multiple communication channels
The data carrying the predetermined information is sequentially switched and output in a predetermined order .

[0009]

The communication device and communication using the ISDN of the present invention
The method is to time-divide a series of data carrying information and transmit it as divided data in a predetermined order for each channel of a plurality of lines, and upon reception, by rearranging the obtained divided data in the predetermined order, Since the transmission rate of the series of data can be set to be a multiple of the total number of channels of the transmission rate specific to each channel, the transmission time can be greatly reduced even when transmitting a large amount of image data such as image data. Can be shortened.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a system that uses the B1 channel and the B2 channel simultaneously as a transmission / reception transmission line of the ISDN basic interface, and divides image information into a plurality of divided data at a communication speed of 128 kbps and transfers the divided data. FIG. In FIG. 1, reference numeral 201 denotes one ISDN terminal device (hereinafter, simply referred to as a terminal);
202 is the other terminal. In the terminal 201, 1 is a video camera for supplying image information, 12 is a video monitor for displaying image information from the terminal 202, 2 is a terminal for encoding image information obtained from the video camera 1 and 2
The image codec device 3 for decoding the image information from 02 is transmitted and activated by the image codec device,
A division transmitting unit for dividing the image information and transmitting the divided data to the partner terminal; and a division receiving unit for receiving the divided data transmitted from the partner terminal, via the output signal line 4 and the input signal line 11. And a terminal adapter for connecting the B1 channel and the B2 channel to the other party via the ISDN. An ISDN 13 connects the terminals 201 and 202. In the terminal 202, 6 includes an input signal line 5 and an output signal line 10, and includes a division transmission unit and a division reception unit.
A terminal adapter 7 for connecting to the other party via the SDN 13; an image codec device 7 for decoding image information transmitted from the terminal 201 via the ISDN 13 and encoding the image information to be transmitted to the terminal 201; A video camera 8 for supplying information and a video monitor 8 for displaying image information from the terminal 201 are shown.

Next, the communication operation of the configuration shown in FIG. 1 will be described with, for example, the terminal 201 as the transmitting side and the terminal 202 as the receiving side.

FIG. 2 shows a synchronization sequence as a call connection procedure after a call is set up. The synchronization sequence includes two sequences, a synchronization establishment sequence and a synchronization confirmation sequence. First, the synchronization establishment sequence process and the synchronization confirmation sequence process executed by the terminal adapter 3 on the transmitting side will be described with reference to the flowcharts shown in FIGS.

In the outgoing-side synchronization establishment sequence processing shown in FIGS. 3 and 4, after the outgoing connection is completed, the terminal adapter 3 activates an overall timer for monitoring the completion of the synchronization sequence (step S1), and all data bits are set. The synchronization pattern 1 of "0" is transmitted to the B1 channel (step S2). Thereafter, the reception of the synchronization pattern 1 in the B1 channel is waited (step S3), and if received, the synchronization pattern 1 is transmitted to the B2 channel (step S4). After that, it waits for reception of the synchronization pattern 1 on the B2 channel (step S5), and if received, sends out the synchronization pattern 2 in which all data bits are "1" to the B1 channel and the B2 channel (step S6). Then B
It waits for the reception of the synchronization pattern 2 on the 1 channel and the B2 channel (steps S7 and S8), and if it is received, the synchronization pattern 3 in which all data bits are “0”.
Is transmitted to the B1 channel and the B2 channel (step S9). That is, by transmitting the synchronization pattern 2 in which the data bits are all "1" and between the synchronization patterns 1 and 3 in which the data bits are all "0", the receiving side clearly defines the synchronization patterns 1, 2, and 3. Can be distinguished. After that, the reception of the synchronization pattern 3 on the B1 channel and the B2 channel is waited (step S10). If the synchronization pattern 3 is received, the synchronization establishment sequence process is terminated and the process proceeds to the synchronization confirmation sequence (step S11).

Steps S12 to S1
In 6, when waiting for the reception of the synchronization patterns 1, 2, and 3, an overall timeout occurs, a call disconnection process is performed (step S17).

In the originating-side synchronization confirmation sequence processing shown in FIG. 5, the terminal adapter 3 operates as shown in FIG.
Byte synchronization confirmation data is transmitted (step S18),
A reception waiting timer is started (step S19). Then, it is monitored whether a timeout has occurred (step S20),
If it is not a timeout, it is determined whether or not a synchronization failure notification in which all eight bytes are “55” as shown in FIG. 11 has been received (step S21). If the synchronization failure notification has not been received, it is determined whether or not data that does not match the synchronization confirmation data transmitted in step S18 has been received (step S22). If the unmatched data has not been received, it waits for the received synchronization confirmation data (step S).
23) Steps S20 to S until reception is completed
Perform each of the 23 steps. If received, synchronization confirmation data is sent (step S24). Next, a communication enable signal is sent to the image codec 2 (step S25), and thereafter, the process proceeds to a communication processing routine (step S26).

In step S21, when the synchronization failure notification shown in FIG. 11 is received, or in step S22
For example, when data including an error as shown in FIG. 10 is received, the process returns to the synchronization establishment sequence process (step S27). If a timeout has occurred in step S20, a call disconnection process is performed (step S28).

Next, the synchronization establishment sequence processing and the synchronization confirmation sequence processing executed by the terminal adapter 6 on the receiving side will be described with reference to flowcharts shown in FIGS.

In the receiving-side synchronization establishment sequence processing shown in FIGS. 6 and 7, after the termination connection is completed, the terminal adapter 6 starts an overall timer for monitoring the completion of the synchronization sequence (step S29), and uses the B1 channel or the B2 channel. It waits for reception of synchronization pattern 1 (step S30 or step S31). Step S
In step 30, when the synchronization pattern 1 is received on the B1 channel, the synchronization pattern 1 is transmitted to the B1 channel (step S32), and it is determined whether the synchronization pattern 1 is received on the B2 channel (step S33). In this case, the synchronization pattern 1 is transmitted to the B2 channel (step S34). On the other hand, when the synchronization pattern 1 is received on the B2 channel in step S31, the synchronization pattern 1 is transmitted to the B2 channel (step S35), and it is determined whether the synchronization pattern 1 is received on the B1 channel (step S36). If it has been received, the synchronization pattern 1 is transmitted to the B1 channel (step S37).

Thereafter, it is determined whether or not the synchronization pattern 2 has been received on the B1 channel (step S38). If it has been received, it is determined whether or not the synchronization pattern 2 has been received on the B2 channel (step S39). Sends the synchronization pattern 2 to the B1 channel and the B2 channel (step S40). Thereafter, the partner reception guarantee timer is started (step S41). When it is determined that the reception guarantee timer has timed out (step S42), the synchronization pattern 3 is transmitted to the B1 channel and the B2 channel (step S43). This partner reception guarantee timer is
This is a timer set to the time until the synchronization pattern 2 transmitted from the receiving side is securely received by the transmitting side. afterwards,
It is determined whether or not the synchronization pattern 3 has been received on the B1 channel and the B2 channel (step S44), and the process proceeds to a receiving-side synchronization confirmation sequence process (step S45).

Steps S46 to S5
In step 1, when a timeout of the reception waiting timer occurs, the process proceeds to a call disconnection process (step S5).
2).

In the receiving side synchronization confirmation sequence processing shown in FIG. 8, the terminal adapter 6 activates a reception waiting timer (step S53), determines whether or not a timeout has occurred (step S54).
It is determined whether or not the synchronization confirmation data that does not match the predetermined data pattern as shown in (1) is received (step S55). If the mismatching data is not received, the reception of the matching synchronization confirmation data is waited. (Step S56) Steps S54 to S56 are executed until the data is received. Figure 9 if received
Is transmitted (step S57).
Thereafter, the reception waiting timer is started (step S5).
8), it is determined whether or not a timeout has occurred (step S5)
9) If not a timeout, it is determined whether a synchronization failure notification as shown in FIG. 11 has been received (step S6).
0) If no synchronization failure notification has been received, reception of synchronization confirmation data is waited for (step S61), and steps S59 to S61 are executed until reception. If it has been received, a communicable display signal is sent to the image codec device 7 (step S62), and the process proceeds to a communication processing routine (step S63).

In step S55, when the mismatched synchronization confirmation data is received, a synchronization failure notification is sent (step S64), and the process proceeds to a synchronization establishment sequence process (step S65). Also, in step S60, when the synchronization failure notification is received, the process proceeds to the synchronization establishment sequence process (step S66). Step S
If a timeout has occurred in 54 and step 59, the process proceeds to a call disconnection process (steps S67 and S68).

Next, the operation of the terminal adapter will be described with reference to the block diagram shown in FIG. In FIG. 12, the same reference numerals shown in circles indicate the same signal lines.

First, an outgoing / incoming call connection method will be described. The outgoing call is activated by the image codec device via the signal line 401 to the control circuit 445, and the incoming call is activated by the ISDN interface circuit 403 to the control circuit 445 via the signal line 443.

The control circuit 445 passes through a signal line 443,
Signal line 40 from ISDN interface circuit 403
The transmission / reception connection with the ISDN 13 is performed using the D channel via the 4,422. After the connection is completed, the terminal adapter executes a synchronization establishment sequence process. Control circuit 4
45 is a synchronous pattern sending circuit 402 via a signal line 411
And instruct the logical level of the signal line 442 to be transmitted to the B1 channel and the logical level of the signal line 444 to be transmitted to the B2 channel. On the other hand, the ISDN interface circuit 403 transmits a B1 channel and B2 channel transmission timing signal as shown in FIG. The synchronous pattern sending circuit 402 detects the sending timing signal and changes the logical level of the signal lines 444 and 442 to the signal line 430, the switching circuit 406, and the signal line 40.
7. Send it to the terminal adapter on the other side via ISDN13. That is, in this state, in the switching circuit 406, the signal line 407 is connected to the signal line 430.

When transmitting the synchronization pattern 1 to the B1 channel, the control circuit 445 sets the signal line 444 to the logical level “0” and sets the signal line 442 to the logical level “1”. When transmitting the synchronization pattern 1 to the B2 channel, the signal line 444 is set to the logical level “1” and the signal line 442 is set to the logical level “0”. Subsequently, the synchronization pattern sending circuit 402 sets the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG.
The signal line 430, the switching circuit 406, the signal line 40
7. Send it to the terminal adapter on the other side via ISDN13. When transmitting the synchronization pattern 2 to the B1 channel and the B2 channel, the signal lines 444 and 442 are both set to the logical level “1”. Subsequently, the synchronization pattern sending circuit 402 sends the B1 channel 8 bits shown in FIG.
The data bits of the 8 bits of the B2 channel are all set to “1” and transmitted to the partner terminal adapter on the same route as the synchronization pattern 1. When transmitting the synchronization pattern 3 to the B1 channel and the B2 channel, the synchronization pattern transmission circuit 402 is activated via the signal line 447. The synchronization pattern sending circuit 402 sets all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 to “0” and sends them to the partner terminal adapter on the same route as the synchronization patterns 1 and 2.

After transmitting the synchronization pattern 3, the synchronization pattern transmission circuit 402 switches the switching circuit 406 via the signal line 420.
Is given a switching instruction. The switching circuit 406 switches the connection of the signal line 407 from the signal line 430 to the signal line 434 according to the switching instruction.
Switch to That is, the switching circuit 41 is connected to the signal line 407.
3 will be supplied.

Next, a method of detecting the synchronization patterns 1 and 2 will be described. Synchronization patterns 1 and 2 transmitted from the other terminal adapter are ISDN 13, signal line 4
22, a control circuit 445, a B1 channel synchronization pattern 3 detection circuit 414, and a B2 channel synchronization pattern 3 via the ISDN interface circuit 403 and the signal line 408.
The signal is input to the detection circuit 415. The control circuit 445 detects the synchronization patterns 1 and 2 from the signal line 408 based on the transmission timing signal obtained from the signal line 424. The B1 channel synchronization pattern 3 detection circuit 414 and the B2 channel synchronization pattern 3 detection circuit 415 start receiving by a start signal given from the control circuit 445 via the signal line 447, and when the synchronization pattern 3 is received, the signal line 439 and the The data storage input / output control circuit 416 is notified via 440. When the data accumulation input / output control circuit 416 receives the synchronization pattern 3 detection notification from both the B1 channel synchronization pattern 3 detection circuit 414 and the B2 channel synchronization pattern 3 detection circuit 415, the control circuit 4 via the signal line 410.
Notify 45. Thus, the synchronization establishment sequence processing ends.

After the completion of the synchronization establishment sequence processing, the synchronization confirmation data and the image data in the subsequent communication processing routine are transmitted after being divided into two channel data of the B1 channel and the B2 channel, and are combined into one channel data after reception. Will be done. At the time of transmission from the terminal adapter on the transmitting side, the amount of delay in the ISDN 13 is often different even if the two channel data are in a predetermined order. In that case, a reception delay difference occurs in the terminal adapter on the receiving side, and it becomes impossible to obtain normal combined channel data. Therefore, in the present embodiment, a method of absorbing the reception delay difference between B1 channel data and B2 channel data and establishing data synchronization is used. Hereinafter, this method will be described.

FIG. 14 shows a case where there is no difference in reception delay between B1 channel data and B2 channel data. The data storage input / output control circuit 416 determines from the control circuit 445 via the signal line 405 which B channel of the other party, that is, the transmitting terminal adapter, is connected to this side, that is, the receiving terminal adapter. Be instructed. The transmitting terminal adapter transmits the head of the synchronization confirmation data after transmitting the synchronization pattern 3. The data accumulation input / output control circuit 416 receives the detection signal of the synchronization pattern 3 from the B1 channel synchronization pattern 3 detection circuit 414 via the signal line 439, and in the next cycle, outputs the signal from the B2 channel synchronization pattern 3 detection circuit 415. , A detection signal of the synchronization pattern 3 is given via a signal line 440. Therefore, the data storage input / output control circuit 416
Can detect that there is no difference in reception delay between the B1 channel data and the B2 channel data. In this case, without activating the B-channel data storage circuit 412, a signal of the logical level “0” is transmitted via the signal line 428 from the end of the reception of the synchronization pattern 3 of the two channels.
The data storage input / output control circuit 416 supplies the data to the switching circuit 417. As a result, in the switching circuit 417, the output signal line 427 is connected to the input signal line 408. Therefore, the combined channel data D1, D2, D3,... As shown in FIG.

FIG. 15 shows a case where the B2 channel data is received later than the B1 channel data. In this case, the data storage input / output control circuit 416
A detection signal of the synchronization pattern 3 is given from the one-channel synchronization pattern 3 detection circuit 414, and in the next cycle, B2
No detection signal of the synchronization pattern 3 is given from the channel synchronization pattern 3 detection circuit 415. Therefore, the data storage input / output control circuit 416 can detect that the B2 channel data is behind the B1 channel data. Then, by giving the logical level “1” to the B channel data storage circuit 412 via the signal line 418, the data D1, D3,... After receiving the synchronization pattern 3 of the B1 channel are stored. Thereafter, when a detection signal of the synchronization pattern 3 is provided from the B2 channel synchronization pattern 3 detection circuit 415 via the signal line 440, the logic level “1” is provided to the B channel data storage circuit 412 via the signal line 409. , The accumulated B1
The channel data is sequentially output to the signal line 429. The logic level of the signal line 428 is
When the B1 channel data is output from “2”, it becomes “1”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 429. On the other hand, when the B2 channel data D2, D4,... Are received on the signal line 408, it becomes “0”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 408. Thus, the switching circuit 417
Outputs the combined channel data D1, D2, D3,... Shown in FIG. 15 to the signal line 427 while switching the connection according to the logic level given via the signal line 428.

FIG. 16 shows a case where the B1 channel data is received later than the B2 channel data. In this case, the data storage input / output control circuit 416
A detection signal of the synchronization pattern 3 is given from the two-channel synchronization pattern 3 detection circuit 415, and in the next cycle, B1
The synchronization pattern 3 detection signal is not supplied from the channel synchronization pattern 3 detection circuit 414. Therefore, the data storage input / output control circuit 416 can detect that the B1 channel data is behind the B2 channel data. Then, the logic level “1” is output via the signal line 418.
Is given to the B-channel data storage circuit 412, so that the data D after receiving the synchronization pattern 3 of the B2 channel
2, D4,... Are accumulated. Thereafter, when a detection signal of the synchronization pattern 3 is given from the B1 channel synchronization pattern 3 detection circuit 414 via the signal line 439, the signal line 41
The data is accumulated by giving a logic level “1” to the B-channel data accumulation circuit 412 via the line 8. Signal line 4
The logic level of the B channel data storage circuit 412
Becomes "1" when the B2 channel data is output from, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 429. On the other hand, when the B1 channel data D1, D3,... Are received on the signal line 408, it becomes “0”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 408. Thus, the switching circuit 417
Outputs the combined channel data D1, D2, D3,... Shown in FIG. 16 to the signal line 427 while switching the connection according to the logic level given via the signal line 428.

Next, the operation of the synchronization confirmation sequence will be described. The control circuit 445 includes the data storage input / output circuit 4
16 recognizes the detection of the synchronization pattern 3 via the signal line 410, and sends the signal to the synchronization confirmation data transmission circuit 423 to the signal line 43.
8, the synchronization confirmation data shown in FIG. 9 or the synchronization failure notification shown in FIG. 11 is output. The synchronization confirmation data transmission circuit 423 includes a signal line 433, a switching circuit 413, and a signal line 43.
4, switching circuit 406, signal line 407, ISDN interface circuit 403 and signal line 404,
After passing through N13, synchronization confirmation data or synchronization failure notification is sent to the partner terminal adapter. The synchronization confirmation data and the synchronization failure notification from the partner terminal adapter are synchronized in the B channel data storage circuit 412 via the signal line 422, the ISDN interface circuit 403, and the signal line 408. The synchronized reception data is supplied to the switching circuit 417, the signal line 427, the switching circuit 43.
1 and the synchronization confirmation data receiving circuit 4 via the signal line 436.
32 and a control circuit 445 via a signal line 446.
Sent to The control circuit 445 identifies the synchronization confirmation data, the synchronization confirmation data mismatch or the synchronization failure notification based on the received data.

After the completion of the synchronization confirmation sequence, the control circuit 44
Reference numeral 5 denotes a switching signal for connecting the signal line 434 and the signal line 421 in the switching circuit 413 and a switching signal for connecting the signal line 427 and the signal line 437 in the switching circuit 431 via a signal line 419. Further, a signal indicating that communication is possible is transmitted to the image codec device 425. As a result, the image data output from the image codec device 425 is
1, switching circuit 413, signal line 434, switching circuit 406,
Signal line 407, ISDN interface circuit 403,
The signal is transmitted to the partner terminal adapter via the signal line 404 and the ISDN 13. The image data transmitted from the other terminal adapter is transmitted to the signal lines 422 and I
SDN interface circuit 403, signal line 408, B
Channel data storage circuit 412, signal line 429, switching circuit 417, signal line 427, switching circuit 431, and signal line 4
The image codec is supplied to the image codec device 425 via 37. As described above, by using both the B1 channel and the B2 channel and realizing synchronization of the two channel data by the optimal algorithm, the transmission speed of each channel is substantially 64 kbps. With a transmission rate of 128 kbps, twice that of
Communication between image codec devices becomes possible.

Next, an embodiment of a system for confirming (testing) whether the synchronization between the B1 channel and the B2 channel is ensured will be described.

FIG. 17 is a diagram showing another configuration of a system for simultaneously using the B1 channel and the B2 channel as a transmission / reception path of the ISDN basic interface and dividing and transferring data at a communication speed of 128 Kbps. FIG. 17 is different from FIG. 1 in that a data communication terminal 14 which is an ISDN terminal device is connected to one terminal adapter 3 and data communication is similarly performed to the other terminal adapter. Terminal 15 is connected. And, by this configuration, 1
Data communication is performed at a communication speed of 28 Kbps (64 Kbps + 64 Kbps).

Next, the communication operation of the second embodiment having the configuration shown in FIG. 17 will be described with, for example, the terminal 201 as the transmitting side and the terminal 202 as the receiving side.

FIG. 18 shows a synchronization sequence which is a call connection procedure of the second embodiment after the call setup. The synchronization sequence includes two sequences, a synchronization establishment sequence and a synchronization confirmation sequence. First, a synchronization sequence executed by the terminal adapter 3 on the transmitting side will be described. Note that the synchronization establishment sequence is the same as the flowcharts shown in FIGS. 3 and 4 and has been described above, and thus description thereof will be omitted.

FIG. 19 is a flowchart showing the synchronization confirmation sequence processing of the transmitting terminal adapter 3 according to the synchronization sequence shown in FIG. Hereinafter, the calling-side synchronization confirmation sequence processing of the terminal adapter 3 will be described with reference to FIG.

In the originating-side synchronization confirmation sequence processing shown in FIG. 19, the terminal adapter 3 sends out 8-byte synchronization confirmation data as shown in FIG. 9 (step S10).
1), start a reception waiting timer (step S10)
2). Next, it is monitored whether or not a timeout has occurred (step S103), and if not, it is determined whether or not a synchronization failure notification in which all eight bytes are "55" as shown in FIG. 11 has been received (step S104). If the synchronization failure notification has not been received, it is determined whether or not data that does not match the synchronization confirmation data transmitted in step S101 has been received (step S105). If no unmatched data has been received, it waits for reception of matched synchronization confirmation data (step S106), and waits until step S106 is received.
Steps 103 to S106 are executed. If received, it is determined whether or not to perform failure detection (step S107). If failure detection is not performed, synchronization confirmation data is sent (step S108). Next, a communication enable display signal is transmitted to the data communication terminal (step S109), and thereafter, the process proceeds to a communication processing routine (step S110).

On the other hand, if it is determined in step S107 that failure detection is to be performed, synchronization confirmation data and a loop creation command are transmitted (step S111), and steps S103 to S107 and step S111 are performed until a loop request confirmation signal is received. And step S1
Step 12 is executed. If received, the data communication terminal 14
(Step S113), and then proceeds to a test processing routine (step S11).
4).

In step S104, when the synchronization failure notification shown in FIG. 11 is received, or in step S1
For example, when data including an error as shown in FIG. 10 is received in 05, the process returns to the synchronization establishment sequence process (step S116). Step S10
If a timeout occurs in step 3, call disconnection processing is performed (step S115).

Next, a synchronization sequence executed by the terminal adapter 6 on the receiving side will be described. Note that the synchronization establishment sequence is the same as the flowcharts shown in FIGS. 6 and 7 and has been described above, and thus description thereof will be omitted.

FIG. 20 is a flowchart showing the synchronization confirmation sequence processing of the terminating terminal adapter 6 according to the synchronization sequence shown in FIG. Hereinafter, the receiving side synchronization confirmation sequence processing of the terminal adapter 6 will be described with reference to FIG.

In the receiving-side synchronization confirmation sequence processing shown in FIG. 20, the terminal adapter 6 activates a reception waiting timer (step S120), determines whether a timeout has occurred (step S121), and if not, as shown in FIG. It is determined whether or not synchronization confirmation data that does not match a predetermined data pattern is received (step S122). If no synchronization confirmation data has been received, reception of the matching synchronization confirmation data is waited for (step S123). ), Until it is received, step S121
To execute each step of step S123. If received, the synchronization confirmation data shown in FIG. 9 is transmitted (step S124). Thereafter, a reception waiting timer is started (step S125), and it is determined whether or not a timeout has occurred (step S126).
It is determined whether or not a synchronization failure notification as shown in FIG. 1 has been received (step S127). If no synchronization failure notification has been received, reception of synchronization confirmation data is waited for (step S1).
28), execute each step of step S126 to step S128 until receiving. If received, it is determined whether a loop creation command has been received. If not received, a communication enable signal is sent to the data communication terminal (step S130), and the process proceeds to the communication processing routine (step S131). On the other hand, when the loop creation command is received in step S129, a loop request confirmation signal is sent to the transmitting side (step S132), and the receiving side line and the transmitting side line are connected to form a data return loop (step S133). .

In step S122, when the synchronization confirmation data that does not match is received, a synchronization failure notification is transmitted (step S135), and the process proceeds to a synchronization establishment sequence process (step S136). Also, in step S127, when the synchronization failure notification is received, the process proceeds to the synchronization establishment sequence process (step S138). If a timeout has occurred in steps S121 and 126, the process proceeds to the call disconnection process (steps S134 and S137).

Next, the operation of the terminal adapter will be described with reference to the block diagram shown in FIG. In FIG. 22, the same reference numerals as those shown in FIG. 12 indicate blocks and signal lines having the same functions. In addition, the operation of the synchronization establishment sequence is the same as that described with reference to FIG.

The operation of the terminal adapter synchronization confirmation sequence will be described below. The control circuit 445 recognizes the detection of the synchronization pattern 3 from the data storage input / output circuit 416 via the signal line 410, and outputs synchronization confirmation data or synchronization confirmation data and a loop creation command transmission circuit 423.
'Via the signal line 438, outputs the synchronization confirmation data shown in FIG. 9, the synchronization failure notification shown in FIG. 11, or the loop creation command shown in FIG. Synchronization confirmation data or synchronization confirmation data and loop creation command sending circuit 423 '
The signal line 433, the switching circuit 413, the signal line 434, the switching circuit 406, the signal line 407, the ISDN interface circuit 403, and the signal line 404
After that, the synchronization confirmation data or the synchronization failure notification or the loop creation command is sent to the other terminal adapter.

The synchronization confirmation data, the synchronization failure notification or the loop request confirmation signal from the partner terminal adapter is transmitted to the B channel data storage circuit 412 via the signal line 422, the ISDN interface circuit 403, and the signal line 408. Done. The synchronized reception data is supplied to the switching circuit 417, the signal line 427, the switching circuit 43.
1 and the synchronization confirmation data or the synchronization confirmation data and the loop creation command receiving circuit 432 ′ via the signal line 436, and are transmitted to the control circuit 445 via the signal line 446. The control circuit 445 identifies the synchronization confirmation data or the loop creation command, the synchronization confirmation data mismatch or the synchronization failure notification based on the received data. When a loop creation command is received, the control circuit 445 sets a signal line 503
The control circuit 501 controls the switching circuit 501 through the control circuit 500 so that all data on the signal line 437 is turned back to the signal line 500.

If the loop creation command is not received, after the completion of the synchronization confirmation sequence, the control circuit 445 sends the signal line 4 via the signal line 419 to the switching circuit 413.
34 and the signal line 421, and the switching circuit 431 gives a switching signal for connecting the signal line 427 and the signal line 437. Further, a signal indicating that communication is possible is transmitted to the image codec device 425. As a result, the image data output from the image codec device 425 includes the signal line 421,
The signal is transmitted to the partner terminal adapter via the switching circuit 413, the signal line 434, the switching circuit 406, the signal line 407, the ISDN interface circuit 403, the signal line 404, and the ISDN 13. The image data sent from the partner terminal adapter is transmitted through the signal line 422 and the ISD
N interface circuit 403, signal line 408, B channel data storage circuit 412, signal line 429, switching circuit 4
17, signal line 427, switching circuit 431, and signal line 437
Is supplied to the data communication terminal 425 'via the.

In the second embodiment, only the procedure for transmitting the test data and performing the test after forming the loop of the terminal adapter on the receiving side is disclosed. However, the communication state is automatically set after the test is completed. can do. It is clear that this can be easily implemented by inserting the synchronization confirmation sequence shown in FIG. 18 between the synchronization confirmation data transmission / reception procedure of the sequence shown in FIG. 2 and the image data transmission / reception procedure. Therefore, it is possible to include a procedure for checking whether the synchronization between the B1 channel and the B2 channel is ensured during the call setting sequence.

If the synchronization is not normally established in this check, the call setup is automatically performed again, so that a 128 Kbps communication path can be provided more efficiently and accurately.

Further, the transmission of the loop creation command for instructing the loop formation on the receiving side and the subsequent test procedure are as follows.
It is not limited to performing at the time of call setup. That is, after the communication path is set, when the data communication terminal is operated (predetermined operation), control is performed so that the loop creation command is transmitted and the subsequent test procedure is executed. ISDN failures can be detected.

In the second embodiment, the failure is detected on the transmitting side, but it is also possible to detect the failure on the receiving side. In this case, a test request signal may be transmitted from the called side to the calling side, and the processing according to the procedures in FIGS. 17 and 18 may be performed, or synchronization confirmation data and a loop creation command may be sent from the called side.

Next, using a plurality of ISDN lines,
An embodiment of a system for performing data communication at a communication speed exceeding 8 Kbps will be described.

FIG. 23 shows, for example, image information at a communication speed of 384 Kbps using three ISDN basic interfaces and using B1 and B2 channels of each line, that is, using six B channels simultaneously. FIG. 2 is a system configuration diagram in the case of communicating with. In FIG.
The connection between the terminal adapter, the image codec device, the video camera and the video monitor is the same as in FIG. 1 except for the input lines 16, 17, 2 to the ISDN.
0, 21 and the output lines 14, 15, 18, 19 are increasing.

FIG. 24 is a diagram showing a synchronization sequence when three ISDN basic interfaces are used. In FIG. 24, this synchronization sequence corresponds to line 2, line 3
Since it is shown that the transmission and reception of the synchronization pattern should be performed for each of the B1 and B2 channels in the same manner as in FIG. 18, detailed description of the operation is omitted. In this figure, the synchronization sequence of synchronization pattern 2 is synchronization pattern 1
And the description of transmission and reception for each channel is also omitted. Also, the transmission side line 1 is not necessarily connected to the reception side line 1, but in this case, by transmitting the synchronization pattern 1 sequentially from the B1 channel of the line 1, the information from the call connection procedure is not used. In each case, it is possible to confirm which B channel of which line on the transmitting side is connected to which B channel of which line on the receiving side.

Further, by immediately transmitting the response pattern after receiving the synchronization pattern, the transmission side of the synchronization pattern can transmit the synchronization pattern from the transmission of the pattern to the reception of the response pattern. By measuring the time, the delay in the network of the B channel can be easily recognized.

The intra-network delay time may cause a problem depending on the communication application. That is, when used as a video conference system according to the method of this embodiment, conversation between people is required. The delay time in the network during conversation is 50m
If it is about S, you will not feel strange, but this is 20
At about 0 ms, the conversation cannot be smoothly performed. Therefore, when the intra-network delay time exceeds a predetermined value, the call is automatically disconnected once, call setting is performed again, and the setting is repeated until the intra-network delay time becomes equal to or less than the predetermined value. Thus, by eliminating the delay time in the network, a smooth conversation becomes possible. This is especially effective for international calls. The reason is that it takes about 320 m
This is because a loss time of S occurs.

Next, the operation of the terminal adapter when using three lines will be described with reference to the block diagram shown in FIG. The same reference numerals shown in circles in FIG. 25 indicate the same signal lines.

First, an outgoing / incoming call connection method will be described. Transmission is started from the image codec device to the control circuit 445 via the signal line 401, and reception is performed from the ISDN interface circuits 403, 500, 530.
The control circuit 445 is activated via 43.

The control circuit 445 receives the signal via the signal line 443,
The signal line 404 from the ISDN interface circuit 403,
Via the 422, 502, 504, 532, and 534, an outgoing / incoming connection is made with the ISDN 13 using the D channel. After the termination of the call connection, the terminal adapter executes a synchronization establishment sequence process. The control circuit 445 controls the signal line 41
Synchronization pattern sending circuit 40 via 1, 520, 550
2,517,547 are activated and signal lines 442,518,
548 logic level to the B1 channel, signal line 444,
It instructs to transmit the logic levels 519 and 549 to the B2 channel. On the other hand, the ISDN interface circuit 40
From 3,500,530, signal lines 424,503,5
33, a B1 channel as shown in FIG.
A channel transmission timing signal is transmitted. The synchronous pattern sending circuits 402, 517, 547 detect this sending timing signal and output the signal lines 444, 442, 518, 5
The logic levels of 19, 548, 549 are changed to signal lines 430, 5
10, 540, the switching circuits 406, 509, 539, the signal lines 407, 521, 551, and the ISDN 13 to send to the partner terminal adapter. That is, in this state, in the switching circuits 406, 509, 539, the signal lines 407, 521, 551 are connected to the signal lines 430, 510, 54.
Connected to 0.

When transmitting the synchronization pattern 1 from the ISDN interface circuit 403 to the B1 channel, the control circuit 445 sets the signal line 444 to the logical level “0”,
The signal line 442 is set to the logic level “1”. When transmitting the synchronization pattern 1 to the B2 channel, the signal line 4
44 is set to the logic level “1”, and the signal line 442 is set to the logic level “0”. Subsequently, the synchronization pattern sending circuit 402
Indicates that all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG.
30, the switching circuit 406, the signal line 407, and the ISDN 13 to send the signal to the terminal adapter on the partner side. When transmitting the synchronization pattern 2 to the B1 channel and the B2 channel, both of the signal lines 444 and 442 are set to the logical level “1”. Subsequently, the synchronization pattern sending circuit 402
Makes all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 "1" and sends them to the partner terminal adapter on the same route as the synchronization pattern 1. When transmitting the synchronization patterns 1 and 2 to the ISDN interface circuits 500 and 530, the signal lines corresponding to the respective signal lines and the like may be controlled in the same manner as described above. ISDN interface circuits 403, 500,
When the synchronization pattern 3 is transmitted to the B1 channel and the B2 channel 530, the synchronization pattern 3 transmission circuit 486 is activated via the signal line 447. At this time, the switching circuits 406, 509, and 539 transmit the signals of the respective signal lines 492 to the signal lines 407, the signals of the signal lines 496 to the signal lines 521, via the signal lines 422 from the control circuit 445.
The signal of the signal line 497 is supplied to the signal line 551.

FIGS. 26 and 27 show signal waveforms in FIG. 25 when transmitting data. FIG.
In (a), (d) and (f), I
SDN interface circuits 403, 500 and 53
These are switching timing signals for the B1 and B2 channels output from the signal lines 424, 503, and 533 of 0.
(B) is a signal waveform of the synchronization pattern 3 transmitted from the signal line 485. (C), (e) and (g) show the signal lines 492 and 49 of the transmission B channel data division circuit 498.
6 shows signal waveforms output from Nos. 6 and 497. Also,
27, (a) shows the signal waveform of the signal line 424, (b) shows the signal waveform of the signal line 434, and (c) to (h) show the time slot signal for each B channel of the signal line 428 (a to f). Is shown. (I) to (k) show the signal lines 492, 496 and 49 of the transmission B channel data division circuit 498.
7 shows the signal waveform of the data output from FIG.

The synchronous pattern 3 transmission circuit 486 outputs 48 data bits “0” of 8 bits to the signal line 485 for one cycle of the signal line 424, that is, for 6 B channels. The switching circuit 413 connects the signal line 485 to the signal line 434 by the signal lines 447 and 487 from the control circuit 445. Transmission B channel data dividing circuit 49
8 divides the data for the B1 and B2 channels for each line by the time slot signal for each B channel on the signal line 428 (A to F) shown in FIG. By multiplying by three (in this embodiment, six B channels are transmitted to each line for every two B channels, so from 384 Kbps to three 128 Kbps)
), And the signal lines 492 and 492 respectively.
14, as shown in FIG. 14, all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 are set to “0”, and the respective switching circuits 406, 509,
From 539, each ISDN interface circuit 403, 50
The data is transmitted to the partner terminal adapter through the route of 0,530. Note that the number of B channels used is 1, 2, 3,.
In the case of n, the number of time slots may be allocated and divided in one period of the timing signal line 424 as shown in FIG.

The timing clock for data transmission / reception output to the image codec device is 64 Kbps × n more than that output from the ISDN interface circuit.
(However, n is a natural number)
Timing signal 4 output from N interface circuit
24, and is output to an image codec device via a signal line 484.

Next, a method of detecting the synchronization patterns 1 and 2 will be described. The synchronization patterns 1 and 2 of each B1 channel transmitted from the partner terminal adapter are ISD
N13, signal lines 422, 502, 532, ISDN
The control circuit 455, B1 via the interface circuits 403, 500, 530 and the signal lines 408, 501, 531
Channel synchronization pattern 3 detection circuit 414, 505, 53
5 and B2 channel synchronization pattern 3 detection circuits 415, 5
06,536. The control circuit 445 detects the synchronization patterns 1 and 2 from the signal lines 408, 501 and 531 based on the transmission timing signals obtained from the signal lines 424, 503 and 533. The B1 channel synchronization pattern detection circuits 414, 505, 535 and the B2 channel synchronization pattern 3 detection circuits 415, 506, 536 are connected to the signal line 4
When reception is started by a start signal given from the control circuit 445 via the control circuit 47 and the synchronization pattern 3 is received, the signal lines 439, 507, 537 and 440, 508, 538 are received.
Data input / output control circuits 416, 516, 5
Notify 46. Data storage input / output control circuit 416,5
When receiving the synchronization pattern 3 detection notification from both of the B1 channel synchronization pattern 3 detection circuits 415, 506, and 536, the control circuit 445 notifies the control circuit 445 via the signal lines 410, 524, and 554. Thus, the synchronization establishment sequence processing ends.

After the completion of the synchronization establishment sequence processing, the synchronization confirmation data and the image data in the subsequent communication processing routine are divided into a plurality of (six in this embodiment) channel data of the B1 and B2 channels of each line. The data is then transmitted and combined into one channel data after reception. At the time of transmission from the terminal adapter on the transmitting side, the delay amounts in the ISDN 13 often differ from each other even if the plurality of channel data are in a predetermined order. In that case, a reception delay difference occurs in the terminal adapter on the receiving side, and it becomes impossible to obtain normal combined channel data. Therefore, in the present embodiment, a method is used in which the reception delay difference between each line and the B1 channel and the B2 channel is absorbed to establish data synchronization. Hereinafter, this method will be described.

First, the operation of the synchronization confirmation sequence will be described. The control circuit 445 controls the signal lines 410, 524,
9 via the signal line 438 to the synchronization confirmation data transmission circuit 423.
Or the synchronization failure data shown in FIG. The synchronization confirmation data transmission circuit 423 includes a signal line 433, a switching circuit 413, a signal line 434, a transmission B channel data division circuit 498, signal lines 492, 496, and 4
97, switching circuits 406, 509, 539, signal line 40
7,521,551, ISDN interface circuit 4
03,500,530 and signal lines 404,504,53
Then, after passing through the ISDN 13 through step 4, the synchronization confirmation data or the synchronization failure notification is sent to the other terminal adapter. Synchronization confirmation data from the other terminal adapter,
Alternatively, the synchronization failure notification is transmitted by the signal lines 422, 502, 53
2. ISDN interface circuits 403, 500, 5
30, data synchronization is performed in the B channel data storage circuits 412, 415 and 542 via the signal lines 408, 501 and 531. The synchronized received data is input to the synchronization confirmation data receiving circuit 432 via the switching circuit 417, the signal line 427, the switching circuit 431, and the signal line 436, and is transmitted to the control circuit 445 via the signal line 446. The control circuit 445 recognizes the synchronization confirmation data, the synchronization confirmation data mismatch, or the synchronization failure notification based on the received data.

After completion of the synchronization confirmation sequence, the control circuit 44
Reference numeral 5 denotes a switching signal for connecting the signal line 434 and the signal line 421 in the switching circuit 413 and a switching signal for connecting the signal line 427 and the signal line 437 in the switching circuit 431 via a signal line 419. Further, a signal indicating that communication is possible is transmitted to the image codec device 425. As a result, the image data output from the image codec device 425 is
1, switching circuit 413, signal line 434, transmission B channel dividing circuit 498, signal lines 492, 496, 497, switching circuits 406, 509, 539, signal lines 407, 521, 5
51, ISDN interface circuits 403, 500, 5
30, and are sent to the partner terminal adapter via the signal lines 404, 504, 534 and ISDN. Also,
The image data sent from the partner terminal adapter is sent to signal lines 422, 502, 532, ISDN interface circuits 403, 500, 530, signal lines 408, 5
01,531, B channel data storage circuits 412,51
2, 542, signal lines 429, 513, 543, switching circuit 417, signal line 427, switching circuit 431 and signal line 43
7, and is supplied to the image codec device 425. As described above, by using both the B1 channel and the B2 channel of a plurality of lines and realizing synchronization of a plurality of channel data by an optimal algorithm, the transmission speed of each channel is 64 Kbp.
Communication between the image codec apparatuses becomes possible at a transmission rate substantially n times (where n is a natural number) as compared with s.

Next, the timing for establishing the synchronization will be described. FIG. 29 is a timing chart showing a method for establishing synchronization of reception data of a plurality of B channels. At what timing, the synchronization pattern 3 is received, how the data storage input / output circuit is controlled, and FIG. 9 is a diagram specifically explaining whether synchronization is established. In FIG. 29, (a), (c) and (e) show the signal waveforms of the signal lines 424, 503 and 533, respectively. (B), (d) and (f) respectively show the signal line 4
It is a waveform of the received signal obtained from 08, 501, and 531. (G), (i), (k), (m), (p) and (r) are signal waveforms indicating the data accumulation timing output from the data accumulation input / output control circuit 416,
(H), (j), (l), (n), (q) and (s)
Is a signal waveform indicating the data read timing output from the data storage input / output control circuit 416. (T) is B
This is a series of data read from the channel data storage circuit 412, and (u) is a signal line 488 of the control circuit 516.
Is a data output enable signal output from.

First, the ISDN interface circuit 403
The case will be described. If you use multiple lines,
The synchronization pattern 3 of all the B channels must be detected, and the period of the next plurality of B channels must be changed as shown in FIG. 28 (at times other than 128 Kbps). Therefore, it is necessary to (always) accumulate B channel data once. As shown in FIG. 29, as shown in FIG. 29, only the B1 channel following the detection of the synchronization pattern 3 in the B1 channel of the signal line 408 is sent to the B-channel data storage circuit 412 via the signal line 418. And the data D1, after the synchronization pattern 3 of the B1 channel,
D7, D13 (according to the use of six B channels in this embodiment, every six data is accumulated).

Similarly, only the next B2 channel in which the synchronization pattern 3 is detected in the B2 channel of the signal line 408 is given a logical level “1” to the B-channel data storage circuit 412 via the signal line 491, Synchronization pattern 3
The subsequent data D2, D8, D14, D20... Are stored.

Thereafter, when pattern 3 is detected in all the remaining B channels, signal lines 410, 524, and 554 are all at logical level "1", and the second of the transmission timings of signal line 424 is performed under these three AND conditions. The data output enable signal of the signal line 488 is output to each of the data accumulation / input / output control circuits 416, 516, and 546 at the rising edge of. Here, the reason why the data output enable signal is output at the second rising edge of the transmission timing of the signal line 424 will be described with reference to FIG. If the output enable signal is output at the timing of the first rising edge, it is necessary to accumulate the B channel data in order to change the cycle.
The timing immediately after receiving the synchronization pattern 3 in all the Bch at 9 is the position of the head of D1 in FIG. 29B, but if the data is output from here, all the data of D1 is input. Before that, all data of D1 must be output, which is impossible. (D in FIG. 29 (g)
1 and D1 in FIG. 29 (h) overlap, and in FIG. 29 (h), it is necessary to finish outputting data earlier, which is impossible. Therefore, the input enable signal (g) and the output enable signal (h) must have a difference of one cycle of the transmission timing 424 at worst. Therefore, a condition that the data output enable signal is output at the second rising edge is required.

Data storage input / output control circuits 416 and 51
6, 546, this signal and the time slot creation circuit 4
The time slot signals A to F given from FIG.
Signal line 49 of FIG. 29 obtained under the AND condition
0, 409, 522, 515, 552, and 553 at the logical level “1”, the respective B-channel data storage circuits 412, 5
Data is output from 12,542. Switching circuit 417
Indicates that the time slot signal output from the time slot creation circuit causes the data to be transmitted to the signal line 427 only while each B channel data storage circuit is outputting data.
., The synchronized data D1, D2, D. shown in the signal line 427 of FIG. ... can be obtained.

In the above embodiment, the basic interface of the ISDN has been described as an example. However, the present invention can be applied to the primary interface and higher-level interfaces, thereby realizing higher-speed data transmission. .

[0078]

According to the present invention, a series of data carrying information is time-divided and transmitted as divided data in a predetermined order for each channel of a plurality of lines. By rearranging the data in a predetermined order, the transmission speed of the series of data can be set to be a multiple of the total transmission speed of the inherent transmission speed of each channel, so that an enormous amount of image data such as image data is transmitted. Even if
The effect is obtained that the transmission time can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a communication device according to a first embodiment using ISDN of the present invention.

FIG. 2 is a diagram showing a synchronization sequence of a communication system using ISDN of the present invention.

FIG. 3 is a flowchart of an originating-side synchronization establishment sequence process.

FIG. 4 is a flowchart of an originating-side synchronization establishment sequence process.

FIG. 5 is a flowchart of an originating-side synchronization confirmation sequence process.

FIG. 6 is a flowchart of a called-side synchronization establishment sequence process.

FIG. 7 is a flowchart of a called-side synchronization establishment sequence process.

FIG. 8 is a flowchart of a called-side synchronization confirmation sequence process.

FIG. 9 is a pattern diagram of synchronization confirmation data.

FIG. 10 is a pattern diagram of synchronization confirmation mismatch data.

FIG. 11 is a data pattern diagram of a synchronization failure notification.

FIG. 12 is a block diagram of a terminal adapter in FIG. 1;

FIG. 13 is a data timing chart of the B1 channel and the B2 channel.

FIG. 14 is a timing chart of received data having no delay difference.

FIG. 15 is a timing chart of received data having a delay difference.

FIG. 16 is a timing chart of received data having a delay difference.

FIG. 17 is a configuration diagram of a communication apparatus according to a second embodiment using the ISDN of the present invention.

FIG. 18 is a diagram showing a synchronization sequence of the communication system according to the second embodiment using the ISDN of the present invention.

FIG. 19 is a flowchart of an originating-side synchronization confirmation sequence process according to the second embodiment.

FIG. 20 is a flowchart of a receiving-side synchronization confirmation sequence process of the second embodiment.

FIG. 21 is a pattern diagram of a loop creation command.

FIG. 22 is a block diagram of the terminal adapter in FIG. 17;

FIG. 23 is a configuration diagram of a communication device according to a third embodiment using the ISDN of the present invention.

FIG. 24 is a diagram illustrating a synchronization sequence of the communication system according to the third embodiment using the ISDN of the present invention.

FIG. 25 is a block diagram of the terminal adapter in FIG. 23.

FIG. 26 is a pattern diagram of pattern 3 of synchronization confirmation data.

FIG. 27 is a timing chart of a time slot signal.

FIG. 28 is a timing chart of the B-channel multiplexing method.

FIG. 29 is a timing chart showing a method for establishing reception data synchronization of a plurality of B channels.

FIG. 30 is a block diagram of a terminal device using a conventional ISDN.

[Explanation of symbols]

 1,9 Video camera 2,7 Image codec device 3,6 Terminal adapter 4,5,10,11 Subscriber line 8,12 Video monitor 101 ISDN

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 7/14 H04L 11/02 Z (56) References JP-A 2000-69000 (JP, A) JP-A 2-222334 (JP) JP-A-5-276212 (JP, A) Patent 2968565 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 29/04 H04L 12/02 H04L 29/08

Claims (2)

(57) [Claims] 1. An ISDN circuit having a plurality of communication channels.
By connecting multiple wires, transmission and reception of data carrying
These are divided into multiple communication channels of multiple ISDN lines.
A communication device using ISDN, the communication device being provided in correspondence with the plurality of ISDN lines,
Multiple line interfaces for interfacing with DN lines
And Esu means, call connection of a plurality of communication channels of said plurality of ISDN lines
When synchronization is completed, the synchronization establishment data is sent.
Data transmission means, and the synchronization establishment received from the synchronization establishment data transmission means.
Divides the data and divides the data
Means for sequentially transmitting data, and a plurality of communication channels for each of the plurality of ISDN lines.
Provided correspondingly, upon receiving the synchronization establishment data,
Multiple synchronization establishment data that output the synchronization establishment data reception signal
Data receiving means and a plurality of line interface means.
To store data received from the ISDN line.
Number of data storage means, the plurality of data storage means and the plurality of synchronization establishment data
Receiving means for receiving the synchronization establishment data.
When a communication signal is detected, the corresponding data storage means is activated.
Request to start data storage, and
Data storage inputs and outputs that control the data output from
Output control means and all of the plurality of synchronization establishment data
When recognizing that the vertical data reception signal has been output,
Outputs data stored in multiple data storage units.
Controlling the plurality of data storage input / output control means so that
Control means for inputting data output from the plurality of data storage means.
These data are supplied according to the supplied switching timing signal.
Switching output means for switching and outputting data, and a signal corresponding to the speed of data carrying the predetermined information.
The data stored in the plurality of data storage means.
Output from the switching output means in a predetermined order.
For supplying a switching timing signal to the switching output means
A communication device using ISDN , comprising: a slot generation unit . 2. An ISDN circuit having a plurality of communication channels.
By connecting multiple wires, transmission and reception of data carrying
Simultaneously use multiple communication channels of multiple ISDN lines
This is a communication method using ISDN performed by using a plurality of ISDN lines on a transmitting side.
Interface with the ISDN line, and call-connect with a plurality of communication channels of the plurality of ISDN lines.
Is completed, the synchronization establishment data is transferred to the plurality of ISDN times.
Transmission to each communication channel of the line, and then dividing the data carrying the predetermined information,
A predetermined order for each communication channel of the plurality of ISDN lines.
The transmission is performed sequentially in order, and the receiving side corresponds to each of the plurality of ISDN lines.
Te, to interface with the ISDN lines, a plurality of communication channels of each of the plurality of ISDN lines
Receive the synchronization establishment data,
And send the data
The divided data carrying the predetermined information is stored, and the divided data is stored in all the plurality of communication channels of the plurality of ISDN lines.
Upon detecting the corresponding synchronization establishment data reception signal,
Depending on the speed of data carrying predetermined information, the plurality of communications
The divided predetermined information stored for each channel is
Communication method data, using the ISDN characterized that you sequentially switching output in a predetermined order to play.