JP3197408B2 - Additional bit processing device for marker identification - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a marker identifying additional bit processing device for decoding a variable length code.

[0002]

2. Description of the Related Art In general, in order to decode a variable length code such as image data, a marker code is required to indicate the size of the variable length code and the start position of re-decoding when a transmission error occurs. One of the draft standards that defines the decoding method for such variable-length code image data is JPEG.
There is a Huffman code decoding method (JPEG method). Hereinafter, this method will be described. For details of the JPEG method, see CD10918-1 Digital Compression Cod
ing ofContinuous-Tone Still Images Part 1: Require
Details are described in the ments and Guidelines.

First, a procedure for inserting a marker code into data composed of a variable length code will be described below. (1) If the end before the insertion ends with a Huffman code and does not reach the byte boundary, the bits of "1" are packed until the byte boundary is reached. (2) After inserting 1 byte of 0xFF in hexadecimal (hereinafter represented by 0x), insert 1 byte of marker code. In the case of a marker code requiring a parameter, information indicating the length of the entire marker code and a parameter included in the marker code follow. In length,
A value obtained by adding the number of bytes of the parameter to its own 2 bytes is written. 0xFF before marker code is usually 1
Although it is a byte, a plurality of 0xFFs may be inserted.

(3) In the case of encoding such a variable length code, when 0xFF occurs in the Huffman code string, 0xFF follows 0xFF in order to distinguish it from 0xFF preceding the marker code. Insert Therefore,
When decoding such a variable length code, 0xF
When 0x00 is received after F, this is removed. On the other hand, when a byte other than 0x00 is received after 0xFF, it is regarded that there is a marker code after 0xFF.

Next, a description will be given of the handling of a marker code when decoding a Huffman-coded variable-length code according to the JPEG method. (1) When a variable length code exists immediately before a marker code, bits up to a byte boundary are "1". (2) At the head of the marker code, 0xFF having a length of 1 byte or more starting from a byte boundary is inserted, followed by a 1-byte marker identifier. When the marker needs a parameter, the number of bytes and the parameter are written. (3) In the byte starting from the byte boundary in the variable length code,
If 0xFF is present, 0x00 bytes are inserted after that. Therefore, when decoding, there is 0xFF at the byte boundary in the coded variable-length code, and 0xFF
When the byte immediately after FF is 0x00, 0x0
Decoding must be performed assuming that there is no 0.

FIG. 2 shows an example of a system using a JPEG Huffman decoder. In FIG. 2, a host processor 1 reads / writes a memory 2 via a bus 5 and controls a JPEG decoding unit 3 and an I / O 4. FIGS. 3 and 4 show the conventional JP in FIG.
FIG. 2 shows a block diagram of a method for realizing an EG decoding unit. The decoding unit 3 includes a data input unit 31 for receiving data, a data shift unit 32 for shifting the captured data, and a decoder unit 33 for extracting and decoding code data from the shifted data. Further, a marker detecting unit 3 for extracting 0xFF00 from the data
4. A communication control unit 35 for communicating with the host processor 1 is provided.

In this example, one code data length is a maximum of 16 bits, and decoded data is obtained as a 16-bit data string. The detailed configuration and operation of each part of the conventional JPEG decoding unit shown in FIGS. 3 and 4 will be described below. (1) The data input unit includes two registers 311, 312 each of 32 bits, and holds two consecutive 32-bit code data supplied from the host processor 1 in the two registers 311, 312. (2) The data shift unit 32 includes a shifter 321 and a 16-bit register 322. The shifter 321 performs a left shift from 1 bit to 32 bits to shift the data held in the data input unit 31 by the number of bits for which decoding has been completed. Then, the result is held in the register 322.

(3) The decoder section 33 includes a decoder 331,
16-bit register 332 and shift amount adder 333
Consists of The decoder 331 decodes the Huffman code shifted by the data shift unit 32. Then, the data of the decoding result is held in the register 332. On the other hand, the shift amount adder 333 is a 5-bit adder having an overflow output, and cumulatively adds the number of bits of the code decoded by the decoder 331. Shift amount adder 33
3 notifies the addition result to the shifter 321 and, when overflow occurs, notifies the communication control unit 35 of the overflow. When the overflow bit of the shift amount adder 333 is output, it indicates that the code held in the register 312 of the data input unit 31 has been decoded and becomes unnecessary. Therefore, at this time, in the data input unit 31, the code of the register 311 is stored in the register 312, and a new 32-bit code is stored in the register 311.

(4) The marker detecting section 34 includes a 0xFF detecting section 342, a 0x00 detecting section 341 and a 0xFF00 detecting section 343. The 0xFF detection unit 342 is a register 3
It detects which byte of the 12 4 bytes or the upper 2 bytes of the register 311 has 0xFF. 0x
00 detection unit 341 determines which byte in the lower 3 bytes of register 312 or the upper 3 bytes of register 311 is 0.
It detects whether x00 exists. 0xFF00 detector 3
43 denotes a 0x00 detection unit 341 and a 0xFF detection unit 342
It is determined from which result 0xFF00 exists in which two consecutive bytes.

(5) The communication control unit 35 includes a marker detection unit 34
Detects that 0xFF00 exists in two bytes in the two registers 311 and 312 of the data input unit 31 or when the overflow of the shift amount adder 333 occurs in the decoder unit 33, Notify that. (6) When the communication control unit 35 notifies the overflow of the shift amount adder 333 of the decoder unit 33 from the communication control unit 35, the host processor 1 registers the register 31 in the data input unit 31.
After the content of 1 is transferred to the register 312, new 32-bit data is written to the register 311 of the data input unit 31. Further, the marker detection unit 34 is connected to the data input unit 31.
0x in 2 bytes of the two registers 311 and 312
When the host processor 1 receives notification that the presence of FF00 has been detected, the host processor 1 removes 0x00 of 0xFF00 at the byte boundary from the data stored in the registers 311 and 312 of the data input unit 31 earlier. The value is written to the two 32-bit registers 311 and 312 of the data input unit 31 again as 0xFF.

In the above configuration and its operation, 0xFF
The operation when 00 is detected and the subsequent operation of the host processor 1 will be specifically described. FIGS. 5 to 8 show the data flow when the host processor 1 transfers the code data in the memory 2 to the register 311 in the decode unit 3, and includes four words 21 to 24 of the memory 2 and the host processor. 1 and register 1 inside host processor 1
1 and 12 and registers 311, 312, a shifter 321, and a register 322 which are part of the decoding unit 3 according to the prior art. Four words 2 of memory 2
A to d, e to h, i to l, m to
Code data of 8 bits × 4 called p is written.

Next, normal operation will be described. The host processor 1 takes out the first word 21 from the memory 2 and writes it into the register 311 in the decode unit 3.
Next, while the data previously written in the register 311 is stored in the register 312, the host processor 1
Reads a new word 22 from the memory 2 and writes it to the register 311 again. FIG. 5 shows the result of the above operation. The decode unit 3 decodes the data obtained by the above operation. Here, consider a state in which the first 8 bits are decoded from the state shown in FIG. FIG. 6 shows the state at this time. In this state, the contents of the register 322 holding the shifter output are different from the state of FIG. That is, next, decoding is performed with the remaining data excluding the byte a.

At this time, the data of b and c is 0xF
It is assumed that F00 is detected. Then, 0x0
Since c, which is 0, is unnecessary data for decoding,
Exclude this. For this purpose, the host processor 1 fills in the register 12 after removing c from the register 12 as shown in FIG. Then, the register 11 is newly added from the memory 2.
The operation of shifting the leading 8 bits e of the word 22 read into the register 12 after d on the register 12 is performed, and the result is written into the register 311. Thereafter, when storing the new word 22 in the register 311 of the decoding unit 3, the host processor 1 performs a shift for removing the first 8 bits from the word 22 as shown in FIG. , The lower 8 bits of the shifted word 22 and the next word 23
To move the first 8 bits of.

[0014]

However, the above-mentioned prior art has the following problems. That is, in the conventional method, if there is a 2-byte 0xFF00 starting from a byte boundary in the variable-length code, as described above, the decoding is temporarily interrupted and the host processor 1
It is necessary to delete the 00 byte and pass the data to the decoding unit 3 again to start. Therefore, there is a problem that the throughput of data processing is reduced. Further, in the conventional method, once the two bytes of 0xFF00 appear, the host processor 1 sets 0x00 as described above.
There is a problem in that the byte alignment for the number of bytes deleted must always be performed each time a word is read from the memory thereafter.

The present invention has been made in view of the above points, and has a marker identification function in which the addition of a host processor is not increased even when an additional code for identifying a marker code is removed and re-decoded. It is an object of the present invention to provide an additional bit processing device.

[0016]

According to the present invention, there is provided a marker identifying additional bit processing apparatus for distinguishing a header code for detecting a marker code representing a start position of data in a bit string from other bit strings. In a processing device for processing an additional bit to be added, a data input unit for holding a bit sequence before a header code preceding a marker code, a data shift unit for shifting a bit sequence held in the data input unit, By synthesizing a bit sequence before the header code held in the data input unit at the time of detecting the bit, a bit sequence similar to the header code, and a bit sequence after the additional bit,
An additional bit processing unit that removes the additional bit, a bit string output by the data shift unit when the additional bit is detected is input via the additional bit processing unit and decoded, and the additional bit processing unit And a decoder for outputting a shift amount so as to shift the same number of bits as the number of bits.

[0017]

In the marker identification additional bit processing device of the present invention, the decoding unit decodes the bit string data input from the host processor as follows. The bit string read into the register of the data input unit is shifted one bit at a time by the data shift unit and decoded by the decoder unit. On the other hand, the bit string read into the register of the data input unit is also sent to the marker detection unit,
The marker detector detects a header code (for example, 0xFF) and an additional bit (for example, 0x00) inserted before the marker code. When an additional bit continuous to the header code is detected at the byte boundary, the bit string from which the additional bit has been removed by the additional bit processing unit is input to the decoder unit. The decoder unit decodes this bit string, shifts the data shift unit by the number of additional bits, and continues decoding the subsequent bit string. Therefore, the host processor does not need to remove the additional bit.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of an additional bit processing device for marker identification according to the present invention. In FIG. 1, a decoding unit 3 'includes a data input unit 31 for taking in data and a data shift unit 3 for shifting the taken data, similarly to the conventional decoding unit 3 shown in FIG.
2. Decoder unit 33 for extracting and decoding code data from the shifted data, 0xFF00 from the data
And a communication control unit 35 for extracting the information. Further, when 0xFF00 at the byte boundary is detected, the additional bit processing unit 36 that removes the additional bit 0x00 and supplies the code data to the decoder unit 33
It has. That is, the decoding unit 3 'has a configuration in which the additional bit processing unit 36 is provided in the conventional decoding unit 3 shown in FIGS. 3 and 4, and the configuration other than this portion is the same as the conventional one.

FIG. 10 shows the contents of the additional bit processing section in detail. The additional bit processing unit 36 includes a register 361 that holds 0xFF, a lower bit combination unit 362 that combines lower bits of the shifter output with 0xFF, and a lower bit combination unit 3
There is provided a lower bit holding register 363 for holding the output of L.62. Further, the additional bit processing unit 36 selects the output of the register 363 and the output of the shifter 321 to select 0x
A 0x00 removal selector 364 for removing 00 and a 3-bit subtractor 365 for subtracting the lower 3 bits of the shift amount adder 333 from the numerical value “8” are provided. Further, the lower bit synthesizing unit 362 is controlled by the output of the 3-bit subtractor 365, and the 0x00 removal selector 364 is controlled by the output of the 0xFF00 detection unit 343 to remove the additional bit of 0x00.

Next, the operation of the additional bit processing section 36 will be described. First, the code output from the data shift unit 32 is input to the decoder 331 one bit at a time, and the decoder 331 performs decoding. And, for example, FIG.
If decoding can be performed with 5 bits of “abcde” shown in FIG. 1, the code length is found to be 5 bits. In such a case, the additional bit processing unit 36 is not activated because the code can be decoded only by the code before 0xFF, not including 0xFF00. On the other hand, when decoding cannot be performed with the five bits “abcde” shown in FIG. 11 and “1111111110000000000fgh” must be input to the decoder 331, the additional bit processing unit 36 is activated. That is, the additional bit processing unit 36 is activated only when the decoding by the decoder 331 is not completed.

When the 0xFF00 detection unit 343 detects that 0xFF00 exists at the byte boundary, the shifter 32
Code bits up to byte boundary of output of 1 and 0x
The FFs are combined by the lower bit synthesizing unit 362 and held in the lower bit holding register 363. Further, the shift amount adder 33
The shifter 321 shifts based on the result of adding “8” by 3. The result is set as the upper bit, and the contents of the lower bit holding register 363 are set as the lower bit, and
The selection is performed by the 0 removal selector 364. Thus, a code obtained by removing 0x00 from the original code sequence can be supplied to the decoder 331.

FIG. 11 shows this operation more specifically.
FIG. 11 shows the output of the lower bit holding register 363, the output of the shift amount adder 333, the output of the shifter 321, and the output of the 0x00 removal selector 364. (1) The initial state is shown in FIG. It is assumed that the output of the shift amount adder 333 is “00011”, and the shifter output is “0xFF00” for “bit 5” to “bit 20”. At this time, the 0xFF00 detection unit 343 notifies the additional bit processing unit 36 and the shift amount adder 333 that the 0xFF00 at the byte boundary has been detected. The additional bit processing unit 36 holds the number of bits obtained by subtracting the lower 3 bits of the current output of the shift amount adder 333 from “8” (ie, 5 bits at this time) together with 0xFF in the lower bit holding register 363.

(2) The next state is shown in FIG. "8" is added to the shift amount adder, and the shift is performed again using the shifter 321 with the result. (3) The next state is shown in FIG. In the 0x00 removal selector 364, “bit 0” to “bit 12” select the output of the lower bit holding register 363, and “bit 13” to “bit 15” select the shifter output. In this manner, 0x00 can be continuously removed, and byte alignment in the prior art is not required.
In the above-described embodiment, the description has been given of the Huffman code decoding method. However, it is needless to say that the present invention is not limited to this, and can be applied to other variable length code decoding methods.

[0024]

As described above, according to the additional bit processing apparatus for marker identification of the present invention, since the additional bit processing section for removing the additional bit is provided, it is possible to identify the marker code. Since the same code as the header in the code sequence is used in the code sequence, an additional bit must be added to the header to indicate that the code is a marker code. It is possible to Therefore, it is possible to eliminate the time for removing by the host processor and the time for byte alignment by the host processor.

[Brief description of the drawings]

FIG. 1 is a block diagram (part 1) of an embodiment of an additional bit processing device for marker identification of the present invention.

FIG. 2 is a block diagram illustrating an example of a system using a JPEG Huffman code.

FIG. 3 is a block diagram (part 1) of an example of a conventional JPEG decoding unit.

FIG. 4 is a block diagram (part 2) of an example of a conventional JPEG decoding unit.

FIG. 5 is a block diagram (part 1) for explaining a conventional marker identification additional bit processing procedure;

FIG. 6 is a block diagram (part 2) for explaining a conventional marker identification additional bit processing procedure;

FIG. 7 is a block diagram (part 3) for explaining a conventional marker identification additional bit processing procedure;

FIG. 8 is a block diagram (part 4) for explaining a conventional marker identification additional bit processing procedure;

FIG. 9 is a block diagram (part 2) of an embodiment of an additional bit processing device for marker identification according to the present invention.

FIG. 10 is a block diagram illustrating a detailed configuration of an additional bit processing unit.

FIG. 11 is an explanatory diagram of a marker identification additional bit processing procedure according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host processor 2 Memory 3 Decoding unit 31 Data input unit 32 Data shift unit 33 Decoder unit 34 Marker detection unit 35 Communication control unit

Claims (1)

(57) [Claims] 1. A processing device for processing a header code for detecting a marker code for indicating a start position of data in a bit string, which is added to distinguish a header code from other bit strings, comprises: A data input unit that holds a bit string before the header code to be shifted, a data shift unit that shifts the bit string held in the data input unit, and a header code that is held before the header code held in the data input unit when the additional bit is detected. An additional bit processing unit that removes the additional bit by synthesizing a bit sequence of the header code, a bit sequence similar to the header code, and a bit sequence subsequent to the additional bit, and the data shift unit outputs when the additional bit is detected. A bit string is input through the additional bit processing unit and decoded, and the data shift is performed. Wherein to perform the shifting of the same number of bits as the number of bits of the additional bits, the marker identification additional bit processing apparatus characterized by comprising a decoder unit for outputting a shift amount to.