JP3195467B2 - Cell reduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell reduction apparatus for integrating cells and deleting unnecessary cells with respect to logical connection information in semiconductor circuit design.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram showing a configuration of a conventional cell reduction device. In FIG. 14, 1 is a logical connection information to be input, 2 is a netlister that creates a netlist by referring to various libraries and external inputs based on the logical connection information 1, and 3 is one function of the netlister 2. A cell reduction unit that is responsible for cell reduction, and a cell reduction library that describes rules for deleting macro cells for performing cell reduction or replacing them with smaller macro cells having fewer functions, and 5 includes a plurality of macro cells. A macro cell library 6 in which macro cell information relating to the CRT is described; and 6, peripheral devices such as a CRT display, a keyboard, and a mouse, which are input / output stages with the cell reduction device.

FIG. 15 is a diagram showing a part of a rule described in a cell reduction library. In the figure,
R10 to R15 are rules separately described in the case where three input AND gates must be replaced. The first row describes the function and pin of the macrocell to be replaced, and the second and subsequent rows describe the function and pin or potential of the macrocell to be replaced. For example, the rule R10 is that the input pin A among the input pins A, B, and C of the three-input AND gate has the power supply potential V _CC
(Hereinafter referred to as a power supply signal class), a rule indicating replacement with a two-input AND gate. When the rule R10 is applied, the rule is input to the input pin B of the three-input AND gate. The signal is connected to the input pin A of the two-input AND gate, and the signal input to the input pin C of the three-input AND gate is connected to the input pin B of the two-input AND gate and to the output pin of the three-input AND gate. The connected signal line is connected to the output pin of the two-input AND gate.

A conventional technique will be described with reference to FIG. FIG. 16A is a diagram showing a state of a logical hierarchy before performing cell reduction. 9, reference numeral 90 denotes a macro cell having a function of a two-input AND gate; 91, a macro cell having a function of a three-input NOR gate; 92, an arbitrary logic circuit; 93, a macro cell having a function of a NOT gate;
4 is a ground signal class, 95 is a 2-input AND gate 9
One of the input pins 96 of the three-input NOR 91 connected to the output pin 0 is an empty portion of the signal in the logic hierarchy 97. There are two types of conventional cell reduction. One is forward reduction, which replaces cells with logic equivalents when a power / ground signal class is defined on the input side of the logic hierarchy, and the other is the output of the logic hierarchy. This is a backward reduction in which unnecessary signals and cells are deleted toward the input side of the logical connection information when there is a signal empty state on the side.

Next, the operation will be described. First, in the case of forward reduction, since the ground signal class 94 is defined on the input side of the logic hierarchy 97, the process proceeds from this point toward the output side of the logical connection information. The cell 90 shows an AND logic, and when '0' is inputted to at least one of the inputs, the output is fixed to '0'. That is, the cell 90 always outputs “0”, and is replaced with the ground signal class with reference to the cell reduction library 4.

Next, the cell 91 indicates NOR logic, and the input 95 is now "0". In this state, the cell 91
Is not fixed and depends on the remaining two inputs. That is, since the input pin 95 of the element 91 does not contribute to the determination of the logic, the input of the input pin 95 is considered to be an unnecessary input. Therefore, the cell 91 is replaced with a logically equivalent two-input NOR with reference to the cell reduction library 4. Thereafter, since the power ground signal class does not propagate, the forward reduction ends at this point.

On the other hand, in the case of backward reduction, the process proceeds toward the input side of the logical connection information based on the empty state of the output side of the logical hierarchy 97 as a clue. The logic hierarchy 97 has a signal vacancy 96, meaning that the output of cell 93 is not used. Therefore, the cell 93 is an unnecessary cell, and the cell 93 is deleted from the logical connection information.
Eventually, the process ends when the output of the cell being used is reached.

As described above, when the logical hierarchy shown in FIG. 16A is reduced, a logical hierarchy 97 as shown in FIG. 16B is obtained.

[0009]

SUMMARY OF THE INVENTION With the current logic synthesizer,
Is, of multi-bit latch, it can not be carried out mapping of the flip-flop, not only can be mapped to a plurality of one-bit latch, flip-flop. Similarly, mapping to a scan flip-flop could not be performed, and only mapping to a plurality of cells, a composite gate and a flip-flop, could be performed. Conventional cell reduction equipment
Since it is configured , with respect to mapping of a logic hierarchy having a plurality of macro cells for inputting a clock signal,
There is a problem that the reduction for integrating such cells cannot be performed, and the cell area (that is, the number of basic cells (BC)) and the number of wirings (that is, the number of pin pairs) cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a part of a circuit mapped to a plurality of macro cells by a logic synthesizer is grouped,
A smaller number of macro cells can be replaced,
It aims to obtain a cell reduction device that can reduce the number of pins and the number of pin pairs, and to provide a mapping library suitable for this device, weighting when grouping, grouping content selection function, and fanout adjustment function after grouping. Aim.

[0011]

According to a first aspect of the present invention, there is provided a cell reduction device comprising: (a) a macro cell library describing a plurality of macro cells; and (b) at least the grouped macro cells are described in the macro cell library. A mapping library describing rules for replacing the macro cells with other macro cells, and (c) the types of macro cells that can be grouped among the macro cells and the case where grouping is possible. And a cell reduction unit that replaces the grouped macro cells with other macro cells described in the macro cell library while referring to the mapping library. ,
Before the predetermined rule corresponds to the logical connection information
The same clock input signal of multiple macro cells
Group input macro cells as the same group
It is characterized by including a rule to do.

A cell reduction device according to a second aspect of the present invention is the cell reduction device according to the first aspect, wherein the predetermined rule considers a mutual relationship between a plurality of macro cells.
Weighting the macro cell to take into account the weighting.
It is characterized by including rules for grouping
You.

The cell reduction device according to a third aspect of the present invention is the cell reduction device according to the first aspect, wherein
When grouping in the cell reduction section,
Macro cells that can be looped, macros after grouping
Macrocells of the macrocell group and the macrocell group
Information and the groupable
A group to be replaced can be specified from among the cross cells.
It is characterized by having.

[0014]

[0015]

[0016]

[0017]

The mapping library in the first invention is
Clarify the rules for grouping which macro cells can be replaced. The cell reduction unit can replace the grouped macro cell with another macro cell described in the macro cell library and having the same function as the grouped macro cell with reference to the mapping library. Further, cell reduction can be controlled by rules described in the mapping library. The cell reduction unit allows replacement with another macro cell having a smaller area and a smaller number of wires than the grouped macro cells. Ma
In addition, the cell reduction unit is made to correspond to the logical connection information.
Input the same clock input signal from multiple macro cells.
Macro cells to be grouped as the same group
After grouping macro cells according to the rules
Grouping while referring to the
Macro cell that is described in the macro cell library
Same macro system input
A plurality of macro cells for inputting signals are
Integrated into a macro cell having the same function as the cell,
The number of wirings can be reduced.

The cell reduction unit according to the second invention is arranged such that a macro cell is provided in consideration of a mutual relation between a plurality of macro cells.
Weighting the glue pin while considering the weight.
After referring to the mapping library,
Macro cell in the macro cell library
Replace with the other macro cell described.
Among multiple macrocells that input lock-related input signals,
Those with the same weight can be integrated.
For example, by replacing a macro cell like this,
It is possible to obtain logical connection information that can be easily controlled.

Cell reduction device according to the third invention
Is a macro cell that can be grouped by the operator, for example.
Group, macrocell group after grouping and macrocell group
Displays information such as the area of each macro cell and the number of wires
Based on a group of macro cells that can be grouped,
Groups can be specified selectively, area and number of wires
Cell reduction in consideration of Guru like this
The grouping content selection function is used for grouping users.
Can increase the degree of freedom.

[0020]

[0021]

[0022]

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing a configuration of a cell reduction device according to a first embodiment of the present invention. In FIG. 1, reference numeral 2a denotes a netlister that creates a netlist by referring to various libraries and external inputs based on the logical connection information 1, and 3a denotes a cell reduction that is responsible for cell reduction, which is one function of the netlister 2a. Department,
Reference numeral 6 denotes a mapping library that describes a rule of grouping in which macro cells can be grouped in order to perform cell reduction and in what case, and which macro cells can be replaced. In addition, the same reference numerals in FIG. The corresponding parts are shown.

As described above, the present invention has the mapping library 6 for providing the grouping rules to the cell reduction unit 3a for performing the cell reduction.
FIG. 2 shows an example of the mapping library 6. In FIG. 2, a rule R1 is a macro cell having a flip-flop (FF4) function of latching 4-bit data with a plurality of macro cells having a flip-flop (FF1) function of latching 1-bit data,
A flip-flop (FF) that latches 8-bit data
The expression indicates that the macro cell having the function of 8) can be replaced. The rule R2 indicates that the macro cell CO
The equation defines that the macro cell SCAN1 can be formed by the NBI1 and the LATCH1. In rule R3, 2
Flip-flop (FF) that latches bit data
It is defined that the macro cell having the function 2) is not to be subjected to cell reduction, and various definitions for controlling the cell reduction can be made in the mapping library 6. Such a rule is mapped to the mapping library 6
It is possible to freely control the cell reduction by defining.

Next, the grouping performed by the cell reduction device will be described with reference to FIG. In FIG. 3A, reference numerals 10 and 11 denote macro cells having a flip-flop function for commonly inputting a clock signal CLK. A data signal DATA is input to the D input of the flip-flop of the macro cell 10, and the macro cell 10 1
The D input of the flip-flop 1 is connected to the Q output of the flip-flop of the macrocell 10. 12,1
Numeral 3 denotes a macro cell having a flip-flop function, to which the inverted logic of the clock signal CLK is commonly input via a NOT gate 16.
The Q inputs of the flip-flops of the macro cells 11 and 12 are connected to the D inputs of the macro cells 2 and 13, respectively.

When the cell reduction unit 3a recognizes the circuit shown in FIG. 6A based on the logical connection information 1, the macro cells 10 to 13 are grouped as macro cells to which the same clock signal is input. Then, the number of stages of the macro cell until reaching the clock input terminal of each macro cell is assigned as a weight. For example, group 14
, And the flip-flop to which the group 15 belongs is weighted such that the number of macrocells is two.

In FIG. 3B, reference numerals 20 and 21 denote macrocells having the function of a flip-flop of the same type CELL1, and reference numeral 22 denotes a macrocell having the function of a flip-flop different from the macrocells 20 and 21. A signal line 24 is commonly connected to the data input terminals of the flip-flops of the macrocells 20 to 22, and a signal line 25 is commonly connected to the clock input terminal. The data DATA is commonly connected to the macrocells 20 to 22. And a clock signal CLK.

When the cell reduction unit 3a recognizes the circuit shown in FIG. 6B based on the logical connection information 1, the macro cells 20 to 22 are grouped as macro cells to which the same clock signal is input. Then, the type of each macro cell is assigned as a weight. That is, since the macro cells 20 and 21 are the same cell CELL1, 1 is assigned as a weight, and the macro cell 22 is CELL2, so that 2 is assigned.
Is assigned as a weight.

When the cell reduction unit 3a performs grouping, those having exactly the same weight are regarded as the same group. Therefore, for example, the macro cells 20 and 21 form a group 23, but the macro cell 22 does not belong to the group 23.

Next, cell reduction using a mapping library in the cell reduction device will be described with reference to FIG. FIG. 4 is a flowchart showing a cell reduction of a macro cell for inputting a clock input signal, which is performed with reference to a mapping library.

First, in step S1, logical connection information 1 is input. Next, the mapping library 4 is input as to which macro cells can be grouped, in which case they can be grouped, and which macro cells can be replaced (step S2). Then, in step S3, the cell reduction unit 3a searches for a clock input signal for each macro cell in the logical connection information 1.

Next, in step S4, the cell reduction 3a groups macro cells having the same clock-system input signal based on the search performed in step S3. Then, each macro cell is weighted as described above according to the rules specific to the cell reduction unit 3a (step S5). Based on this weighting, the cell reduction unit 3a further proceeds to group the macro cells (step S6).

Next, in step S7, the cell reduction unit 3a selects one group to be processed from a plurality of grouped groups. Then, by referring to the rules of the mapping library 6, it is examined whether there is any macro cell that satisfies the replacement rule in the group (step S8). If there is no rule that satisfies the rule, the grouping of the group is canceled in step S9, and the process returns to step S7. If there is a rule that satisfies the rule, the process proceeds to step S10, and the macro cell is replaced / erased according to the replacement rule in the mapping library 6.

In step S11, it is determined whether or not replacement of all groups has been completed. If there is a group that has not been replaced, the process returns to step S7 to repeat the above operation. Finally, a report on replacement / erasure is output to the input / output means 7 such as a CRT, and the operation of cell reduction is completed (step S12).

An example in which cell reduction is performed using the mapping library 6 will be described with reference to FIGS. In FIG. 5, reference numerals 30 to 33 denote macrocells having the same type of 1-bit flip-flop function, reference numerals 34 to 37 denote data input terminals of the flip-flops of the macrocells 30 to 33, and reference numeral 38 denotes a clock input terminal. Here, it is assumed that each flip-flop of the four macro cells 30 to 33 has the function of the flip-flop FF1. First, the connection is analyzed from the input side, and the clock signal 38 is output from the macro cells 30 to 3.
Recognizing that the macro cells are common to the three macro cells, the four macro cells are grouped as one group. According to the rule R1 described in the mapping library 6 of FIG.
It can be replaced with one macro cell having the function of F4 or 8-bit flip-flop FF8. The cell reduction unit 3a can replace the four flip-flops with the macrocell 39 having the function of one 4-bit flip-flop by adopting the rule R1.

As a result, the number of macro cells is reduced from four to one, the number of BCs at the time of layout is reduced, and the number of pin pairs is reduced by three by using one clock input terminal.

In the above example, an example has been described in which a plurality of macro cells having the function of a 1-bit flip-flop are replaced with a macro cell having a function of one multi-bit flip-flop. Can be realized by a similar method.

Next, a second embodiment will be described.

In the first embodiment, four macrocells having a 1-bit flip-flop function are replaced with one macrocell having a 4-bit flip-flop function because they have a common clock input signal. However, according to the present invention, it is possible to apply a different weighting to the grouping to be replaced than in the first embodiment. FIG. 8 is a circuit diagram showing the configuration of a logical hierarchy before and after performing cell reduction by weighting.

In FIG. 8A, reference numerals 41 to 46 denote macrocells having the function of the same type of D flip-flop;
a and 47b are clock signals CLK1 and CLK2, respectively.
, 48a and 48b are signal lines for transmitting data DATA1 and DATA2, respectively, 49 is a signal line for transmitting a reset signal RESET, 50 is NA
This is a macro cell having an ND gate function. The clock signal CLK1 is input to the macro cells 41 to 45 through the signal line 47a. The macro cell 46 has a signal line 4
The clock signal CLK2 is input through 7b. The reset signal RESET is commonly input to each of the macro cells 41 to 46.

The data DATA1 is input to the macro cell 41 via the signal line 48a, and the Q output of the flip-flop of the macro cell 41 is input to the D input of the flip-flop of the macro cell 42. The Q output of the flip-flop of the macro cell 43 is input to the D input of the flip-flop of the macro cell 43, and the Q output of the flip-flop of the macro cell 43 is input to the D input of the flip-flop of the macro cell 44 . The Q output of the flip-flop of the macro cell 44 is input to one input terminal of the NAND gate of the macro cell 50,
The output terminal of the D gate is connected to the D input of the macro cell 45.

In this case, there are six D flip-flops. However, considering, for example, clocks of clock signals, commonality of reset signals, and short distance between macro cells as weighting conditions, the macro cells 41 to 44 are the same. Grouped as having weight. By referring to the mapping library based on the grouping result, as shown in FIG. 8B, the group is replaced with one serial-in-parallel-out 4-bit shift register.
Also in this example, both the number of BCs and the number of pin pairs can be reduced by the replacement, and the speed of data transmission between the flip-flops 41 to 44 can be increased. In this example, the macro-cells closer to each other are preferentially grouped. Conversely, if the macro-cells are farther apart, grouping is preferentially performed (common clock-related signals) to obtain a circuit that can be easily controlled in timing. it can.

FIGS. 6 and 7 are flowcharts showing the cell reduction of a macro cell performed by weighting and referring to a mapping library. The operations of steps S21 to S24 are performed in the same procedure as steps S1 to S4 shown in FIG. 4 of the first embodiment. Step S
At 25, it is determined whether or not a grouping rule (weighting) is designated from outside. When the grouping rule is not input from outside, the process proceeds to step S26,
The mapping rules are read from the mapping library 6, and the process proceeds to step S28. If a mapping rule is to be input from outside, the mapping rule is input using the input / output means 7 such as a keyboard in step S27. Then, in step S28, the cell reduction unit performs weighting according to the mapping rule, and in step S29, performs macro cell grouping in consideration of the weighting. The replacement performed in the following steps S30 to S35 is described in steps S7 to S7 shown in FIG.
This is performed in the same procedure as in step S12.

As described above, by inputting the mapping rule from the outside, it is possible to selectively use the preferential grouping according to the distance in accordance with the situation.

Next, a third embodiment will be described.

In the first and second embodiments, a plurality of macro cells having the function of a 1-bit flip-flop are replaced with one macro cell having the function of a multi-bit flip-flop. According to the present invention, it is not always necessary to substitute one macro cell. The user can recognize the content of the grouping, the macrocell after the replacement, and the effect of the replacement, and can select the content of the grouping suitable for the needs from among them. The function of providing information on the group of macrocells and the group of macrocells, and the numbers of BCs and pin pairs, and enabling selection of any of them will be described below. Hereinafter, the above function is referred to as a grouping content selection function.

In FIG. 11, reference numerals 60 to 67 denote macrocells having the same type of flip-flop FF1. Reference numeral 68 denotes a signal line for transmitting the clock signal CLK. Actually, eight macro cells 60 to 67 are connected to the signal line 68.
And are connected in parallel so as to commonly input a clock signal CLK. These macrocell groups are shown in FIG.
By applying the rule R1, the two macro cells having the function of the 4-bit flip-flop FF4 or the one having the function of the 8-bit flip-flop FF8
It can be seen that replacement can be performed by the macro cells.

The contents of the two types of grouping and replacement,
Furthermore, for a total of three cases without replacement, the BC
Calculate the number and the number of pin pairs. The change in the number of pin pairs
It can be obtained by comparing the logical connection information of the groupable macro cell group before replacement with the logical connection information of the replaced macro cell. The change in BC number can be obtained from the BC number description section of the macro cell library. Table 1 shows an example of the BC number description section of the macro cell library.

[0050]

[Table 1]

Next, a list of groupable macrocells is displayed on, for example, the CRT of the input / output means 7, and further indicating what kind of macrocell can be replaced, and the change in the number of BCs and the number of pin pairs when the macrocell is replaced. Table 2 shows an example.

[0052]

[Table 2]

The operator selects a replacement method suitable for the needs from these, and designates the replacement method using a keyboard or a mouse. Table 2 is an example of a grouping content selection screen for the groupable macro cells in FIG. Table 2
In, the user has selected to replace eight FF1s with one FF8. Then, finally, the cell reduction unit replaces the macro cell according to the method selected by the user.

Finally, a fourth embodiment will be described.

In the first embodiment, since the grouping replacement is performed without considering the maximum fan-out number of each macro cell, there is a risk that a fan-out check error occurs. In the following, a description will be given of a function of performing a fan-out adjustment when a fan-out check error occurs after replacing a macro cell, replacing the macro cell with a macro cell of the same type having high drivability and repeating the process until the fan-out limit is satisfied. Hereinafter, the above function is referred to as a fan-out adjustment function.

FIG. 12A shows a macrocell having the function of a 4-bit flip-flop obtained by using the grouping permutation according to the present invention. 70 is a macrocell having the function of a 4-bit flip-flop FF4S;
Is one of the output pins of the flip-flop of the macrocell 70. In FIG. 12A, a plurality of paths are branched from the output pin 71. First, the cell reduction device obtains the number of fan-outs for each pin of the replaced macro cell from the logical connection information 1. The fan-out number of the output pin 71 of the macro cell 70 is FO.

Next, the maximum fan-out number f of the output pin 71 of the macro cell 70 as information of the 4-bit flip-flop FF4S from the macro cell library 5 shown in FIG.
Ob1 is obtained. Table 3 is an example of the maximum fan-out number description section in the macro cell library. Here, fob1 <
It is assumed that FO <fob2 and foc <FO.

[0058]

[Table 3]

Next, the maximum fan-out number fob1 is compared with the actual fan-out number FO. Here, fob1 <F
The result is O, which indicates that the macro cell 70 needs to be replaced with a macro cell having higher drivability than the 4-bit flip-flop macro cell FF4S and having the same function. The macro cell library 5 is searched for a macro cell that meets the conditions. In the example of Table 3, FF4W
Is fob2> FO, which satisfies the condition. Finally FF4S
Is replaced with FF4W. FIG. 12B shows an example in which the fan-out adjusting function is applied to FIG. FIG. 12 (b)
In the figure, 72 is a macro cell having the function of a 4-bit flip-flop FF4W, and 73 is one of the output pins of the macro cell 72. The fan-out number for the pin 73 is FO like the fan-out number for the pin 71 in FIG.
Is the maximum fan-out number fob2> FO, and no fan-out check error occurs.

In the above example, a case has been described in which a macro cell having the same function as that of a macro cell in which a fan-out check error occurs and having higher drivability is described in the macro cell library. The case where such a macro cell is not described in the macro cell library will be described below.

FIG. 13 shows a macrocell having the function of an 8-bit flip-flop obtained by using the grouping permutation according to the present invention. Reference numeral 80 denotes a macro cell having the function of the 8-bit flip-flop FF8, and reference numeral 81 denotes one of the output pins of the macro cell 80. The number of fan-outs of the output pin 81 is FO. Cell reduction unit 3a
Is the output pin 81 of the macrocell 80 having the function of the 8-bit flip-flop FF8 from the macrocell library 5.
To obtain the maximum fan-out number foc. Next, the maximum fan-out number foc is compared with the actual fan-out number FO. Here, foc <FO, and it is necessary to replace a macro cell having higher drivability than the 8-bit flip-flop FF8 and having the same function. However, such a macro cell is not described in the macro cell library 5. In this case, the cell reduction device displays the grouping content selection screen again. However,
Specifying that a fan-out check error will occur when replacing with FF8, and prompting the user to perform grouping replacement by another method. Table 4 shows a grouping content selection screen in the case where a macro cell having the same function as a macro cell in which a fan-out check error occurs and having higher drivability is not described in the macro cell library.

[0062]

[Table 4]

[0063] was treated so that the error does not occur with respect to the number of fan-outs in the previous example, by the same process, file
It is possible to prevent the occurrence of a run-out capacity error .

[0064]

As described above, according to the cell reduction device of the first aspect of the present invention, (b) at least a rule for replacing a grouped macro cell with another macro cell described in a macro cell library is described. In the cell reduction unit, a plurality of macro cells corresponding to the logical connection information are grouped according to a predetermined rule, and then, by referring to the mapping library, the grouped macro cells are stored in the macro cell library. Since the described macro cell is replaced with another described macro cell, there is an effect that cell reduction that can reduce the area and the number of wirings of a plurality of macro cells can be performed. In addition, cell reduction section
Of the macro cells corresponding to the logical connection information
Macro cells that input the same clock input signal
Group according to the rules for grouping as a group.
Replace the pinged macro cell, so the same clock
By integrating macro cells that input system input signals,
A cell that can reduce the cross-cell area and the number of wires
There is an effect that reduction can be performed.

According to the second aspect of the present invention, the cell reduction unit includes a plurality of macro cells.
Weighting the macro cells in consideration of the
According to the rules for grouping while taking into account
Replace the grouped macro cells, so the macro
Cell relationships can be reflected in cell reduction.
There is an effect that can be cut.

According to the third aspect of the present invention, the grouping in the cell reduction unit is performed.
At the time, group of macro cells, group
Macro cell group after macro
Displays crosscell information and allows grouping
Group to be replaced can be specified from among various macro cell groups
Therefore, substitutions such as reduction of macro cell area and number of wiring
Can be replaced in consideration of the results
It is said that cell reduction suitable for the circuit can be performed
Has the effect.

[0067]

[0068]

[0069]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cell reduction device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a mapping library illustrated in FIG. 1;

FIG. 3 is a diagram for explaining grouping in the first embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure for performing cell reduction using a mapping library according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of a logical hierarchy before and after cell reduction according to the first embodiment of the present invention.

FIG. 6 is a flowchart showing a first half of a procedure for performing cell reduction using a mapping library according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing a latter half of a procedure for performing cell reduction using a mapping library according to a second embodiment of the present invention;

FIG. 8 is a diagram showing an example of a logical hierarchy before and after cell reduction according to a second embodiment of the present invention.

FIG. 9 is a flowchart showing a first half of a procedure for performing cell reduction using a mapping library according to a third embodiment of the present invention.

FIG. 10 is a flowchart showing a latter half of a procedure for performing cell reduction using a mapping library according to a third embodiment of the present invention.

FIG. 11 is a diagram showing an example of a logical hierarchy before and after cell reduction according to a third embodiment of the present invention.

FIG. 12 is a diagram showing an example of a logical hierarchy after cell reduction according to a fourth embodiment of the present invention.

FIG. 13 is a diagram showing another example of the logical hierarchy after cell reduction according to the fourth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional cell reduction device.

FIG. 15 is a diagram showing an example of the cell reduction library shown in FIG.

FIG. 16 is a diagram showing an example of a logical hierarchy before and after performing a conventional cell reduction.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logical connection information 2, 2a Netlister 3, 3a Cell reduction part 4 Cell reduction library 5 Macro cell library 6 Mapping library 7 Input / output means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-158571 (JP, A) JP-A-3-276375 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 27/04

Claims (3)

(57) [Claims] 1. A macro cell library describing a plurality of macro cells, and (b) a rule for replacing at least the grouped macro cells with other macro cells described in the macro cell library. A mapping library, and (c) a plurality of macro cells corresponding to the logical connection information,
The macrocells are grouped according to a predetermined rule that defines the types of macrocells that can be grouped and the cases where grouping is possible, and then, with reference to the mapping library, the grouped macrocells are described in the macrocell library. And a cell reduction unit for replacing the macro connection with another macro cell , wherein the predetermined rule is associated with the logical connection information.
The same clock input signal of multiple macro cells
Group input macro cells as the same group
Cell reduction device , including rules to do . 2. The method according to claim 1, wherein the predetermined rule includes a plurality of macro cells.
Weighting the macro cell in consideration of the correlation of
Rules for grouping while taking
No cell reduction apparatus according to claim 1. 3. A glue in the cell reduction section.
When pinging, macro cells that can be grouped,
The macrocell group after looping and the macrocell group
While displaying the information of each macro cell,
Glue to be replaced from the loopable macro cell group
The cell reduction device according to claim 1, wherein a loop can be specified .