JP3192913B2 - YUV / RGB converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inputting a plurality of different formats of YUV format data,
The present invention relates to a YUV / RGB converter for converting data into a format.

[0002]

2. Description of the Related Art Generally, MPEG video decoders and CDs are used.
In many cases, RGB data is transmitted as output data from the -G decoder, but the luminance signal Y and the color difference signal U (B
−Y) and V (R−Y) in the YUV format may be output. Normally, when RGB data is input, the input RGB data is converted into a luminance signal and a chrominance signal in a matrix circuit in the RGB encoder, but the YUV data is converted into a luminance signal and a chrominance signal as described above. Conventionally, when such YUV data is input because it is composed of signals, it is sufficient to perform the processing without conversion by a matrix circuit.

In addition, MPEG video decoders and CD-G
When an OSD signal for displaying characters or the like is inserted into video data from a decoder, an OSD signal is conventionally inserted into a signal obtained by adding a luminance signal and a chrominance signal.

[0004]

Conventionally, as described above, the MPEG video decoder and the CD-G decoder
There was no need to perform any conversion when UV format data was input. However, when inserting an OSD signal into such video data, after adding a luminance signal and a chrominance signal,
Since an SD signal is inserted, only colors having a luminance component of black and white can be displayed, and so-called color character display cannot be performed. Of course, it was possible to forcibly perform color display, but in this case, it was very difficult to adjust the phase of the color signals, and the circuit had to be complicated.

[0005] Therefore, the data of YUV format is once converted into RGB data.
It is conceivable to convert the data into data and insert an OSD signal corresponding to RGB in this state. However, in the YUV format data, Y, U, and V data are not multiplexed in a first format (hereinafter, Y-format). U-V data),
A second format in which U and V data are multiplexed (hereinafter referred to as Y-UV data), and a third format in which all Y, U and V data are multiplexed (hereinafter Y-UV data) There are a plurality of different formats. Therefore, in order to be able to cope with any of these formats, a complicated circuit configuration has to be adopted.

[0006]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a data input terminal capable of inputting a plurality of different formats of YUV format data, and a YUV format data input to the input terminal. A multi-stage delay circuit for sequentially delaying, a synthesizing circuit for synthesizing each data of YUV obtained through the delay circuit to generate each data of RGB, and inputting a switching signal corresponding to the plurality of formats; An identification circuit that identifies which format the data is; a counter that starts counting in response to a blank signal indicating the start of input data; and an output circuit of the identification circuit that is inserted between the delay circuits of the plurality of stages. And a plurality of selectors for selecting which output of the delay circuit is to be sent to the next-stage delay circuit in accordance with the contents of the counter. Y of the scan that has not been formatted
It is characterized in that both UV format data and multiplexed YUV format data can be converted into RGB data.

Further, the present invention further comprises a delay circuit for delaying each of the RGB data output from the synthesizing circuit, wherein a data in a format in which all the YUV data are multiplexed is input. Only the delay circuit at the subsequent stage of the synthesizing circuit is bypassed. In the present invention, the data input terminal is RG
B data can be input, and RG is used as the switching signal.
When a switching signal indicating the B data is input, each of the YUV data obtained through the delay circuit is output as it is, bypassing the synthesizing circuit.

[0008]

According to the present invention, a plurality of stages of delay circuits for sequentially delaying input YUV format data are provided, and a selector is inserted between these plurality of stages of delay means. According to the output of the identification circuit for identifying the format and the contents of the counter that starts counting in response to the blank signal indicating the start of the input data, the output of which delay unit is sent to the delay unit of the next stage is selected. Therefore, when the unmultiplexed YUV format data of the first format is input, the input YUV data is simply delayed and output as it is, and the multiplexed second and third data are output. When the YUV format data of the input format is input, the input YUV
The data is demultiplexed, and each of the Y, U, and V data is output. These data are converted into RGB data by the combining circuit.

[0009]

FIG. 6 shows a YUV / R as an embodiment of the present invention.
FIG. 1 is an overall block diagram of a digital RGB encoder LSI1 including a GB converter. Reference numerals 2, 3, and 4 denote video data input terminals for inputting a plurality of different formats of YUV format video data or RGB video data from an MPEG decoder or a CD-G decoder. , 5, and 6 are switching signal input terminals for inputting 2-bit switching signals SEL1 and SEL2 corresponding to a plurality of formats of YUV format data, and 7 is a blank signal input for inputting a blank signal BLANK representing the existence period of input video data. A terminal 8 is a YUV for converting the YUV format video data input to the input terminals 2, 3, and 4 into RGB 8-bit video data.
/ RGB converters, 9, 10, and 11 denote 1-bit OSDRGB data OSR, OSG, and OSD as OSD signals.
B, an OSD signal input terminal for inputting B, an OSD blank signal input terminal 12 for inputting an OSD blank signal OSBLK indicating an existence period of the OSD signal, a plurality of RGB levels set in advance, and a YUV / RGB converter 8 RGB video data and OSDRGB data and an OSD blank signal to be input are input. When there is no OSD signal, converted RGB data and RGB data are output, and when there is an OSD signal, settings corresponding to the OSD signal are made. OSD signal insertion circuit for outputting RGB data
Reference numeral 4 denotes a matrix circuit that converts the RGB data output from the OSD signal insertion circuit 9 into digital data representing a luminance signal and a chrominance signal.

Reference numeral 15 denotes a burst signal generation circuit, 16 denotes a luminance signal processing circuit, 17 denotes a color signal processing circuit, and 18 and 1
9 is a DA converter, 20 is a timing generation circuit,
Reference numerals 2, 23, 24, and 25 denote an external subcarrier clock FSCIN, a horizontal synchronization signal HSYNC, a composite synchronization signal CSYNC, a color signal / composite video signal switching signal CCSEL, and an external subcarrier clock FSCIN, respectively.
This is a signal input terminal for inputting a system clock signal CLKIN having a frequency four times that of the above.

FIG. 1 shows YUV / RGB in this embodiment.
FIG. 3 is a circuit diagram showing a specific configuration of the converter 8, wherein 30 and 31 are D flip-flops for inputting 2-bit switching signals SEL1 and SEL2, respectively, and 32 is a D flip-flop 30;
31 and decode signals DCS0 to DCS
S3 is a decoder that outputs S3, and these constitute an identification circuit that identifies the format of the input data. Then, the switching signals SEL1 and SEL2 become “0”.
When the data format is "0", "01", "10", or "11", the data formats correspond to RGB data, YUV data, YUV data, and YUV data, respectively.
Decode signals DCS0, DCS1, DCS2, DCS3
Are respectively output.

Reference numeral 33 denotes a 2-bit counter which detects a falling edge of the input blank signal BLANK.
By being reset by the output of the flip-flop 34, counting is started in synchronization with the fall of the blank signal BLANK, and the count contents are decoded by the decoder 35. 36, 37, 38
Are an R combining circuit, a G combining circuit, and a B combining circuit that input each data of Y, U, and V and combine each data of R, G, and B according to a predetermined arithmetic expression. A three-stage D flip-flop 360, 36
1, 362 and a G synthesizing circuit 3
7 and an input terminal 3, a delay circuit composed of three stages of D flip-flops 370, 371 and 372 is arranged.
A delay circuit including three-stage D flip-flops 380, 381, and 382 is arranged between the B combining circuit 38 and the input terminal 4. Then, between the D flip-flops constituting these delay circuits, in order to select which output of the D flip-flop is to be sent to the next D flip-flop in accordance with the decode signal from the decoder 32 and the decoder 35. Selectors 363, 364, 373,
374 and 384 are inserted. Each of these selectors has a D flip-flop 361, 362, 3
Outputs of 71, 372 and 382 are fed back.

Further, a selector 366, a D flip-flop 367, and a selector 368 are sequentially connected between the R synthesizing circuit 36 and the R data output terminal 365. Similarly, the G synthesizing circuit 37 and the G data output terminal are connected. A selector 376, a D flip-flop 377, and a selector 378 are also connected between the terminals 375 in order. A selector 386, a D flip-flop 387, and a selector 388 are also connected between the B synthesizing circuit 38 and the B data output terminal 385. It is connected. The D flip-flops and counters all operate in synchronization with the same clock signal CLKIN.

Hereinafter, the operation of this embodiment will be described in detail.
First, when YUV data of the first format is input, "01" is set as the switching signals SEL1 and SEL2.
Is input, the decoder 32 outputs the decode signal DC
S1 is output. When this signal DCS1 is output,
All selectors 363 and 36 inserted in the delay circuit stage
4, 373, 374, and 384 select the output of the preceding delay circuit in each of the delay stages of YUV, so that the Y, U, and V data input to the input terminals 2, 3, and 4 are all three stages. Delayed by three clocks by the delay circuit,
G and B are input to the synthesis circuits 36, 37 and 38.

In this case, the selectors 366, 37
6, 386 select the output of each synthesis circuit and
8, 378 and 388 are the D flip-flop 36 immediately before.
7, 377 and 387 are selected.
65, 375, and 385 include synthesis circuits 36, 37, and 38, respectively.
, The data obtained by delaying the R, G, and B data output by one clock, respectively, are output.

On the other hand, when RGB format data is input, "00" is input as switching signals SEL1 and SEL2.
Is output. When this signal DCS0 is output, all the selectors 363, 364, 3
73, 374, and 384 select the output of the preceding delay circuit in each of the RGB delay stages as in the case of the YUV data, so that R and G input to the input terminals 2, 3, and 4, respectively. , B data are all delayed by three clocks by a three-stage delay circuit. However, in this case, the selectors 366, 376, and 386 select the inputs, not the outputs, of the R, G, and B combining circuits 36, 37, and 38.
This input is a D flip-flop 367, 377, 387
Is applied to Then, the selectors 368, 378, 38
8 selects the outputs of the D flip-flops 367, 377, 387, so that the output terminals 365, 375, 385
In the end, R, G, input to the input terminals 2, 3, 4
Each data of B is output after being delayed by four clocks.

Next, when the multiplexed Y-UV data of the second format is input, the Y data is applied to the input terminal 2 and the UV data obtained by multiplexing the U data and the V data is input to the input terminal 4. Is input to Then, “10” is input as the switching signals SEL1 and SEL2, and the decoder 32 outputs the decode signal DCS2. When this signal DCS2 is output, the selectors 363 and 364 among the selectors inserted into the delay circuit stage select the outputs of the D flip-flops 360 and 361 of the preceding stage, respectively, and the selector 373 sets the D flip-flop to which the UV data is input. Since the output of the loop 380 is selected, the connection state finally becomes as shown in FIG. Hereinafter, the operation will be described in detail with reference to the timing charts of FIGS.

The input Y data is delayed by one clock as shown in FIG. 4A by a D flip-flop 360 to become a, and is further shown by two subsequent D flip-flops 361 and 362 as shown in FIG. Thus, the signal is delayed by a total of three clocks, and the synthesis circuits 36, 37,
Sent to The counter 33 has a blank signal BLANK.
Counting is started in response to the falling edge of FIG.
Since the number of bits is 2 bits, the count content cnt is “0”, “1”, “2”,
"3" is sequentially repeated. And selectors 374, 38
4 are the D flip-flops 371 and 171 only when the content cnt of the counter 33 is an odd number of “1” and “3”, respectively.
380 output is selected, and the content of the counter 33 is "0",
When the even number “2” is selected, the feedback output of the D flip-flops 372 and 382 at the subsequent stage is selected, so that the output d of the selector 374 is the count value of the multiplexed UV data c of FIG. Only when the count value is an odd number, only the U data is extracted as shown in FIG. 4, and when the count value is an even number, the extracted U data is held as it is. As the output e of the selector 384, only the V data when the count value is an odd number is extracted as shown in FIG. 4 from the multiplexed UV data b in FIG. Holds the extracted V data as it is. Accordingly, from the D flip-flops 372 and 382, as shown in FIGS.
FIG. 4 U in which data d and e of FIG.
Data and V data are output. The amount of delay of these U and V data is three clocks like Y data.

Finally, when inputting the multiplexed YUV data in the third format, the multiplexed YUV data is input to the input terminal 4.
The switching signals SEL1 and SEL2 are "11".
And the decoder 32 outputs a decode signal DCS3. When this signal DCS3 is output, all the selectors inserted in the delay circuit stage make selection according to the contents of the counter 33, and the connection state is substantially as shown in FIG. Hereinafter, the details of the operation will be described with reference to the timing charts of FIGS.

First, the selector 363 selects the output a of the preceding D flip-flop 360 only when the content cnt of the counter 33 is an odd number of "1" and "3".
When the even value of "0" or "2" is selected, the feedback output of the subsequent D flip-flop 361 is selected. Therefore, as shown in FIG.
Only the data is extracted, and when the count value is an even number, the extracted Y data is held as it is. The next selector 364 selects the output of the preceding D flip-flop 361 only when the content cnt of the counter 33 is an even number, and selects the feedback output of the succeeding D flip-flop 362 when the content cnt of the counter 33 is an odd number. As shown in FIG. 5, when the count value is an even number, Y data obtained by delaying the Y data b in FIG. 5 by one clock is selected, and when the count value is an odd number, the feedback output of the D flip-flop 362 is selected. Selected. Then, the data is further delayed by one clock by the next D flip-flop 362, and only the Y data as shown in FIG. 5 is demultiplexed and output. However, in this case, the output Y data is 4 times smaller than the input data.
Delayed by clock.

On the other hand, only when the content cnt of the counter 33 is an even number “0” or “2”, the selector
The output of the flip-flop 360 is selected, and "1",
If the odd number is "3", the subsequent D flip-flop 3
As shown in FIG. 5C, U and V data when the count value is an even number are taken out, and when the count value is an even number, the taken out data is taken out. It is kept as it is. Then, the data is further delayed by one clock by the next-stage D flip-flop 371 to obtain UV data e as shown in FIG. The next selector 374 selects the output of the preceding D flip-flop 371 only when the content of the counter 33 is “2”,
Otherwise, since the feedback output of the subsequent D flip-flop 372 is selected, its output f is, as shown in FIG.
Only the U data when the count value is “2” is extracted, and when the count value is other than “2”, the extracted U data
Data is retained. Then, the data is further delayed by one clock by the next-stage D flip-flop 372, and only U data as shown in FIG. 5 is obtained.

The selector 384 operates the D flip-flop 36 only when the content cnt of the counter 33 is "2".
Since the output of 0 is selected and the feedback output of the subsequent D flip-flop 382 is selected in other cases, the output g thereof is V when the count value is "2" as shown in FIG.
Only data is taken out, and when the count value is other than "2", the taken out V data is held. Then, the data is further delayed by one clock by the next-stage D flip-flop 382 to obtain only V data as shown in FIG.

However, in this case, similarly to the Y data, the U data and the V data are delayed by four clocks as compared with the input data. As described above, the demultiplexing of the YUV data is realized, but the delay amount of each of the obtained Y, U, and V data is four clocks, which is one clock longer than in the other formats. Stage selectors 368, 37
8, 388, D flip-flops 367, 378,
Each of the RGB synthesizing circuits 36, 3
Outputs 365, 375, 3 of output terminals 7, 38 as they are
85 to adjust the amount of delay.

After the RGB data is obtained as described above, these data are input to the OSD signal insertion circuit 13, where the RGB data input to the input terminals 9, 10, 11 are input.
The OSD signal corresponding to B is inserted based on the OSD blank signal. That is, when there is no OSD signal, YUV
The RGB data from the / RGB converter 8 is output as it is, and when an OSD signal exists, predetermined RGB data according to the content of the OSD signal is output. The RGB data is converted by the matrix circuit 14 into a luminance signal Y and a chrominance signal C, and the converted luminance signal Y
And the chrominance signal C are input to the luminance signal processing circuit 16 and the chrominance signal processing circuit 17, respectively.

The luminance signal processing circuit 16 receives a composite synchronizing signal CSYNC and a blank signal BLANK. The luminance signal processing circuit 16 synchronizes with the synchronizing signal based on a timing signal in the circuit. , Where it is converted to an analog signal and output. The burst signal generation circuit 15 is provided with a subcarrier clock FSCIN and a horizontal synchronization signal HSYN from outside.
C, a burst signal is generated from the system clock signal CLKIN and output to the color signal processing circuit 17. The color signal processing circuit 17 performs a process of adding the burst signal to the color signal C from the matrix circuit 14. Also, this color signal processing circuit 1
Reference numeral 7 has a function of switching and outputting a color signal and a composite video signal. When the switching signal CCSEL is at an H level, the switching signal CCSEL outputs a color signal to which a burst signal is added to the DA converter 19, and the switching signal CCSEL Is low, a luminance signal is further added to the color signal to which the burst signal has been added based on the composite blank signal BLANK and the timing signal to generate a composite video signal, and this signal is output to the DA converter 19. These signals are converted into analog signals by a DA converter and output.

As described above, the digital RGB encoding process is executed.

[0027]

According to the present invention, the circuit configuration of the YUV format data in a plurality of different formats, that is, the YUV format data in a non-multiplexed format and the YUV format data in a multiplexed format, is complicated. It can be converted to RGB data without any need. Further, it is possible to input RGB data by adding a small configuration with one LSI.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a YUV / RGB converter as an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration when inputting Y-UV data in the embodiment.

FIG. 3 is a circuit diagram showing a configuration when inputting YUV data in the embodiment.

FIG. 4 is a diagram showing a timing chart when inputting Y-UV data in the embodiment.

FIG. 5 is a diagram showing a timing chart when inputting YUV data in the embodiment.

FIG. 6 is an overall block diagram of a digital RGB encoder LSI including a YUV / RGB converter as an embodiment.

[Explanation of symbols]

 2, 3, 4 Data input terminal 5, 6 Switching signal input terminal 7 Blank signal input terminal 8 YUV / RGB converter 9, 10, 11 OSD signal input terminal 12 OSD blank signal input terminal 13 OSD signal insertion circuit 14 Matrix circuit 15 Burst signal generation circuit 16 Luminance signal processing circuit 17 Color signal processing circuit 18, 19 DA converter 32, 35 Decoder 33 Counter 36 R synthesis circuit 37 G synthesis circuit 38 B synthesis circuit 360, 361, 362, 367 D flip-flop 370, 371,372,377 D flip-flop 380,381,382,387 D flip-flop 363,364,366,368 selector 373,374,376,378 selector 384,386,388 selector

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/67

Claims (3)

(57) [Claims] 1. A data input terminal capable of inputting a plurality of YUV format data in different formats, a multi-stage delay circuit for sequentially delaying YUV format data input to the input terminal, and a delay circuit obtained through the delay circuit. A synthesizing circuit for synthesizing the respective YUV data to generate RGB data, an identification circuit for inputting a switching signal corresponding to the plurality of formats and identifying which format the input data is; A counter that starts counting in response to a blank signal indicating the start of data, and a counter that is inserted between the delay circuits of the plurality of stages and outputs any one of the delay circuits according to the output of the identification circuit and the content of the counter. A plurality of selectors for selecting whether to send the signal to a delay circuit of the next stage, and a Y signal of a format which is not multiplexed.
A YUV / RGB converter wherein both UV format data and multiplexed YUV format data can be converted to RGB data. 2. The YUV / RGB converter according to claim 1, further comprising a delay circuit for delaying each of the RGB data output from said synthesizing circuit, wherein all the YUV data are multiplexed. A YUV / RGB converter characterized in that a delay circuit at a subsequent stage of the synthesizing circuit is bypassed only when format data is input. 3. The YUV / RGB converter according to claim 1, wherein said data input terminal is capable of inputting RGB data, and said delay is provided when a switching signal indicating RGB data is input as said switching signal. A YUV / RGB converter characterized in that RGB data obtained through a circuit is output as it is, bypassing the synthesizing circuit.