JP3184380B2 - Interrupt control method and multitask system for implementing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control method for a multitask system requiring real-time processing, and to a multitask system for realizing the method.

[0002]

2. Description of the Related Art In a computer system that requires real-time processing, it is necessary to execute a program (hereinafter, internal processing) in synchronization with external processing (hereinafter, external processing). Therefore, the corresponding internal processing must be completed within the time allowed in the external processing. In order to satisfy this time requirement, when an external process requests execution of a new internal process whose time requirement is stricter than the currently executed internal process, the current internal process is temporarily interrupted and the new process is interrupted. Must be performed in advance.

Therefore, in order to enable such real-time processing by a computer, an interrupt processing mechanism of the computer is used to transmit a request for execution of internal processing from the external processing to the computer. Also,
As a method for giving priority to internal processing with strict time requirements, a preemptive method in which necessary internal processing is programmed as a task, and a priority is set for each task, and the CPU resources of the computer are allocated in the order of tasks having higher priority. A multitask control program that performs task switching is used based on a method of priority scheduling.

In a multitask control program,
Various functions such as task generation, suspension, resumption, termination, and priority change are usually provided in the form of subroutine calls or software interrupts (hereinafter, system calls). Each function is executed by calling them in a task or interrupt processing. Usually, when a system call is executed from a task, and as a result, a task switch to another task is required, a task switch process is executed at the end stage of the execution of the system call.

However, when the task switch processing is performed by the system call during the interrupt processing as in the case of the task, the remaining part of the interrupt processing is executed until the processing returns to the interrupt processing by the occurrence of the task switch again. In the worst case, there is a possibility that a task switch to return to the interrupt processing will not occur and the execution of the interrupt processing will not be continued. Further, while the interrupt processing is not completed, the computer may not accept an interrupt having a level equal to or lower than the interrupt request level, and may miss another request from the external processing.

In order to avoid such a problem, in a conventional multitask system requiring real-time processing,
If a system call is executed during interrupt processing, the task switch is not performed even if the task switch is necessary at that point in time, and the task switch is executed until the system call for task switch processing called at the end of this interrupt processing is executed. The switch is forbidden.

FIG. 3 shows a time chart of multiple interrupts in a multitask system requiring real-time processing. As shown in the figure, in the case of multiple interrupts in which a higher-level interrupt occurs during the interrupt processing, the task switch is completed at the end of the lowest-level interrupt processing after returning to the task after completing the high-level interrupt processing. The task switch needs to be executed by the system call for. As described above, a program that executes a system call in interrupt processing always returns control to the multitask control program at the time of termination, and a special procedure for performing a task switch is indispensable.

[0008]

However, in a multitask system requiring real-time processing, a special procedure for task switching is required at the end of interrupt processing as described above. As described above, there is a problem that interrupt control cannot be performed using a general type of interrupt processing in which the end of the processing is written by an interrupt return instruction.

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks and provides a multi-task system requiring real-time processing without requiring a special procedure for task switching at the end of interrupt processing. Is the interrupt processing written by the interrupt return instruction,
An interrupt control method capable of controlling an interrupt of a multi-task system for real-time processing is provided.

[0010]

In order to solve this problem, an interrupt control method according to the present invention is an interrupt control method in a multitask system that requires real-time processing . Execution ad
The interrupt is saved on the stack, and whether the interrupt is a multiple interrupt is determined. If the interrupt is not a multiple interrupt, the start address of the task switch process is set to the stack.
In the upper part of the execution address in the
After completion of the interrupt, whether the interrupt is a multiple interrupt
Regardless, the start instruction is returned by an interrupt processing return instruction.
The method is characterized in that control is transferred to the address stored at the top of the block .

Here, whether or not the interrupt is a multiple interrupt
Check whether the interrupt is being processed by referring to the flag.
The interrupt processing flag indicates that the interrupt is
Set when the task switch processing is not
Is reset at In addition, the task switch processing
The storage of the logical start address is executed prior to the execution of the interrupt .

Further, the multitask system according to the present invention comprises:
In a multitasking system that requires real-time processing , a stack that stores data in a last-in first-out manner,
In response to an interrupt request, the current execution address is
A first storing means for storing a click, a confirmation means for the interrupt to check whether multiple interrupts or, if the interrupt is not <br/> multiple interrupts, the first task switch process
Address on the stack above the execution address
Second storage means for storing in the second place, after completion of the interrupt
Regardless of whether the interrupt is a multiple interrupt or not.
The top of the stack is
And control means for transferring control to the address stored in the storage device .

[0013] Here, the confirmation means is in the process of interrupt processing.
Refer to the flag and execute the interrupt processing flag
Is set if the interrupt is not a multiple interrupt.
Reset in the task switch process.
Further, the second storage means may execute the interrupt before executing the interrupt.
Stand up and save the start address of the task switch process
You.

[0014]

【Example】

(Embodiment 1) An embodiment of an interrupt control method according to the present invention will now be described with reference to the flowchart of FIG.
This will be described in detail according to the system configuration diagram of FIG.

The computer of the system configuration diagram of FIG.
When an interrupt is received from the interrupt request signal line 73,
The current execution address and the status register value necessary for suspending and resuming normal processing are stored in a stack area (hereinafter referred to as a stack) 723.
The interrupt vector corresponding to the vector number is referred to by referring to an interrupt vector table 721 (hereinafter referred to as a vector table) existing in a specific area in the memory using an interrupt vector number (hereinafter referred to as a vector number) input from the IO through the bus 74 as a key. After the start address (in FIG. 7, the start address of the pre-interrupt processing) is obtained, the execution is shifted to this address, and so on. Therefore, the vector table 7
21 is registered with the start address of the interrupt process corresponding to each vector number in a format according to the hardware requirements before the execution of the program. Here, since the pre-interrupt processing is executed prior to the execution of the interrupt processing, the head address of the pre-interrupt processing is set in the vector table 72 in advance.
Register to 1.

When an interrupt occurs, execution proceeds to the pre-interrupt processing shown in FIG. 1 according to the above procedure.
At this stage, the stack 723, which is a first-in-first-out memory area of FIG. 7, which is normally used by the computer as a work space, has at least the minimum necessary for returning to the program before the interrupt by the interrupt return instruction after the interrupt processing is completed. , The program counter before interruption (hereinafter P
C) Execution address which is the value of 712 and status register 71
4 are stored. FIG. 6 shows the state of the stack being executed. At this stage, the stack is used up to the point a in FIG. Computer 71 (CPU)
Has a stack pointer (hereinafter referred to as SP) 713 in FIG. 7 in order to manage the used area of the stack, and the SP at this stage indicates the address of the point a.

In the pre-interrupt processing, first, a determination S1 of an interrupt processing to be executed as described below is executed (see FIG. 1). This process is performed in the following procedure.

(Determination of Interrupt Processing S1) In order to secure a work space required for pre-interrupt processing, the stack 7
23, a frame creation procedure S11 is performed. As a result of this processing, from the point a on the stack 723 in FIG.
Up to the point is secured as a frame 61. By securing the frame, the SP 713 moves to the point b, which is the upper end of the frame. A frame pointer (hereinafter referred to as FP) 62 for managing a used area in a frame as in SP713.
Create First, in order to store the current value of the register 711 used as the FP 62, the value is stacked on the stored register value area above the point b, and then the register assigned to the FP 62 is pointed to the lower point a of the frame. Is initialized to

In the register value storing procedure S12 in FIG.
All other registers 711 used in pre-interrupt processing
Are sequentially stored in the storage register value area of FIG.

Procedure S1 for obtaining start address of interrupt
No. 3 obtains the start address of the interrupt processing by adding the current execution address and the offset address value up to the interrupt processing obtained at the time of linking the execution object by program counter relative addressing or the like.

Procedure S for saving start address of interrupt processing
At 14, the obtained start address of the interrupt process is temporarily stored in a register or the like until the execution is shifted from the pre-interrupt process to the interrupt process.

After executing the above-described individual processing after obtaining the vector number, the processing jumps to the multiple interruption confirmation S2 in the jump processing S15. The processing below this can be described as a common procedure that does not depend on the vector number, and can be arranged as a program area on a memory as indicated by 722 in FIG.

(Multiple Interrupt Confirmation S2) As shown in FIG. 1, in the multiple interrupt confirmation S2, the return destination at the end of the interrupt processing in the case of the multiple interrupt and in the other case is switched. In the multiple interrupt flag confirmation procedure S21, an interrupt processing flag is confirmed to determine whether or not the multiple interrupt has occurred during the interrupt processing.

If the interrupt processing flag is not set, it is understood that this interrupt is not a multiple interrupt. In this case, in order to detect multiple interrupts occurring during this interrupt processing, an interrupt processing flag setting procedure S22 is performed, and as shown in FIG. 2, the task switch processing is performed by the last return instruction of the described interrupt processing. In order to shift the execution, the process branches to return destination change S3 after the interrupt processing.

If the interrupt processing flag is already set, the flow branches to a multiple interrupt processing branch S4. Following this procedure, the computer can be brought into a multiple interrupt enabled state as needed.

(Change of return destination after interrupt processing S3) FIG.
In the return destination change S3 after the interrupt processing, return destination change processing is executed such that execution is shifted to the task switch processing by the last return instruction of the interrupt processing as shown in FIG.
In the procedure S31 of loading the start address of the task switch process and the status register in the frame, the return destination of the interrupt return instruction is loaded on the point a in FIG. At this time, leaving the execution address of the task before the interrupt and the status register on the stack is
This is so that the task can be returned to the interrupted task by the task switch process. After this processing, in order to use the frame as a first-in first-out memory, a procedure S32 of moving the value of the FP 62 to the point d is executed. After execution of this procedure, an interrupt processing branch S4 is executed.

(Interrupt processing branch S4) The interrupt processing branch S4 executes processing for branching to an interrupt processing to be executed. The procedure S41 of loading the start address of the interrupt processing on the frame is already determined by the start interrupt processing determination S
The start address of the interrupt process obtained in step 1 and temporarily stored in a register or the like is stacked on point d of the frame indicated by FP 62 in FIG.

After this process, a procedure S42 for moving the value of the FP 62 to the point e is executed in order to use the frame as a first-in first-out memory.

In the register value recovery procedure S43, in order to make it appear that the interrupt processing of FIG. 2 has been executed virtually immediately after the interrupt, all the register values used in the pre-interrupt processing other than SP713 and FP62 are used. return.

In the frame deletion procedure S44, the current FP
The SP 713 is moved to the point e in FIG. 6 indicated by the value of 62. After that, since the FP 62 becomes unnecessary, the value of the register used for the FP 62 is recovered from the storage register value area of FIG. By executing the last return instruction S45, the start address of the interrupt process is fetched from the stack,
Execution is shifted to interrupt processing.

In the interrupt processing of FIG. 2 whose execution has been shifted, the highest address on the stack and the value of the status register are read by executing the interrupt return instruction at the end of this processing. Execution resumes at the value of. That is, in the case of an interrupt that is not a multiple interrupt, the top of the stack is the start address of the task switch process and the status register value at point d in FIG. It will return to processing. In the task switch process,
The interrupt processing flag is set when the task switch is executed.

On the other hand, in the case of multiple interrupts, the top of the stack is the execution address before the interrupt and the status register value at point a in FIG. 6, and the process returns to the low-level interrupt process in which the interrupt occurred.

FIG. 4 shows a time chart of the above-mentioned multiple interrupts according to the present embodiment.

(Embodiment 2) Another embodiment of the interrupt control method of the present invention will be described with reference to FIG.

In order to shift the execution to the interrupt processing after the execution of the pre-interrupt processing, a table of the start address of the interrupt processing (structure similar to the interrupt vector table) is separately created in the memory.

In the first embodiment shown in FIG. 1, the start address of the interrupt processing to be executed is obtained as a result of the determination S1 of the interrupt processing to be executed. In the processing decision S51, the identification number of each interrupt vector (interrupt processing) embedded as a direct value obtained in the procedure S513 is stored in the procedure S514.
To temporarily save to a register or memory.

In the subsequent interrupt processing branch S54, the start address of the interrupt processing is obtained by referring to the table in the procedure S541 using this identification number. This procedure includes:
A table is prepared in which the start addresses of the above-described interrupt processing are sequentially arranged in the memory, the start address of the table is added to the offset address obtained from the identification number, and the start address of the interrupt processing is obtained from the address of the addition result. Is read. Thereafter, execution is shifted to interrupt processing by a jump instruction S544.

In the multiple interrupt confirmation S2 of the first embodiment shown in FIG. 1, the multiple interrupt is determined by software using the interrupt processing flag. The multiple interrupt confirmation means S52 in FIG. 5 is an embodiment in the case where hardware such as an interrupt controller capable of confirming the occurrence of multiple interrupts is provided in the computer. First, the status of the interrupt controller is read (procedure S521), and from this status, it is checked in step S522 whether an interrupt lower in level than the current interrupt is waiting. If it does not exist, the interrupt is not a multiple interrupt, so the return destination change S3 after the interrupt processing is executed as in the first embodiment.

In this embodiment, before entering the first low-level interrupt processing, the pointer to the task switch processing and the status register are stacked on the stack in the pre-interrupt processing, but from the last low-level interrupt processing. Even if the pointer to the task switch process and the status register are stacked on the stack in the same pre-return process before the return process, the same effect as in the present embodiment can be achieved. Also, the flowchart of the pre-interrupt processing shown in the present embodiment is an example, and the present invention is not limited to this as long as the same function can be achieved. For example, if the multiple interrupt confirmation is executed first and the save / restore of registers and the like is minimized at the time of multiple interrupts, the processing at the time of multiple interrupts can be speeded up. Further, the pre-interrupt processing of the present embodiment may be realized by software or may be realized by hardware. Furthermore, it can also be realized by firmware combining hardware and software. Further, the present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0040]

As described above, according to the present invention,
In a multitasking system that requires real-time processing, the current execution address is
Save to stack and check if interrupt is multiple interrupt
Task switch processing when there are no multiple interrupts
Of the execution address in the stack.
At the top of the
Return order of interrupt processing regardless of whether it is a heavy interrupt
Control the address stored at the top of the stack.
Control, so if there are multiple interrupts, interrupt
It is possible to return to the previous processing and multiple interrupts
If not, the process can proceed to the task switch process.
This makes it possible to perform interrupt control written in the interrupt return instruction at the end of interrupt processing without requiring a special procedure for task switching at the end of interrupt processing. Became possible.

Recently, an interrupt program can be easily described in a high-level language. This is because the compiler compiles the subroutine declared to be the interrupt processing into the format shown in FIG.
Therefore, an interrupt processing program created in a high-level language can be used in a multitask system that requires real-time processing by applying the present invention.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a procedure of pre-interrupt processing according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a procedure of an interrupt process used in the embodiment.

FIG. 3 is a time chart of multiple interrupts of a multitask system that requires real-time processing.

FIG. 4 is a time chart showing multiple interrupts according to the embodiment.

FIG. 5 is a flowchart illustrating a procedure of pre-interrupt processing according to the second embodiment;

FIG. 6 is a diagram illustrating a usage state of the stack of FIG. 1;

FIG. 7 is a diagram for explaining the system of the present embodiment.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junji Yamada 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-5-120038 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) G06F 9/46 G06F 9/42

Claims (6)

(57) [Claims] An interrupt control method in a multitask system requiring real-time processing, wherein a current execution address is stacked in response to an interrupt request
Stored in the interrupt confirm whether multiple interrupts or, if the interrupt is not a multiple interrupts, Tasukusui
The start address of the switch process in the stack.
Stored above the row address, after the end of the interrupt, the interrupt
Regardless of whether or not the
Control transfers to the address stored at the top of the stack.
Interrupt control method, characterized in that to. 2. A method according to claim 1, wherein said interrupt is a multiple interrupt.
Is determined by referring to the interrupt processing flag.
The interrupt processing flag indicates that the interrupt is a multiple interrupt.
This is set when there is no
2. The interrupt control method according to claim 1, wherein the resetting is performed by resetting . 3. The start address of the task switch process.
3. The interrupt control method according to claim 1 , wherein the storing of the interrupt is performed prior to the execution of the interrupt. 4. In a multitask system requiring real-time processing , a stack for storing data in a last-in first-out manner and a current execution address in response to an interrupt request are stored in the stack.
First storing means for storing the interrupt in a memory , checking means for checking whether or not the interrupt is a multiple interrupt, and a task switch when the interrupt is not a multiple interrupt.
The start address of the switch process in the stack.
A second storing means for storing the upper row address, after completion of the interrupt, the interrupt multiple interrupts
Regardless of whether or not the
Control transfers to the address stored at the top of the stack.
A multitasking system comprising: 5. The apparatus according to claim 1, wherein said confirming means includes an interrupt processing flag.
The interrupt processing flag is set as described above.
Set when the interrupt is not a multiple interrupt, and
5. The multitask system according to claim 4, wherein the system is reset in the task switch process . 6. The interruption means according to claim 1 , wherein
Prior to execution, the start address of the task switch process
The multitasking system according to claim 4, wherein the multitasking system is stored .