JP3182621B2 - Test program monitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test program monitor for monitoring the execution state of a test program (hereinafter referred to as "TP") used for testing hardware input / output devices in a computer.

[0002]

2. Description of the Related Art FIG. 6 is a flowchart showing a processing procedure of a test program in a conventional monitor device.

In the conventional program processing, first, various hardware
A parameter setting process associated with the hardware input / output device is performed (step 61). Next, a hardware initialization process (step 62), a test process for actually testing the hardware (step 63), and a termination process for restoring the hardware state (step 64) are performed. The processing procedure from step 61 to step 64 is executed for each hardware input / output device.

[0004]

However, according to a series of program processing procedures shown in FIG. 6, when a specification of a hardware test itself is changed, a plurality of hardware input / output devices are provided. Due to the presence of the TP, it was necessary to execute the same processing procedure a plurality of times. For this reason, the program source code becomes enormous, and there is a disadvantage that maintainability is poor, for example, when an additional change occurs in each processing procedure, a change occurs in other processing procedures.

The present invention improves the maintainability so as not to affect other processes by making a process change such as performing a common process procedure for a plurality of hardware input / output devices together. It is an object to provide a test program monitor device.

[0006]

SUMMARY OF THE INVENTION The present invention provides an input / output device.
A monitor that monitors the execution status of the test program that performs the test.
In the program monitor for
Tests that store the individual parameters used for placement
Definition table, the test definition table and a plurality of input / output
Stores common parameters commonly used for force devices
Stored multiple phase definition tables and each table
It has a header table and a phase definition table and test
Specifying the phase definition table
Parameters in the test and individual parameters in the test definition.
Test program management means for instructing to sequentially perform program processing by referring to the
You .

[0007]

According to the present invention, a plurality of phase definition tables
Stores individual parameters used for different input / output devices
Common to multiple test definition tables and multiple input / output devices
Stores common parameters used for
While maintaining the flexibility of program processing for output devices
Perform appropriate program processing specific to each input / output device
be able to.

[0008]

FIG. 4 is a block diagram showing an overall configuration of a hardware device in which a test program monitor according to the present invention functions. A disk 42, a display 43, a keyboard 44, a memory 45, and a target input / output device 46 are connected to a processor 41 having a central processing (program execution) function via a bus 47. .

The disk 42 has an external storage function for storing programs, data, and the like. Display 4
Reference numeral 3 has a function of displaying a program execution process. The keyboard 44 has a data input function, and the memory 45 has a main storage function for storing programs and various arithmetic processing results. The target input / output (I / O) device 46 is an input / output device to be tested by a test program.

FIG. 5 is a diagram for explaining a test mode for the target input / output device, and shows each test processing unit. The test processing unit is composed of two types: a test 51 as a minimum unit for testing the apparatus, and a phase 52 as an arbitrary set of the tests 51.

FIG. 1 is a block diagram showing a schematic configuration of a TP-dedicated monitor according to an embodiment of the present invention in which the TP operates. The TP-dedicated monitor 10 is configured to exchange data with an externally provided disk 70, display 80, and keyboard 90. The TP dedicated monitor 10 includes a supervisor 11, a file management unit 12, a file driver 13, a command interpreter 14, a console management unit 15, a console driver 16, a program management unit 17, and a TP management unit 18. I have.

The supervisor 11 generates / manages / manages tasks.
It has a delete and hardware resource management function. The file management unit 12 has an information management function of an arbitrary file format. The file driver 13 executes writing and reading of programs and data with the disk 70. The command interpreter 14 analyzes and executes various commands. The console management unit 15 checks input or output data. The console driver 16 includes a display 80 and a keyboard 90.
The data input / output operation is performed between and. The program management unit 17 manages status information of each program process. The TP management unit 18 is provided according to the present invention, and
Performs execution management of P.

FIG. 2 is a diagram showing an interface between the TP management unit 18 and the TP shown in FIG. 1 and a standard configuration unique to the TP. The TP management unit 18 executes various processing steps with reference to the standard configuration 20 of the TP. Standard configuration of TP 2
0 is standard header table 21, parameter input processing 2
2. Parameter input processing 22 for performing input processing common to each phase / individual within a phase / individual test, initiator processing 23 for initializing hardware input / output devices,
It comprises a terminator process 24 for terminating the hardware input / output device and an actual test process 25.

FIG. 3 is a diagram showing the structure of a standard header table. The test form shown in FIG. 5, the standard structure unique to the TP shown in FIG. 2, and information for processing by the TP management unit 18 shown in FIG. Shows the structure of the table associated with. The standard header table has pointer (address) information for the TP management unit 18 to transfer control, and when executing the TP, the TP management unit 18 copies all the information and uses it as TP management information. The uppermost header table 31 is a pointer of the phase definition pointer table and a map table pointer for the memory map of the TP and the current number of the TP.
Stores the John number.

The phase definition pointer table 32 stores the number of phases and each phase constant table pointer. Further, the phase definition table 33 exists as many as the number of phases, and has the number of tests, a common parameter input processing pointer, and pointer data of each test definition table. The test definition table 34 includes a test pointer and a definition of parameter presence / absence, an individual parameter input processing pointer, a conversation presence / absence definition, a pre-conversation data table pointer, and a post-conversation data table pointer. Have. The map table 35 is a TP processing task pointer, T
P processing task ID data is stored.

The version number in the header table 31 is used as version data displayed on the display at the start of TP execution. The pre / post conversation data table in the test definition table 24 is conversation data for confirming to the TP operator at the start / end of the TP execution. The TP processing task pointer in the map table 35 is an area for storing an assigned address on the memory of the TP at the time of executing the TP. The TP processing task ID is a TP management number at the time of executing the TP.

Next, the operation of the TP will be described. First, the TP-dedicated monitor 10 shown in FIG. 1 is read from the disk 42 shown in FIG. The keyboard shown in FIG.
When the TP execution instruction is input from the command 44, the execution instruction is analyzed by the console driver 16, the console management unit 15, the command interpreter 14, the supervisor 11, and the program management unit 17 shown in FIG. It prompts the TP management unit 18 to execute a TP.

The TP management unit 18 reads out all information of the standard configuration 20 of the TP shown in FIG. Further, according to the execution instruction, referring to the information of the header table 31, the phase definition pointer table 32, the phase definition table 33, the test definition table 34, and the map table 35 of FIG. The parameter input processing 22, the initiator processing 23, the terminator processing 24 and the test processing 25 in the standard configuration 20 are executed as required.

When the execution of the phase 52 to the target input / output device shown in FIG. 5 is performed, the phase definition pointer table is read from the phase table pointer in the header table 31 of FIG. Referring to the phase definition pointer designated by the phase definition pointer table 32, the common parameter input processing pointer and the test definition pointer in the phase definition table 33 are referred to. And the like, and furthermore, the actual program is processed while referring to the test pointer and the like in the test definition table 34.

All of these series of processes are executed and terminated by the TP management unit 18 shown in FIG. 1 by a software interrupt with the standard configuration 20 of the TP shown in FIG. As described above, the processing of all TPs is performed by the text shown in FIG.
This is done by referring to the tables 31-34.

[0021]

As described above with reference to the embodiments, in the present invention, a program closely related to an individual input / output device is used.
A common program can be loaded to a plurality of related input / output devices.
Since it can be stored physically, professional
Unique to each I / O device while maintaining the flexibility of gram processing
Of being able to perform appropriate program processing
The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a TP-dedicated monitor according to one embodiment of the present invention.

FIG. 2 is a diagram showing an interface between a TP management unit and a TP according to the present invention and a standard configuration unique to the TP.

FIG. 3 is a diagram showing a configuration of a standard header table according to the present invention.

FIG. 4 is a block diagram showing the overall configuration of hardware on which the present invention functions.

FIG. 5 is a diagram showing a test mode for a target input / output device.

FIG. 6 is a flowchart showing a processing procedure of a test program in a conventional apparatus.

[Explanation of symbols]

 10 TP dedicated monitor 17 Program management unit 18 TP management unit

Claims (1)

(57) [Claims] In a test program monitor for monitoring the execution state of a test program for testing an input / output device, individual parameters used for the individual input / output devices are stored.
A plurality of test definition tables, and a common test definition table and a plurality of input / output devices.
Multiple phase definitions containing common parameters used
And defined table, and a header table that stores the each table, the phase definition table and said test definition table
While specifying, common parameters in the phase definition table
Data and individual parameters in the test definition
A test program monitor device comprising a test program management means for instructing to execute a program process .