JP3175394B2 - Nonvolatile semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor device having a structure having a floating gate and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor device capable of improving charge retention.

[0002]

2. Description of the Related Art Floating gates and control gates
EPROM or E ^Two Like a PROM
In semiconductor devices such as non-volatile memories, floating
Holding charge (generally electrons) on the ggate
This means that even if the power is turned off after writing data,
The feature is that the data does not disappear. Therefore, non-volatile
In a semiconductor device, the injection into the floating gate
So-called charge retention
Characteristics are an important point in device reliability.
You.

However, actually, the charges injected into the floating gate gradually escape to the control gate and the semiconductor substrate according to the heat release model.
The following three routes can be considered as a route through which electric charges leak. As a first route, there is a route that leaks to the substrate side through a gate insulating film between the floating gate and the semiconductor substrate. As a second route, there is a route that leaks from the side of the floating gate to the side of the control gate. As a third route, there is a route that leaks to the control gate side through the intermediate insulating layer.

Conventionally, in order to prevent the first leak, conditions for forming a gate insulating film (forming temperature, atmosphere, etc.)
Is being optimized. Further, in order to prevent the second leak, the sidewall formed on the side of the gate is optimized. Further, in order to prevent the third leak, as an intermediate insulating layer, O having excellent insulating properties and film forming properties is used.
ONO using a NO film (SiO ₂ / SiN / SiO ₂ )
The SiN film in the film is optimized. The use of the SiN film having a high dielectric constant in the intermediate insulating layer also has an advantage that the coupling ratio between the floating gate and the control gate can be increased.

[0005]

Although the above countermeasures against the first leak and the second leak have a relatively sufficient effect, it is apparent that the countermeasures against the third leak are insufficient. It has become to. In order to prevent leakage of electrons injected into the floating gate and improve charge retention, it is important to sufficiently prevent leakage through the intermediate insulating layer. Charge leak means a decrease in data retention in the case of a non-volatile memory.
Device failure. Therefore, there has been a demand for a material and a structure of the intermediate insulating layer that minimize charge leakage from the floating gate. The ONO film is formed of the third
There is a need for an intermediate insulating film that has a certain effect on the above-mentioned leakage countermeasures but has a lower leakage. In particular, the SiN film in the ONO film has a function of stopping contamination mobile ions such as Na ⁺ to some extent, but it is not at a sufficient level, and it is considered that contamination ions may enter from the upper surface of the floating gate, and the charge retention property is considered. (Data retention characteristics)
Could not be improved to some extent.

The present invention has been made in view of such circumstances, and in particular, a nonvolatile semiconductor which can effectively prevent charge leakage through an intermediate insulating layer, improve charge retention, and improve data retention characteristics. It is intended to provide a device.

[0007]

In order to achieve the above object, a nonvolatile semiconductor device according to the present invention has a control gate laminated on a floating gate via an intermediate insulating layer. Above intermediate insulation
The layers are a lower silicon oxide film and an intermediate silicon nitride film.
And a silicon oxide film on the upper layer.
Of the upper silicon oxide film and the upper silicon oxide film
Or the intermediate silicon nitride film contains phosphorus
It is characterized by having been done. Or floating
A control gate is placed above the gate with an intermediate insulating layer
In a stacked nonvolatile semiconductor device,
The phosphorus concentration in the roll gate is
Is formed above the control gate.
Higher than the insulating film side interface . Also on
In order to achieve the above object, a nonvolatile semiconductor device according to the present invention is provided.
The manufacturing method of the above, in the step of forming the intermediate insulating layer
The lower silicon oxide film and the upper silicon oxide
On both the silicon film and the intermediate silicon nitride film.
Characterized in that it is formed by containing In the present invention, the aspect of the region containing phosphorus is the lower layer silicon oxide.
Con film, intermediate silicon nitride film, upper silicon oxide
The silicon oxide layer on the lower side of the intermediate insulating layer having a multilayer structure with the film
Both the silicon film and the upper silicon oxide film, or
Is the above-mentioned intermediate silicon nitride film. Alternatively,
The phosphorus concentration in the roll gate is
Is formed above the control gate.
Higher than the insulating film side interface.

[0008]

The present inventors have conducted intensive studies on means for improving the charge retention of a nonvolatile semiconductor device. As a result, a phosphorus-doped region was formed at the interface between the intermediate insulating layer and the control gate on the intermediate insulating layer side. By doing so, it has been found that, in particular, charge leakage through the intermediate insulating layer is greatly reduced, and charge retention is greatly improved. Although the mechanism for reducing the charge leak by including the region containing phosphorus in such a position is not necessarily clear, the phosphorus-containing film blocks gettering of contaminant ions such as Na ⁺ by blocking the floating gate. It is thought that this may be due to the prevention of the movement of mobile ions such as Na ⁺ between the gate and the control gate, and the high resistance of the insulating film.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG.
FIG. 2 is a schematic cross-sectional view of a main part of an EPROM according to an embodiment of the present invention, FIGS. 2A to 2E are schematic cross-sectional views of a main part showing a manufacturing process of the EPROM of the embodiment, and FIG. FIG. 4A is a schematic sectional view of a main part of an EPROM according to an embodiment of the present invention.
(D) is a schematic cross-sectional view of a main part showing a manufacturing process of the EPROM of the embodiment, FIG. 5 is a schematic cross-sectional view of a main part of an EPROM according to still another embodiment of the present invention, and FIGS. 6 (A) to (F ). FIG. 7 is a schematic sectional view of a main part of an EPROM according to still another embodiment of the present invention, and FIG. 7 is a plan view of the EPROM in a manufacturing process.

As shown in FIG. 1, a nonvolatile semiconductor device according to a first embodiment of the present invention is an EPROM. For example, a gate insulating layer 6 is formed on the surface of a silicon semiconductor substrate 2, and a gate insulating layer is formed. On 6, a floating gate 8 is formed. Gate insulating layer 6 is formed by oxidizing the surface of semiconductor substrate 2 and is made of a silicon oxide film. The floating gate 8 is, for example, a CV
It is composed of a polysilicon film formed by the method D.

A control gate 12 is stacked on the floating gate 8 with an intermediate insulating layer 10 interposed. The control gate 12 is composed of a polysilicon film or a polycide film (a laminated film of a silicide film such as tungsten silicide, molybdenum silicide, titanium silicide, and tantalum silicide and a polysilicon film).

The film formation patterns of the floating gate 8 and the control gate 12 are arranged such that the floating gates 8 are arranged at predetermined intervals along the longitudinal direction of the control gate 12 below the control gates 12 arranged in rows at predetermined intervals. It is a pattern like this. The pattern of each floating gate 8 corresponds to one memory cell.

On the surface of the semiconductor substrate 2 after the floating gate 8 and the control gate 12 are formed in a predetermined pattern, an impurity diffusion layer 24 serving as a source / drain region is formed in a self-aligned manner by an ion implantation method or the like. I have. The impurity diffusion layer 24 is not particularly limited, but is configured by an N ⁺ impurity diffusion layer when the semiconductor substrate 2 is a P-type semiconductor substrate.

On the control gate 12, a metal electrode layer 16 made of aluminum or the like is laminated in a predetermined pattern via an interlayer insulating layer 14. The predetermined metal electrode layer 16 is connected through a contact hole 26 to an impurity diffusion layer 24 serving as a source / drain region of a memory cell. Further, another predetermined metal electrode layer 16 is
Control gate 1 through contact hole 27
2 are connected. An overcoat layer 32 is formed on the metal electrode layer 16.
A contact hole exposing the surface of the metal electrode layer 16 is formed. The interlayer insulating layer 14 is formed of, for example, a PSG film (phosphorus-doped silicate glass film). The overcoat layer 32 is formed of, for example, a silicon oxide film or a silicon nitride film.

In this embodiment, such an EPROM is used.
The intermediate insulating layer 10 has, for example, a low leakage current.
ONO film (SiO_Two / SiN / S
iO _Two ). The ONO film is made of silicon oxide
Film, intermediate silicon nitride film, and upper silicon oxide film
And a multilayer structure. Particularly, in this embodiment, such O
Upper silicon oxide film and lower silicon oxide film in NO film
At least one of the films is a phosphorous-containing film P
It is composed of an SG film. The concentration of phosphorus in PSG film is
Is not limited to 1 × 10¹⁹cm^-3That is all.

Next, a method of manufacturing an EPROM according to a first embodiment of the present invention will be described with reference to FIG. FIG. 2 (A)
As shown in FIG. 1, first, a semiconductor substrate 2 composed of a silicon wafer or the like is prepared, and a pad oxide film 1 is formed on the surface thereof.
8 was formed to a thickness of about 50 nm, an oxidation prevention film 20 of about 120 nm made of a silicon nitride film or the like was formed thereon in a predetermined pattern, and ion implantation for a channel stopper was performed toward the channel stopper region 22. Later, LO
Thermal oxidation for COS is performed to form a LOCOS 4 for isolating each memory cell as shown in FIG. At the time of ion implantation for the channel stopper, the N channel and the P channel may be separately formed. The ion implantation conditions for the channel stopper are not particularly limited. In the case of the P channel, for example, Phos ^{+ is set} to 50
Ion implantation is performed under the condition of a dose of 1 × 10 ¹² / cm ² at energy of KeV. In the case of N channel, for example, B ⁺ is implanted at 5 × 10 ¹³ / cm ² at energy of 100 KeV.
The ion implantation is performed under the condition of the dose amount. Also, LOCO
The thickness of S4 is not particularly limited.
m. Next, as shown in FIG.
A gate insulating layer 6 is formed on the surface of the semiconductor substrate 2 located between the COSs 4 by a thermal oxidation method. The condition of the thermal oxidation is, for example, wet oxidation at about 850 to 1000 ° C. The thickness of the gate insulating layer 6 is not particularly limited.
It is about 0 nm.

Next, a first polysilicon film to be a floating gate 8 is formed on the surface of the gate insulating layer 6 by a CVD method or the like. Although the thickness of the first polysilicon film is not particularly limited, it is, for example, about 100 to 300 nm, and preferably about 150 nm. In order to increase the conductivity of the first polysilicon film, an impurity such as phosphorus is introduced into the first polysilicon film. As a method for introducing phosphorus, a phosphorus predeposition method or the like is used.
Using the gas of No. ₃ , diffusion is performed at a temperature of about 800 to 1000 ° C. for 20 to 60 minutes. This first polysilicon film is
First, it is etched into a vertically long predetermined pattern.

Next, as shown in FIG. 1D, an intermediate insulating layer 10 is formed so as to cover the first polysilicon film serving as the floating gate 8. In this embodiment, since the intermediate insulating layer 10 has a three-layer structure of a lower-layer PSG film, an intermediate silicon nitride film, and an upper-layer PSG film, these films are continuously formed using a CVD method. Film. Although the thickness of each film is not particularly limited, the thickness of the lower PSG film is
For example, it is 8 to 20 nm, preferably 10 nm. The thickness of the intermediate silicon nitride film is, for example, about 8 to 20.
nm, preferably about 15 nm. Upper PSG
The thickness of the film is, for example, about 8 to 20 nm, preferably 10 to 20 nm.
nm. After these films are formed, a 30 nm oxide film may be formed on the surfaces of these films by a thermal oxidation method.

Next, on the surface of the intermediate insulating layer 10, a second polysilicon film having a thickness of about 300 nm to be the control gate 12 is formed by a CVD method or the like. Impurities such as phosphorus are introduced into the second polysilicon in the same manner as in the first polysilicon film in order to reduce the resistance. Then, the second polysilicon film is first etched by RIE or the like with a resist film, and then the intermediate insulating layer 10 and the first polysilicon film are continuously self-etched to obtain a floating gate 8 and a control gate 12 of a predetermined pattern. . When the control gate 12 has a polycide structure, a polysilicon film is formed to a thickness of about 100 nm, and a metal silicide film such as tungsten silicide is formed thereon to a thickness of about 150 nm.
The film is formed by a VD method or the like.

Thereafter, ion implantation and annealing are performed on the surface of the semiconductor substrate 2 in order to form an impurity diffusion layer 24 serving as a source / drain region in a self-aligned manner with respect to the gate. The conductivity type of the impurity used at the time of ion implantation is a conductivity type impurity having a polarity opposite to that of the semiconductor substrate 2.
N-type impurities such as s and P. The energy at the time of the ion implantation is not particularly limited.
Energy of 00 to 500 KeV, about 10 for P
Ion implantation is performed at an energy of 0 to 200 KeV. Although the dose is not particularly limited, for example, about 3 × 10 ¹⁵ c
m- ² .

Next, as shown in FIG. 1E, an interlayer insulating layer 14 is formed on the control gate 12. The interlayer insulating layer 14 is not particularly limited.
It is composed of a silicon oxide film or a PSG film obtained by the method. In the interlayer insulating layer 14, a contact hole 26 facing the impurity diffusion layer 24 serving as a source / drain region of the memory cell and a contact hole 27 desired for the control gate 12 are formed. The interlayer insulating layer 14
Electrode layer 1 made of aluminum or the like on the surface of
6 is formed and etched into a predetermined pattern. Thereafter, an overcoat layer 32 made of a silicon nitride film or the like is formed by a CVD method. Thereafter, post-processing steps such as opening of a connection pad window and RIE are performed.

In the EPROM 20 of this embodiment, a PSG film serving as a phosphorus-containing film is laminated on the intermediate insulating layer 10, so that this PSG film becomes a barrier layer against charge leakage, and the charge through the intermediate insulating layer 10 is reduced. Leakage can be greatly reduced, and charge retention can be greatly improved. The mechanism of reducing the charge leak by interposing a thin film containing phosphorus between the floating gate 8 and the control gate 12 is not necessarily clear, but the phosphorus-containing film is made of Na ⁺
This is thought to be due to such reasons as blocking contamination such as contamination, preventing movement of mobile ions such as Na ⁺ , and high resistance as an insulating film.

In the above embodiment, the intermediate insulating layer 1
Although a multilayer film having a multilayer structure of a PSG film, a silicon nitride film, and a PSG film was used as 0, the present invention is not limited to this. For example, a phosphorus-containing film such as a PSG film or a BPSG film may be used. The insulating layer itself can be formed. Further, such a phosphorus-containing film may constitute a part of the intermediate insulating layer, or may be included in the interface of the control gate 12 on the intermediate insulating layer side.

The method of forming a PSG film as a phosphorus-containing film is not limited to a vapor phase growth method such as a CVD method, but may be a liquid phase growth method such as a phosphorus predeposition method, a solid phase growth method, or an ion implantation method. Etc. can be used.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, a phosphorus-containing film such as a PSG film is laminated on a part of the intermediate insulating layer 10 and a control gate 12 is formed.
Further, a sidewall 66 is provided on a side portion of the floating gate 8. Moreover, the side wall 66 includes the phosphorus-containing film 40 in contact with the side portions of the control gate 12 and the floating gate 8, the silicon nitride film 62 as an oxidation prevention film in contact with the outside, and the silicon oxide film 64 laminated outside the film. And a multilayer film.
In addition, the control gate 12 and the sidewall 6
On top of 6, a cap layer 68 is laminated so as to cover them. Cap layer 68 is made of, for example, a silicon oxide film. The source / drain region is L
It is composed of impurity diffusion layers 60 and 70 having a DD structure.

In this embodiment, not only the charge leak through the intermediate insulating layer 10 but also the charge leak from the side of the floating gate can be prevented. In order to manufacture the EPROM according to this embodiment, first, as shown in FIG. 4A, a semiconductor substrate 2 composed of a silicon wafer or the like is first prepared, and a pad oxide film is formed on the surface thereof by about 50 nm. After forming an anti-oxidation film of about 120 nm composed of a silicon nitride film or the like in a predetermined pattern thereon and performing ion implantation for a channel stopper,
LOCOS thermal oxidation is performed to form LOCOS 4 for element isolation of each memory cell. The ion implantation conditions for the channel stopper are not particularly limited. For example, B ⁺ is implanted at 1 × 10 ¹³ / cm 3 at an energy of 50 KeV.
Ion implantation is performed under the condition of a dose amount of ² . With this channel stopper, a channel stopper region 22 is formed below LOCOS4.

The thickness of the LOCOS 4 is not particularly limited, but is, for example, about 400 nm. Next, FIG.
As shown in FIG. 5, a gate insulating layer 6 is formed on the surface of the semiconductor substrate 2 located between the LOCOSs 4 by a thermal oxidation method. The condition of the thermal oxidation is, for example, wet oxidation at about 850 to 1000 ° C. The thickness of the gate insulating layer 6 is not particularly limited, but is, for example, about 20 nm.

Next, as shown in FIG. 2B, a first polysilicon film to be a floating gate 8 is formed on the surface of the gate insulating layer 6 by a CVD method or the like. The thickness of the first polysilicon film is not particularly limited.
It is about 0 nm. In order to increase the conductivity of the first polysilicon film, an impurity such as phosphorus is introduced into the first polysilicon film. As a method for introducing phosphorus, a phosphorus predeposition method or the like is used, and diffusion is performed at a temperature of about 950 ° C. for 50 minutes using a POCl ₃ gas.

After the first polysilicon film is etched into a vertically long predetermined pattern, an intermediate insulating layer 10 is formed in the same manner as in the embodiment shown in FIGS. Next, a second polysilicon film having a thickness of about 200 nm serving as the control gate 12 is formed on the surface of the intermediate insulating layer 10 by CVD.
The film is formed by a method or the like. Also for this second polysilicon,
In order to reduce the resistance, an impurity such as phosphorus is introduced as in the case of the first polysilicon film. The second polysilicon film is first etched by RIE or the like with a resist film, and then the intermediate insulating layer 10 and the first polysilicon film are successively self-etched by RIE or the like to form a floating gate 8 having a predetermined pattern and a control gate. Gate 12 is obtained. When the control gate 12 has a polycide structure, the polysilicon film is
After forming a film with a thickness of about 0 nm, a metal silicide film such as tungsten silicide is formed thereon with a thickness of about 150 nm by a CVD method or the like.

Thereafter, the surface of the semiconductor substrate 2 is
First impurity for forming source / drain regions of structure
The material diffusion layer 60 is formed in a self-aligned manner with respect to the gate.
For this purpose, ion implantation and annealing are performed. ion
The conductivity type of the impurity used at the time of implantation is
And impurities of opposite conductivity type, and the semiconductor substrate 2 has P
If it is a type, for example, N-type impurities such as As and P
Things. Energy during ion implantation is particularly limited
However, if it is P, the energy is about 50 KeV.
Perform ON injection. The dose is not particularly limited.
For example, about 8 × 10 ¹⁴cm^-2It is.

Next, as shown in FIG. 2C, a PSG film constituting the phosphorus-containing film 40 is first formed on the control gate 12 by a CVD method or the like. The thickness of the PSG film is not particularly limited, but is, for example, about 100 nm. The concentration of phosphorus in the phosphorus-containing film 40 is not particularly limited, but is, for example, 5.0% by weight. Next, a silicon nitride film 62 as an oxidation prevention film and a silicon oxide film 64 for forming an outermost sidewall are formed on the phosphorus-containing film 40 by a continuous CVD method together with the phosphorus-containing film. The thickness of the silicon nitride film 62 is not particularly limited, but is, for example, 10 nm, and the thickness of the silicon oxide film 64 is about 300 nm. These phosphorus-containing films 4
0, the thickness of the silicon nitride film 62 and the thickness of the silicon oxide film 64 are not particularly limited.
Various modifications can be made within the range of 600 nm. For example, a phosphorus-containing film + a silicon nitride film + a silicon oxide film are 50 + 10 + 350 nm and 300 + 10
+100 nm, 100 + 5 + 400 nm or 100+
It can be changed to 50 + 400 nm or the like.

Next, these films 40, 62, and 64 are
Etch back by anisotropic etching such as E to oxidize the phosphorus-containing film 40 and the silicon nitride film 62 on the sides of the control gate 12 and the floating gate 8.
A side wall 66 provided inside the silicon film 64 is formed. Next, as shown in FIG. 4D, after a cap layer 68 of about 50 nm made of a silicon oxide film is formed, ion implantation is performed to obtain a source / drain region having an LDD structure, By diffusion, a high concentration second impurity diffusion layer 70 is obtained. The dose at the time of ion implantation is not particularly limited, but is, for example, 5 × 10 ¹⁵ cm ² . During the heat treatment for forming the source / drain regions, the phosphorus-containing film 40 becomes the silicon nitride film 6 as an oxidation prevention film.
2, diffusion of phosphorus due to thermal oxidation at the interface between the phosphorus-containing film 40 and the control gate 12 or the floating gate 8 is prevented.

Next, the interlayer insulating layer 14 is formed on the cap layer 68. The interlayer insulating layer 14 is not particularly limited, but is composed of, for example, a silicon oxide layer obtained by a CVD method. A contact hole 26 is formed in the interlayer insulating layer 14 facing the impurity diffusion layer 70 serving as a drain region of the memory cell, and the surface of the interlayer insulating layer 14 is coated with aluminum or the like so as to enter the contact hole 26. After the metal electrode layer 16 is formed and etched into a predetermined pattern, an overcoat layer 32 made of a silicon nitride film or the like is formed on the surface by CVD. Thereafter, post-processing steps such as opening of a connection pad window and RIE are performed. The thickness of the metal electrode layer 16 is not particularly limited, but is, for example, about 1000 nm.

In this embodiment, since the silicon nitride film 62 as an oxidation preventing layer is provided outside the phosphorus-containing film 40, the phosphorus-containing film 40 and the control gate 12 or the floating gate can be formed even during the heat treatment for forming the source / drain regions. At the interface with 8, the diffusion of phosphorus due to thermal oxidation is prevented, and the phosphorus-containing film 40 is kept at a high phosphorus concentration. As a result, charge retention is improved.

FIG. 5 shows a modification of the embodiment shown in FIGS. 3 and 4, in which an oxidation preventing cap layer 72 made of a silicon nitride film is provided outside a cap layer 68 made of a silicon oxide film. Are laminated. The thickness of the oxidation preventing cap layer 72 is not particularly limited, but is, for example, 50 n.
m.

According to this embodiment, since the heat treatment for forming the source / drain regions is performed after the formation of the cap layer 72 for preventing oxidation, the interface between the phosphorus-containing film 40 and the control gate 12 or the floating gate 8 is The diffusion of phosphorus due to thermal oxidation is prevented, and the phosphorus-containing film 40 is kept at a high phosphorus concentration. As a result, charge retention is improved. In the case of this embodiment, the oxidation preventing cap layer 72 prevents diffusion of phosphorus due to thermal oxidation at the interface between the phosphorus-containing film 40 and the control gate 12 or the floating gate 8. The silicon film 62 is not necessarily required, and the entire sidewall 66 can be formed of a PSG film or a PSG film + a silicon oxide film.

Next, a third embodiment of the present invention will be described with reference to FIGS. In order to manufacture the EPROM of this embodiment, first, as shown in FIG. 6A, a semiconductor substrate 2 composed of a silicon wafer or the like is prepared, and an oxide film for a pad is formed on its surface to a thickness of about 50 nm. Then, an oxidation prevention film of about 120 nm made of a silicon nitride film or the like is formed thereon in a predetermined pattern, ion implantation for a channel stopper is performed, and then thermal oxidation for LOCOS is performed.
LOCOS 4 for isolating each memory cell is formed. The ion implantation conditions for the channel stopper are not particularly limited. For example, B ⁺ ions are implanted at an energy of 50 KeV and a dose of 1 × 10 ¹³ / cm ² . With this channel stopper, LOCO
A channel stopper region is formed below S4.
FIG. 7 shows a formation pattern of the LOCOS 4, for example.

The thickness of the LOCOS 4 is not particularly limited, but is, for example, about 700 nm. Next, each LOCO
A gate insulating layer 6 is formed on the surface of the semiconductor substrate 2 located between S4 by a thermal oxidation method. The conditions for thermal oxidation are, for example, 8
This is wet oxidation at about 50 to 1000 ° C. The thickness of the gate insulating layer 6 is not particularly limited.
m.

Next, a first polysilicon film to be the floating gate 8 is formed on the surface of the gate insulating layer 6 by a CVD method or the like. Although the thickness of the first polysilicon film is not particularly limited, it is, for example, about 100 nm. In order to increase the conductivity of the first polysilicon film, an impurity such as phosphorus is introduced into the first polysilicon film. As a method for introducing phosphorus, limp Rede such deposition method is used, using a gas of POCl _3, about 800 to 10
Diffusion at a temperature of about 00 ° C. for 20 to 60 minutes.

The first polysilicon film is first etched into a vertically long predetermined pattern. FIG. 7 shows a processing pattern of the first stage of the first polysilicon film to be the floating gate 8.

Next, in the present embodiment, an intermediate insulating layer 10a is formed so as to cover the first polysilicon film serving as the floating gate 8. In the present embodiment, the intermediate insulating layer 10a
A lower silicon oxide film, an intermediate silicon nitride film,
It has a three-layer structure with an upper silicon oxide film. The lower silicon oxide film is formed, for example, by oxidizing the surface of the first polysilicon layer, and has a thickness of, for example, 8 to 20 nm, preferably 10 nm.

The intermediate silicon nitride film is formed by, for example, a CVD method and has a thickness of, for example, about 8 to 20 n.
m, preferably about 15 nm. In this embodiment,
During the formation of the intermediate silicon nitride film, phosphorus is introduced into the silicon nitride film. The upper silicon oxide film is formed by thermally oxidizing a silicon nitride film. Further, a CVD method can also be used. The thickness of the upper silicon oxide film is, for example, about 8 to 20 nm, preferably about 10 nm. After forming these films,
An oxide film of 30 nm may be formed on the surface of these films by a thermal oxidation method.

Next, as shown in FIG. 6C, on the surface of the intermediate insulating layer 10, about 25
A second polysilicon film having a thickness of about 0 nm is formed by a CVD method or the like. Impurities such as phosphorus are introduced into the second polysilicon in the same manner as in the first polysilicon film in order to reduce the resistance. Then, the resist film is used to first etch the second polysilicon film by RIE or the like, and the control gates 12 arranged at predetermined intervals are formed.
Get. FIG. 7 shows a plan view of this state.

Next, using the same resist film, the intermediate insulating layer 10 and the first polysilicon film are successively self-etched to obtain a floating gate 8 having a predetermined pattern.

When the control gate 12 has a polycide structure, a polysilicon film is formed to a thickness of about 100 nm, and a metal silicide film such as tungsten silicide is formed thereon to a thickness of about 150 nm by a CVD method or the like.

Thereafter, the surface of the semiconductor substrate 2 is
First impurity for forming source / drain regions of structure
The material diffusion layer 60 is formed in a self-aligned manner with respect to the gate.
For this purpose, ion implantation and annealing are performed. ion
The conductivity type of the impurity used at the time of implantation is
And impurities of opposite conductivity type, and the semiconductor substrate 2 has P
If it is a type, for example, N-type impurities such as As and P
Things. Energy during ion implantation is particularly limited
However, if it is P, the energy is about 50 KeV.
Perform ON injection. The dose is not particularly limited.
For example, about 8 × 10 ¹⁴cm^-2It is.

Next, as shown in FIG. 6D, sidewalls 80 are formed on the sides of the control gate 12 and the floating gate 8. Side wall 8
0 is formed, for example, by vertically anisotropically etching an insulating film of about 300 nm. It is preferable that the side wall 80 be formed of a phosphorus-containing film such as a PSG film.

Next, as shown in FIG.
A cap layer 68 of about 30 nm made of
After film formation, source / drain regions with LDD structure are obtained
For high concentration by thermal diffusion
Is obtained. Dose during ion implantation
Although the amount is not particularly limited, for example, 5 × 10^Fifteencm ^Two 
It is.

Next, the interlayer insulating layer 14 is formed on the cap layer 68. The interlayer insulating layer 14 is not particularly limited, but is composed of, for example, a silicon oxide layer obtained by a CVD method. A contact hole 26 is formed in the interlayer insulating layer 14 facing the impurity diffusion layer 70 serving as a drain region of the memory cell, and the surface of the interlayer insulating layer 14 is coated with aluminum or the like so as to enter the contact hole 26. After the metal electrode layer 16 is formed and etched into a predetermined pattern, an overcoat layer made of a silicon nitride film or the like is formed on the surface by CVD. Thereafter, post-processing steps such as opening of a connection pad window and RIE are performed. The thickness of the metal electrode layer 16 is not particularly limited, but is, for example, about 1000 nm.

In this embodiment, the ONO is used as the intermediate insulating layer 10a.
Since the film has a film structure and contains phosphorus in the intermediate silicon nitride film, this intermediate silicon nitride film getster contaminant ions such as Na ⁺ and blocks the passage thereof. In addition, the phosphorus-containing sidewall 80
Since the intrusion of contaminant ions from the side is also prevented, the surroundings of the floating gate 8 are covered with a film through which the contaminant ions do not easily pass except for the gate insulating layer 6 on the lower surface. It is greatly improved.

Further, the phosphorus-containing silicon nitride film has almost the same dielectric constant as that of a normal silicon nitride film.
The coupling ratio between the floating gate 8 and the control gate 12 is not impaired. Furthermore, the manufacturing method of the present invention has no additional steps compared to the conventional process, and thus the manufacturing cost is low.

The present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the present invention.

For example, in the embodiment described above, the present invention
Although an example has been described applied to a PROM, E ² PRO
The present invention can be applied to all semiconductors having a floating gate, such as M and flash type E ² PROM.

[0054]

As described above, according to the present invention, the region doped with phosphorus is formed at the interface between the intermediate insulating layer and the control gate on the intermediate insulating layer side.
In particular, charge leakage through the intermediate insulating layer can be significantly reduced, and charge retention can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of an EPROM according to an embodiment of the present invention.

FIGS. 2A to 2E are schematic cross-sectional views of main parts showing a manufacturing process of the EPROM of the embodiment.

FIG. 3 is a schematic sectional view of a main part of an EPROM according to another embodiment of the present invention.

FIGS. 4A to 4D are schematic cross-sectional views of a main part showing a manufacturing process of the EPROM of the embodiment.

FIG. 5 is a diagram illustrating an E according to still another embodiment of the present invention.
It is a principal part schematic sectional drawing of PROM.

[6] FIG. 6 (A) ~ (F) is a main part schematic cross-sectional view of the EPROM according to still another embodiment of the present invention.

FIG. 7 is a plan view of the EPROM in a manufacturing process.

[Explanation of symbols]

 Reference Signs List 2 semiconductor substrate 4 LOCOS 6 gate insulating layer 8 floating gate 10, 10a intermediate insulating layer 12 control gate 24 impurity diffusion layer for source / drain region 66, 80 sidewall 40 phosphorus-containing film

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-295644 (JP, A) JP-A-62-247570 (JP, A) JP-A-64-11370 (JP, A) JP-A 64-64 15985 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] 1. A nonvolatile semiconductor device in which a control gate is stacked on a floating gate with an intermediate insulating layer interposed therebetween, wherein the intermediate insulating layer includes a lower silicon oxide film and an intermediate nitride film.
It has a multilayer structure of a silicon film and an upper silicon oxide film.
Ri, the lower layer side silicon oxide film and and upper silicon oxide
A non-volatile semiconductor device, characterized in that both films contain phosphorus . 2. The lower silicon oxide film and the upper silicon oxide film.
2. The method according to claim 1, wherein both of the silicon oxide films are PSG films.
Nonvolatile semiconductor device. 3. A control on a floating gate.
Non-volatile half-gate stacked with an intermediate insulating layer
In the conductor device, the intermediate insulating layer includes a lower silicon oxide film and an intermediate nitride film.
It has a multilayer structure of a silicon film and an upper silicon oxide film.
Ri, especially that phosphorus are contained in the intermediate silicon nitride film
Nonvolatile semiconductor device. 4. A control on a floating gate.
Non-volatile half-gate stacked with an intermediate insulating layer
In a conductor device, the phosphorus concentration at the control gate is
The interface on the edge layer side is formed above the control gate.
Characteristically higher than the interface on the insulating film side formed
Non-volatile semiconductor device. 5. A control device on a floating gate.
Non-volatile half-gate stacked with an intermediate insulating layer
Forming a gate insulating layer on a surface of a semiconductor substrate; and forming a floating gate on the gate insulating layer in the method of manufacturing a conductor device.
And forming a lower silicon oxide layer on the floating gate.
Film, intermediate silicon nitride film, and upper silicon oxide film
Forming an intermediate insulating layer having a multilayer structure of: and forming a control gate above the intermediate insulating layer
Process and the semiconductor on both sides of the floating gate
In the substrate, chromatic and forming source and drain regions
In the step of forming the intermediate insulating layer, the lower layer side
Both silicon oxide film and upper silicon oxide film
Non-volatile semiconductor, characterized by containing
Manufacturing method of body device. 6. The lower silicon oxide film and the upper silicon oxide film.
A PSG film is formed as a silicon oxide film, and the PSG film is formed by thermally oxidizing the surface of the polysilicon film to form an acid.
After forming a silicon nitride film, the phosphor predeposition method
Therefore, phosphorus is added to the silicon oxide film more than 1 × 10 ¹⁹ cm ⁻³ .
6. The non-volatile semiconductor device according to claim 5, wherein said non-volatile semiconductor device is formed by being contained at a concentration.
A method for manufacturing a conductor device. 7. The lower silicon oxide film and the upper silicon oxide film.
A PSG film is formed as a silicon oxide film, and the PSG film is formed by a CVD method.
Then, the silicon oxide film is repaired by ion implantation.
6. The method according to claim 5, which is formed by doping
A method for manufacturing a volatile semiconductor device. 8. A control on a floating gate.
Non-volatile half-gate stacked with an intermediate insulating layer
Forming a gate insulating layer on a surface of a semiconductor substrate; and forming a floating gate on the gate insulating layer in the method of manufacturing a conductor device.
And forming a lower silicon oxide layer on the floating gate.
Film, intermediate silicon nitride film, and upper silicon oxide film
Forming an intermediate insulating layer having a multilayer structure of: and forming a control gate above the intermediate insulating layer
Process and the semiconductor on both sides of the floating gate
In the substrate, chromatic and forming source and drain regions
In the step of forming the intermediate insulating layer, the intermediate nitride
Characterized in that it contains phosphorus in silicon nitride film
Of manufacturing a nonvolatile semiconductor device.