JP3163996B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which leakage between a gate and a source / drain is prevented.

[0002]

2. Description of the Related Art CMOS transistor integrated circuits are widely used for memories and microcomputers because they can be highly integrated. However, as the degree of integration of CMOS transistor integrated circuits increases, the devices themselves become finer, so that diffusion becomes difficult. The layer resistance and the resistance component of the gate electrode cannot be ignored in the device function. In order to reduce this resistance, a technique using a metal silicide of a diffusion layer and a silicide of a gate electrode has been proposed. An example is disclosed in Japanese Patent Application Laid-Open No. 60-52044.
This technique will be described with reference to FIG.

[0003] First, as shown in FIG. 3 (a), a 500 nm
After the formation of the field oxide film 2 of about
A gate structure including a gate oxide film 3, a polysilicon gate electrode 4, and a sidewall 5 made of an oxide film is formed in accordance with the S transistor forming process. Next, source / drain regions 6 of the MOS transistor are formed by introducing predetermined impurities using an ion implantation method.

Next, as shown in FIG. 3B, a metal 10 (for example, Ti) which can be silicided is formed to a thickness of about 200 nm. Further, as shown in FIG. 3C, the surfaces of the gate electrode 4 and the source / drain regions 6 are silicided by a heat treatment at 700 ° C. for about 30 minutes in a nitrogen atmosphere to form a metal silicide film 7. . At this time, the upper metal film 10 such as the field oxide film 2 that does not react with silicidation becomes metal nitride (TiN) or remains as unreacted metal (Ti). Next, as shown in FIG.
The metal nitride and the unreacted metal film 10 on the field oxide film 2 are wet-etched, for example, H ₂ SO ₄ + H ₂ O.
After removing the _2, 800 ° C., a metal silicide film 7 is formed as a low-resistance layer by heat treatment at about 15 minutes of nitrogen or in an inert atmosphere of argon or in a vacuum.

However, in this technique, FIG.
Since the step of removing the metal nitride and the unreacted metal film 10 above the field oxide film 2 is performed by etching using a H ₂ SO ₄ + H ₂ O ₂ solution, the unreacted metal film 10 is sufficiently removed due to insufficient etching. Otherwise, a short circuit between the source and the gate or between the drain and the gate may occur through the unreacted metal film 10.

As a technique for solving such a problem, there is a technique proposed in Japanese Patent Application Laid-Open No. Hei 5-47785. This technique will be described with reference to FIG. First, as shown in FIG. 4A, a field oxide film 2 having a thickness of about 500 nm is formed on a silicon substrate 1 using a known selective oxidation method, and then a gate oxide film is formed in accordance with a normal MOS transistor formation process. 3. A gate structure including the polysilicon gate electrode 4 is formed. Then, a thermal oxide film 11 having a substantially L-shaped section is formed along the side wall of the polysilicon gate electrode 4 by thermal oxidation.
To form

Next, as shown in FIG. 4B, after forming a sidewall 12 of a Si ₃ N ₄ film on the thermal oxide film 11, a metal 10 which can be silicided is formed on the entire surface. Using the mask as a mask, impurities are implanted into the silicon substrate 1 to form the source / drain regions 6. afterwards,
As shown in FIG. 4C, a Si ₃ N ₄ film 13 is formed on the entire surface, and a heat treatment is further performed to cause a silicidation reaction on the gate electrode 4 and the source / drain regions 6 to form a metal silicide film 7. Then, Figure 4 the upper layer of the Si ₃ N ₄ film 13 as shown in (d), the unreacted metal film 10, and Si ₃
The sidewall 12 made of the N ₄ film is etched.

[0008]

In the improved technique shown in FIG. 4, since the sidewalls 12 are etched, unreacted portions remain on the sidewalls 12 as described in the technique of FIG. Even if the metal film 10 is left,
Since it is removed together with the side wall 12, it is possible to prevent a short circuit phenomenon between the source / gate and the drain / gate. However, when the sidewall 12 is etched by the Si ₃ N ₄ film, the metal silicide film may be over-etched due to an error in the etching selectivity and other control of the etching condition, and the like. The resistance of the metal silicide film 7 is increased. For this reason, the effect of lowering the resistance originally intended by the metal silicide film is reduced, or the resistance is varied, and the characteristics and reliability of the integrated circuit using the MOS transistor are deteriorated. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which the characteristics and reliability of an integrated circuit using MOS transistors can be improved by preventing over-etching of a silicide film, thereby preventing an increase or variation in resistance. It is to provide a manufacturing method.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a gate electrode on a semiconductor substrate, a step of forming a source / drain region on a surface of the semiconductor substrate, and a step of forming a side wall on a side surface of the gate electrode. Forming a metal film on the entire surface, and heat-treating to form a metal silicide film on at least the source / drain regions;
Removing the metal silicide layer unreacted entire
Under conditions where it is difficult to form a film on the surface of the side wall of the sidewall.
An insulating film made of a plasma oxide film by ECRCVD,
Alternatively, a step of forming an insulating film made of an oxide film by a bias ECRCVD method and performing dry etching on the insulating film until the surface of the sidewall of the sidewall is partially etched. And performing the following. In the case where an insulating film is formed using an oxide film by a bias ECRCVD method, dry etching of the oxide film is performed by A
It is preferable to carry out by the r sputtering method.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view in the order of steps for explaining a first embodiment of the present invention. First, FIG.
As shown in FIG. 2, after a field oxide film 2 of about 500 nm is formed on a silicon substrate 1 by using a known selective oxidation method, a gate oxide film 3 and a polysilicon gate electrode 4 are formed in accordance with a normal MOS transistor formation process. Then, a gate structure including the sidewall 5 is formed. Then, a predetermined impurity is introduced by using an ion
The source / drain region 6 of the transistor is formed. Further, although not shown in the figure, a metal (eg, Ti) that can be silicided is formed to a thickness of about 200 nm,
By heat treatment at 00 ° C. for about 30 minutes, the surfaces of the gate electrode 4 and the source / drain regions 6 are silicided to form a metal silicide film 7. Thereafter, the nitride and the unreacted metal film on the field oxide film 2 and the sidewalls 5 are wet-etched, for example, H ₂ SO 4.
After removal by ₄ + H ₂ O ₂ , the metal silicide film 7 is formed as a low resistance layer by heat treatment at 800 ° C. for about 15 minutes in an inert atmosphere of nitrogen or argon or in a vacuum.

Next, as shown in FIG. 1B, under the condition that an oxide film does not grow on the surface of the sidewall 5, 10.
A plasma oxide film 8 of about 0 nm is grown. As a method of growing the plasma oxide film, a known method such as a bias ECRCVD method (J. Vac. Sci. Technol., 15 (3), May / Jun
e 1978 p1105) can be adopted. In doing so,
As shown in FIG. 1C, the plasma oxide film 8 is removed by about 50 nm by isotropic SiO ₂ dry etching. In this etching, since the plasma oxide film 8 is formed by the ECRCVD method under the above-described conditions, the film is almost not formed on the steeply inclined surface of the sidewall 5, here, at the shoulder of the sidewall 5. At the shoulder portion of the sidewall 5, a part of the surface of the sidewall 5 is etched together with the etching of the plasma oxide film 8.

Therefore, even if the metal generated in the silicide process that causes a short circuit (leak) between the source and the gate and between the drain and the gate remains on the surface of the sidewall 5, the metal residue is completely removed. It will be removed and the short circuit phenomenon in each will be completely prevented. Further, in this etching, since the etching can be completed while the plasma oxide film 8 remains on the surface of the metal silicide film 7, the metal silicide film 7 is not exposed to the dry etching. The electrically stable characteristics are maintained.

FIG. 2 is a longitudinal sectional view showing a part of a process for explaining a second embodiment of the present invention. In the figure,
Portions equivalent to those in the first embodiment are denoted by the same reference numerals. In this embodiment, as shown in FIGS. 1A and 1B, a field oxide film 2 of about 500 nm is formed on a silicon substrate 1 by using a known selective oxidation method, and a gate oxide film is further formed. 3, a gate structure including a polysilicon gate electrode 4 and a sidewall 5 is formed, and then a predetermined impurity is introduced by ion implantation to form a source / source electrode.
A drain region 6 is formed, and a metal (for example, Ti) that can be silicided is formed thereon.
Then, the surface of the source / drain region 6 is subjected to a silicidation reaction to form a metal silicide film 7. Thereafter, the nitride and the unreacted metal film on the field oxide film 2 and the sidewall 5 are wet-etched, for example, H ₂ S.
After removal by O ₄ + H ₂ O ₂ ,
The metal silicide film 7 is formed as a low-resistance layer by heat treatment in an inert atmosphere of nitrogen or argon for about a minute or in a vacuum.

Then, an oxide film 8 is grown by a bias ECRCVD method. At this time, the side wall 5 is etched while controlling the flow rate, pressure, and RF power of Ar gas during the film formation. The oxide film 9 can be grown. Even in this case, the oxide film 9 is hardly formed on the shoulder portion of the sidewall 5. Therefore, similarly to the first embodiment, the unreacted metal film existing on the sidewall 5 can be removed without damaging the metal silicide film 7 by etching, and the source-gate and drain-metal regions can be removed.
The short circuit between the gates can be prevented. Further, the isotropic dry etching step performed in the manufacturing process of the first embodiment becomes unnecessary, and the number of steps can be reduced.

The manufacturing method of the present invention can be similarly applied to a MOS semiconductor device having a source / drain having an LDD structure. Needless to say, the metal for forming the metal silicide film is not limited to Ti described above.

[0017]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the entire surface including the sidewalls formed on the side surfaces of the gate electrode is covered with the surface of the sidewalls.
Is plasma oxidation by ECRCVD under conditions where film formation is difficult
By an insulating film made of a film or a bias ECRCVD method
Since an insulating film made of an oxide film is formed and the insulating film is dry-etched on the insulating film, a part of the sidewall of the sidewall can be etched without etching the metal silicide film. This makes it possible to remove the metal film even when a metal remains on the surface of the side wall of the sidewall, thereby effectively improving the short-circuit phenomenon between the source and the gate and between the drain and the gate. In addition, it is possible to prevent damage to the metal silicide film, improve characteristics and improve reliability, and realize a semiconductor device having a higher yield than a conventional manufacturing method. Further, by forming an oxide film by a bias ECRCVD method, an independent etching step is not required, and the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an example of a conventional manufacturing method in the order of steps.

FIG. 4 is a cross-sectional view showing another example of the conventional manufacturing method in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 field oxide film 3 gate oxide film 4 polysilicon gate electrode 5 side wall 6 source / drain region 7 metal silicide film 8 ECRCVD plasma oxide film 9 bias ECRCVD oxide film

Claims (3)

(57) [Claims] A step of forming a gate electrode on a semiconductor substrate; a step of forming source / drain regions on a surface of the semiconductor substrate; a step of forming sidewalls on side surfaces of the gate electrode; a metal film is formed, and forming a metal silicide film at least on said source and drain regions by heat-treating, and removing the metal silicide film which has not reacted, the side wall side wall on the entire surface
Under the conditions where film formation is difficult,
Forming an insulating film made of a zuma oxide film , and dry etching the insulating film, and performing this etching until a part of the surface of the sidewall is etched. Semiconductor device manufacturing method. 2. A step of forming a gate electrode on a semiconductor substrate, a step of forming source / drain regions on a surface of the semiconductor substrate, a step of forming sidewalls on side surfaces of the gate electrode, a metal film is formed, and forming a metal silicide film at least on said source and drain regions by heat-treating, and removing the metal silicide film which has not reacted, the side wall side wall on the entire surface
Bias ECRCVD under conditions where film formation is difficult on the surface of
Forming an insulating film made of an oxide film, and a step of performing dry etching on the insulating film and performing this etching until a part of the surface of the sidewall is etched. Semiconductor device manufacturing method. 3. A dry etching of the oxide film is an Ar sputtering at the bias ECRCVD apparatus according to claim
2. The method for manufacturing a semiconductor device according to item 2 .