JP3163484B2 - Waveform shaping circuit and digital signal analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform shaping circuit for shaping and outputting an input digital signal, and a digital signal input in synchronization with a clock signal such as a logic analyzer or an error measuring device. The present invention relates to a digital signal analyzer for analyzing.

[0002]

2. Description of the Related Art Generally, in a digital signal analyzer such as a logic analyzer or an error measuring device described above, a digital signal input from the outside is shaped by a waveform shaping circuit comprising a comparator. Thereafter, the binary determination is made.

In this type of waveform shaping circuit, it is necessary to set the operating point of the comparator to the best operating point that corresponds to the offset of the input digital signal and is not affected by noise. Conventionally, one of the following three methods has been implemented to set the operating point.

(1) A method of manually setting the threshold level (reference voltage) for the comparator to an optimum state while monitoring the output waveform of the comparator.

(2) A method in which an input digital signal is input to a comparator via a capacitor to remove the influence of offset.

(3) A method in which a DC average level of an input digital signal is assumed in advance and manually changed by a level shifter and input to a comparator.

However, in the above-mentioned methods (1) and (3), setting the operating point manually is troublesome, and the setting operation must be performed every time the level or offset of the input signal changes.

In the above-mentioned method (2), the digital signal input to the comparator according to the mark rate of the input digital signal (the ratio of the total number of generated bits to the number of marks included therein). , The offset voltage changes, and the waveform cannot be reliably shaped with a fixed threshold value.

For this reason, a method of inputting an intermediate voltage between a high level voltage and a low level voltage of an input digital signal to a comparator as a threshold value can be considered.

However, this method is effective in the case of a relatively low-speed comparator having a wide common-mode input range, but has a common-mode input range such as a comparator for shaping a waveform of an ultrahigh-frequency (several GHz) signal. If it is extremely narrow,
There is a problem that the comparator itself is saturated by a change in the offset voltage of the input signal, and a normal waveform shaping operation cannot be performed.

On the other hand, a digital signal analyzer which performs a binary decision on a waveform-shaped digital signal and analyzes the digital data has conventionally been constructed as shown in FIG.

That is, the data signal to be measured input to one input terminal 1 is equal to the reference voltage Vr from the reference voltage generator 2.
The waveform is shaped by the comparator 3 with the threshold value as. Since the reference voltage Vr is set to the best value in advance by any of the above-described methods, the fluctuation component in the amplitude direction of the data signal to be measured shown in FIG. As shown in (1), the waveform is shaped and input to the data input terminal D of the discriminator 4 composed of a D-type flip-flop.

The clock signal input to the other input terminal 5 is input to the clock terminal CP of the discriminator 4 via the variable delay 6.

The variable delay unit 6 is adjusted in advance so that the clock signal rises at the timing when the binary level of the data signal input to the discriminator 4 is most stable.

As this adjustment, the output signal of the comparator 3 shown in FIG. 18B and the clock signal shown in FIG. 18C are displayed on a dual phenomenon oscilloscope, and the rising timing of the clock signal is Approximately midpoint between digital signal state transition points I and II (point with the largest phase margin)
A method of manually adjusting the delay amount of the variable delay device 6 so as to position the variable delay device 6 has been conventionally employed.

In this way, the digital signal from the comparator 3 is binary-identified at the rising timing of the clock signal input to the discriminator 4, and its decision output is input to the data analyzer 7 together with the clock signal. Then, predetermined data analysis is performed.

However, in the conventional digital signal analyzer having such a configuration, in addition to the manual adjustment of the waveform shaping circuit described above, the manual adjustment of the delay amount must be performed. There has been a problem that a difference in the set amount is likely to occur, and a difference will also appear in the analysis result.

Further, when making adjustments by observing the waveform with an oscilloscope, not only is the connection between the devices complicated, but also the signal waveform is disturbed by the connection of the oscilloscope.
It may cause malfunction. In particular, as described above, when a cable for observing a waveform is connected to an ultra-high frequency (several GHz) signal, the waveform is greatly disturbed, and accurate adjustment is difficult.

For this reason, there is a method of providing a monitor terminal for waveform observation in the digital signal analyzer, but it is necessary to always prepare a waveform observation device such as an oscilloscope, which is very inconvenient. there were.

An object of the present invention is to provide a waveform shaping circuit and a digital signal analyzer which solve the above-mentioned problems.

[0021]

In order to solve the above-mentioned problems, a waveform shaping circuit according to the present invention comprises a level shifter (12) for variably controlling a DC offset voltage of an input digital signal, and an output signal from the level shifter. A comparator for comparing the digital signal with a predetermined reference voltage, shaping and outputting the waveform, a maximum value detecting circuit for detecting a maximum value of the digital signal output from the level shifter, and detecting a minimum value of the digital signal A digital signal output from the level shifter, comprising an intermediate voltage output circuit that outputs an intermediate voltage between the maximum value detected by the maximum value detection circuit and the minimum value detected by the minimum value detection circuit. Intermediate voltage detecting means (15) for detecting and outputting an intermediate voltage between the high level voltage and the low level voltage of the intermediate voltage; Receiving the intermediate voltage output from the output means and the predetermined reference voltage, and outputting a control signal for changing the DC offset voltage to the level shifter in order to make the intermediate voltage equal to the predetermined reference voltage. control means (21), is output from the control means
Holding means (25) for holding the control signal obtained,
When the control signal is held by the holding means,
Stop means (26, 2) for stopping the operation of the inter-voltage detection means.
7) .

The digital signal analyzer of the present invention compares a level shifter (52) for variably controlling a DC offset voltage of an input digital signal and a digital signal output from the level shifter with a predetermined reference voltage, A comparator (60) for shaping and outputting a waveform, and a maximum value of a digital signal output from the level shifter
Detection circuit for detecting the minimum value of the digital signal
The minimum value detection circuit and the maximum value detection circuit for detecting
The maximum value detected and the minimum value detected by the minimum value detection circuit
An intermediate voltage output circuit that outputs an intermediate voltage of
Intermediate voltage detecting means (55) for detecting and outputting an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter; an intermediate voltage output from the intermediate voltage detecting means; A first control means for receiving the reference voltage and outputting a control signal to the level shifter for changing the DC offset voltage to make the intermediate voltage equal to the predetermined reference voltage (61).
A variable delay device (71) for relatively varying the phase between the input clock signal and the output of the comparator
Receiving the clock signal and the output of the comparator, the phase of which is relatively varied by the variable delay device,
A discriminator (72) for judging the sign of the output signal of the comparator at the time of rising or falling of the clock signal, and comparing a judgment signal from the discriminator with a reference signal corresponding to the input digital signal; An error measuring device (75) that outputs an error signal by detecting an error signal, and detects an intermediate delay amount that is approximately the middle of a delay amount in which the error signal has a maximum value adjacent to each other in response to the output of the error measuring device; Second control means (80) for transmitting an intermediate delay amount to the variable delay device and reducing the error signal output from the error measuring device.

[0023]

With such a configuration, in the waveform shaping circuit of the present invention, the input digital signal is input to the comparator via the level shifter, and is shaped by a predetermined reference voltage. Further, an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter is detected by the intermediate voltage detecting means and output to the control means together with the reference voltage. The control means outputs a control signal for making the intermediate voltage equal to the reference voltage to the level shifter, and varies the DC offset voltage of the input digital signal.

In the digital signal analyzer of the present invention, the output signal of the comparator whose waveform has been shaped by the waveform shaping circuit having the same configuration as that of the waveform shaping circuit of the present invention described above and the clock signal input from the input terminal are in between. The phase is changed by the variable delay device and input to the discriminator.
The determination signal from the discriminator is compared with a reference signal corresponding to the input digital signal by the error measuring device.
The error signal detected by the error measuring device is input to the second control means. The second control means varies the delay amount of the variable delay device while receiving the error signal from the error measurement device, and detects an almost intermediate delay amount of the delay amount in which the error signal is maximized adjacent to each other. Output to variable delay.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a waveform shaping circuit 10 according to the first embodiment.
FIG. 3 is a circuit diagram showing the configuration of FIG.

In FIG. 1, an input digital signal input to a terminal 11 is terminated by an input resistor R ₀ (for example, 50Ω) and input to a level shifter 12.

The level shifter 12 varies the average DC (offset) voltage level of the input digital signal in accordance with the magnitude of an error signal (control signal) Ve from a control circuit 21 described later. For this purpose, the level shifter 12 is configured, for example, as shown in FIG.

That is, the average DC voltage of the input digital signal is detected by an integrating circuit including a resistor R ₁ and a capacitor C ₁ and is input to the adder 13. The adder 13 adds the error signal Ve to the average DC voltage, the sum voltage, and outputs through a resistor R _2. Between the resistor R ₂ and the terminal 11, the capacitor C ₂ is provided for passing only the AC component of the input digital signal. Therefore, from the connection point between the capacitor C ₂ and the resistor R ₂ , a signal obtained by adding the output voltage from the adder 13 to the AC component of the input digital signal, that is, the error voltage Ve
A signal whose level has been shifted by only this is output.

The resistors R ₁ and R ₂ have a high resistance value of about several tens KΩ which does not affect the transmission impedance of 50Ω.

As shown in FIG. 1, the output of the level shifter 12 is input to an intermediate voltage detection circuit 15 and a comparator 20, which will be described later.

The intermediate voltage detection circuit 15 includes the level shifter 1
Maximum value detection circuit 16 for detecting the maximum voltage of the output signal of
A minimum value detection circuit 17 for detecting the minimum voltage of the output signal of the level shifter 12, and an intermediate voltage between the output voltages of the two detection circuits 16, 17, which are connected in series to two resistors R ₃ having the same resistance value. It is constituted by the intermediate voltage output circuit 18 to be output from the connection point of R _4.

The comparator 20 has one input terminal IN
The level of the output signal of the level shifter 12 input to the
It outputs a high level digital signal when it is higher than a predetermined reference voltage (hereinafter also referred to as threshold voltage) Vr applied to the other input terminal REF, and outputs a low level digital signal when it is lower. The comparator 20 is configured by a semiconductor element for ultra-high frequency (for example, gallium-arsenic FET) or the like.

The intermediate voltage Vo and the threshold voltage Vr output from the intermediate voltage detection circuit 15 are input to a control circuit 21 which is control means of the waveform shaping circuit 10.
The control circuit 21 detects the difference between the input intermediate voltage Vo and the threshold voltage Vr by the subtracter 22 and outputs the difference voltage signal via the low-pass filter 23 to the level shifter 1.
2 to control the shift amount of the level shifter 12 in a direction in which the intermediate voltage Vo matches the threshold voltage Vr.

FIG. 3 shows an example of a more specific circuit of the intermediate voltage detection circuit 15 and the control circuit 21.

That is, the maximum value detection circuit 16 includes a diode 16 having an anode connected to the output of the level shifter 12.
and a, a cathode of the diode 16a has a positive peak detector circuit formed by a capacitor 16b connected between ground and the negative power source -V ₁ connection point and a given this diode 16a and the capacitor 16b Between them, a constant current source 16c for flowing a small forward bias current to the diode 16a is connected.

The minimum value detecting circuit 17 includes a diode 17 having a cathode connected to the output of the level shifter 12.
a, and a negative peak detection circuit formed by a capacitor 17b connected between the anode side of the diode 17a and the ground.
Between a connection point and a predetermined positive power source + V ₁ and 7b, a constant current source 17c to flow a forward bias current of the very small is connected to the diode 17a.

[0038] Therefore, from the connection point between the diode 16a and the capacitor 16b of the peak value detector 16, of the digital signal output from the level shifter 12, or the negative power source -V ₁ voltage of a high level voltage is output, the minimum Diode 17a and capacitor 17b of value detection circuit 17
A low-level voltage equal to or lower than the positive power supply voltage + V ₁ is output from the connection point with.

The forward bias currents from the constant current sources 16c and 17c to the diodes 16a and 17a have almost no effect on the input digital signal, and also compensate for the non-linearity of the detection operation of the diodes 16a and 17a. It is set to a current value of about 1 μA necessary for the operation.

The capacitance of the capacitors 16c and 17c is about 1000 PF which can hold the peak value of a digital signal having a repetition period of 1 kHz or more, considering that the forward bias current to each of the diodes 16a and 17a is about 1 μA. Is set to the value of

The subtracter 22 of the control circuit 21 is formed by a differential amplifier 22a and a feedback resistor 22b.
A voltage corresponding to the difference between o and the threshold voltage Vr is output from the differential amplifier 22a. Resistor 23a and capacitor 23b
The low-pass filter 23 formed by the differential amplifier 22
The error signal Ve obtained by removing the noise component from the output of “a” is output to the level shifter 12.

Therefore, when the intermediate voltage Vo decreases with respect to the threshold voltage Vr, the output voltage of the differential amplifier 22a increases, so that the error signal Ve increases and the level of the digital signal output from the level shifter 12 increases. Rises throughout. Conversely, when the intermediate voltage Vo increases with respect to the threshold voltage Vr, the output voltage of the differential amplifier 22a decreases, so that the error signal Ve decreases and the level of the digital signal output from the level shifter decreases as a whole. Will do.

Next, the operation of the waveform shaping circuit 10 will be described.

Now, suppose that at time t ₀ , the level shifter 12
As shown in FIG. 4A, the intermediate value between the maximum value and the minimum value of the digital signal input to
Of the threshold voltage Vr.

In this case, since the output of the subtractor 22 of the control circuit 21 becomes zero, the digital signal input to the level shifter 12 is input to the comparator 20 as it is,
The waveform is shaped by the threshold voltage Vr.

At time t ₁ , as shown in FIG. 4A, it is assumed that the DC offset voltage of the input digital signal rises in a step-like manner. In response to this, the output signal of the level shifter 12 also rises as shown in FIG. 3B, and the maximum value detection circuit 1 of the intermediate voltage detection circuit 15
6. The output voltage of the minimum value detection circuit 17 is also shown in FIG.
It changes stepwise as shown in (d).

For this reason, the intermediate voltage Vo to the subtractor 22
Also changes stepwise as shown in (e) of the figure, and the output of the subtractor 22 largely changes in the negative direction as shown in (f) of the figure.

Therefore, the low-pass filter 23 outputs an error signal Ve which decreases at a speed corresponding to the time constant, as shown in FIG.

As a result, the shift amount of the level shifter 12 gradually increases to the negative side, so that the intermediate value of the digital signal input to the comparator 20 becomes the threshold voltage Vr as shown in FIG. In the direction that matches.

As a result, at time t ₂ , the subtracter 2
The difference between the two input voltages becomes substantially zero. Thereafter, this stable state is maintained, and a digital signal whose waveform has been reliably shaped is obtained from the output of the comparator 20.

Thereafter, even if the offset of the input digital signal changes, the intermediate voltage of the digital signal input to the comparator is always subjected to feedback control in a direction approaching the threshold voltage Vr. Continue stably.

[0052]

Second Embodiment In the first embodiment, the control loop for controlling the shift amount of the level shifter 12 is always closed. However, the shift amount with respect to the input digital signal stably becomes an appropriate amount. Then, the shift amount may be held to open the loop, and the detection operation of the intermediate voltage detection circuit 15 connected to the signal line may be stopped.

FIG. 5 shows the configuration of a hold-type waveform shaping circuit 10 'according to a second embodiment. The waveform shaping circuit 10 'includes a hold circuit 25 for receiving a hold signal (stop signal) and holding the magnitude of the error signal, and a maximum value detection circuit 1 closed by the hold signal (stop signal).
6. Switches 26 and 27 (stop means) for applying a reverse bias voltage ± V ₂ to the diodes 16 a and 17 a of the minimum value detection circuit 17.

The waveform shaping circuit 10 'constructed as described above.
Then, when the hold signal (stop signal) is input after the shift amount of the level shifter 12 with respect to the input digital signal becomes an appropriate amount by the same loop control as described above, the value of the error signal Ve giving the appropriate shift amount is changed to the hold circuit. 25, the shift amount of the level shifter 12 is fixed to an appropriate amount. At this time, the diodes 16a, 1b of the two detection circuits 16, 17 of the intermediate voltage detection circuit 15 are used.
Since 7a is electrically separated from the digital signal line by the reverse bias voltage, it is possible to prevent the adverse effect (deterioration of high frequency characteristics) of diode connection to this line.

In the waveform shaping circuit 10 'shown in FIG. 5, the reverse bias voltage ± V ₂
Has been described simply applied to the maximum value detection circuit 16 and the minimum value detection circuit 17, but the diodes 16a and 17
When the constant current source 16c with respect to a, from 17c are making small current in the forward direction, the switching of the constant current source and the reverse bias voltage ± V _2, may be performed by a hold signal.

[0056] FIG. 6 is a constant current source 16c, by switching between 17c and the reverse bias voltage ± V _2, which shows a specific circuit configuration of the stop circuit 29 for stopping the detection operation of the intermediate voltage detecting circuit 15 .

The stop circuit 29 receives the hold signal as a stop signal, and switches the switches 26 'and 27' from the normal mode to the hold / limiter mode. In the normal mode, diodes 16a, 17
Since a small forward bias current is supplied to a from the constant current sources 16c and 17c as described above, the intermediate voltage detection circuit 15 detects the maximum value and the minimum value of the digital signal from the level shifter 12.

In the hold mode, the input digital signal is sufficiently larger than the maximum and minimum values (for example, 4
Volts) reverse bias voltage ± V ₂
a, 17a, the intermediate voltage detection circuit 15
Stops the operation of detecting the maximum value and the minimum value.

In the limiter mode, the diode 1
6a, 17a of the forward voltage drop 0.7 volts expectation of 1.3 volts of reverse bias voltage ± V ₂ is a diode 16a, to be added to 17a, a limiter at approximately ± 2V to the input digital signal You can call.

As described above, in the circuit of FIG. 6, the voltage set as the reverse bias voltage ± V ₂ is variably controlled to be 4 volts or 1.3 volts depending on the state at that time. Both the hold mode and the limiter mode can be switched and used together with the above-mentioned normal mode. Note that, in FIG.
7d is a buffer amplifier.

If the stop circuit 29 is configured as shown in FIG. 7, it is possible to operate the diodes 16a and 17a as limiters in both the normal mode and the hold mode.

In the stop circuit 29 shown in FIG. 7, a reverse bias voltage ± V _{3 of} about 0.6 volt is always applied to the diodes 16a and 17a via the diodes 30 and 31. The switch 2 on the maximum value detection circuit 16 side
A constant current source 17c on the minimum value detection circuit 17 side is connected to the hold side of 6 ', and a constant current source 16c on the maximum value detection circuit 16 side is connected to the hold side of the switch 27' on the minimum value detection circuit 17 side. Is connected.

For this reason, in the normal mode, the diodes 16a and 17a are connected to the respective constant current sources 16c and 16c.
The forward bias from 17c is applied to detect the maximum value and the minimum value of the input digital signal in the same manner as in the circuit of FIG.

However, in this normal mode,
When the output voltage from the level shifter 12 becomes lower than -2 V, the diode 17a and the diode 31 of the minimum value detection circuit 17 conduct, so that the minimum value detection circuit 17 side has-.
Limiter will can take at 2V (-V ₃ -1.4V).

In the normal mode, when the output voltage from the level shifter 12 becomes higher than +2 V, the diode 16a and the diode 30 of the maximum value detection circuit 16 become conductive, so that the maximum value detection circuit 16 becomes + 2V.
(+ V ₃ +1.4 V), the limiter is applied.

In the above description, -1.4 V is the voltage drop at the diodes 17a and 31 and + 1.4V is the voltage drop at the diodes 16a and 30.

In the hold mode, diodes 16a and 17a are connected to constant current sources 17c and 16c, respectively.
The reverse bias from the c side stops the operation of detecting the maximum value and the minimum value for the input digital signal.

However, in this hold mode,
If the output voltage from the level shifter 12 is lower than −2 V or higher than +2 V if ± V ₁ = ± 1.3 V is set, −2 V or +2 V respectively as in the normal mode described above. The limiter starts to work.

As the hold circuit 25 shown in FIGS. 5, 6, and 7, a digital hold circuit can be used as shown in FIG. 8 in addition to the analog hold circuit.

The hold circuit 25 shown in FIG. 8 converts the error signal Ve from the control circuit 21 into a digital value by the A / D converter 32, and converts the digital value when the hold signal (switch signal) is input. It is stored in the memory circuit 33. The digital value stored in the memory circuit 33 is converted to an analog voltage by a D / A converter 34,
Is output to the level shifter 12 via the.

The switch circuit 35 outputs the error signal from the control circuit 21 to the level shifter 12 as it is when the hold signal is not input, and outputs the signal from the D / A converter 34 when the hold signal is input. Is output. Such a digital hold circuit is advantageous when a long-time hold operation is required because there is no change in the hold output as compared with an analog hold circuit.

Further, in the above description, the subtractor 22 and the low-pass filter 23 are configured separately as specific circuits of the control circuit 21, but as shown in FIG.
The control circuit can be simplified by using an integrating circuit in which the output of 1a is fed back by the capacitor 21b.

In the above embodiment, when it is desired to know the shift amount in the level shifter 12, the error signal V
Reading the magnitude of e with a voltmeter, as shown in FIG.
If the difference between the average DC voltage between the input and output of the level shifter 12 detected by the integrating circuit of the resistor R ₅ and the integrating circuit of the capacitor C ₅ is read by the voltmeter 37, the level shifter 12
Can be known. Also, the threshold level of the input digital signal can be known from the level shift amount. When the digital hold circuit 25 shown in FIG. 8 is used, the shift amount in the level shifter 12 can be detected by the A / D converter 32, so that the circuit shown in FIG. 10 is unnecessary.

In the above embodiment, the waveform shaping circuit used at an ultra-high frequency has been described. However, the waveform shaping circuit of the present invention can be applied to a waveform shaping circuit in a low frequency band.

Further, as the comparator, not only the gallium-arsenic type FET of the above-described embodiment but also, for example, a comparator formed of a silicon bipolar transistor or a hetero bipolar transistor (HBT) may be used. . As the level shifter, in addition to the configuration of the above-described embodiment, various types such as a level shifter including a DC blocking capacitor and a high-frequency blocking coil can be used.

[0076]

Third Embodiment Next, a digital signal analyzer using the above-described waveform shaping circuit will be described.

FIG. 11 is a block diagram showing the configuration of a third embodiment in which the digital signal analyzer of the present invention is applied to an error measuring device.

This error measuring device shapes the waveform of the data signal to be measured which is input together with the clock signal, identifies the binary decision at a timing synchronized with the input clock signal, and inputs the identified signal. It is configured to compare with the data of the reference signal corresponding to the obtained digital signal.

The data signal to be measured is input to a waveform shaping circuit 50 having the same configuration as the waveform shaping circuit 10 shown in FIG.

That is, the data signal to be measured inputted from the input terminal 51 is terminated by the input resistance R ₀ (for example, 50Ω) and inputted to the level shifter 52. Level shifter 52
Varies the DC average (offset) voltage of the input measured data signal according to the magnitude of the error signal Ve.

The output of the level shifter 52 is input to the intermediate voltage detection circuit 55 and the comparator 60. The intermediate voltage detection circuit 55 converts a high level peak voltage and a low level peak voltage of the digital signal output from the level shifter 52 into a high level peak detection circuit (maximum value detection circuit) 56 and a low level peak detection circuit (minimum value). (Detection circuit) 57, and outputs an intermediate voltage Vo from the middle point between two equal resistors R.

The intermediate voltage Vo is supplied to the reference voltage generator 5
9 together with the reference voltage (threshold voltage) Vr from the first control circuit 61.

First control circuit 61 as first control means
Is a low-pass filter (hereinafter, LP) that outputs an error signal Ve obtained by integrating a subtraction output of the subtraction circuit 62 with a subtraction circuit 62 that detects a difference between the reference voltage Vr and the intermediate voltage Vo.
The shift amount of the level shifter 52 is feedback controlled so that the intermediate voltage Vo always approaches the reference voltage Vr.

The comparator 60 outputs a high-level digital signal when the digital signal output from the level shifter 52 is higher than the reference voltage Vr, and outputs a low-level digital signal when the digital signal is lower than the reference voltage Vr, and shapes the waveform of the input digital signal.

As described above, the configuration described above is exactly the same as that of the waveform shaping circuit 10 shown in FIG. 1, and the details and modifications of each unit are as described above.

On the other hand, the clock signal input to the input terminal 70 is input via the variable delay unit 71 to the discriminator 72 and the error measuring unit 75 which is an error measuring unit. The variable delay unit 71 delays the input clock signal according to the control signal, and relatively varies the phase of the clock signal with respect to the data signal under measurement. As the variable delay device 71,
A variable-length slab line structure in which the amount of delay is varied by varying the signal line length by slag is used for ultra-high frequencies.

The discriminator 72 performs a binary decision on the level of the digital signal output from the comparator 60 at the rising (or falling) timing of the clock signal input from the variable delay unit 71, and determines the discrimination output. Output to the error measuring unit 75.

An error measuring unit 75, which is a data analyzing unit of the error measuring device according to this embodiment, includes a reference data generator 76,
It comprises a sign comparator 77, a mismatch counter 78 and a clock counter 79.

The reference data generator 76 outputs the reference data having the same pattern as the data to be measured to the variable delay device 7.
The signal is output to the sign comparator 77 at a timing synchronized with the clock signal from the first signal.

The sign comparator 77 judges whether the sign of the output of the discriminator 72 matches the sign of the reference data, and outputs a mismatch signal to the mismatch counter 78 in the case of mismatch.

The mismatch counter 78 is provided in the control unit 8 described later.
While receiving the gate signal from 0, counting of the mismatch signal is continuously performed. The clock counter 79 includes the control unit 8
While receiving the gate signal from 0, the clock signal output from the variable delay unit 71 is counted.

The control section 80 as the second control means of the error measuring device is constituted by a microprocessor (CPU) or the like, and mainly has two processing modes.

That is, in the first processing mode, after the non-coincidence counter 78 and the clock counter 79 are simultaneously counted for a predetermined period of time, the counting results of both counters are read, and the calculation of the bit error rate is performed. This is a normal measurement process to be displayed at 81. In the second processing mode, before the measurement processing, the delay amount with respect to the clock signal of the variable delay unit 71 is continuously varied in a predetermined range, error rate data for the delay amount is obtained, and stored in the memory 80a. This is the optimum delay amount detection processing for detecting the delay amount at which the error rate is minimized.

The A / D converter 65 shown in FIG. 11 is configured to output the error signal V from the first control circuit 61 of the waveform shaping circuit 50.
e is converted to a digital value, and this value is
Is output to the control unit 80 as the shift amount of. Control unit 80
Stores the shift amount in the memory 80a or displays the shift amount on the display 81.

Next, the operation of the error measuring device will be described.

When the measured data signal and the clock signal are input to the input terminals 51 and 70, respectively, the waveform shaping circuit 50 refers to the intermediate voltage Vo between the high level and the low level of the input measured data signal. The shift amount is controlled in a direction to match the voltage Vr.

This operation is exactly the same as the operation described with reference to FIG.

For this reason, from the comparator 60, FIG.
As shown in FIG. 2A, the threshold voltage (reference voltage) V
The data signal to be measured which is shaped by r and has no fluctuation in the amplitude direction is output.

The fact that the shift amount of the level shifter 52 has become stable can be determined by displaying the shift amount from the A / D converter 65 on the display 81 or by performing the stability determination processing by the control unit 80 itself. You can check.

Next, the control unit 80 performs the above-described optimum delay amount detection processing.

That is, after inputting the gate signal to the clock counter 79 for a predetermined time, the control unit 80 obtains the period T of the clock signal from the count result. Then, as shown in (b ₁ ), (b ₂ ), and (b ₃ ) of FIG. 12, the delay amount of the variable delay unit 71 is changed from the initial value D ₀ to at least one cycle of the clock signal in a predetermined step d. The error rate is obtained for each predetermined step while changing the result, and the result is stored in the memory 80a.
To memorize.

FIG. 12C shows a change in the error rate with respect to a change in the delay amount stored in the memory 80a.
As is apparent from this figure, the rising edge of the clock signal from (b ₁ ) to (b ₃ ) in the figure with respect to the output signal ((a) in the figure) of the comparator 60 having a fluctuation in the phase component. The change in the error rate when the timing is varied by 1.5 cycles becomes the maximum at the state transition point of the output signal of the comparator 60, and two maximum points are obtained.

Based on the stored error rate data, the control unit 80 determines, for example, the delay amounts D ₂ and D _{6 at which the} error rate is maximized.
The intermediate value D _4, is automatically set to the variable delay unit 71 as the optimum delay amount with most phase margin.

After making the above settings, the control unit 80
A normal error measurement process is performed, and the measured error rates are sequentially displayed on the display 81.

The level shift amount from the A / D converter 65 and the threshold level of the measured data signal calculated from the level shift amount and the reference voltage Vr to the comparator 60 are also displayed on the display 81 as needed. .

Further, in the error measuring apparatus of the third embodiment, the result of subtraction between the intermediate voltage and the reference voltage is input to the level shifter 52 via the LPF 63, but as shown in FIG. The result is digitally converted by the A / D converter 65 into subtraction data, a shift amount for the subtraction data to approach zero is calculated by the arithmetic control unit 90, and the calculated shift amount data is converted into a D / A converter. The signal may be sent to the control signal 66 to control the shift amount of the level shifter 52. It should be noted that the arithmetic control unit 90 includes a control unit 80
Together with one CPU.

Further, the intermediate voltage output from the intermediate voltage detecting circuit 55 is directly A / D converted, and
And the arithmetic control unit 90 compares the intermediate voltage data with the reference voltage data, and outputs shift amount data corresponding to the difference to the level shifter 52 via the D / A converter 65. It is possible. In this case, the arithmetic control unit 90 becomes the first control unit.

In the third embodiment, in order to set the optimum delay amount for the clock signal, the maximum error rate obtained by varying the delay amount over one cycle of the clock signal is calculated as follows. Although the optimum value has been determined, the delay amount at which the error rate becomes the minimum value may be set as the optimum value as it is. This large phase fluctuation of the input or output signal is an effective method when a very narrow flat portions between D ₅ from D ₃ of FIG. 12 (c).

Further, two delay amounts that give an equal error rate instead of the maximum error rate as in the above embodiment (for example, FIG. 1)
Alternatively, an intermediate value of D ₃ and D ₅ ) may be set as the optimum delay amount.

By operating input means such as a switch provided on the display, a series of operations for setting an optimum threshold voltage of the data signal to be measured is started, and after the operation is completed, an optimum delay amount is set. May be performed, and the set threshold level and delay amount may be displayed on the display.

In the third embodiment, the phase on the clock signal side is delayed. However, this is not a limitation of the present invention. For example, as shown in FIG. It may be provided between the input terminal 51 on the data signal under measurement side and the level shifter 52. Further, the variable delay unit 71 is connected between the level shifter 52 and the comparator 60, or
It may be provided between the comparator 60 and the discriminator 72.

Also, in the third embodiment, the waveform shaping of the input signal is performed by the waveform shaping circuit 50 having the same configuration as the waveform shaping circuit 10 shown in FIG. The waveform shaping circuit 10 'of the second embodiment (FIG. 5) having the function of stopping the operation of the voltage detection circuit 55 may be used. Similarly, the circuit having the limiter function shown in FIGS. 6 and 7 as a modification of FIG. 5 may be used.

Further, the circuit shown in FIG.
5, the digital hold circuit described with reference to FIG. 8 may be formed.

The arithmetic and control unit 90 of this configuration determines by itself that the loop of the waveform shaping circuit 50 is stably at the optimum shift amount, and outputs a hold signal (stop signal) to the switch circuit 35 and the stop circuit. 69, the optimum shift amount is fixedly set to the level shifter 52, and the detection operation of the intermediate voltage detection circuit 55 is stopped (the stop circuit 69 has the same configuration as the stop circuit 29 described above).

As described above, the arithmetic control unit 90 for controlling the setting of the optimum shift amount to the level shifter 52 and the stop control of the intermediate voltage detecting operation, and the control unit for controlling the setting of the optimum delay amount for the variable delay unit 71. If the CPU 80 is constituted by one CPU, the processing for setting the optimum shift amount and the processing for setting the optimum delay amount for the data signal to be measured are continuously performed by a series of programs by a simple key operation or the like. In addition, there is an advantage that data can be exchanged with another device easily by using the communication function of the CPU.

FIG. 16 shows a more specific example of the error measuring apparatus according to the third embodiment of the present invention. In particular, FIG. 16 shows an example of an apparatus for measuring an error of a data signal to be measured of an ultra-high frequency.

In FIG. 16, the input data applied to the waveform shaping circuit 101 and the input clock applied to the variable delay unit 102 are respectively optimized as described above and output to the discriminator 103.

The data identified by the identifier 103 as described above is supplied to the 1 / N demultiplexer 104 by the 1 / N clock generated from the timing generator 105 based on the output clock of the variable delay unit 102. Demultiplexed to 1 / N. For example, if the input data is 10 GHz and N = 32, the input data is 3
The signal is demultiplexed to 10 MHz, and the error is detected by the error detector 106 as 32 channel data. This error result is displayed on the display unit 1 via the error counting unit 107.
08 and the synchronization control unit 109. The reference pattern generation section 110 generates reference pattern data to be provided to the error detection section 106 according to the output from the synchronization control section 109.

The error detector 106, the reference pattern generator 110, the error counter 107, and the synchronization controller 10
9 is controlled by the 1 / N clock from the timing generator 105. A control unit 111 including a CPU controls each unit. Note that the auto search unit 112 controls the waveform shaping circuit 101 and the variable delay unit 102 under the control of the control unit 111 so that each of them is in an appropriate state as in the above-described embodiments.

In this error measuring device, the data signal identified at the optimal timing by the identifier 103 is divided into 1 / N-speed parallel data and error-determined as in the previous embodiment. The error measurement of the data signal can be reliably performed.

Although the above embodiment has been described with respect to an example in which the digital signal analyzing apparatus of the present invention is applied to an error measuring apparatus, the present invention can be similarly applied to other digital analyzing apparatuses such as a logic analyzer.

[0122]

As described above, the waveform shaping circuit of the present invention determines the DC offset voltage of the input digital signal, that is, the intermediate voltage between the high-level voltage and the low-level voltage of the output signal of the level shifter. The shift amount of the level shifter is controlled in a direction approaching the threshold value, and the output signal of the level shifter is configured to be waveform-shaped at a predetermined threshold value.

For this reason, the center of the amplitude of the digital signal input to the comparator is always driven to a state in which it matches the predetermined threshold value without troublesome waveform observation or manual adjustment, and a reliable waveform is obtained. Shaping can be performed.

Further, in the holding circuit for holding the magnitude of the error signal with respect to the level shifter and the waveform shaping circuit having the stopping means for stopping the operation of the intermediate voltage detecting circuit, the shift amount can be fixed to an appropriate amount. This has the effect of not deteriorating the high-frequency characteristics of the signal path.

Further, as described above, the digital signal analyzer of the present invention provides an error signal obtained by relatively varying the phase of the digital signal and the clock signal output from the waveform shaping circuit by a predetermined range. Based on the measurement results,
Detects the amount of delay required to enter the discrimination timing at the optimum position between adjacent state transition points of the digital signal input from the comparator to the discriminator, and sets the delay amount to the variable delay unit. Have been.

Therefore, the operation point and identification timing of the waveform shaping by the comparator can be changed without error or individual difference due to waveform disturbance without complicated manual voltage adjustment and phase adjustment operation while observing the waveform. With, it can be set to the optimal state.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific circuit of a main part of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a specific circuit of a main part of FIG. 1;

FIG. 4 is a signal diagram for explaining the operation of one embodiment.

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a modification of the main part of the second embodiment.

FIG. 7 is a circuit diagram showing a modification of the main part of the second embodiment.

FIG. 8 is a circuit diagram showing a modification of the main part of the second embodiment.

FIG. 9 is a circuit diagram showing a modification of the main part of the first and second embodiments.

FIG. 10 is a circuit diagram for directly reading a shift amount.

FIG. 11 is a block diagram showing a configuration of a third example of the present invention.

FIG. 12 is a diagram for explaining the operation of the third embodiment.

FIG. 13 is a main part block diagram showing a modification of the third embodiment.

FIG. 14 is a block diagram showing another modification of the third embodiment.

FIG. 15 is a block diagram showing another modification of the third embodiment.

FIG. 16 is a block diagram more specifically showing a main part of the third embodiment.

FIG. 17 is a block diagram showing a configuration of a conventional device.

FIG. 18 is a signal diagram for explaining the operation of the conventional device.

[Explanation of symbols]

 10, 10 'Waveform shaping circuit 12 Level shifter 15 Intermediate voltage detecting circuit 16 Maximum value detecting circuit 17 Minimum value detecting circuit 18 Intermediate voltage output circuit 20 Comparator 21 Control circuit 22 Subtractor 23 Low-pass filter 25 Hold circuit 26, 27 Switch 29 Stop circuit 32 A / D converter 33 Memory circuit 34 D / A converter 35 Switch 37 Voltmeter 50 Waveform shaping circuit 52 Level shifter 55 Intermediate voltage detection circuit 60 Comparator 61 First control circuit 65 A / D converter 71 Variable delay Unit 72 discriminator 75 error measuring unit 76 reference data generator 77 sign comparator 78 mismatch counter 79 clock counter 80 control unit 81 display 90 operation control unit 101 waveform shaping circuit 102 variable delay unit 103 discriminator 104 1 / N demultiplexer 105 Timing generating unit 106 the error detection unit 107 the error counting section 108 display section 109 synchronization control unit 110 the reference pattern generating unit 111 CPU 112 auto search unit

Claims (3)

(57) [Claims] 1. A DC offset of an input digital signal.
A level shifter (12) for variably controlling the switching voltage, and converting a digital signal output from the level shifter into a predetermined signal.
Comparator for comparing with reference voltage, shaping waveform and outputting
(20), the maximum of the digital signal output from the level shifter
Maximum value detection circuit for detecting the value, minimum value of the digital signal
Minimum value detection circuit for detecting a value and the maximum value detection circuit
And the minimum value detected by the minimum value detection circuit.
It has an intermediate voltage output circuit that outputs an intermediate voltage
Of the digital signal output from the level shifter.
Detects and outputs an intermediate voltage between the bell voltage and the low level voltage.
Intermediate voltage detecting means (15) to be applied, an intermediate voltage output from the intermediate voltage detecting means,
Receiving a constant reference voltage and changing the intermediate voltage to the predetermined voltage.
To make the DC offset voltage equal to the reference voltage,
Control for outputting a control signal to be changed to the level shifter
Means (21), Holding the control signal output from the control means.
Holding means (25), When the control signal is held by the holding means,
Stopping means (2) for stopping the operation of the intermediate voltage detecting means;
6, 27) and Equipped waveform shaping circuit. (2)DC offset of the input digital signal
A level shifter (52) for variably controlling the gate voltage; The digital signal output from the level shifter is
Comparator for comparing with reference voltage, shaping waveform and outputting
(60) The maximum of the digital signal output from the level shifter
Maximum value detection circuit for detecting the value, minimum value of the digital signal
Minimum value detection circuit for detecting a value and the maximum value detection circuit
And the minimum value detected by the minimum value detection circuit.
It has an intermediate voltage output circuit that outputs an intermediate voltage
Of the digital signal output from the level shifter.
Detects and outputs an intermediate voltage between the bell voltage and the low level voltage.
While empowering Inter-voltage detection means (55); The intermediate voltage output from the intermediate voltage detecting means and
Receiving a constant reference voltage and changing the intermediate voltage to the predetermined voltage.
To make the DC offset voltage equal to the reference voltage,
Outputting a control signal to be changed to the level shifter;
Control means (61); Between the input clock signal and the output of the comparator
A variable delay (71) for relatively varying the phase between the two; The core whose phase is relatively varied by the variable delay device.
Receiving the output of the comparator and the clock signal,
Before the rising or falling edge of the lock signal
The discriminator (7) for determining the sign of the output signal of the comparator
2) The judgment signal from the discriminator and the input digital signal
Outputs an error signal by comparing with a reference signal corresponding to
An error measuring device (75); Receiving the output of the error measuring device, the error signal adjacent to each other is minimized.
Detects a delay that is almost halfway between the large delays, and
Then, the intermediate delay amount is sent to the variable delay device to
A second control for reducing the error signal output by the measuring instrument.
A digital signal analysis device provided with control means (80). (3)The control output from the first control means;
Holding means (25) for holding a control signal; When the control signal is held by the holding means,
Stopping means (2) for stopping the operation of the intermediate voltage detecting means;
6. The method according to claim 2, further comprising: De
Digital signal analyzer.