JP3161319B2 - Multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly, to a multiprocessor system that prevents the entire system from stopping when a master processor fails.

[0001]

2. Description of the Related Art In this type of conventional technology, when a master processor fails, the system is restarted with one of the remaining normal processors as a new master processor and the other processors as slave processors. I do. For example, Japanese Patent Application Laid-Open No. 61-253551 discloses that a service processor notified of a failure from a master processor disconnects the master processor from the system and makes one of the normally operating slave processors a new master processor. The technology is described.

[0002]

In the above-mentioned prior art,
A device such as a service processor is provided separately from the plurality of processors, and this device sets a master processor. Therefore, when a failure occurs in a device such as a service processor, there is a problem that the entire system stops.

[0003] An object of the present invention is to provide a multiprocessor system that prevents the entire system from stopping.

[0004]

In order to solve the above-mentioned problems, a multiprocessor system according to the present invention is a multiprocessor system including a plurality of processors and storage means accessed by the plurality of processors. Means for storing usable information indicating whether each of the plurality of processors is usable or not; each of the plurality of processors reading the usable information in the storage means; Selection means for selecting one of the plurality of processors that can be used based on the above, a specification means for specifying the processor selected by the selection means as a master processor, and when the specification means specifies a master processor. And preventing another processor of the plurality of processors from designating a master processor. And a stop means.

In another multiprocessor system according to the present invention, when the inhibiting means has successfully accessed the usable information by the selecting means, the other processors of the plurality of processors have the usable information. Includes means to prohibit access to.

Further, in another multiprocessor system according to the present invention, each of the plurality of processors may include, at the time of system initialization, information indicating that the own processor is usable as a part of the usable information. Setting means for writing to the storage means;

In another multiprocessor system according to the present invention, each of the plurality of processors activates the selecting means after the information setting process of the setting means is completed in all of the plurality of processors. Including a waiting means.

Further, another multiprocessor system of the present invention is activated when the setting means and the selecting means of the plurality of processors are initialized.

In another multiprocessor system according to the present invention, when a failure occurs in at least one of the plurality of processors, the system is initialized, and the setting means of the failed processor transfers the data to the storage means. It includes a cutting means for suppressing writing of information.

Further, in another multiprocessor system according to the present invention, the disconnection means electrically disconnects a transmission line connecting the failed processor and the storage means.

In another multiprocessor system according to the present invention, an identification number is given to each of the plurality of processors, and the selecting means selects a processor having the smallest identification number among available processors. .

In another multiprocessor system according to the present invention, an identification number is given to each of the plurality of processors, and the selecting means selects a processor having the largest identification number among available processors. .

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the multiprocessor system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in a multiprocessor system according to an embodiment of the present invention, processors 10 and 11 are connected to reset circuit 3 via buses 6 and 7, and reset circuit 3 connects buses 1 and 2 to each other. It is connected to the main storage device 5 through the main memory. Processors 12 and 13 are connected to reset circuit 4 via buses 8 and 9, and reset circuit 4 is connected to main storage device 5 via buses 1 and 2.

Each of the processors 10, 11, 12, and 13
Has dip switches 14, 15, 16 and 17 to which respective processor numbers are set.
Each DIP switch 14, 15, 16 and 17 has
Hexadecimal numbers 8, 9, A and B are set respectively. That is, each processor 10, 11, 12, and 1
The processor numbers of 3 are hexadecimal numbers 8, 9, and A, respectively.
And B are set.

The bus 1 is a data transmission path between the processors 10, 11, 12, and 13 and the main storage device.

The reset circuit 3 includes a failure information holding circuit 18 that stores failure information when a failure occurs in the connected processors 10 and 11. The failure information is sent from the processors 10 and 11 to the reset circuit 3 via the bus 7. When the failure information is stored, the reset circuit 3 sends a reset signal to the processors 10 and 11 to disconnect the connected processors 10 and 11 from the bus 1. At the same time, the reset circuit 3
A reset signal is also sent to the main storage device 5 via the bus 2.

The reset circuit 4 includes a failure information holding circuit 19 for storing failure information when a failure occurs in the connected processors 12 and 13. The failure information is sent from the processors 12 and 13 to the reset circuit 4 via the bus 9. When the failure information is stored, the reset circuit 4 sends a reset signal to the processors 12 and 13 to disconnect the connected processors 12 and 13 from the bus 1. At the same time, the reset circuit 4
A reset signal is also sent to the main storage device 5 via the bus 2.

Reset circuits 3 and 4 operate as a connection circuit between bus 1, bus 6 and bus 8 during normal operation.

The bus 2 is a transmission path used for transmitting a reset signal from the reset circuits 3 and 4 to the main storage device 5.

The main storage device 5 stores a processor number of each of a plurality of processors constituting the multiprocessor system and connection information indicating whether or not a processor corresponding to the processor number is connected. 200 is stored. The main storage device 5
Has a master processor number holding circuit 21 in which the processor number of the master processor is stored.

Referring to FIG. 1 and FIG. 2, connection information table 200 stores connection information 220 corresponding to processor number 21. Processors 10, 11, 12
And 13, the processor numbers of decimals 8, 9,
1 indicating that the processor is connected is stored in a location corresponding to A and B. In a location corresponding to another processor number, 0 indicating that the processor is not connected is stored.

Next, the operation of one embodiment of the multiprocessor system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, FIG. 2 and FIG. 3, when the power is turned on, all the processors simultaneously start the operation for registration in connection information table 200. Processor 1
0, 11, 12 and 13 are each DIP switch 1
The respective processor numbers are read from 4, 15, 16 and 17 (step 31). Each processor writes 1 to the connection information 220 of the corresponding processor number 21 in the connection information table 200 by the read processor number (step 32). Each processor waits for a certain period of time until the other processors constituting the multiprocessor system complete the operations of steps 31 and 32 (step 33). After a certain period of time, access to the connection information table 200 is started (step 3).
4).

Referring to FIG. 1, FIG. 2 and FIG. 4, the processor that first accesses the connection information table has exclusive use right and sends a lock command to other processors constituting the multiprocessor system ( Step 42). Here, the description will be given on the assumption that the processor that first accesses the connection information table is the processor 12. The processor 12 sets an internal counter to 0 (Step 42). Using the internal counter as the processor number, it is determined whether or not the connection information 220 of the connection information table 200 corresponding to this processor number is 1 (step 43). If the connection information 220 is 0, the content of the internal counter is increased by 1 (step 4).
4) Return to step 43 operation.

When the internal counter reaches 8, the connection information 2
The value of 20 becomes 1. The processor 12 has the processor 1 having the processor number of the internal counter value 8 at this time.
0 is selected, and the processor 10 is set as a master processor (step 45). After the master processor is set in step 45, the processor 12 writes the processor number of the master processor in the master processor number holding circuit 21 of the main storage device 5 (step 4).
6). The processor 12 sends an unlock command to the other processors 10, 11 and 13 constituting the multiprocessor system (step 47), and the processor 1
The operation of selecting and designating the master processor in 2 is completed. Each of the processors 10, 11, 12, and 13 constituting the multiprocessor system includes a main storage device 5
The master processor number written in the master processor number holding circuit 21 is read. The processor 10 recognizes that it is the master processor and starts operating as the master processor. Processors 11 and 12
And 13 each include a master processor number holding circuit 2
A master processor number of 1 identifies which processor is the master processor.

Referring to FIG. 1, when a failure occurs in the processor 10 during operation of the multiprocessor system using the processor 10 as a master processor, failure information is sent to the reset circuit 3 via the bus 7. The reset circuit 3 holds the failure information and sends a reset signal to the processors 10 and 11 connected to the reset circuit 3. By this processing, the failed processor 10 is disconnected from the multiprocessor system. The reset circuit 3 also sends a reset signal to the main storage device 5 and resets the connection information table 200 and the master processor number holding circuit 21 with this reset signal.

When the power is turned on during the execution of the restart operation, all the processors are connected again to the connection information table 2.
The operation for registration to 00 is started. Reset circuit 3
, The reset signal is continuously transmitted to the processor 10 in the fault state and the processor 11 connected to the same reset circuit 3 as the processor 10. Thus, processors 10 and 1
1 remains disconnected from the multiprocessor system.

Since the processors 10 and 11 are separated, a multiprocessor system is constituted by the processors 12 and 13. Processors 12 and 1
3 performs the operation for registration in the connection information table 200 shown in FIG. 3 again. Processors 12 and 13
Performs again the operation of selecting and specifying the master processor shown in FIG. 4, and as a result, processor 12 operates as the master processor.

When the processor 10 is released from the fault state, the fault information of the reset circuit 3 is erased, so that the processors 10 and 11 are incorporated in the multiprocessor system again and operated.

As described above, according to the multiprocessor system of one embodiment of the present invention, the connection information table 200 for storing the connection information of the plurality of processors 10, 11, 12, and 13 constituting the multiprocessor system is provided. By using this table to select and designate the processor having the smallest processor number connected as the master processor, it is possible to select and designate the master processor without providing a device such as a service processor. it can.

Further, when a failure occurs in the master processor, a failure information holding circuit 1 for storing information on the failure is provided.
8 and a reset circuit 3 for transmitting a reset signal and disconnecting the failed master processor. For this reason, the failed master processor can be disconnected from the multiprocessor system, and the processor having the lowest processor number among the remaining normally operating processors can be determined as the master processor, and the system can be started, thereby preventing the entire system from stopping can do.

Further, a reset circuit is provided between the bus 1 and the bus 6 to disconnect the connection therebetween. For this reason, it is possible to prevent data from being transmitted to the bus 6 by the failed processor and from propagating the data to the entire multiprocessor.

Next, a second embodiment of the multiprocessor system of the present invention will be described in detail with reference to the drawings.

The second embodiment differs from the first embodiment only in that a reset circuit is provided for each processor, and otherwise operates in the same manner as the first embodiment.

Referring to FIG. 5, a reset circuit 22 is provided between the bus 6 and the bus 7 and the processor 10, and a reset circuit 23 is provided between the bus 6 and the bus 7 and the processor 11.
A reset circuit 24 between the buses 8 and 9 and the processor 12;
And a reset circuit 25 between them.

When a failure occurs while the processor 10 is operating as the master processor, the processor 10 sends failure information to the reset circuit 22. The reset circuit 22 sends a reset signal to the processor 10 and outputs the reset signal to the processor 1.
Disconnect 0.

As described above, according to the second embodiment of the present invention, since the reset circuit is provided for each processor, when disconnecting a failed processor, a non-failed processor can be disconnected. Effective use of resources can be achieved.

[0039]

As is apparent from the above description, according to the present invention, the bus connected to the failed master processor is disconnected, and the processor having the smallest processor number among the remaining normally operating processors is removed. Since the system is determined as the master processor and the system is started, it is possible to prevent the entire system from stopping.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multiprocessor system according to the present invention.

FIG. 2 is a diagram showing one embodiment of a connection information table of the present invention.

FIG. 3 is a diagram showing an operation of processing for storing connection information in a connection information table according to the present invention.

FIG. 4 is a diagram showing an operation of a master processor selection and designation process of the present invention.

FIG. 5 is a diagram showing a configuration of a multiprocessor according to a second embodiment of the present invention.

[Explanation of symbols]

 1, 2 bus 3, 4 reset circuit 5 main storage device 6, 7, 8, 9 bus 10, 11, 12, 13 processor 14, 15, 16, 17 dip switch 18, 19 failure information holding circuit 200 connection information table 210 Master processor number holding circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/177 678

Claims (7)

(57) [Claims] 1. A plurality of processors, a main memory instrumentation to be accessed by the plurality of processors
Connecting location and, between any of the plurality of processors
A plurality of connection means; and a plurality of connection means connected between the plurality of connection means and the main storage device.
The main storage device stores usable information indicating whether each of the plurality of processors is usable, and each of the plurality of processors includes: , rated in the main storage device
Specifying a selecting means for selecting the one of those available among the plurality of processors based on the available information by reading the available information paid has been, a processor selected by the selection unit as a master processor Designating means, and suppressing means for suppressing, when the designating means designates a master processor, another processor of the plurality of processors designating a master processor ;
When the system is initialized, it is automatically included as part of the
The information indicating that the processor can be used is described in the main note.
Look including a setting means for writing the憶device, said reset circuit is small among said plurality of processors
Initialize the system when at least one fails
Processor that failed and the
Connects to the connection means to which the failed processor is connected
The setting means of the processor to be executed stores information in the main storage device.
A multiprocessor system characterized in that writing of information is suppressed . 2. The information processing apparatus according to claim 1, wherein the inhibiting unit includes a unit that inhibits another processor of the plurality of processors from accessing the available information when the selecting unit successfully accesses the available information. The multiprocessor system according to claim 1, wherein: 3. Each of the plurality of processors includes a queuing unit that activates the selection unit after the information setting process of the setting unit is completed in all of the plurality of processors. The multiprocessor system according to claim 2 . 4. The multiprocessor system according to claim 2 , wherein said setting means and said selecting means of said plurality of processors are activated when the system is initialized. Wherein said cutting means is a multi-processor system according to claim 1, wherein the electrically disconnecting the transmission line connecting the said main storage device and the failure processor. 6. A given each identification number of said plurality of processors, said selecting means, according to claim 1, wherein the selecting the one having the smallest identification number among the processors can be used Multiprocessor system. 7. An apparatus according to claim 1, wherein an identification number is given to each of said plurality of processors, and said selecting means selects a processor having the largest identification number among available processors. Multiprocessor system.