JP3157151B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a phase-locked loop circuit (hereinafter referred to as a PLL) which is used for a communication device and a broadcasting device, and is adjusted to a substantially constant voltage value and operates by a reference voltage. Circuit)
And a semiconductor integrated circuit having a reference voltage generation circuit for generating the reference voltage.

(Prior art) Conventionally, as for technology in such a field,
For example, there was one as shown in FIG.

FIG. 2 is a schematic block diagram showing an example of a conventional semiconductor integrated circuit.

This semiconductor integrated circuit has an input terminal 1 and a control terminal 2 for inputting a timing signal Sin as an input signal from an external circuit and a power down instruction signal Sd as a digital signal, respectively. The control terminal 2 is connected to, for example, a reference voltage generating circuit 3, an analog PLL circuit 4, and a signal processing unit 5, respectively.

The reference voltage generation circuit 3 receives the supply voltage VDD, for example, and adjusts the reference voltage VRE to a substantially constant voltage value.
A circuit for generating F, and a power-down means 3a for shifting the circuit to a power-down mode (function stop state) by a power-down instruction signal Sd is provided.

The PLL circuit 4 is a circuit that receives the timing signal Sin from the input terminal 1 and tracks the phase thereof, and outputs an internal timing signal Sout that is an output signal synchronized with the timing signal Sin. 1, an analog filter 4-2, a voltage controlled oscillator (VCO) 4-3, and a frequency divider 4-4.

Here, the phase comparator 4-1 is a circuit that compares the phase of the timing signal Sin with the output signal of the frequency divider 4-4 and generates a voltage corresponding to the phase difference. Reference numeral 2 denotes, for example, a low-pass filter for smoothing the output voltage of the phase comparator 4-1 and extracting a voltage component proportional to the phase difference. The voltage-controlled oscillator 4-3 is a circuit whose oscillation frequency is controlled by the output voltage of the analog filter 4-2 and outputs an internal timing signal Sout synchronized with the timing signal Sin. This is a circuit for dividing the timing signal Sout and feeding it back to the phase comparator 4-1. The analog filter 4-2 and the voltage-controlled oscillator 4-3 are configured to operate based on the reference voltage VREF, for example, as an analog unit, and each of the circuits is shifted to a power-down mode by a power-down instruction signal Sd. Power down means 4-2a and 4-
3a is provided. The signal processing unit 5 is connected to the PLL circuit 4.

For example, the signal processing unit 5 supplies P
A switch circuit 5a for switching the supply of the reference voltage VREF based on the power-down instruction signal Sd in the power-down mode, and an internal timing signal based on the power-down instruction signal Sd. A gate circuit 5b for switching the supply of Sout, and a gate circuit 5b receiving a reference voltage VREF via a switch circuit 5a.
And a signal processing circuit 5c for performing a signal distance of the internal timing signal Sout input through the signal processing circuit 5c.

 Next, the operation will be described.

When the power down instruction signal Sd is not input to the control terminal 2 (during the power-on mode), the reference voltage VREF is generated by the reference voltage generation circuit 3 and supplied to the PLL circuit 4 and the signal processing unit 5; Timing signal via 1
Sin is input to the PLL circuit 4.

When the timing signal Sin is input to the PLL circuit 4, the phase comparator 4-1 compares the timing signal Sin with the internal timing signal fed back from the voltage controlled oscillator 4-3 via the frequency divider 4-4. The phases are compared, and a voltage corresponding to the phase difference is output.
2 to the voltage-controlled oscillator 4-3. Then, the voltage controlled oscillator 4-3 oscillates at an oscillation frequency that eliminates the phase difference and outputs the internal timing signal Sout. Thus, the PLL circuit 4 outputs the timing signal S
It tracks in and outputs an internal timing signal Sout synchronized with the timing signal Sin to the signal processing unit 5.

In the signal processing unit 5 to which the internal timing signal Sout is input, the internal timing signal Sout is input to the signal processing circuit 5c through the gate circuit 5b, and the signal processing circuit 5c receives the reference voltage VREF input through the switch circuit 5a. Performs signal processing of the internal timing signal Sout. In this manner, the semiconductor integrated circuit of FIG. 2 operates in a normal state (power-on mode).

When the power down instruction signal Sd is input to the control terminal 2, the power down instruction signal Sd is transmitted to the power down means 3a of the reference voltage generating circuit 3, the power down means 4-2a of the analog filter 4-2, the voltage controlled oscillator. 4-3 Power Down Means 4-3a, Switch Circuit 5a, and Gate Circuit 5b
Is input to each of. Then, in this semiconductor integrated circuit, the reference voltage generating circuit 3 and the PLL circuit 4 are brought into a function stop state by the power down means 3a, 4-2a, and 4-3a, and the signal processing circuit is turned on by the switch circuit 5a and the gate circuit 5b. 5c enters the function stop state and shifts to the power down mode.

FIG. 3 is a schematic block diagram showing another example of a conventional semiconductor integrated circuit. In the figure, the same elements as those in FIG. 2 are denoted by the same reference numerals.

This semiconductor integrated circuit has a reference voltage generating circuit 3A and a PLL circuit 4A in addition to the input terminal 1 and the signal processing unit 5 similar to those of the semiconductor integrated circuit of FIG.

The reference voltage generating circuit 3A has substantially the same configuration as the reference voltage generating circuit 3, but does not include the power down means 3a.

The PLL circuit 4A has a phase comparator 4-
1 and a frequency divider 4-4, and an analog filter 4-2.
An analog filter 4-5 having no power down means 4-2a, and a voltage controlled oscillator 4-6 having a voltage controlled oscillator 4-3 having no power down means 4-3a.
It has newly provided out-of-synchronization detecting means 4-7. Here, the out-of-synchronization detecting means 4-7 uses, for example, a PLL based on an output voltage corresponding to the phase difference from the phase comparator 4-1.
The circuit 4A has a function of detecting an out-of-synchronization signal and outputting, for example, an out-of-synchronization signal Sa which is a digital signal, and is constituted by, for example, a gate circuit or the like.

This semiconductor integrated circuit operates similarly to the semiconductor integrated circuit of FIG. 2 during normal operation (during power-on mode),
The operation of shifting to the power down mode is performed as follows.

When the semiconductor integrated circuit is shifted to the power down mode, for example, the supply of the timing signal Sin to the input terminal 1 is stopped in the external circuit that outputs the timing signal Sin. As a result, the timing signal Sin
No longer supplied to the circuit 4A, the tracking operation by the internal timing signal Sout is not performed, and the PLL circuit 4A loses synchronization. Then, the phase comparator 4 of the PLL circuit 4A
In response to the output of -1, the out-of-synchronization detecting means 4-7 detects the out-of-synchronism and outputs the out-of-synchronization signal Sa to the switch circuit 5a and the gate circuit 5b of the signal processing unit 5. When the out-of-synchronization signal Sa is input to each of the switch circuit 5a and the gate circuit 5b, the signal processing unit 5 shifts to the power down mode and enters a function stop state.

(Problems to be solved by the invention) However, the semiconductor integrated circuit having the above configuration has the following problems.

In the semiconductor integrated circuit shown in FIG. 2, power down control is performed by supplying a power down instruction signal Sd to the control terminal 2 and the reference voltage generating circuit 3, the PLL circuit 4, and the signal processing unit 5 are all controlled. Power down and power on are performed at the same time. Therefore, in this semiconductor integrated circuit, the control terminal 2 for power down control is required, and the number of terminals increases when, for example, an IC chip is formed.

In the semiconductor integrated circuit shown in FIG.
Power down control of the signal processing unit 5 can be performed by Sa,
The power down control of the reference voltage generation circuit 3A and the PLL circuit 4A cannot be performed. When the power down control of the reference voltage generating circuit 3A and the PLL circuit 4A is to be performed by the out-of-synchronization signal Sa, the transition from the power-on mode to the power-down mode can be performed by the out-of-synchronization signal Sa. But,
In that case, the reference voltage generation circuit
Once the 3A and the PLL circuit 4A are shifted to the power down mode, the timing signal Si is input to the input terminal 1 when the mode is shifted from the power down mode to the power on mode.
Even if n starts to be input, the reference voltage generator 3A and the PLL circuit
4A is still in power-down mode, so PLL circuit 4
A does not perform the synchronization pull-in operation, the out-of-synchronization signal Sa remains output, and the out-of-synchronization of the PLL circuit 4A is not recovered. As described above, in the semiconductor integrated circuit of FIG. 3, since the power down control cannot be performed on the reference voltage generating circuit 3A and the PLL circuit 4A, the power consumption in the power down mode cannot be sufficiently reduced. The power consumption in the power down mode increases as compared with the circuit of FIG.

An object of the present invention is to provide a semiconductor integrated circuit which solves the problem of the prior art that the number of terminals is increased or power consumption at power down is increased.

(Means for Solving the Problems) In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention is supplied with a third voltage and tracks the phase of an input signal that is input. A PLL circuit that outputs an output signal synchronized with the input signal, and outputs an out-of-sync signal based on a phase shift between the input signal and the output signal;
A first voltage necessary for driving the circuit is generated based on a power supply voltage, and when the out-of-sync signal is input, the first voltage is generated.
A voltage generation circuit for stopping generation of a voltage, a power supply voltage dividing circuit for dividing the power supply voltage and generating a second voltage,
A selector configured to supply one of the first voltage and the second voltage to the PLL circuit as the third voltage based on the out-of-sync signal.

According to a second aspect, in the semiconductor integrated circuit according to the first aspect, the PLL circuit compares a phase of the frequency of the output signal with a phase of the input signal and the phase of the frequency-divided output signal. A phase comparator that outputs a comparison result, an out-of-synchronization detection unit that outputs the out-of-sync signal based on the comparison result, an analog filter that smoothes the comparison result, and the output based on an output of the analog filter. And a voltage-controlled oscillator for outputting a signal.

(Operation) According to the first and second aspects of the present invention, since the semiconductor integrated circuit is configured as described above, when the semiconductor integrated circuit is in the power-on mode, the voltage generation circuit is, for example, substantially constant based on the power supply voltage. A first voltage adjusted to the voltage value of the above is generated, and the PLL circuit operates by the first voltage. When an input signal is input to the PLL circuit, the PLL circuit tracks the phase of the input signal and outputs an output signal synchronized with the input signal. When the PLL circuit is outputting an output signal synchronized with the input signal, this PLL circuit has not lost synchronization,
For example, the out-of-sync detecting means does not output the out-of-sync signal.

Here, for example, when the semiconductor integrated circuit is shifted to the power down mode, the supply of the input signal is controlled, for example, when the input signal is not supplied to the PLL circuit, the PLL circuit loses synchronization, for example, the loss of synchronization is detected. The means detects the loss of synchronization and outputs a loss of synchronization signal.

On the other hand, the power supply voltage dividing circuit divides the power supply voltage and
Generates a voltage of The second voltage is set to, for example, the same value or almost the same value as the first voltage, or a voltage value in a range that does not hinder the synchronization pull-in operation of the PLL circuit when the second voltage is supplied. The power supply voltage dividing circuit, for example, converts a desired second voltage that is not as stable as the first voltage from the voltage generating circuit but does not hinder the synchronization pull-in operation of the PLL circuit into a very small current. Supply in quantity.

The selector selects one of the first voltage and the second voltage based on the out-of-synchronization signal and supplies the selected voltage to the PLL circuit as a third voltage. For example, the selecting means selects the first voltage when the out-of-sync signal is not output and supplies the first voltage to the PLL circuit, and supplies the second voltage to the PLL circuit when the out-of-sync signal is output. .

Accordingly, the power down control of the semiconductor integrated circuit is performed by the supply control of the input signal. In the power down mode, for example, the out-of-synchronization signal is output from the out-of-synchronization detecting means. Is supplied to the PLL circuit.

Therefore, for example, even if the voltage generation circuit is powered down by the out-of-synchronization signal or the like and shifted to the power-down mode, the PLL circuit operates with the second voltage and performs the synchronization pull-in operation when the power-down is released. The out-of-synchronization detecting means stops the out-of-synchronization signal, and the power down mode of the semiconductor integrated circuit is released.

FIG. 1 is a schematic block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. In the figure, the same elements as those in FIG. 3 are denoted by the same reference numerals. FIG.
FIG. 5 is a circuit diagram of the power supply voltage dividing circuit in FIG. 5, and FIG. 5 is a circuit diagram of the analog switch in FIG.

This semiconductor integrated circuit has an input terminal 1 similar to that of the semiconductor integrated circuit of FIG. 3, a phase comparator 4-1 and a frequency divider 4
-4, analog filter 4-5, voltage controlled oscillator 4-6
And a PLL circuit 4A having an out-of-synchronization detecting means 4-7,
In addition to the signal processing unit 5 having the switch circuit 5a, the gate circuit 5b, and the signal processing circuit 5c, a reference voltage generation circuit 11 which is a voltage generation circuit, and a power supply voltage which is a feature of the present embodiment and is a voltage dividing means The circuit includes a dividing circuit 12 and an analog switch 13 serving as a selection unit.

The reference voltage generation circuit 11 generates a reference voltage VREF which is a first voltage adjusted to a substantially constant voltage value based on the power supply voltage VDD, and outputs the reference voltage VREF to, for example, a PLL.
Analog filter 4-5 of circuit 4A and voltage controlled oscillator 4
-6, etc., a switch circuit 5a of the signal processing unit 5, and a circuit for outputting to the analog switch 13, and a power down means 11a for shifting the circuit to a power down mode by an out-of-sync signal Sa is provided. .

The power supply voltage dividing circuit 12 is a circuit which divides the power supply voltage VDD and outputs a divided voltage Vd which is a second voltage having a voltage value substantially equal to the reference voltage VREF to the analog switch 13, for example, as shown in FIG. As shown in the figure, a resistor 12-1 and a resistor 12-2 are connected in series between a power supply voltage VDD and a ground potential GND, and a connection point of these resistors 12-1 and 12-2 is formed. It is connected to the analog switch 13.

The analog switch 13 selects one of the reference voltage VREF from the reference voltage generating circuit 11 and the divided voltage Vd from the power supply voltage dividing circuit 12 based on the out-of-synchronization signal Sa,
A circuit that supplies the third voltage Vs to the PLL circuit 4A,
For example, a MOS transistor 13-1 that is turned on / off by the out-of-synchronization signal Sa and selects the divided voltage Vd when on to output the voltage Vs, and an inverter 13-2 that inverts and outputs the signal level of the out-of-synchronization signal Sa , This inverter 13-
On / off control complementary to the MOS transistor 13-1 is performed by the output of the MOS transistor 13-1.
The MOS transistor 13-3 outputs s. Here, the MOS transistors 13-1 and 13-3 are configured, for example, of the same conductivity type, and
2 is configured using, for example, a MOS transistor.

 Next, the operation will be described.

During normal operation (power-on mode), the reference voltage generation circuit 11 generates a reference voltage VREF based on the power supply voltage VDD and outputs it to the signal processing unit 5 and the analog switch 13. VDD is divided and the divided voltage Vd is output to the analog switch 13. When the reference voltage VREF is input to the signal processing unit 5, the reference voltage VREF is supplied to the signal processing circuit 5c via the switch circuit 5a, and the signal processing circuit 5c operates. Also, the reference voltage VREF
In the analog switch 13 to which the input and the divided voltage Vd are input, the MO
The S transistor 13-1 turns off and the MOS transistor 13-3
Turns on, selects the reference voltage VREF, and supplies the voltage Vs to the PLL circuit 4A.
To supply. The supply of this voltage Vs operates the PLL circuit 4A.

When the timing signal Sin, which is an input signal from an external circuit, is normally input to the input terminal 1 while the PLL circuit 4A and the signal processing unit 5 are operating in this way, the timing signal Sin 4A is input to the phase comparator 4-1. The phase comparator 4-1 compares the phase of the timing signal Sin with the phase of the output signal of the frequency divider 4, and detects an out-of-synchronization output voltage according to the phase difference. It is output to the means 4-7 and the analog filter 4-5. At this time, the PLL circuit 4A is not out of synchronization, and the out-of-synchronization detecting means 4-7 does not output the out-of-sync signal Sa.

The analog filter 4-5 to which the output voltage from the phase comparator 4-1 has been input smoothes the output voltage of the phase comparator 4-1 and outputs the voltage controlled oscillator 4-6 by the output of the analog filter 4-5. Is an internal timing signal that oscillates at an oscillation frequency synchronized with the timing signal Sin and is an output signal.
Sout is output, and the internal timing signal Sout is frequency-divided by the frequency divider 4-4, fed back to the phase comparator 4-1 and output to the signal processing unit 5. Then, in the signal processing unit 5, the internal timing signal Sout is input to the signal processing circuit 5c via the switch circuit 5b, and the signal processing circuit 5c performs signal processing on the internal timing signal Sout.

When the input of the timing signal Sin from the external circuit to the input terminal 1 is stopped in order to put the normally operating semiconductor integrated circuit in the function stop state (power down mode), the PLL circuit 4A is synchronized. Cause a loss,
An out-of-synchronization detecting means 4- based on the output of the phase comparator 4-1
7 detects the loss of synchronization and outputs a loss of synchronization signal Sa. This out-of-sync signal Sa is an analog switch
13, power down means 11a of the reference voltage generation circuit 11,
The signal is input to the switch circuit 5a and the gate circuit 5b of the signal processing unit 5, respectively.

When the out-of-synchronization signal Sa is input to the analog switch 13, the MOS transistor 13-3 is turned off, and the MOS transistor 13-3 is turned off.
13-1 turns on, the divided voltage Vd is selected, and the voltage Vs is
It is supplied to the circuit 4A. As a result, the PLL circuit 4A operates with the voltage Vs including the divided voltage Vd instead of the reference voltage VREF. In the reference voltage generation circuit 11, the out-of-synchronization signal Sa
Is input to the power down means 11a, and the entire circuit shifts to the power down mode, and the reference voltage VREF is stopped or suppressed. Further, the switch circuit 5a and the gate circuit 5b of the signal processing unit 5 stop or suppress the input of the output of the reference voltage generation circuit 11 and the output of the PLL circuit 4A, respectively, and the signal processing circuit 5c and the like shift to the power down mode. I do.

In order to shift the semiconductor integrated circuit that has shifted to the power-down mode in this way to the power-on mode again,
When the supply of the timing signal Sin to the input terminal 1 is restarted, the PLL circuit 4A immediately starts the synchronization pull-in operation because the voltage Vs including the divided voltage Vd having a voltage value substantially equal to the reference voltage VREF is supplied. I do. At this time, the out-of-sync signal Sa is output until the synchronization in the PLL circuit 4A is normally established. After the synchronization is established, the output of the out-of-sync signal Sa from the out-of-sync detection unit 4-7 is stopped. You. The reference voltage generation circuit
11 and the signal processing unit 5 are turned on, and in the analog switch 13, the MOS transistor 13-1 is turned off and the MOS transistor 13-1 is turned off.
The transistor 13-3 is turned on, the reference voltage VREF from the reference voltage generation circuit 11 is selected, the voltage Vs is supplied to the PLL circuit 4A, and the PLL circuit 4A returns to the normal operation.

 This embodiment has the following advantages.

(A) In the semiconductor integrated circuit of this embodiment, the divided voltage Vd of the power supply voltage dividing circuit 12 is used as a reference voltage source when the PLL circuit 4A loses synchronization. Therefore, since it is sufficient to supply the voltage to the PLL circuit 4A, the current flowing to the power supply voltage dividing circuit 12 may be very small, and can be almost negligible. Further, by configuring the analog switch 13 with a MOS transistor, power consumption can be extremely reduced (for example, to almost zero).

In this embodiment, the out-of-synchronization signal Sa from the out-of-synchronization detecting means 4-7 is used as a signal for power-down control, and the out-of-synchronization signal Sa is used as a selection signal by providing the analog switch 13. When the PLL circuit 4A is pulled in as a reference voltage source of the PLL circuit 4A, the reference voltage VREF from the reference voltage generation circuit 11 is selected.
At the time of 4A loss of synchronization, the divided voltage Vd of the power supply voltage dividing circuit 12
Can be selected.

Therefore, in the semiconductor integrated circuit of the present embodiment, there is no need to prepare a special input terminal for power down control.
In addition, since power-down can be performed on the reference voltage generation circuit 11, reduction in power consumption during power-down can be effectively achieved.

(B) In the present embodiment, when the semiconductor integrated circuit is powered down, the reference voltage VR supplied to the PLL circuit 4A during normal operation.
Since the division voltage Vd having a voltage value substantially equal to EF is supplied, when the timing signal Sin starts to be input to the input terminal 1, the PLL circuit 4A immediately starts the synchronization pull-in operation. Therefore, in the semiconductor integrated circuit of the present embodiment, the switching operation between power down and power on is smoothly performed without any trouble.

FIG. 6 is a circuit diagram of a power supply voltage dividing circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

The power supply voltage dividing circuit 12A is provided, for example, in the semiconductor integrated circuit of FIG. 1 in place of the power supply voltage dividing circuit 12, and includes a load MOS transistor 13A connected in series between the power supply voltage VDD and the ground potential GND. -1 and 13A-2.

In the second embodiment, the same operation as in the first embodiment,
The effect is obtained, and the advantage that the circuit area can be reduced as compared with the first embodiment is obtained.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. The following are examples of such modifications.

(I) The semiconductor integrated circuits of the first and second embodiments show one configuration example, and include a PLL circuit circuit 4A, an out-of-synchronization detecting means 4-7, a signal processing unit 5, a reference voltage generating circuit 11 ,
It is possible to change, omit and add configurations of the power supply voltage dividing circuit 12, the analog switches 13, 13A, etc., or change the operation example.

For example, the PLL circuit 4A may be configured without the frequency divider 4-4. The out-of-synchronization detecting means 4-7 may be provided outside the PLL circuit 4A, or may output the out-of-synchronization signal Sa other than the output of the phase comparator 4-1. The signal processing unit 5 includes a switch circuit 5a and a gate circuit.
Power down control may be performed by another configuration instead of 5b. The power supply voltage dividing circuits 12 and 12A may be constituted by other voltage dividing means, or may be constituted so as not to output the divided voltage Vd during a normal operation, for example. In the analog switch 13, the MOS transistors 13a and 13b may be configured to have complementary conductivity types, or may be configured in place of other selection means.

In the semiconductor integrated circuit of the above embodiment, if the reference voltage generation circuit 11 responds slowly at power-on and the output of a normal output is delayed, an analog switch
A delay circuit for delaying the out-of-sync signal 13 to the signal 13 may be provided.

Further, in the semiconductor integrated circuit and the like of the above-described embodiment, the description of the supply of the power supply voltage VDD to each part of the circuit is omitted, but the supply is appropriately performed. Also, the reference voltage V
The REF supply portion is not limited to the above-described embodiment at all, and is appropriately set according to, for example, the configuration of the PLL circuit 4A and the signal processing unit 5 and other additional circuit configurations.

(II) Although the semiconductor integrated circuit of the above embodiment includes a configuration up to the signal processing unit 5, the signal processing circuit 5 and the like may be set as an external circuit.

(III) The semiconductor integrated circuit of the present invention is not limited to the above embodiment, but can be widely applied to various circuits having a PLL circuit and a reference voltage generating circuit.

(Effects of the Invention) As described in detail above, according to the first and second inventions, a power supply voltage dividing circuit that divides a power supply voltage to generate a second voltage, a first voltage or a second voltage. And a selecting means for selecting one of the above voltages and supplying a third voltage to the PLL circuit, and using an out-of-synchronization signal from the PLL circuit as a selection signal of the selecting means.

For this reason, in the present semiconductor integrated circuit, an out-of-synchronization signal is used as a power-down control signal, and based on the out-of-synchronization signal, the selecting means instructs the PLL circuit to apply the first out of Voltage
When the PLL circuit loses synchronization, the second voltage from the power supply voltage dividing circuit can be selected and supplied. Further, in the power supply voltage dividing circuit, a second voltage that does not hinder the synchronization pull-in operation of the PLL circuit can be supplied to the PLL circuit, and the amount of current required to obtain the second voltage is very small. it can. For example, the amount of current in that case is almost negligible compared to the current flowing through the voltage generation circuit when the first voltage is generated.

Therefore, in the semiconductor integrated circuits of the first and second inventions,
There is no need to prepare a special input terminal for power down control, and power down can be performed on the voltage generation circuit, so that power consumption during power down can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a semiconductor integrated circuit showing a first embodiment of the present invention, FIG. 2 is a configuration block diagram showing an example of a conventional semiconductor integrated circuit, and FIG. FIG. 4 is a circuit diagram of a power supply voltage dividing circuit in FIG. 1, FIG. 5 is a circuit diagram of an analog switch in FIG. 1, and FIG. 6 is a second embodiment of the present invention. FIG. 2 is a circuit diagram of a power supply voltage dividing circuit of the semiconductor integrated circuit according to the embodiment. 4A PLL circuit, 4-1 phase comparator, 4-4 frequency divider, 4-5 analog filter, 4-6 voltage-controlled oscillator, 4-7 out-of-synchronization detection means , 11: Reference voltage generating circuit, 12: Power supply voltage dividing circuit, 13: Analog switch, Sin: Timing signal, Sout: Internal timing signal, Sa: Loss of synchronization signal, VREF: Reference voltage, Vd ... Divided voltage.

Claims (2)

(57) [Claims] A third voltage is supplied to output an output signal synchronized with the input signal by tracking the phase of the input signal, and an out-of-synchronization signal based on a phase shift between the input signal and the output signal. A phase locked loop circuit that outputs a first voltage necessary for driving the phase locked loop circuit based on a power supply voltage, and generates the first voltage when the out-of-synchronization signal is input. A voltage generating circuit for stopping, a power supply voltage dividing circuit for dividing the power supply voltage to generate a second voltage, and either one of the first voltage or the second voltage based on the out-of-sync signal A semiconductor integrated circuit comprising selection means for supplying the third voltage to the phase locked loop circuit. 2. A phase locked loop circuit comprising: a frequency divider for dividing the output signal; and a phase comparator for comparing phases of the input signal and the divided output signal and outputting a comparison result. An out-of-synchronization detection unit that outputs the out-of-sync signal based on the comparison result; an analog filter that smoothes the comparison result; and a voltage-controlled oscillator that outputs the output signal based on the output of the analog filter. The semiconductor integrated circuit according to claim 1, wherein: