JP3152600B2 - Time setting device and electronic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time setting device for setting a clock time based on time data contained in an EDS (Extended Data Service) signal during a vertical blanking period of a video signal, and a time setting device therefor. The present invention relates to an electronic device provided.

[0002]

2. Description of the Related Art In a video tape recorder (hereinafter, referred to as a VTR), channel setting and time setting are operations that must be performed before a user starts using a device. In recent years, it has an automatic channel selection function of automatically searching for and storing a channel that is a station, and a time setting function of setting a time based on an additional signal of a vertical blanking period of a video signal (television signal). There is a VTR in which a time setting device is realized, and which is equipped with the device and simplifies an operation to be performed by a user.

[0005] Broadcasting stations transmit various information using a vertical blanking period such as a caption. Currently, PDC (Program De-
livery Control) and teletext (teletext). In the United States, a new data service (EDS = Extended Data Service) in which a data signal is superimposed on a video signal using a vertical blanking period was started in April 1994. The EDS signal also includes time data, broadcast station (channel) information, and the like, similarly to the additional signal in the vertical blanking period, and the clock is set using the time data. . Also, since 1995, INDEX
As part of the PLUS + system, time data called a G-CLOCK packet is transmitted.

[0004] As shown in FIG. 6, the EDS signal is superimposed on the 21st horizontal synchronizing signal in the vertical blanking period of the even field of the video signal (television signal).
17 bits including the start bit s3 are transmitted per one even field. Therefore, although the data part is 2 bytes, 1 character code is assigned to 1 byte,
Each byte has parity bits p1 and p2.
The EDS signal first has a control code (1 byte)
And a type code (1 byte) are transmitted, and these two codes indicate the type of information to be transmitted. (Example: time data (07, 01), broadcast station (channel) information (05, 0)
2)) After the type of information to be transmitted is determined by the above-described code, information specified in the specification (the number of bytes, format, etc.) is transmitted, and after the information transmission is completed, a control code (OF) indicating the end is transmitted.
Send

The time data of the EDS signal is composed of, for example, a total of 10 bytes (5 even fields = 5 frames) as follows. (07,01)-(minute, hour)-(day, month)-(day, year)
-(OF, any code) In the time data of the EDS signal, the sixth bit (b5) of the "month" data is used as a second reset flag ("Z" bit) indicating that the second of the time is just 0 second. I have.

A conventional VTR has a predetermined period (for example, 1
Times / day, once / lap, etc.), in a situation where other operations such as timer reservation are not hindered, a broadcasting station that is automatically started and finds an EDS signal that has been found in advance is selected. The channel is tuned to receive the EDS signal, and the date and time are set according to the time data of the EDS signal. At this time, E
Since the DS signal does not include the second data as described above, the time of the clock is set once by setting the second value of the time data to 00 seconds. This operation is continued until the above-mentioned "Z" bit is received, and when the "Z" bit is received, the time value is set such that the second value of the time data is 00 seconds, and the setting operation ends. In addition, a predetermined time limit is provided, and even if the “Z” bit cannot be received within the time limit, the process ends.

[0007]

[Problems to be solved by the invention] EDS rules (EIA-60
8, "Recommended Practice for Line 21 Data Service",
June 17.1993), the transmission cycle of the time data of the EDS signal is specified to be transmitted once every 1 to 10 minutes, and is not specified to be transmitted at exactly 0 seconds. Therefore, there is no guarantee that the "Z" bit can be received.
In addition, since the above-mentioned G-CLOCK packet does not include the “Z” bit, the time cannot be set by the above-described method.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to provide a time setting device capable of setting a time in units of seconds and an electronic apparatus including the time setting device. .

[0009]

A time setting device according to a first aspect of the present invention includes a tuner for receiving a transmission signal,
In a time setting device for setting time data in a clock circuit based on time data included in the transmission signal, time data detection means for sequentially detecting and storing time data included in the transmission signal, and the time data detection means A change time detecting means for reading the time data stored in the clock circuit at a predetermined cycle and detecting a time when the time data changes, and setting the time data in the clock circuit at the time when the change time detecting means detects the time data. It is characterized by what it does.

In this time setting device, the time data detecting means detects and stores the time data included in the transmission signal.
The change time point detecting means reads out the time data stored in the time data detecting means at a predetermined cycle, and detects a time point at which the time data changes. Then, time data is set in the clock circuit at the time when the change time detecting means detects the change. This makes it possible to detect when the minute unit of the time data included in the transmission signal has changed, and at this time,
Time data can be set in the clock circuit.

A time setting device according to a second aspect of the present invention includes a tuner for receiving a television signal, extracts an EDS signal superimposed during a vertical blanking period from the television signal, and converts the EDS signal into time data included in the EDS signal. A time setting device that sets time data in a clock circuit based on
A time data detecting means for sequentially detecting and storing time data included in the EDS signal; and a change time point for reading the time data stored by the time data detecting means at a predetermined cycle and detecting a time point at which the time data changes. Detecting means for setting time data in the clock circuit at the time point detected by the change time point detecting means.

In this time setting device, the time data detecting means detects and stores the time data included in the EDS signal. The change time point detecting means reads out the time data stored in the time data detecting means at a predetermined cycle, and detects a time point at which the time data changes. Then, time data is set in the clock circuit at the time when the change time detecting means detects the change.
As a result, it is possible to detect a point in time at which the minute unit of the time data included in the EDS signal changes, and to set the time data in the clock circuit at the time of the change.

A time setting device according to a third aspect of the present invention is a time data comparing device that compares the time data stored in the time data detecting device with the time data of the clock circuit at the time point detected by the change time detecting device. Means and clock circuit setting means for setting the second value of the time data of the clock circuit to 00 seconds when the comparison result of the time data comparing means is advanced by one minute.

In this time setting device, the change time point detecting means detects the time point when the time data contained in the EDS signal changes, and the time of the clock circuit with respect to the time data stored in the time data detecting means at this time point. The time data comparing means detects the advance / delay of the data. And, when the comparison result of the time data comparing means is advanced by one minute,
The clock circuit setting means sets the second value of the time data of the clock circuit to 0.
Set to 0 seconds. As a result, the clock circuit is set only when the time data of the clock circuit is set more accurately. By repeating this setting, the time data of the clock circuit with respect to the time data stored by the time data detecting means is set. Can be reduced.

In the time setting device according to a fourth aspect of the present invention, the clock circuit setting means is configured to output the time data to the clock circuit when the comparison result of the time data comparing means is delayed or advanced by two minutes or more. It is characterized in that time data in which the second value of the time data stored in the detection means is 00 seconds is set.

In this time setting device, when the result of the comparison by the time data comparing means is delayed or advanced by two minutes or more, the clock circuit setting means sets the time data stored in the time data detecting means in the clock circuit. Is set to time data with a second value of 00 seconds. This allows the clock circuit to be set more accurately only when the time data stored in the time data detection means is more accurate than the time data of the clock circuit.
By repeating this setting, the degree of delay and advance of the time data of the clock circuit with respect to the time data stored by the time data detecting means can be reduced.

The time setting device according to a fifth aspect of the present invention is characterized in that the time setting device is provided with starting means for starting at a predetermined cycle.

In this time setting device, since the starting means is started at a predetermined cycle, the time of the clock circuit can be automatically corrected periodically and the time of the clock circuit can be accurately maintained.

According to a sixth aspect of the present invention, there is provided an electronic apparatus.
And a clock circuit for setting the time data by the time setting device.

In this electronic device, the time setting device can automatically and accurately keep the time of the clock circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing an embodiment. FIG. 1 shows an electronic device according to a sixth aspect of the present invention including the time setting device according to the first to fifth aspects.
FIG. 2 is a block diagram showing a main configuration of an example VTR.
The time setting device built in the VTR sets the time based on the EDS signal which is one of the additional signals in the vertical blanking period. The television signal captured by the antenna 1 is received and selected by the tuner 2, and the video signal processing circuit 14
, And output as a video signal.
The output of the tuner 2 is provided to the EDS processing circuit 4. In the EDS processing circuit 4, only the EDS signal is selectively passed and supplied to the VTR control unit 8 and the time data detection circuit 6.

A VTR control unit 8 having a microcomputer is connected to a time data detection circuit 6 for detecting and storing time data contained in the EDS signal, and a clock circuit 9 for setting the time by the VTR control unit 8. I have. VTR
The microcomputer of the control unit 8 reads out the time data stored in the time data detection circuit 6 at a predetermined cycle,
The time point at which the time data changes is detected, and the time data stored in the time data detection circuit 6 and the time data of the clock circuit 9 at the detected time point are compared.

When the result of the comparison is advanced by one minute, the clock circuit 9 is set to 00 seconds of the time represented by the time data of the clock circuit 9. When the comparison result is late or 2
When the time is advanced by more than one minute, the time data in which the second value of the time data stored in the time data detection circuit 6 is 00 seconds is set in the clock circuit 9. The microcomputer of the VTR control unit 8 performs the setting operation of the time setting device once /
It is executed in a cycle such as once a day / period.

The VTR control section 8 includes a display control circuit 17 for controlling the display section 18, an input control section 11 for transmitting an operation of the keys 13 or the remote controller 12 to the VTR control section 8, and a tuning operation of the tuner 2. And a power supply circuit 7 for individually supplying power to the tuner 2, the tuning circuit 3, each unit of the VTR, and the time setting device under the control of the VTR control unit 8.

Hereinafter, a time setting device having such a configuration will be described.
Flow chart showing the operation of the provided VTR
This will be described with reference to FIGS. The time setting device is 1
Cycle time T such as day, week, etc._FiveIs completed (S3
6), start the time adjustment operation (S10). At this time,
Time limit T for time adjustment operation ₆(S1)
2). Next, the time setting device determines when the time is included in the EDS signal.
Time from the time data detection circuit 6 which detects and stores the time data
Time data T₁Is read (S14). At this time,
Interval T₆If the time measurement has not been completed (S16), the time
Data T_TwoRead cycle time T₇(Less than 1 second is desirable
Waits for elapse) (S18) and time data detection
Time data T from circuit 6_TwoIs read (S20).

Next, the time setting device reads the time data T read out from the time data detection circuit 6 with a cycle time T ₇ therebetween.
₁ and T ₂ (S22), and the time data detection circuit 6 is read every read cycle time T ₇ until T ₁ ≠ T _2.
It reads the time data T ₂ from (S20). The time setting device updates the time data T ₁ with the time data T ₂ when the time data T ₁ , T ₂ becomes T ₁ ≠ T ₂ (S
23), reads out the time data T ₃ of the clock circuit 9 from the clock circuit 9 (S24). Next, T ₂ −T ₃ = T ₄ is calculated (S26), and the magnitudes (leading / lagging) of the time data T ₂ , T ₃ are compared (S28).

The time data T ₂ and T ₃ were compared (S2
8) As a result, if the time data T ₂ and T ₃ are equal, the time setting of the clock circuit 9 is not performed, and if the counting of the time limit T ₆ is not completed (S16), the read cycle time of the time data T ₂ is set. waiting for the T ₇ has elapsed (S18), reads the time data T ₂ from the time data detection circuit 6 (S2
0).

The time data T ₂ and T ₃ were compared (S2
8) As a result, if the time data T ₃ is ahead of the time data T ₂ by one minute (S30), the time data T
The time data with the second value of ₃ being 00 seconds is set (S4
0). Then, if not finished counting the time limit T ₆ is (S16), the read cycle time of the time data T ₂ T ₇
But wait for the elapse (S18), reads the time data T ₂ from the time data detection circuit 6 (S20).

The time data T ₂ and T ₃ were compared (S2
8) As a result, when the time data T ₃ is later than the time data T ₂ or advances by 2 minutes or more (S30), the time data T ₂ stored in the time data Set time data with a value of seconds of 00 seconds (S
32). Then, if not finished counting the time limit T ₆ is (S16), the read cycle time of the time data T ₂ T
₇ Wait for the elapsed (S18), reads the time data T ₂ from the time data detection circuit 6 (S20).

The time setting device performs the above operation for the time limit T
Repeat until the timing of ₆ is completed (S16), and the time limit T
_{When 6} clocking of finished (S16) ends the time adjustment operation (S33), 1 day, it starts measuring the period time such as 1 week T ₅ (S34).

FIGS. 4A and 4B are time charts showing the case where the time of the clock circuit 9 is delayed in the above-described time correction operation, wherein FIG. 4A shows the correct time and FIG. 4B shows the time data contained in the EDS signal. Is changed and the time data is
(C) shows the time data set by the clock circuit 9 and the time data of the clock circuit 9 before the setting.
In (b), the packet of the time data included in the EDS signal is received more frequently, but is omitted except for the time when the time data changes (FIG. 3 (S22)), so that the description is omitted. .

When the packet of the time data is received, the time data of the clock circuit 9 and the time data of the packet are both X minutes (year, month, day and time are omitted), so the time setting of the clock circuit 9 is not executed (S28). . Next, when a packet of time data is received, the time data is (X + 1) minutes, but the time data of the clock circuit 9 is delayed and is still X minutes. (X + 1) minutes and 00 seconds are set (S32).

Next, when a packet having a delay of b seconds smaller than a second from the correct time of the time data of the packet is received, that is, the packet is received one minute after the packet is received. Then, the time data is (X + 2) minutes. On the other hand, the clock circuit 9
Since the time data of (X) is set to (X + 1) minutes and 00 seconds, 1 minute has not elapsed and is (X + 1) minutes, the time of the clock circuit 9 is set to (X + 2) minutes and 00 seconds ( S3
2).

Next, when a packet having a delay of c seconds greater than b seconds from the correct time in the time data of the packet is received, that is, the packet is received one minute after the packet is received. At that time, the time data is (X + 3) minutes. On the other hand, the clock circuit 9
Is set to (X + 2) minutes 00 seconds, one minute has elapsed since the time data was set to (X + 2) minutes 00 seconds, and has already been set to (X + 3) minutes. Since the two match, the time setting of the clock circuit 9 is not executed. (S28).

Next, the packet of the correct time, that is,
When a packet having time data that changes by one minute coincides with the fact that the correct time changes by one minute, the time data is (X + 4) minutes. On the other hand, the clock circuit 9
Is not (X + 3) minutes 00 seconds, 1 minute has not elapsed since (X + 3) minutes 00 seconds, and the time of the clock circuit 9 is set to (X + 4) minutes 00 seconds (S3).
2). As described above, only the packet at the reception time point closer to the correct time is adopted, and the delay of the time data of the clock circuit 9 is corrected substantially at the reception time point. Therefore, this correction operation is performed until the time limit time measurement ends. By repeating this, the time data of the clock circuit 9 can be gradually and accurately set in seconds. The case where the time data of the clock circuit 9 is advanced by two minutes or more is the same as the case where the time of the clock circuit 9 is delayed.

FIG. 5 is a time chart showing a case where the time of the clock circuit 9 is advanced in the above-described time correction operation. FIG. 5A shows the correct time, and FIG. 5B shows the time data contained in the EDS signal. Is changed and the time data is
(C) shows the time data set by the clock circuit 9 and the time data of the clock circuit 9 before the setting.
In (b), the packet of the time data included in the EDS signal is received more frequently, but is omitted except for the time when the time data changes (FIG. 3 (S22)), so that the description is omitted. .

If the time data packet is received and the time data is set to X minutes (the date and time of Sunday, month and day are omitted), the time data of the clock circuit 9 is advanced and is (X + 1) minutes. Is set to (X + 1) minutes 00 seconds (S40).

Next, when a packet having a delay of one minute ahead of the correct time in the packet time data, that is, a packet having a delay of e seconds smaller than the delay of d seconds from the correct time + 1 minute, that is, receiving the packet, Since then 1
When a packet is received after the lapse of minutes, the time data is (X + 1) minutes. On the other hand, the time data of the clock circuit 9 becomes 1 after (X + 1) minutes 00 seconds is set.
Since the minutes have elapsed and the time is (X + 2) minutes, the time of the clock circuit 9 is set to (X + 2) minutes 00 seconds (S4
0).

Next, when a packet having a delay of f seconds larger than e seconds from the correct time + 1 minute of the time data of the packet is received, that is, the packet is deleted before one minute elapses from the reception of the packet. When received, the time data is (X + 2) minutes. On the other hand, the time data of the clock circuit 9 is set to (X + 2) minutes 00 seconds, and one minute has not elapsed since the time data was set to (X + 2) minutes. Is not executed (S28).

Next, the packet at the correct time,
When a packet having time data that changes by one minute coincides with the fact that the correct time changes by one minute, the time data is (X + 4) minutes. On the other hand, the clock circuit 9
The time data is (X + 2) minutes 00 seconds, two minutes have elapsed since the time was set, and (X + 4) minutes. Since the two coincide, the time setting of the clock circuit 9 is not executed ( S28).

Even when the time data of the packet at the correct time is (X + 3) minutes, the time data of the clock circuit 9 is
One minute elapses after the setting of (X + 2) minutes 00 seconds, and since (X + 3) minutes and both coincide,
The time setting of the clock circuit 9 is not performed (S28), which is the same as when the time data of the packet of the correct time is (X + 4) minutes. As described above, only the packet at the reception time closer to the correct time + 1 minute is adopted, and the time data of the clock circuit 9 (1
The time data of the clock circuit 9 can be gradually and accurately set in seconds by repeating this correction operation until the time measurement of the time limit ends. .

[0042]

According to the time setting devices according to the first to fifth aspects of the present invention, a time setting device capable of setting the time in units of seconds can be realized.

According to the electronic apparatus according to the sixth aspect of the invention, an electronic apparatus capable of setting a time in units of seconds with a built-in time setting device can be realized.

[Brief description of the drawings]

FIG. 1 shows a sixth embodiment provided with a time setting device according to the first to fifth inventions.
FIG. 2 is a block diagram showing a main configuration of a VTR which is an example of the electronic apparatus according to the invention.

FIG. 2 is a flowchart showing an operation of the VTR shown in FIG.

FIG. 3 is a flowchart showing an operation of the VTR shown in FIG.

FIG. 4 is a time chart showing a case where the time of the clock circuit is delayed in the time adjustment operation.

FIG. 5 is a time chart showing a case where the time of the clock circuit is advanced in the time adjustment operation.

FIG. 6 is an explanatory diagram showing a configuration example of an EDS signal and time data included therein.

[Explanation of symbols]

 2 Tuner 4 EDS processing circuit 6 Time data detection circuit 8 VTR control section 9 Clock circuit

Continuation of front page (56) References JP-A-2-41047 (JP, A) JP-A-5-1557859 (JP, A) JP-A-5-249256 (JP, A) JP-A-2-275392 (JP) , A) Fully open sho 59-100336 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G04G 5/00 G04G ⁷ /00-7/02

Claims (6)

(57) [Claims] 1. A time setting device comprising a tuner for receiving a transmission signal and setting time data in a clock circuit based on the time data included in the transmission signal, wherein the time data included in the transmission signal is sequentially detected. Time data detecting means for reading and storing the time data stored in the time data detecting means at a predetermined period, and detecting a time point at which the time data changes. A time setting device for setting time data in the clock circuit at the time when the time is detected. 2. A tuner for receiving a television signal, extracting an EDS signal superimposed during a vertical blanking period from the television signal, and transmitting a time data to a clock circuit based on the time data included in the EDS signal. A time setting device for sequentially detecting and storing time data included in the EDS signal; and reading the time data stored by the time data detecting device at a predetermined cycle, and A time setting device comprising: a change time point detecting means for detecting a change time point; and setting time data in the clock circuit at the time point when the change time point detecting means detects the change time point. 3. A time data comparing means for comparing the time data stored in the time data detecting means with the time data of the clock circuit at the time detected by the change time detecting means, and the time data comparing means When the comparison result is advanced by one minute, the second value of the time data of the clock circuit is set to 0.
3. The time setting device according to claim 1, further comprising a clock circuit setting unit that sets the time to 0 second. 4. The clock circuit setting means, when the comparison result of the time data comparison means is delayed or advanced by two minutes or more, the time stored by the time data detection means in the clock circuit. 4. The time setting device according to claim 3, wherein the time value in which the second value of the data is 00 seconds is set. 5. The time setting device according to claim 1, further comprising a starting unit that starts at a predetermined cycle. 6. An electronic apparatus, comprising: the time setting device according to claim 1; and a clock circuit for setting the time data by the time setting device.