JP3150088B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multilayer wiring having a structure suitable for a custom LSI and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional custom LSI, a plurality of semiconductor elements are formed on the surface of a semiconductor substrate, and the surface of the semiconductor substrate including the semiconductor elements is prepared in a state covered by a first interlayer insulating film. The semiconductor element was connected to the semiconductor substrate according to customer requirements. This connection includes a step of forming a first contact hole reaching the semiconductor element in the first interlayer insulating film, a step of filling the first contact hole with a first contact plug made of a conductive film, and a step of first filling. Forming a first wiring on the surface of the interlayer insulating film;
Forming a second interlayer insulating film covering the first interlayer insulating film including the first wiring, forming a second contact hole reaching the first wiring in the second interlayer insulating film, conductive film And a step of forming a second wiring on the surface of the second interlayer insulating film, and the like.

[0003]

As described above, in order to complete a desired semiconductor device by forming a connection in the semiconductor base according to a customer's request, two contact holes must be formed and two contact holes must be formed. It is necessary to form a contact plug, form wiring twice, and form at least one interlayer insulating film. Of these, the formation of the contact hole and the wiring involves a photolithography step. In order to form this connection, at least four photolithography steps are essential. For this reason, in a conventional semiconductor device, a TAT (Turn-Aro) in a process of manufacturing a semiconductor device from a semiconductor substrate is used.
There is a disadvantage that und-Time) becomes longer.

Accordingly, an object of the present invention is to provide a custom LSI in which the TAT to a semiconductor device in which connection information is taken from a semiconductor substrate provided with a base wiring can be easily reduced.
It is another object of the present invention to provide a semiconductor device having a structure suitable for such a custom LSI, and a method for manufacturing a semiconductor device suitable for such a custom LSI.

[0005]

[0006]

[0007]

[0008]

Means for Solving the Problems The configuration of the semiconductor device of the present invention
A field insulating film filled with a first insulating film is provided in a groove formed in an element isolation region on a surface of a semiconductor substrate, and at least an element forming region on the surface of the semiconductor substrate is provided in the groove. A semiconductor element, and a conductor film pad made of a first conductor film is provided on a surface of the field insulating film at a portion separated from the semiconductor element. The surface of the semiconductor substrate including the element, the conductor film pad, and the field insulating film is covered with a first interlayer insulating film made of a silicon oxide based insulating film, and is formed on the surface of the first interlayer insulating film. Is provided with a first wiring made of a second conductor film,
Further, a first dummy pattern made of the second conductor film is provided on a required portion of the surface of the first interlayer insulating film, and the first dummy pattern including the first wiring and the first dummy pattern is provided. The surface of the first interlayer insulating film is covered with a second interlayer insulating film made of a silicon oxide-based insulating film, and the surface of the second interlayer insulating film is covered with a third conductor film. And a second dummy pattern made of the third conductor film is provided on a required portion of the surface of the second interlayer insulating film. The surface of the second interlayer insulating film including the wiring and the second dummy pattern is covered with a third interlayer insulating film made of a silicon oxide-based insulating film. The second wiring via the second interlayer insulating film; And the first wiring has a first cross section intersecting, provided we portion of the semiconductor element
A second intersection portion where the second wiring and the first wiring intersect via the second interlayer insulating film immediately above the field insulating film except for the first insulating film. A contact made of a fourth conductor film at the intersection of
A first wiring penetrating contact hole filled with a plug and having a diameter smaller than the line width of the first and second wirings is formed from the surface of the third interlayer insulating film to the third interlayer insulating film. The second wiring, the second interlayer insulating film, and the first wiring and the first interlayer insulating film to reach the semiconductor element, and at the second intersection, Filled with a contact plug,
And a second wiring through contact hole having a diameter smaller than the line width of the second wiring is formed from the surface of the third interlayer insulating film to the third interlayer insulating film, the second wiring, and the second wiring. Two interlayer insulating films, these first wirings, and the first interlayer insulating film, and reach the field insulating film.
Plug filled with the second wiring and the first wiring.
A third wiring through contact hole having a diameter smaller than the line width of the dummy pattern is formed from the surface of the third interlayer insulating film to the third interlayer insulating film, the second wiring, and the second wiring. And reaches the semiconductor elements through the interlayer insulating film, the first dummy pattern and the first interlayer insulating film, and is filled with the contact plug immediately above the semiconductor element. The second dummy
A pattern and a fourth wiring through-contact hole having a diameter smaller than the line width of the first wiring are formed from the surface of the third interlayer insulating film to the third interlayer insulating film and the second dummy insulating film. The semiconductor device is penetrated through the pattern, the second interlayer insulating film, the first wiring and the first interlayer insulating film, reaches the semiconductor elements, and is provided on the surface of the field insulating film. Immediately above the conductor film pad, the surface of the third insulating film penetrates through the third interlayer insulating film, divides the second wiring, and penetrates the second interlayer insulating film. A first wiring dividing opening which divides one dummy pattern, penetrates the first interlayer insulating film and reaches these conductor film pads, is provided on the surface of the field insulating film; Immediately above the above-mentioned conductor film pad, The third from the serial surface of the third insulating film
, The second dummy pattern is divided, the second insulating film is penetrated, the first wiring is divided, and the first wiring is penetrated through the first interlayer insulating film. A second wiring cut-off opening reaching the conductive film pad is provided, and the first and second wiring cut-off openings are filled with a second insulating film.

[0009]

[0010]

[0011]

[0012]

The structure of the method for manufacturing a semiconductor device according to the present invention is as follows.
Forming a field insulating film by forming a groove in an element isolation region on a surface of a semiconductor substrate and filling the groove with a first insulating film; and forming a semiconductor element in at least an element forming region of the semiconductor substrate. Forming a conductive film pad made of a first conductive film in a required region on the surface of the field insulating film; and forming a conductive film pad of the semiconductor substrate including the semiconductor element, the conductive film pad and the field insulating film. Forming a first interlayer insulating film made of a silicon oxide based insulating film covering the surface; and forming a first interlayer insulating film on the surface of the first interlayer insulating film.
Forming a first wiring made of a second conductor film and a first dummy pattern in a second predetermined region; and forming the first interlayer insulating film including the first wiring. Forming a second interlayer insulating film made of a silicon oxide-based insulating film covering the surface of the second interlayer insulating film; and forming a second conductor film in third and fourth predetermined regions on the surface of the second interlayer insulating film. Forming a second wiring and a second dummy pattern made of silicon, and forming a third interlayer made of a silicon oxide-based insulating film covering the surface of the second interlayer insulating film including the second wiring. Forming an insulating film, and using at least the third photoresist film pattern as a mask, at least the third interlayer insulating film, the second wiring, the second dummy pattern, and the second interlayer insulating film; A film, the first wiring, and the first dummy pattern; The anisotropic etching is sequentially performed on the first interlayer insulating film and the third interlayer insulating film, the second wirings, and the second interlayer insulating film from the surface of the third interlayer insulating film. Film, these first wirings and this first wiring
And reaches the semiconductor element through the first interlayer insulating film.
From the surface of the third interlayer insulating film, the third interlayer insulating film, the second wiring, the second interlayer insulating film, the first wiring, and the first wiring. A second wiring penetrating contact hole that penetrates through the interlayer insulating film and reaches the field insulating film; and a third interlayer insulating film, these second wirings, and the like from the surface of the third interlayer insulating film. A third wiring through contact hole penetrating through the second interlayer insulating film, the first dummy pattern, and the first interlayer insulating film to reach these semiconductor elements;
Through the third interlayer insulating film, the second dummy pattern, the second interlayer insulating film, the first wiring, and the first interlayer insulating film from the surface of the first interlayer insulating film. Forming a third wiring penetrating contact hole reaching these semiconductor elements, forming a fourth conductor film over the entire surface by LPCVD, etching back the fourth conductor film, Forming contact plugs respectively filling the first, second, third and fourth wiring through contact holes; and forming the second wiring and the second wiring using the second photoresist film pattern as a mask. Anisotropic etching is performed on the third interlayer insulating film until the upper surface of the dummy pattern is exposed, and the third interlayer insulating film is removed until the second wiring and the second dummy pattern are removed. these Anisotropically etched for the second wiring and the second dummy pattern, the first
The second interlayer insulating film is subjected to anisotropic etching until the upper surface of the wiring and the first dummy pattern is exposed, and the second wiring and the first dummy pattern are removed until the first wiring and the first dummy pattern are removed. Anisotropic etching is performed on the second interlayer insulating film and the second wiring and the second dummy pattern, and further, the difference between the first interlayer insulating film and the first interlayer insulating film is reached until the upper surface of the conductive film pad is reached. Anisotropic etching is performed to penetrate the third interlayer insulating film from the surface of the third interlayer insulating film, divide these second wirings, penetrate the second interlayer insulating film, And a first wiring dividing opening penetrating the first interlayer insulating film and reaching these conductor film pads, and a surface of the third interlayer insulating film. This third layer Penetrating the edge film, dividing the second dummy patterns, penetrating the second interlayer insulating film, dividing the first wirings, and further penetrating the first interlayer insulating film. Forming a second wiring separating opening reaching these conductor film pads, and forming an insulating film over the entire surface by LPCVD, and using the insulating film to form the first and second wiring separating openings. And a filling step.

[0014]

Next, the present invention will be described with reference to the drawings.

The configuration of a semiconductor device of a technical example related to the present invention is as follows. The surface of the semiconductor substrate provided with the semiconductor element is covered with the first interlayer insulating film,
A first wiring is provided on a surface of the first interlayer insulating film;
The surface of the first interlayer insulating film is covered with the second interlayer insulating film, the second wiring is provided on the surface of the second interlayer insulating film, and the surface of the second interlayer insulating film is formed of the third interlayer insulating film. It is covered with an interlayer insulating film. There is an intersection where the second wiring and the first wiring intersect directly above the semiconductor element via the second interlayer insulating film, and at the intersection, the third interlayer insulating film extends from the surface of the third interlayer insulating film. A wiring through-contact hole reaching the semiconductor element through the film, the second wiring, the second interlayer insulating film, the first wiring, and the first interlayer insulating film is provided, and the wiring through-contact hole is formed of a conductor film. Filled with a contact plug consisting of Further, in a portion excluding the crossing portion, a wiring separation opening penetrating from the surface of the third interlayer insulating film to penetrate the third interlayer insulating film, separate the second wiring, and reaches the second interlayer insulating film. The wiring opening is provided with an insulating film. In the first embodiment of the present invention,
The semiconductor substrate is prepared in a state where the wiring through contact hole and the wiring cutting opening are not provided, and a photo mask for photolithography to be provided for forming the wiring through contact hole and the wiring cutting opening according to a customer request is formed. Then, a required semiconductor device is formed using these.

FIG. 1 is a schematic plan view of a semiconductor device, FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line AA and BB in FIG. 1, and FIG. 3 is a circuit diagram. When referred to together, this technical example is applied to a two-input NAND including a pair of CMOS transistors, and is configured as follows. In FIG. 2, hatching for the interlayer insulating film is omitted to avoid complication of the drawing.

On the surface of a P-type silicon substrate 101, a P well 102 and an N well 103 are provided.
2, element formation regions 104, 1
A LOCOS field oxide film 106 is provided in an element isolation region on the surface of the P-type silicon substrate 101. Gate electrodes 111 and 1 provided on the surface of element formation region 104 via gate oxide film 108
Numerals 12 each extend on the surface of the field oxide film 106 and further extend on the surface of the element formation region 105 via the gate oxide film 108. The gate electrode 111,
Reference numeral 112 is made of, for example, a tungsten polycide film. The gate electrode 111,
N-type source / drain regions 116
a, 116b, and 116c are provided, and the element formation region 10
4 includes N channel MOS transistors Q _N1 and Q _N2.
Are provided. Q _N1 is a gate electrode 111, a gate oxide film 108, and N-type source / drain regions 116a, 1
Is composed of a 16b, Q _N2 is the gate electrode 112 and the gate oxide film 108 and the N-type source and drain regions 116 b,
116c. P-type source / drain regions 117a, 117b, and 117c are provided on the surface of the element forming region 105 in a self-aligned manner with the gate electrodes 111 and 112. In the element forming region 105, P P channel MOS transistors Q _P1 and Q _{P2 are provided.} Are provided. Q _P1
Is composed of a gate electrode 111, a gate oxide film 108, and P-type source / drain regions 117a and 117b.
_P2 includes a gate electrode 112, a gate oxide film 108, and P-type source / drain regions 117b and 117c. On the surface of P-type silicon substrate 101, a basic cell including a first CMOS transistor including Q _N1 and Q _P1 and a second CMOS transistor including Q _N2 and Q _P2 is provided.

The field oxide film 106 and the first and second
P-type silicon substrate 1 including CMOS transistors
01 is made of a silicon oxide insulating film (first)
It is covered with an interlayer insulating film 120. Interlayer insulating film 12
The surface of 0 is preferably flattened by chemical mechanical polishing (CMP) or the like. On the surface of the interlayer insulating film 120,
For example, the wirings 121a, 121b, 121c, 122 (which are the first wirings) made of a tungsten silicide film
a, 122b, 122c, 123a, 123b, 123
For example, c and the like are provided in the horizontal direction (on the paper surface of FIG. 1). Here, the positions where the wirings 122b and 123b are provided remain only on one basic cell, but the wirings 121a to 121c, 122a, 122c and 1
23a, 123c is that not extend over the elementary cells adjacent in the lateral direction (the plane in the FIG. 1).

The surface of the interlayer insulating film 120 including these wirings 121a and the like is made of a silicon oxide based insulating film.
2) is covered with an interlayer insulating film 130. The surface of the interlayer insulating film 130 is also preferably planarized by CMP or the like. On the surface of the interlayer insulating film 130, a second wiring is provided. These second wirings are preferably formed of, for example, a tungsten silicide film, like the first wirings.
They are provided in parallel in the vertical direction. The second wiring provided on one basic cell includes, for example, (a wiring 131 described later).
Are divided) Wirings 131a, 131b, 131c
And the wiring 13 (the wiring 132 described later is divided).
2a, 132b, 132c and wirings 133a, 133b, 133c (which are obtained by dividing a wiring 133 described later),
133d. Wirings 131a, 132a, 133
a wiring 131c, 132c, and 133d, that are extending respectively (in the plane of FIG. 1) on the basic cells adjacent in the vertical direction.

Immediately above the first and second CMOS transistors, the second wiring and the first wiring are interposed via an interlayer insulating film 130.
A plurality of intersections are provided between the wirings. The locations where these intersections are provided are as follows. Immediately above the gate electrode 111, between the wiring 121a and the wiring 131a, between the wiring 121b and the wiring 131b,
And between the wiring 121c and the wiring 131c. Immediately above the gate electrode 112, the wiring 121a and the wiring 133a
, Between the wiring 121b and the wiring 133b, and between the wiring 121c and the wiring 133d. N-type source
Immediately above the drain region 116a, the wirings 122a and 122a
2b and 122c and the wiring 131b. Immediately above the N-type source / drain region 116b, the wiring 122
a, 122b and 122c and the wiring 132c. Immediately above the N-type source / drain region 116c, it is between the wirings 122a, 122b and 122c and the wiring 133c. Immediately above the P-type source / drain region 117a, the wirings 123a, 123b and 123c and the wiring 1
31b. P-type source / drain region 117
b, wirings 123a, 123b and 123c
And the wiring 132b. Immediately above the P-type source / drain region 117c, it is between the wirings 123a, 123b and 123c and the wiring 133b. In FIG. 1, the line width of the first wiring and the line width of the second wiring are all the same, but the present invention is not limited to this. For example, the line width of the first wiring and the line width of the second wiring at the intersection may be increased.

The surface of the interlayer insulating film 130 including the second wiring is covered with a (third) interlayer insulating film 140 made of a silicon oxide based insulating film. The surface of the interlayer insulating film 140 is also preferably planarized by CMP or the like. The interlayer insulating film 140 penetrates through the interlayer insulating film 140, the second wiring, the interlayer insulating film 130, the first wiring, and the interlayer insulating film 120 from the surface of the interlayer insulating film 140 at a part of the intersection. A wiring through contact hole 141 reaching the first or second CMOS transistor, and a surface of the interlayer insulating film 140 (directly above the field oxide film 106 in a portion where the first and second CMOS transistors are not provided). A wiring separation opening 147 that penetrates through the interlayer insulating film 140 to cut the second wiring and reaches the interlayer insulating film 130 is provided. The diameter of the wiring through contact hole 141 is set to be smaller than the line width of the first and second wirings (at least at the intersection). The wiring through contact hole 141 is
1 is covered with a contact plug 146 composed of a conductive barrier film that directly covers the bottom and side surfaces (for example, a titanium film is laminated on a titanium film) and a tungsten film that covers the surface of the conductive barrier film. ing. The wiring separation opening 147 is filled with an insulating film 150 made of, for example, a silicon oxide film, and the insulating film 150 covers the surface of the interlayer insulating film 140.

The wiring 131, which will be described later, is formed by the wiring dividing opening 147 so that the wiring 131a, the wiring 131b, and the wiring 131c are formed.
The wiring 132 described later is divided into a wiring 132a, a wiring 132b, and a wiring 132c, and the wiring 133 described later is divided into a wiring 133a, a wiring 133b, a wiring 133c, and a wiring 133d. Wiring separation opening 14
7, the second wiring and the first wiring are connected to each other through a wiring through contact hole 141 (and a contact plug 146) provided at a required portion of the intersection. The two-input NAND of this embodiment is connected to the basic cells.

In this example, the input signal line IN-1, the input signal line IN-2, the power supply line VDD, the ground line GND, and the output signal line OUT are connected to a line 121a and a line 12, respectively.
1c, wiring 123a, wiring 122c, and wiring 123c
It is composed of Wiring 1 that is input signal line IN-1
21a is connected to the gate electrode 111 via the wiring through contact hole 141 and also to the wiring 131a. The wiring 121c (which is IN-2) is connected to the gate electrode 112 via the wiring through contact hole 141 and also to the wiring 133d. (VDD
The wiring 123 a is a wiring through contact hole 141.
Is connected to the P-type source / drain region 117b through the wiring 132b. The wiring 122c (which is GND) is connected to the N-type source / drain region 116c via the wiring through contact hole 141 and also to the wiring 133c. The wiring 123c (which is OUT) is connected to the P-type source / drain region 117a via the wiring through contact hole 141 and also to the wiring 131b, and is connected to the P-type source / drain through another wiring through contact hole 141. Drain region 11
7c and also to the wiring 133b. The wiring 131b connected to the wiring 123c is
Further, it is connected to the N-type source / drain region 116a via another wiring through contact hole 141 and also to the wiring 122b.

In the two-input NAND of this technical example, the second wiring directly functioning as a connection wiring is only the wiring 131b provided for a part of the connection of the output signal line OUT. Wirings 131a, 132b, 133b, 133c, 1
The reason for providing the 33d or the like is that, as described later,
Related to the manufacturing method of the technical example.

Although this technical example is a two-input NAND, the wiring penetrating contact hole 1 is provided for one basic cell.
By selecting the intersection where the 41 is to be provided and selecting the setting position of the wiring dividing opening 147, respectively, a two-input NO
Other basic gates, such as R, two-stage inverters, etc., can be configured. Further, another basic gate can be formed using a plurality of basic cells.

FIG. 4 to FIG. 6 which are schematic plan views of the manufacturing process of the semiconductor device, and FIG. 7 which is a schematic cross-sectional view of the manufacturing process along the line AA in FIG.
When a cross-sectional schematic view of a manufacturing process of the semiconductor device, and FIG. 8 is a schematic sectional view of a manufacturing process of the line BB of Figure 1, Referring also the FIGS. 1 and 2, in this example technique The semiconductor device is formed as follows.

First, a P-well 102 and an N-well 103 are provided in predetermined regions on the surface of a P-type silicon substrate 101, respectively.
Is formed. For example, a LOCOS type field oxide film 10
6 are formed, and element formation regions 104 and 105 are defined on the surfaces of the P well 102 and the N well 103, respectively. Note that what is formed in the element isolation region is not limited to only the field oxide film 106. After a gate oxide film 108 is formed on the surfaces of the element formation regions 104 and 105 by thermal oxidation, gate electrodes 111 and 112 made of, for example, a tungsten polycide film are formed. The constituent materials of the gate electrodes 111 and 112 are not limited to the tungsten polycide film. N-type source / drain regions 116a and 116 are formed on the surface of the element formation region 104 by ion implantation using the field oxide film 106 and the gate electrodes 111 and 112 as a mask.
b, 116c are formed, and the element formation region 105 is further formed.
Of the P-type source / drain regions 117a, 117
b, 117c are formed to form a basic cell of this technical example [FIGS. 4, 7 (a), 8 (a)].

Next, for example, a silicon oxide film, BP
An SG film is formed, the BPSG film is reflowed by heat treatment, CMP is applied, and a silicon oxide film is formed again on the entire surface, has a flattened surface, and is made of a silicon oxide-based insulating film (first). 2) An interlayer insulating film 120 is formed. In this technical example, the reason why the interlayer insulating film 120 is preferably formed of a silicon oxide-based insulating film is to simplify an etching process for forming a wiring through contact hole and a wiring cutting opening in a later process. The surface of the interlayer insulating film 120 is preferably planarized in order to facilitate formation of a contact plug filling the through-hole contact hole. Next, a first conductor film made of, for example, a tungsten silicide film is formed on the entire surface and is patterned to form (first) wirings 121a to 121a.
121c, 122a to 122c, 123a to 123c, etc. are formed on the surface of the interlayer insulating film 120 [FIGS.
(B), FIG. 8 (b)]. In this technical example, the constituent material of the first conductor film is not limited to the tungsten silicide film, but may be an N-type polycrystalline silicon film or an N-type polycrystalline silicon film.
An amorphous silicon film, another refractory metal silicide film, a refractory metal film, a titanium nitride film, an aluminum alloy film, or the like may be used.

Subsequently, a (second) interlayer insulating film 130 having a flattened surface and made of a silicon oxide-based insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 120. Next, a second conductor film made of, for example, a tungsten silicide film is formed on the entire surface and patterned to form (second) wirings 131, 132, 133, etc. on the surface of the interlayer insulating film 130 [ Figures 6 and 7
(C), FIG. 8 (c)]. The constituent material of the second conductor film is preferably the same as the constituent material of the first conductor film,
It is not limited to this. When the constituent materials of the first and second conductor films are the same, the etching is simplified when forming the wiring through contact hole and the wiring dividing opening in a later step.

Thereafter, a (third) interlayer insulating film 140 having a flattened surface and made of a silicon oxide insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 120. At this stage, the formation of the semiconductor substrate (prepared before customer request) according to the present embodiment is completed. On the basis of connection information requested by a customer, a first photomask (not shown) for connection between the first wiring, the second wiring and the basic cell, and a separation for the second wiring are provided. A second photo mask (not shown) is created.

Using the first photo mask, a first photo resist film pattern (not shown) is formed on the surface of the interlayer insulating film 140. This first photo
Using the resist film pattern as a mask, for example, CF ₄ + C
The interlayer insulating film 140 is selectively anisotropically etched by the first etching gas of HF ₃ . continue,
For example, the wirings 131, 132 and 133 are selectively anisotropically etched by a second etching gas of Cl ₂ + O ₂ . Further, a selective anisotropic etching of the interlayer insulating film 130 with the first etching gas and a second
Wirings 121a, 121c, 1 by the etching gas of
Selective anisotropic etching such as 22b, 122c, 123a, 123c and the like and selective anisotropic etching of the interlayer insulating film 120 with the first etching gas are sequentially performed, and Gate electrode 11
1, 112, N-type source / drain regions 116a, 11
6c, P-type source / drain regions 117a, 117b,
Wiring through contact holes 14 each reaching 117c etc.
1 is formed. When the first or second wiring is made of, for example, an aluminum alloy film, the second etching gas for the wiring is, for example, BCl ₃ + Cl ₂
Is used.

After the first photo-resist film pattern is removed, a titanium film and a titanium nitride film (not explicitly shown) are sequentially formed on the entire surface by, for example, sputtering and reactive sputtering. A tungsten film (not explicitly shown) is formed on the entire surface. A tungsten film, a titanium nitride film, and a titanium film are etched back to fill the wiring through contact hole 141 (comprising a third conductor film composed of the tungsten film, the titanium nitride film, and the titanium film). [FIG. 2, FIG. 7 (d), FIG.
(D)]. The third conductor film forming the contact plug 146 is not limited to a tungsten film or the like. For example, an aluminum film or a copper film formed by LPCVD, an aluminum film formed by high-temperature sputtering at about 500 ° C. For example, formation of an aluminum alloy film may be used.

Next, a second photo resist film pattern (not shown) is formed on the surface of the interlayer insulating film 140 by using the second photo mask. Using the second photo-resist film pattern as a mask, a wiring dividing opening 147 is formed, and the wiring 131 is replaced with a wiring 131a.
To 131c, and the wiring 132 is divided into wirings 132a to 132c.
32c, and the wiring 133 is divided into wirings 133a to 133
d. The method of forming these wiring dividing openings 147 is as follows. First, the wirings 131 to 133
The interlayer insulating film 140 is selectively anisotropically etched by the first etching gas until the upper surface of the substrate is exposed. Subsequently, anisotropic etching of the interlayer insulating film 140 and the wirings 131 to 133 is performed until the wirings 131 to 133 are removed. The interlayer insulating film 140 and the wiring 131
To 133, there are two methods. The first method is a method in which the first insulating gas and the second etching gas are alternately used to divide the interlayer insulating film 140 and the wirings 131 to 133 into several stages to perform etching removal. In this method, termination is performed by etching using a first etching gas. The second method is a method using a mixed gas of the first etching gas and the second etching gas. In either method, the wiring dividing opening 147 and the bottom surface are located lower than the surface of the interlayer insulating film 130. The wiring 13
A part of the diameter of each of the wiring dividing openings 147 that divides the wirings 131, 132, and 133 has the wiring 131, 13, respectively.
It is necessary that the line width is wider than 2,133. The formation of the wiring through contact hole 141 requires high-precision etching that suppresses over-etching of the second and first wirings. On the other hand, the wiring separation opening 1
In the formation of 47, since the second wiring is cut off,
Rough etching can be performed to some extent as compared with the formation of the wiring through contact hole 141.

After the second photo-resist film pattern is removed, an insulating film 150 made of, for example, a silicon oxide film is used.
Is formed on the entire surface by LPCVD. As a result, the wiring dividing opening 147 is filled with the insulating film 150, and the semiconductor device according to this technical example is completed [FIGS. 1, 2, 7 (e), 8 (e)]. In this technology example, the second wiring (for example, wiring 13) that does not directly contribute to wiring connection
The provision of the method 2) makes it possible to form the wiring through contact hole by such sequential etching. For example, if the second wiring (and the first wiring) is formed only in the portion directly contributing to the wiring connection, such as the wiring 132b in which the wiring 131 is divided, it is necessary to form the transfer disconnection opening. The photolithography process of the above becomes unnecessary. However, in addition to the photolithography step for forming the wiring through contact hole 141, the wiring 1 (without penetrating the first wiring)
A photolithography step for forming a contact hole for directly connecting 32b and the N-type source / drain region 116a, and a wiring 123 (without penetrating the second wiring)
A photolithography step for forming a contact hole directly connecting c and the P-type source / drain region 117c is required separately.

[0035]

In the above technical example, only one kind of wiring through contact hole penetrates the second wiring and the first wiring provided on the semiconductor substrate and reaches the semiconductor element provided on the surface of the semiconductor substrate. However, in the second technical example , in addition to the above-mentioned wiring through contact hole, the semiconductor device is provided on the semiconductor substrate without being directly connected to the semiconductor element provided on the surface of the semiconductor substrate. At least another type of wiring through contact hole penetrating the second wiring and the first wiring and used only for the direct connection of the second wiring and the first wiring is provided.

Referring to FIG. 9 which is a schematic plan view of the semiconductor device, and FIG. 10 which is a schematic cross-sectional view of the semiconductor device taken along line AA, BB and CC of FIG.
The second technical example has a pair of CMOs similar to the first technical example.
This is applied to a two-input NAND composed of S transistors. The second example technique, the differ in the first technical example, without being subjected to the connection between the semiconductor element provided on a surface of the semiconductor substrate, the second provided on a semiconductor substrate
Through the first wiring and the second wiring and the first wiring.
A second wiring penetrating contact hole provided only for connection of the first wiring, and a second wiring dividing opening for dividing the first wiring. The configuration of the semiconductor device according to the second technical example is as follows.

On the surface of a P-type silicon substrate 201, a P well 202 and an N well 203 are provided.
2, element formation regions 204, 2
A LOCOS field oxide film 206 is provided in an element isolation region on the surface of the P-type silicon substrate 201. A gate electrode 211 made of, for example, a tungsten silicide film, which is a first conductive film, is formed on the surface of the element forming region 204 via the gate oxide film 208.
212 are provided, and these gate electrodes 211 and 212 are provided.
Extend on the surface of the field oxide film 206, respectively.
It extends over the surface of the element formation region 205 via the gate oxide film 208. Further, in a predetermined region on the surface of the field oxide film 206, a conductor film pad 214 made of the first conductor film in the same layer as the gate electrodes 211 and 212 is provided.

N-type source / drain regions 216a, 216b and 216c are provided on the surface of the element forming region 204 in a self-aligned manner with the gate electrodes 211 and 212, and two N-channel MOS transistors are provided in the element forming region 204. Have been. One N-channel MOS transistor includes a gate electrode 211, a gate oxide film 208, and N-type source / drain regions 216a and 216b, and the other N-channel MOS transistor has a gate electrode 212.
, Gate oxide film 208 and N-type source / drain region 21
6b and 216c. Element formation area 2
The P-type source / drain regions 217a, 217b, 21
7c are provided, and two P-channel MOS transistors are provided in the element formation region 205. One P-channel MOS transistor has a gate electrode 211, a gate oxide film 208, and P-type source / drain regions 217a and 217a.
17b, and the other P-channel MOS transistor includes a gate electrode 212, a gate oxide film 208, and P-type source / drain regions 217b and 217c. On the surface of P-type silicon substrate 201, a first CMOS transistor including one N-channel MOS transistor and one P-channel MOS transistor, and a second CMOS transistor including the other N-channel MOS transistor and the other P-channel MOS transistor
A basic cell including a transistor is provided.

The field oxide film 206 and the first and second
The surface of the P-type silicon substrate 201 including the CMOS transistor and the conductive film pad 214 is covered with a (first) interlayer insulating film 220 made of a silicon oxide based insulating film. The surface of the interlayer insulating film 220 is preferably formed by CMP.
And so on. On the surface of the interlayer insulating film 220, the wirings 221a and 221 (first wirings) made of a second conductor film such as a tungsten silicide film, for example.
21b, 221c, 222aa, 222ab, 222a
c, 222b, 222ca, 222cb, 223aa,
For example, 223ab, 223b, 223c, etc. are provided in parallel in the horizontal direction (on the paper surface of FIG. 9). Wiring 2
22aa, the wiring 222ab, and the wiring 222ac are obtained by dividing the wiring 222a (described later) by a second wiring dividing opening (described later). The wiring 223aa and the wiring 223ab are separated by a second wiring separating opening (to be described later).
Wire 223a is (to be described later) Ru der those separated by the second wiring dividing the opening.

The surface of the interlayer insulating film 220 including these wirings 221a and the like is made of a silicon oxide based insulating film (second
2) is covered with an interlayer insulating film 230. The surface of the interlayer insulating film 230 is also preferably planarized by CMP or the like. On the surface of the interlayer insulating film 230, a second wiring made of a third conductive film is provided. These second
Is preferably formed of, for example, a tungsten silicide film like the first wiring (see FIG. 9).
(In the plane of the drawing). The second wiring provided on one basic cell includes, for example, wirings 231a, 231b, and 231c (a wiring 231 described later is divided by a first wiring dividing opening described later).
And wirings 232a, 232b (which are formed by dividing a later-described wiring 232 by a first wiring dividing opening described later).
232c and wirings 233a and 2 (a wiring 233 described later is divided by a first wiring dividing opening described later).
33b, 233c, 233d, wiring 234, and wiring 2
35. Each of these wirings 234 such that not extend over the elementary cells adjacent in the vertical direction (in the plane of FIG. 9).

Immediately above the gate electrode 211, the wiring 2
A first intersection is formed between the wiring 21a and the wiring 231a, the wiring 221b and the wiring 231b, and the wiring 221c and the wiring 231c with an interlayer insulating film 230 interposed therebetween. Immediately above the gate electrode 212, a first intersection is formed between the wiring 221a and the wiring 233a, between the wiring 221b and the wiring 233b, and between the wiring 221c and the wiring 233d via the interlayer insulating film 130.

Immediately above the N-type source / drain regions 216a, the wirings 222ab, 222b and 222cb
A first intersection is formed between the first wiring and the wiring 231b with an interlayer insulating film 230 interposed therebetween. Immediately above the N-type source / drain region 216b, the wiring 222ab,
First intersections are formed between 222b and 222cb and wiring 132c with an interlayer insulating film 230 interposed therebetween. Immediately above the N-type source / drain region 216c, a first intersection is formed between the wirings 222ab, 222b and 222cb and the wiring 233c with an interlayer insulating film 230 interposed therebetween. Immediately above the P-type source / drain regions 217a, the wirings 223ab, 2
First intersecting portions are formed between the wires 23b and 223c and the wiring 131b with an interlayer insulating film 230 interposed therebetween. Immediately above the P-type source / drain region 217b, the wirings 223ab, 223b and 223c and the wiring 2
First intersecting portions are formed between the first intersecting portions 32b and the second intersecting portions 32b, respectively. Immediately above the P-type source / drain regions 217c, the wirings 223ab, 223b
And 223c and a wiring 233b, a first intersection is formed with an interlayer insulating film 230 interposed therebetween.
Further, immediately above the conductor film pad 214, the wiring 2
34a and the wiring 223ab, and the wirings 234b and 222
cb through the interlayer insulating film 230 respectively.
Are formed. Although the second intersection is formed other than directly above the conductor film pad 214, a second wiring through contact hole described later is not provided in such a second intersection.

The surface of the interlayer insulating film 230 including the second wiring is covered with a (third) interlayer insulating film 240 made of a silicon oxide based insulating film. The surface of the interlayer insulating film 240 is also preferably planarized by CMP or the like. In the interlayer insulating film 240, at the first intersection provided at a required position, the interlayer insulating film 240, the second wiring, the interlayer insulating film 230, the first wiring, and the interlayer insulating film 240 are separated from the surface of the interlayer insulating film 240. There is provided a first wiring through contact hole 241 that penetrates through the film 220 and reaches the first or second CMOS transistor. Further, in the interlayer insulating film 240, at least a part of the second intersection provided directly above the conductor film pad 214, the interlayer insulating film 240, the second wiring, The conductor film pad 21 penetrates through the interlayer insulating film 230, the first wiring and the interlayer insulating film 220, respectively.
4, a second through-wire contact hole 242 is provided. The (line) width of the conductor film pad 214 is set wider than the line width of the first and second wirings (and the diameter of the second wiring through contact hole 242) at the second intersection.

Further, the interlayer insulating film 240 penetrates from the surface of the interlayer insulating film 240 (immediately above the field oxide film 206 in a portion where the first and second CMOS transistors are not provided) from the surface of the interlayer insulating film 240. A first wiring separation opening 247 that divides the second wiring to penetrate the interlayer insulating film 230 and reaches the interlayer insulating film 220;
The first wiring is formed from the surface of the interlayer insulating film 240 through the interlayer insulating film 240 and through the interlayer insulating film 230 (immediately above the field oxide film 106 in a portion where the second CMOS transistor is not provided). A second wiring dividing opening 248 is provided which is divided and reaches the interlayer insulating film 220.

The diameters of the wiring through contact holes 241 and 242 are set smaller than the line widths of the first and second wirings (at least at the intersections). The wiring through contact holes 241 and 242 have the wiring through contact holes 241 and 241 respectively.
242 is filled with a contact plug 246 composed of a conductive barrier film that directly covers the bottom and side surfaces (for example, a titanium nitride film is laminated on a titanium film) and a tungsten film that covers the surface of the conductive barrier film. ing. The wiring separating openings 247 and 248 are filled with an insulating film 250 made of, for example, a silicon oxide film.
0 covers the surface of the interlayer insulating film 240.

[0047] 2-input NAND in this second example technique
Here, the first input signal line (IN-1), the second input signal line (IN-2), the power supply wiring (VDD), and the ground wiring (GN
D) and the output signal line (OUT)
a, a wiring 221c, a wiring 234a, a wiring 234b, and a wiring 223c. The wiring 221a is connected to the gate electrode 211 via the wiring through contact hole 241 and also to the wiring 231a. The wiring 221c is connected to the gate electrode 212 via the wiring through contact hole 241 and also to the wiring 233d. The wiring 234a is a wiring through contact hole 2
42, and is connected to the wiring 233ab.
3ab is connected to the P-type source / drain region 217b via the wiring through contact hole 241. Wiring 23
4c denotes a wiring 222 through a wiring through contact hole 242.
The wiring 222 cb is connected to the N-type source / drain region 216 via the wiring through contact hole 241.
c. The wiring 223 c is connected to the P-type source / drain region 217 through the wiring through contact hole 241.
a as well as the wiring 231b. The wiring 233b is connected to the P-type source / drain region 217c through another wiring through contact hole 241.
Is also connected. The wiring 231b connected to the wiring 223c is connected to another wiring through contact hole 241.
Is connected to the N-type source / drain region 216a via the wiring 222ab.

In the second technical example, unlike the first technical example, the power supply wiring and the ground wiring are composed of the second wiring, and these wirings are orthogonal to the input signal lines and the output signal lines. Are arranged as follows. Such an arrangement becomes possible by providing the second wiring through contact hole and the second wiring dividing opening. As a result, this second
The technical example has a higher degree of freedom in design than the first technical example.

In the two-input NAND of the second technical example, the first wiring that directly functions as the connection wiring is the first wiring.
221a, 221c and 223c as input signal lines, second input signal lines and output signal lines, and a wiring 223a.
b and 222cb. Wirings 223ab and 2
Reference numeral 22cb denotes a first wiring divided by the wiring dividing opening 248. The second wirings that directly function as connection wirings are wirings 234a and 234b, which are a power supply wiring and a grounding wiring, and a wiring 231b. The wiring 231b is a second wiring divided by the wiring dividing opening 247.

Although the second technical example is a two-input NAND, the wiring penetrating contact hole 241 and the wiring penetrating contact hole (including the set position of the conductive film pad 214) are provided for one basic cell. 242, wiring division opening 24
By selecting 7,248 setting positions, 2
It is possible to form another basic gate with an input NOR, a two-stage inverter. Further, another basic gate can be formed using a plurality of basic cells.

FIG. 10 is a schematic cross-sectional view of the manufacturing process of the semiconductor device, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG.
9 and FIG. 9 are schematic cross-sectional views of a semiconductor device manufacturing process.
Referring to FIG. 12, which is a schematic cross-sectional view of the manufacturing process using the CC line, and FIGS. 9 and 10, the semiconductor device of the second technical example is formed as follows.

First, a P-well 202 and an N-well 203 are provided in predetermined regions on the surface of a P-type silicon substrate 201, respectively.
Is formed. For example, a LOCOS type field oxide film 20 is formed in an element isolation region on the surface of the P-type silicon substrate 201.
6 are formed, and element formation regions 204 and 205 are defined on the surfaces of the P well 202 and the N well 203, respectively. Note that what is formed in the element isolation region is not limited to only the field oxide film 206. The gate oxide film 2 is formed on the surfaces of the element formation regions 204 and 205 by thermal oxidation.
08 are formed, the gate electrodes 211 and 112 made of a first conductive film, for example, a tungsten polycide film are formed.
12 and a conductor film pad 214 are formed. The constituent materials of the gate electrodes 211 and 212 and the conductor film pad 214 are not limited to the tungsten polycide film. Field oxide film 206, gate electrode 21
The N-type source / drain regions 21 are formed on the surface of the
6a, 216b and 216c are formed, and the P-type source / drain regions 21
7a, 217b and 217c are formed to form the basic cell of the second embodiment.

Next, for example, a silicon oxide film, BP
An SG film is formed, the BPSG film is reflowed by heat treatment, CMP is performed, and a silicon oxide film is formed again on the entire surface, has a flattened surface, and is made of a silicon oxide-based insulating film (first). 2) An interlayer insulating film 220 is formed. Next, a second conductor film made of, for example, a tungsten silicide film is formed on the entire surface and patterned to form (first) wirings 221a to 221c and 222a to 2c.
22c, 223a to 223c and the like are formed on the surface of the interlayer insulating film 220. In the first embodiment, the constituent material of the second conductor film is not limited to the tungsten silicide film, but may be an N-type polycrystalline silicon film or an N-type polycrystalline silicon film.
An amorphous silicon film, another refractory metal silicide film, a refractory metal film, a titanium nitride film, an aluminum alloy film, or the like may be used.

Subsequently, a (second) interlayer insulating film 230 having a planarized surface and made of a silicon oxide-based insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 220. Next, a third conductor film made of, for example, a tungsten silicide film is formed on the entire surface and patterned to form (second) wirings 231 to 233, 234a, and 23.
4b and the like are formed on the surface of the interlayer insulating film 230 [FIG.
1 (a), FIG. 12 (a)]. The constituent material of the third conductor film is preferably the same as the constituent material of the second conductor film, but is not limited thereto.

Thereafter, a (third) interlayer insulating film 240 having a flattened surface and made of a silicon oxide-based insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 220. At this stage, the formation of the semiconductor substrate (prepared before customer request) according to the second technical example is completed. Based on connection information requested by a customer, a first photo-coupler for connection to the first and second wirings and the basic cell and connection to the first and second wirings (and conductor film pads). A mask (not shown) and a second photomask (not shown) for separating the first and second wirings are created.

Using the first photo mask, a first photo resist film pattern (not shown) is formed on the surface of interlayer insulating film 240. This first photo
Using the resist film pattern as a mask, for example, CF ₄ + C
The interlayer insulating film 240 is selectively anisotropically etched by the first etching gas of HF ₃ . continue,
For example, the wirings 231 to 233, 234a, and 234b are selectively anisotropically etched by a second etching gas composed of Cl ₂ + O ₂ . Further, selective anisotropic etching of the interlayer insulating film 230 with the first etching gas and wirings 221a, 221a,
221c, 222a, 222b, 223a, 223c and the like, and selective anisotropic etching of the interlayer insulating film 220 with the first etching gas are sequentially performed. Cell gate electrodes 211 and 212, N-type source / drain regions 2
16a, 216c, P-type source / drain regions 217
a, 217b, 217c, etc. (first)
Wiring through contact hole 241 and conductor film pad 214
(Second) wiring through contact hole 242 is formed [FIGS. 11 (b) and 12 (b)]. This second technique
In the surgical example, by providing the conductor film pad 214, the wiring through contact hole 242 can be formed by such sequential etching.
When the first or second wiring is made of, for example, an aluminum alloy film, for example, BCl3 + Cl2 is used as the second etching gas.

After the first photo-resist film pattern is removed, a titanium film and a titanium nitride film (not explicitly shown) are sequentially formed on the entire surface by, for example, sputtering and reactive sputtering. A tungsten film (not explicitly shown) is formed on the entire surface. The tungsten film, the titanium nitride film and the titanium film are etched back to fill the wiring through contact holes 241 and 242 (comprising a fourth conductor film composed of these tungsten film, titanium nitride film and titanium film). A plug 246 is formed. The fourth conductor film forming the contact plug 246 is not limited to a tungsten film or the like. For example, an aluminum film or a copper film formed by LPCVD, an aluminum film formed by high-temperature sputtering at about 500 ° C. For example, formation of an aluminum alloy film may be used.

Next, a second photo-resist film pattern (not shown) is formed on the surface of the interlayer insulating film 240 using the second photo-mask. Using the second photoresist film pattern as a mask, wiring dividing openings 247 and 248 are formed by the following method, and wiring 231 is divided into wirings 231a to 231c.
The wiring 232 is divided into the wirings 232a to 232c, and the wiring 233 is divided into the wirings 233a to 233d.
2a is divided into wirings 222aa to 222ac,
The wiring 22c is divided into the wirings 222ca and 222cb, the wiring 223a is divided into the wirings 223aa and 223ab, and the wiring 223c is divided into the wirings 223ca and 223cb [FIGS. 9, 10, 11, 11C, and 12C]. ].

The method of forming the wiring dividing openings 247 and 248 is as follows. First, the wirings 231 to 233
The interlayer insulating film 240 is selectively anisotropically etched by the first etching gas until the upper surface of the substrate is exposed. Subsequently, until the wirings 231 to 233 are removed, the anisotropic etching of the interlayer insulating film 240 and the wirings 231 to 233 (only the interlayer insulating film 240 in a portion where the second wiring wiring dividing opening is formed) is performed. Done. Further, wiring 2
21a, 221b, 222a, 222c, 223a, 2
The interlayer insulating film 230 is selectively anisotropically etched by the first etching gas until the upper surface of 23c is exposed. Subsequently, the wirings 221a, 221b, 222
until a, 222c, 223a, 223c are removed
The interlayer insulating film 230 and the wirings 221a, 221b, 222
Anisotropic etching of a, 222c, 223a, 223c and (only the interlayer insulating film 230 in the portion where the first wiring / interconnection opening is formed) is performed. For example, there are two methods for anisotropic etching of the second wiring and the interlayer insulating film 240, as in the example of the first embodiment. The first method uses the first etching gas and the second etching gas alternately to form the interlayer insulating film 240 and the wirings 231 to 233 (in the portion where the second wiring wiring separating opening is formed, the interlayer insulating film 240 and the wiring 231 to 233 are formed). In this method, only the insulating film 240 is divided into several stages to perform etching removal. The second method is a method using a mixed gas of the first etching gas and the second etching gas. In any case, the bottom surfaces of the wiring separation openings 247 and 248 are positioned lower than the surface of the interlayer insulating film 220. Note that the wirings 231 to 233 (or the wirings 221a and 221
1b, 222a, 222c, 223a, and 223c), a part of the diameter of each of the wiring cutting openings 247 (or the wiring cutting openings 248) is divided into the wiring 23
1 to 233 (or the wirings 221a, 221b, 222
a, 222c, 223a, 223c).

After the second photo-resist film pattern is removed, an insulating film 250 made of, for example, a silicon oxide film
Is formed on the entire surface by LPCVD. As a result, the wiring separating openings 247 and 248 are filled with the insulating film 250, and the semiconductor device according to the second technical example is completed [FIGS. 9 and 10].

[0061]

The second technical example has first and second wiring through contact holes and first and second wiring separating openings,
Although the conductor film pad is used for forming the second wiring through contact hole, in the embodiment of the present invention ,
A trench is formed in the element isolation region, and the trench is filled with a field insulating film. It is provided on the surface of the insulating film. Further, in this embodiment , the first dummy pattern is provided by the second conductive film in the same layer as the first wiring, and the second dummy pattern is provided by the third conductive film in the same layer as the second wiring.・ A pattern is provided. Thus, in the present embodiment, first,
The second wiring dividing opening reaches the conductor film pad. Further, a third wiring penetrating contact hole penetrating through the second wiring and reaching the semiconductor element at a portion except for the first intersection, and penetrating the first wiring at a portion excluding the first crossing. As a result, it becomes possible to provide a fourth wiring through contact hole reaching the semiconductor element.

FIG. 13 which is a schematic plan view of a semiconductor device,
AA line in FIG. 13, referring to FIG. 14 and is a schematic sectional view of line BB and line CC, those embodiments of the invention, which is applied to the N-channel MOS transistor constituting a part of the random logic And is as follows.

A P-well 202 is provided on the surface of P-type silicon substrate 201, an element formation region 204 is provided on the surface of P-type silicon substrate 201, and a groove is provided on an element isolation region on the surface of P-type silicon substrate 201. In this groove, a field insulating film 207 made of, for example, a silicon oxide based insulating film is provided.
Is filled. A gate oxide film 208 is provided on the surface of the element formation region 204. Preferably, the height of the surface of the field insulating film 207 substantially coincides with the height of the surface of the portion including the element formation region 204 of the P-type silicon substrate 201. A gate electrode 213 made of, for example, a tungsten silicide film, which is a first conductor film, is provided on the surface of the element formation region 204 via a gate oxide film 208. The gate electrode 213 extends on the surface of the field insulating film 207. In a predetermined region on the surface of the field insulating film 207, a conductor film pad 215 made of the first conductor film in the same layer as the gate electrode 213 is provided. The conductor film pad 215 in the second embodiment is the same as the first embodiment in the second embodiment.
Unlike the first embodiment, at a position apart from the gate electrode 213 and the element formation region 204, first and second wiring separating openings described later reach, and first, second, third or later described later. It is provided at a position distant from the fourth wiring through contact hole.

An N-type source / drain region 216 is self-aligned with the gate electrode 213 on the surface of the element formation region 204.
a and N-type source / drain regions 216b are provided. N-channel MOS transistor has gate electrode 2
13 and a gate oxide film 208 and N-type source / drain regions 216a and 216b.

Field insulating film 207 and N-channel MO
The surface of the P-type silicon substrate 201 including the S transistor and the conductor film pad 215 is covered with an interlayer insulating film 220 made of a silicon oxide insulating film. The surface of the interlayer insulating film 220 is preferably planarized by CMP or the like. On the surface of the interlayer insulating film 220, wirings 225, 226a, 226b, and 2 (which are first wirings) made of a second conductor film such as a tungsten silicide film are used.
27, 228, etc. are provided. The wiring 226a and the wiring 226b are obtained by dividing the wiring 226 (described later) by a second wiring dividing opening (described later). Further, on the surface of the interlayer insulating film 220, a first dummy pattern 229 made of a second conductor film in the same layer as the first wiring is formed.
Is provided. The position where the dummy pattern 229 is provided is immediately above the conductor film pad 215 and immediately below the second wiring described later, and the position where the second wiring separating opening described later can be provided. The above N channel M
Immediately above the OS transistor, directly below a second wiring described later, and at a position where a third wiring through contact hole described later can be provided.

The surface of interlayer insulating film 220 including these wirings 225 and dummy patterns 229 is covered with interlayer insulating film 230 made of a silicon oxide insulating film. The surface of the interlayer insulating film 230 is also preferably planarized by CMP or the like. On the surface of the interlayer insulating film 230, a second wiring made of a third conductive film is provided. These second wirings are preferably formed of, for example, a tungsten silicide film similarly to the first wirings. For example, (a wiring 235 described later is divided by a first wiring dividing opening described later. ) Wiring 235
a, 235b, 235c, a wiring 236, and wirings 237a, 237b (a wiring 237 described later is divided by a first wiring dividing opening described later). Further, on the surface of the interlayer insulating film 230, a second dummy pattern 239 made of a third conductive film in the same layer as the second wiring is formed.
Is provided. The position where the dummy pattern 239 is provided is immediately above the conductor film pad 215 and the first wiring, and a position where a first wiring dividing opening described later can be provided, and the position where the N-channel MOS transistor and This is a position directly above the first wiring and at which a fourth wiring through contact hole described later can be provided.

A first crossing portion is formed immediately above the N-type source / drain region 216a between the wiring 226b and the wiring 236 via an interlayer insulating film 230. Immediately above the field insulating film 207 where the conductor film pad 215 is not provided, between the wiring 235a and the wiring 225, between the wirings 235b and 226b and the wiring 227, between the wiring 235c and the wiring 228, and between the wiring 236 and the wiring 236. A second intersection is formed between the wiring 225 and the wiring 228 and between the wiring 237a and the wiring 228 via an interlayer insulating film 230.

Second wiring and dummy pattern 239
Is covered with a (third) interlayer insulating film 240 made of a silicon oxide based insulating film. The surface of the interlayer insulating film 240 is also preferably planarized by CMP or the like. The interlayer insulating film 240 includes, for example, the interlayer insulating film 240, the wiring 236, and the interlayer insulating film 2 from the surface of the interlayer insulating film 240 at the first intersection.
30, the wiring 226b, and the interlayer insulating film 220, each reaching the N-type source / drain region 216b.
The wiring through contact hole 245a and the surface of the interlayer insulating film 240 at a part of the second intersection, for example, the interlayer insulating film 240 and the wiring 235a or the wiring 237b and the wiring 237b and the interlayer insulating film 230 and the wiring 226b or the wiring 227 or the wiring 228 And a second through-hole contact hole 245b that penetrates through the gate insulating film 220 and reaches the field insulating film 207, and a wiring from the surface of the interlayer insulating film 240 to the interlayer insulating film 240 immediately above the N-channel MOS transistor. 237a, the interlayer insulating film 230, the dummy pattern 229, and the third wiring through contact hole 245c which reaches the N-type source / drain region 216b through the interlayer insulating film 220;
Immediately above the transistor, a fourth wiring through contact reaching the gate electrode 213 from the surface of the interlayer insulating film 240 through the interlayer insulating film 240, the dummy pattern 239, the interlayer insulating film 230, the wiring 225, and the interlayer insulating film 220, for example. A hole 245d is provided. The diameters of the wiring through contact holes 245a to 245d are determined by the line width of the second wiring or the dummy pattern 239, which each penetrates.
Each line is set to be narrower than the line width of the first wiring or the dummy pattern 229.

Further, the interlayer insulating film 240 penetrates the interlayer insulating film 240 from the surface of the interlayer insulating film 240, divides the second wiring, penetrates the interlayer insulating film 230, and divides the dummy pattern 229. First wiring cut-off opening 247 that reaches conductive film pad 215 through interlayer insulating film 220
a, penetrating the interlayer insulating film 240 from the surface of the interlayer insulating film 240, dividing the dummy pattern 239, penetrating the interlayer insulating film 230, dividing the first wiring, and
A second wiring separation opening 247b penetrating through the first conductive film pad 0 and reaching the conductor film pad 215 is provided.

Wiring through contact holes 245a to 245d
Is composed of a conductive barrier film that directly covers the bottom and side surfaces of the wiring through contact holes 241 and 242 (for example, a titanium film is laminated on a titanium film) and a tungsten film that covers the surface of the conductive barrier film. Contact plug 2
46 are filled. Wiring separation opening 24
7a and 247b are filled with a second insulating film 250 made of, for example, a silicon oxide film, and the insulating film 250 covers the surface of the interlayer insulating film 240.

In this embodiment , the wiring through contact hole 2
The wiring 236 connected to the N-type source / drain region 216a through the wiring through hole 45a
a to the wiring 226b.
Is a wiring 235b through a wiring through contact hole 245b.
The wiring 235b is connected to the wiring 227 via another wiring through contact hole 245b. Also, a wiring 237 connected to the N-type source / drain region 216b via the wiring through contact hole 145c
a is the wiring 22 through the wiring through contact hole 245b.
8 is connected.

In the present embodiment , by providing the third and fourth wiring through-contact holes, the degree of freedom of design is further increased as compared with the second technical example. The present embodiment is concerned with N-channel MOS transistor constituting a part of a random logic, - C MOS transistors, Bi-CMOS transistor or bipolar
The present invention can be applied to a semiconductor device including a transistor and the like.

FIGS. 15 and 16 which are schematic plan views of the manufacturing process of the semiconductor device, and cross-sectional schematic diagrams of the manufacturing process of the semiconductor device, and FIG. 17 which is a cross-sectional schematic diagram of the manufacturing process along line AA in FIG. FIG. 18 is a schematic cross-sectional view of a manufacturing process of the semiconductor device, and FIG. 18 is a schematic cross-sectional view of the manufacturing process along line BB in FIG. 13, and FIG.
FIG. 19 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIG. 13.
13 and FIG. 14 together, the present embodiment
The semiconductor device of the embodiment is formed as follows.

First, a P well 202 and the like are formed in a predetermined region on the surface of a P-type silicon substrate 201. In the element isolation region on the surface of the P-type silicon substrate 201, the P-type silicon substrate 201 is anisotropically etched to form a groove, and a first insulating film is formed on the entire surface. Thus, a field insulating film 207 is formed. The surface of the element formation region 204 defined by the field insulating film 207 is covered with the gate oxide film 2 by thermal oxidation.
08 is formed. Thereafter, a gate electrode 21 made of, for example, a tungsten polycide film as a first conductor film is formed.
3 and the conductive film pad 215 are formed [FIG.
(A), FIG. 17 (a), FIG. 18 (a), FIG.
(A)]. The constituent materials of the gate electrode 213 and the conductor film pad 215 are not limited to the tungsten polycide film. By ion implantation using the field insulating film 207 and the gate electrode 213 as a mask, the N-type source / drain regions 2
16a, 216b and the like are formed.

Next, for example, a silicon oxide film, BP
An SG film is formed, the BPSG film is reflowed by heat treatment, CMP is performed, and a silicon oxide film is formed again on the entire surface, has a flattened surface, and is made of a silicon oxide-based insulating film (first). 2) An interlayer insulating film 220 is formed. Next, a second conductor film made of, for example, a tungsten silicide film is formed on the entire surface and patterned to form (first) wirings 2225, 226, 227, and 228.
And the like and the (first) dummy pattern 229 are formed on the surface of the interlayer insulating film 220 [FIG. 15 (b), FIG.
(B), FIG. 18 (b), FIG. 19 (b)]. The second
Also in the embodiment, the constituent material of the second conductor film is not limited to the tungsten silicide film.
A polycrystalline silicon film, an N-type amorphous silicon film, another refractory metal silicide film, a refractory metal film, a titanium nitride film, an aluminum alloy film, or the like may be used.

Subsequently, a (second) interlayer insulating film 230 having a flattened surface and made of a silicon oxide-based insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 220. Next, a third conductor film made of, for example, a tungsten silicide film is formed on the entire surface and patterned, so that the (second) wirings 235, 236, 237 and the like and the (second) dummy pattern 239 are formed. Interlayer insulating film 23
0 [FIG. 16 (a), FIG.
(C), FIG. 18 (c), FIG. 19 (c)]. The constituent material of the third conductor film is preferably the same as the constituent material of the second conductor film, but is not limited thereto.

Thereafter, a (third) interlayer insulating film 240 having a flattened surface and made of a silicon oxide-based insulating film is formed by, for example, the same method as the formation of the interlayer insulating film 220. At this stage, the formation of the semiconductor substrate (prepared before a request from a customer or the like) according to the present embodiment is completed. The first wiring and the second wiring are based on the connection information according to the request of the customer or the like.
A first photo mask (not shown) for providing a connection between the wiring of FIG.
And a second photo mask (not shown) for dividing the second wiring.

Using the first photo mask, a first photo resist film pattern (not shown) is formed on the surface of interlayer insulating film 240. This first photo
Using the resist film pattern as a mask, for example, CF ₄ + C
The interlayer insulating film 240 is selectively anisotropically etched by the first etching gas of HF ₃ . continue,
For example, a necessary portion of the wirings 235 to 237 and a required portion of the dummy pattern 239 are selectively anisotropically etched by a second etching gas of Cl ₂ + O ₂ . Further, selective anisotropic etching of the interlayer insulating film 230 is performed by the first etching gas, and selection of a necessary portion of the wirings 225 to 228 and a required portion of the dummy pattern 229 by the second etching gas. Anisotropic etching is performed, and selective anisotropic etching of interlayer insulating film 220 is performed with the first etching gas. By such sequential etching, the (first) wiring through contact hole 245a reaching the N-type source / drain region 216a and the like, and the (second) wiring through contact hole 2 reaching the field insulating film 207.
45b and a (fourth) wiring through contact hole 245d reaching the gate electrode 213 and the like, such as a (third) wiring through contact hole 245c reaching the N-type source / drain region 216b and the like [FIG. b), FIG.
(D), FIG. 18 (d), FIG. 19 (d)]. In the present embodiment , by providing the dummy patterns 229 and 239, it is also possible to form the wiring through contact holes 245c and 245d by such sequential etching. If the first or second wiring is made of, for example, an aluminum alloy film, the second etching
BCl3 + Cl2 is used as the gas.

In the present embodiment , unlike the first technical example, the second wiring through contact hole 245b is formed in the field insulating film 2 (instead of reaching the conductor film pad 215).
07 has been reached. When the field insulating film 207 is made of a silicon oxide-based insulating film, the bottom surface of the wiring through contact hole 245b is located lower than the surface of the field insulating film 207. In the present embodiment , the first technique
Different from the surgical example, a large number of locations (second intersections) that can become the second wiring through contact holes are provided in close proximity. Therefore, it is not preferable to provide the conductor film pads in an isolated shape so that the second wiring through contact hole reaches these conductor film pads. In the present embodiment , the field insulating film 207 having the above-mentioned shape (in place of the LOCOS type field oxide film) is formed by the interlayer insulating film 2 when the second wiring through contact hole is formed.
This is because the etching of No. 20 is adapted to the etching of the interlayer insulating film 220 when the third and fourth wiring through contact holes are formed.

After the first photo-resist film pattern is removed, a titanium film and a titanium nitride film (not explicitly shown) are sequentially formed on the entire surface by, for example, sputtering and reactive sputtering. A tungsten film (not explicitly shown) is formed on the entire surface. The tungsten film, the titanium nitride film, and the titanium film are etched back to fill the wiring through contact holes 245a to 245d (comprising a fourth conductor film composed of the tungsten film, the titanium nitride film, and the titanium film). A plug 246 is formed. Note that the fourth conductor film forming the contact plug 246 is not limited to a tungsten film or the like, but may be, for example, an LPCVD film.
Of an aluminum film or an aluminum alloy film by high-temperature sputtering at about 500 ° C. may be used.

Next, a second photo resist film pattern (not shown) is formed on the surface of the interlayer insulating film 240 using the second photo mask. Using the second photoresist film pattern as a mask, wiring dividing openings 247a and 247b are formed by the method described below, and wiring 235 is divided into wirings 235a to 235c, and wiring 237 is divided into wirings 237a and 237b. Divided,
Wirings 226 are wirings 226a and 226b [FIG.
4].

The method of forming the wiring dividing openings 247a and 247b is as follows. First, wiring 235, 2
37 and the upper surface of the dummy pattern 239 are exposed by the first etching gas until the upper surface of the dummy pattern 239 is exposed.
0 is selectively anisotropically etched. Then, wiring 2
The interlayer insulating film 240 and the wirings 235 and 2
Anisotropic etching with 37 and dummy pattern 239 is performed. Further, the first etching process is performed until the upper surfaces of the wiring 226 and the dummy pattern 229 are exposed.
The interlayer insulating film 230 is selectively anisotropically etched by the gas. Subsequently, the anisotropic etching of the interlayer insulating film 230, the wiring 226, and the dummy pattern 229 is performed until the wiring 226 and the dummy pattern 229 are removed and separated. Further, the interlayer insulating film 220 is selectively anisotropically etched until the conductive film pad 215 is reached. In the second embodiment, the conductive film pad 2 is used for anisotropic etching of the interlayer insulating film 220.
Reference numeral 15 functions as an etching stopper.

Anisotropic etching of second wiring and dummy pattern 239 made of second conductive film and interlayer insulating film 240, first wiring and dummy pattern 229 made of first conductive film, There are two methods for anisotropic etching with the interlayer insulating film 230 as in the first technical example. In the first method, the first insulating gas and the second etching gas are alternately used to form the interlayer insulating film 24.
0, wiring 235, 237 and dummy pattern 239
(Further, the interlayer insulating film 230, the wiring 226, and the dummy pattern 229) are divided into several stages, and are etched and removed. The second method is the first
And a mixed gas of the second etching gas and the second etching gas. The wirings 235 and 23
7, a part of the diameter of each of the wiring division openings 247a (or the wiring division openings 247b) that divides the dummy pattern 229 (or the wiring 226 and the dummy pattern 239) is divided into the wirings 235 and 237 and the dummy
It must be wider than the line width of the pattern 239 (or the wiring 226 and the dummy pattern 239).

In the present embodiment , the dummy pattern 23
9,229 are present, since the conductive film pads 215 functions as an etching stopper, the first from the first technique <br/> example, to control the formation of the second wiring dividing opening easily Become.

After the second photo resist film pattern is removed, an insulating film 250 made of, for example, a silicon oxide film is formed.
Is formed on the entire surface by LPCVD. As a result, the wiring separation openings 247a and 247b are filled with the insulating film 250, and the semiconductor device according to the present embodiment is completed (FIGS. 13 and 14).

[0087]

As described above, in the semiconductor device according to the present invention, at least the first wiring is provided on the surface of the first interlayer insulating film covering the surface of the semiconductor substrate provided with the semiconductor element. At least a second wiring is provided on the surface of the second interlayer insulating film covering the surface of the first interlayer insulating film;
The surface of the second interlayer insulating film is covered with the third interlayer insulating film. Further, the third interlayer insulating film includes a third interlayer insulating film, a second wiring, a second interlayer insulating film, a first wiring, and a wiring that reaches the semiconductor element through the first interlayer insulating film. At least a through contact hole and a wiring dividing opening for penetrating the third interlayer insulating film and dividing the second wiring are provided.

Since the semiconductor device has such a structure, according to the present invention, a semiconductor substrate formed up to the third interlayer insulating film is prepared, and the above-mentioned wiring through contact hole and wiring dividing opening are prepared according to a customer request. By performing two photolithography steps or the like necessary for forming a part, a semiconductor device that captures connection information that satisfies customer requirements can be formed.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device of one technical example related to the present invention.

2 is a schematic cross-sectional view of line AA and line BB in FIG.

FIG. 3 shows a two-input NAND for explaining a first technical example ;
It is a circuit diagram of.

FIG. 4 is a schematic plan view of a manufacturing step of the semiconductor device of FIG . 1 ;

FIG. 5 is a schematic plan view of a manufacturing step of the semiconductor device of FIG . 1 ;

FIG. 6 is a schematic plan view of a manufacturing step of the semiconductor device of FIG . 1 ;

FIG. 7 is a schematic cross-sectional view of the semiconductor device along the line AA in FIG . 1 during the manufacturing process;

FIG. 8 is a schematic cross-sectional view of the manufacturing process of the semiconductor device taken along the line BB of FIG . 1 ;

FIG. 9 is a schematic plan view of a second technical example related to the present invention.

[10] AA line of FIG. 9 is a schematic cross-sectional view of line BB and line CC.

11 is a cross-sectional schematic view of a manufacturing process of the line AA in FIG.

FIG. 12 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIG . 9;

13 is a schematic plan view of an embodiment of the present invention.

[14] Figure 13 the line AA is a schematic cross-sectional view of line BB and line CC.

FIG. 15 is a schematic plan view of the manufacturing process of the semiconductor device in FIG . 13 ;

16 is a schematic plan view of a manufacturing step of the semiconductor device in FIG . 13 ;

17 is a cross-sectional schematic view of a manufacturing process of the line AA in FIG. 13.

18 is a cross-sectional schematic view of a production process at the BB line of FIG. 13.

19 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIG . 13.

[Explanation of symbols]

101, 201 P-type silicon substrate 102, 202 P well 103, 203 N well 104, 105, 204, 205 Element formation region 106, 206 Field oxide film 108, 208 Gate oxide film 111, 112, 211, 212, 213 Gate electrode 116a to 116c, 216a to 216c N-type source / drain regions 117a to 117c, 217a to 217c P-type source / drain regions 120, 130, 140, 220, 230, 240
Interlayer insulating films 121a-121c, 122a-122c, 123a-
123c, 131, 131a to 131c, 132, 13
2a to 132c, 133, 133a to 133d, 221
a to 221c, 222a, 222aa to 222ac, 2
22b, 222c, 222ca, 222cb, 223
a, 223aa, 223ab, 223b, 223c, 2
25, 226, 226a, 226b, 227, 228,
231, 231a to 231c, 232, 232a to 23
2c, 233, 233a to 233d, 234a, 234
b, 235, 235a to 235c, 236, 237, 2
37a to 237c Wirings 141, 241, 242, 245a to 245d Wiring through contact holes 146, 246 Contact plugs 147, 247, 247a, 247b, 248 Wiring opening 150, 250 Insulating film 207 Field insulating film 214, 215 Conductor Membrane pads 229, 239 Dummy patterns Q _N1 , Q _N2 N-channel MOS transistors Q _P1 , Q _P2 P-channel MOS transistors IN-1, IN-2 Input signal line OUT Output signal line V _DD Power supply wiring GND Ground wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A field insulating film filled with a first insulating film is provided in a groove formed in an element isolation region on a surface of a semiconductor substrate, and at least an element forming region on a surface of the semiconductor substrate. In
A semiconductor element is provided; and a conductor film pad made of a first conductor film is provided on a surface of the field insulating film in a portion separated from the semiconductor element. , The surface of the semiconductor substrate including the conductor film pad and the field insulating film is covered with a first interlayer insulating film made of a silicon oxide based insulating film, and the surface of the first interlayer insulating film is A first wiring made of a second conductor film is provided, and a first dummy pattern made of the second conductor film is provided on a required portion of the surface of the first interlayer insulating film. A surface of the first interlayer insulating film including the first wiring and the first dummy pattern is covered with a second interlayer insulating film made of a silicon oxide based insulating film; On the surface of the interlayer insulating film A second wiring made of a third conductive film is provided, and a second dummy pattern made of the third conductive film is provided on a required portion of the surface of the second interlayer insulating film. The surface of the second interlayer insulating film including the second wiring and the second dummy pattern is covered with a third interlayer insulating film made of a silicon oxide based insulating film; wherein the second of said interlayer insulating film and the second wiring through a first wiring is it has a first cross section intersecting at right above the semiconductor device was provided et the semiconductor element A second intersection portion where the second wiring intersects with the first wiring via the second interlayer insulating film immediately above the field insulating film excluding the portion; A contact plug made of a fourth conductor film at the intersection of And the first and second
A first wiring through contact hole having a diameter smaller than the line width of
Through the second interlayer insulating film, the second wiring, the second interlayer insulating film, the first wiring, and the first interlayer insulating film to reach the semiconductor element; A second wiring penetrating contact hole filled with the contact plug and having a diameter smaller than the line width of the first and second wirings is formed from the surface of the third interlayer insulating film to the third wiring insulating film; Through the interlayer insulating film, the second wiring, the second interlayer insulating film, the first wiring and the first interlayer insulating film to reach the field insulating film. Immediately above, a third wiring through contact hole filled with the contact plug and having a diameter smaller than the line width of the second wiring and the first dummy pattern is formed in the third interlayer insulating film. The third interlayer insulating film and the second The semiconductor device is penetrated through the wiring, the second interlayer insulating film, the first dummy pattern, and the first interlayer insulating film, and reaches the semiconductor element. A fourth wiring through contact hole, which is filled and has a diameter smaller than the line width of the second dummy pattern and the first wiring, is formed between the surface of the third interlayer insulating film and the third interlayer insulating film. A film, the second dummy pattern, the second interlayer insulating film, the first wiring, and the first interlayer insulating film, which reach the semiconductor element; and a surface of the field insulating film. Immediately above the conductive film pad provided thereabove, penetrates the third interlayer insulating film from the surface of the third insulating film, divides the second wiring, and forms the second interlayer insulating film. Through the first dummy pattern. A first wiring cut-off opening penetrating the first interlayer insulating film and reaching the conductive film pad; and the conductive film pad provided on the surface of the field insulating film. Directly above the third insulating film, penetrates the third interlayer insulating film from the surface of the third insulating film, divides the second dummy pattern, penetrates the second insulating film, and connects the first wiring And a second wiring dividing opening penetrating the first interlayer insulating film and reaching the conductor film pad is provided, and the first and second wiring dividing openings are formed in the second wiring dividing opening. A semiconductor device which is filled with an insulating film. 2. A step of forming a groove in an element isolation region on a surface of a semiconductor substrate and filling the groove with a first insulating film to form a field insulating film; Forming a device, forming a conductive film pad made of a first conductive film in a required region on the surface of the field insulating film, including the semiconductor device, the conductive film pad and the field insulating film. Forming a first interlayer insulating film made of a silicon oxide-based insulating film covering the surface of the semiconductor substrate, and forming a second interlayer insulating film on first and second predetermined regions on the surface of the first interlayer insulating film. Forming a first wiring and a first dummy pattern made of a conductive film, and a silicon oxide-based insulating film covering the surface of the first interlayer insulating film including the first wiring. Second interlayer insulating film Forming a second wiring made of a second conductive film and a second dummy pattern in third and fourth predetermined regions on the surface of the second interlayer insulating film. Forming a third interlayer insulating film made of a silicon oxide based insulating film covering the surface of the second interlayer insulating film including the second wiring; and masking the first photoresist film pattern And at least the third interlayer insulating film, the second wiring, the second dummy pattern, the second interlayer insulating film, the first wiring, the first dummy pattern, and the second Anisotropic etching is sequentially performed on the first interlayer insulating film, and the third interlayer insulating film, the second wiring, the second interlayer insulating film, and the like are formed from the surface of the third interlayer insulating film. The semiconductor element penetrating through a first wiring and the first interlayer insulating film; The first wiring through the contact hole and an interlayer insulating film and the second wiring and the second third from the surface of the third interlayer insulating film to reach
A second wiring penetrating contact hole that penetrates through the interlayer insulating film, the first wiring, and the first interlayer insulating film to reach the field insulating film; 3
A third wiring through contact that reaches the semiconductor element through the second interlayer insulating film, the second wiring, the second interlayer insulating film, the first dummy pattern, and the first interlayer insulating film; The third interlayer insulating film, the second dummy pattern, the second interlayer insulating film, the first wiring, and the first interlayer insulating film are formed from the hole and the surface of the third interlayer insulating film. Forming a third wiring through contact hole that reaches the semiconductor element through the semiconductor device; forming a fourth conductor film over the entire surface by LPCVD; etching back the fourth conductor film; Forming contact plugs respectively filling the first, second, third and fourth wiring through contact holes; and forming the second wiring and the second wiring using the second photoresist film pattern as a mask. Until the upper surface of the second dummy pattern is exposed. Anisotropic etching is performed on the inter-layer insulating film, and the third interlayer insulating film and the second wiring and the second dummy pattern are removed until the second wiring and the second dummy pattern are removed. Anisotropic etching is performed, and the first wiring and the first dummy
Anisotropic etching is performed on the second interlayer insulating film until the upper surface of the pattern is exposed, and the second interlayer insulating film and the second interlayer insulating film are removed until the first wiring and the first dummy pattern are removed. Anisotropic etching is performed on the wiring and the second dummy pattern, and further, anisotropic etching is performed on the first interlayer insulating film until reaching the upper surface of the conductive film pad. From the surface of the interlayer insulating film, penetrates the third interlayer insulating film, divides the second wiring, penetrates the second interlayer insulating film, divides the first dummy pattern, A first wiring cut-off opening penetrating through the first interlayer insulating film and reaching the conductor film pad, and a third interlayer insulating film penetrating from the surface of the third interlayer insulating film to the third interlayer insulating film; Then, the second dummy pattern is divided and the second interlayer insulating film is formed. Forming a second wiring separation opening which penetrates the first wiring and further penetrates the first interlayer insulating film and reaches the conductor film pad; And filling the first and second wiring separation openings with the insulating film.