JP3146263B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system for efficiently determining a frame synchronization signal detected from a plurality of frames in a digital signal system having an error correction code using a block code and a frame synchronization signal.

[0002]

2. Description of the Related Art In a conventional frame synchronization system, a frame synchronization signal used for synchronous multiplexing and demultiplexing, and a series of multiplexed digital signals obtained by multiplexing additional bits and the like used for error correction are input to a frame synchronization circuit. Then, the frame synchronization signal detected from the multiplexed signal is monitored serially over a plurality of frames, and if the frame synchronization code matches the reference frame code pattern over a plurality of frames (backward protection), this frame is Establish frame synchronization by synchronization. After that, error correction was performed based on the frame synchronization signal.

As shown in FIG. 2, a conventional circuit configuration is a one-series multiplexed signal 101 obtained by multiplexing a frame synchronization signal from a demodulator (not shown) and additional bits used for error correction.
Is input to the error correction decoder 1 and the frame synchronization circuit 4.
The error correction decoder 1 includes an arithmetic circuit 2, a delay circuit 3, and an error correction circuit 5. Here, as shown in the signal format shown in FIG. 3, the frame synchronization circuit 4 outputs frame synchronization signals F1 to F6 added to the one-series multiplexed signal 101.
Is established by serially monitoring a plurality of frames in series. For example, if the six frame synchronization patterns F1 to F6 match the reference frame pattern within the time τ in FIG. 3, it is determined that synchronization has been established. The frame synchronization signal 102 with which the synchronization is established controls the arithmetic circuit 2 in the error correction decoder 1, and outputs the error correction signal 103 to the error correction circuit 5. In the error correction circuit 5, the multiplexed signal 101A delayed by the operation time of the operation circuit 2 by the delay circuit 3 is output.
And output the error-corrected output signal 104 to the subsequent stage.

[0004]

As described above, in the conventional frame synchronization method, a frame synchronization signal of a series of multiplexed signals is sequentially monitored over a plurality of frames in order to establish frame synchronization. A lot of time is required for the synchronization pull-in time. In particular, when there is a lot of line noise in satellite communication or the like, it takes much time to determine the mismatch. On the other hand, in order to reduce the frame synchronization pull-in time, there is a method of increasing the redundancy of the frame synchronization signal, that is, increasing the rate of addition of the frame synchronization signal to be monitored to the main signal.
There is a drawback that the time slot of the main signal is reduced and the transmission efficiency is reduced.

[0005]

According to the frame synchronizing method of the present invention, a first frame multiplexed signal obtained by multiplexing a frame having a frame synchronizing signal at the head is input, and the frame synchronizing signal is monitored over a plurality of frames. In a frame synchronization system having a frame synchronization circuit for performing synchronization establishment determination, the first frame multiplexed signal is delayed by a predetermined time t (t <0 <T) within a time interval T that is a repetition period of the frame synchronization signal. And a delay circuit that generates a second frame multiplexed signal, and receives the second frame multiplexed signal and the first frame multiplexed signal to determine frame synchronization establishment.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 4 is an explanatory diagram of a signal format of the present embodiment.

In FIG. 1, the same reference numerals as those in the conventional example of FIG. 2 have the same configuration and function. That is, in this embodiment, a delay circuit 6 is added, and a signal obtained by delaying a multiplexed signal 101 described later by a predetermined time is also input to the frame synchronization circuit.

In FIG. 1, a one-series multiplexed signal 101 from a demodulator (not shown) in which a frame synchronization signal and additional bits used for error correction are multiplexed is transmitted to an error correction decoder 1 and a frame synchronization circuit 4. Is entered. The multiplexed signal 101 input to the error correction decoder 1 is input to an arithmetic circuit 2 and a delay circuit 3, respectively.
Is output as the input signal 101A.
In the frame synchronization circuit 4, the multiplexed signal 101 and the delay circuit 6
By generating a multiplexed signal 105 delayed by t time, which will be described later, and monitoring the frame synchronization signal included in the two-stream multiplexed signal of the frame synchronization signal 101 and the delay multiplexed signal 105 at the present time, the frame synchronization is performed. Establish. After synchronization is established, the frame synchronization signal 10
2, the arithmetic circuit 2 in the error correction decoder 1 is controlled,
The error correction circuit 103 outputs the error correction signal 103 to the error correction circuit 5, performs an error correction operation, and outputs the output signal 104 to a subsequent stage.

Here, in the conventional example shown in FIG. 3, the frame synchronization signal for six frames is monitored during the time τ. In the embodiment of the present invention shown in FIG. 4, the multiplexed signal is monitored during the same time τ. In addition to the six frame synchronization signals of F1 to F6 of 101, five frame synchronization signals of F1 to F5 delayed by t time are monitored again. F1 to F at τ + t time
6, a total of 12 frame synchronization signals are monitored. This will be described with reference to FIG.

FIG. 4 shows a frame synchronization signal F multiplexed on a multiplexed signal 101 within a unit time τ in a conventional circuit configuration.
The state of monitoring of 1 to F6 is shown. As is clear from FIG. 4, the frame synchronization method according to the present invention is a two-system simultaneous monitoring, and the number of monitoring frame synchronization signals within a unit time τ is twice that of the conventional example. Therefore, the frame synchronization pull-in time becomes equivalently shorter.

In this embodiment, since one delay circuit is used,
In this case, the number of simultaneous monitoring can be increased by arranging t × n delay times t of the delay circuit 6 in one frame period T. By monitoring the same frame synchronization signal a plurality of times, redundancy can be increased and the reliability of synchronization establishment can be improved.

[0012]

As described above, according to the frame synchronization method of the present invention, the two multiplexed signals are parallelized by adding a signal obtained by delaying the same multiplexed signal as the multiplexed signal obtained by multiplexing the frame synchronization signal by a predetermined time. Since frame synchronization is established by simultaneous monitoring, the reliability of frame synchronization establishment can be improved without lowering transmission efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional frame synchronization method.

FIG. 3 is an explanatory diagram showing monitoring of a signal format in a conventional example.

FIG. 4 is an explanatory diagram illustrating monitoring of a signal format according to the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Error correction decoder 2 Operation circuit 3, 6 Delay circuit 4 Frame synchronization circuit 5 Error correction circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/08 H04J 3/06

Claims (2)

(57) [Claims] 1. A frame having a frame synchronization circuit for inputting a first frame multiplexed signal obtained by multiplexing a frame having a frame synchronization signal at the beginning and monitoring the frame synchronization signal over a plurality of frames to determine synchronization establishment. In the synchronization method, the first frame multiplexed signal is
A predetermined time t (0) within a time interval T that is a repetition cycle.
A delay circuit for generating a second frame multiplexed signal with a delay of <t <T) , and inputting the second frame multiplexed signal and the first frame multiplexed signal to determine frame synchronization establishment A frame synchronization method. 2. A maximum of N (N < T / t) delay circuits are connected in parallel, the first frame multiplexed signal is input in parallel, and an N-sequence second frame multiplexed signal is output. Is supplied to the frame synchronization circuit.