JP3146077B2 - Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed processing of a conditional branch instruction in a processor having a plurality of arithmetic processing units which can be executed in parallel.

[0002]

2. Description of the Related Art In recent years, high performance processors have been
Multiple arithmetic units called perscalar and VLIW are prepared, and a method of executing multiple instructions at once in parallel has come to be adopted. Among those commercialized by these methods, there is known a microprocessor MC88100 of MOTOROLA and the like (“MC88100 MICROPROCESSOR U by MOTOROLA”).
SER'S MANUAL SECOND EDITION ").
By using these methods, an instruction sequence that has been conventionally executed sequentially can execute a plurality of instructions at once.

[0003] In addition, regarding the execution order of instructions, instead of executing in the order in which the instruction sequence is arranged, instructions having no data dependency are executed from the executable one.
A high-speed method called out-of-order execution is also known. Regarding these high-speed techniques, IEICE Technical Report CPSY-90-54 ('90.
7) "Improvement policy of superscalar processor based on SIMP (single instruction flow / multiple instruction pipeline) method"
("An Extended Superscalar Processor Prototype Ba
sed on the SIMP (Sngle Instruction stream / Multipl
e instruction Pipelining) Architecture ”).

[0004] Even if the branch of the conditional branch instruction is not determined, the processor of the prior art predicts the branch to which branch and executes the instruction in advance (referred to as speculative execution). Speeding up was attempted. As a prediction method, for example, there is a method of predicting that the same conditional branch instruction that has appeared before will branch to the same side as the previous one.

[0005]

However, according to the above-mentioned prior art, there are the following problems. Generally, when a plurality of instructions are executed at the same time, the frequency of occurrence of branch instructions per processing cycle increases. In the case of a conditional branch instruction, the condition is fixed (usually PS
R: change of Program Status Register), it cannot be determined whether to branch. For this reason, the instruction stream is interlocked for each conditional branch instruction, and the performance reaches a state of ending. (The dependencies due to these branches are called control dependencies.) In the method of predicting whether or not to branch and processing the instruction in advance (called speculative execution), the prediction of each conditional branch instruction is If this is the case, the speedup is achieved, but if the prediction is incorrect, the execution returns to the other instruction sequence and the instruction is executed again, which is a great cost. Furthermore, speeding up of the execution of the entire program is not always achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor which executes instructions speculatively even if a condition corresponding to a conditional branch instruction is not determined, has few interlocks, and executes a program at high speed. .

[0007]

In order to solve the above problems, a processor according to the present invention has a plurality of execution units, and a plurality of instructions fetched from a memory are executed by a plurality of execution units.
A-processor to run in parallel in the knitting, main
Instruction type discriminating means for discriminating the type of a conditional branch instruction included in a plurality of instructions fetched from the memory and whose condition depends on the execution result of another instruction; and conditional branching until the success or failure of the branch is determined Depending on the type of instruction: (a) Instruction at branch destination
(B) both the instruction sequence at the branch destination and the instruction sequence following,
(C) Plurality of instructions from any of the following instruction strings
Means for issuing instructions in parallel to the execution units of the instruction branch, and branch determination for judging the success or failure of the branch of the conditional branch instruction determined by the instruction type determining means when another instruction on which the conditional branch depends is executed Means, and execution result management means for determining whether the execution results of the plurality of execution units are valid or invalid so as to match the result of the determination of the success or failure of the branch of the conditional branch instruction. Conditional branch instruction.

The instruction type discriminating means discriminates between an instruction of a first type, which is a conditional branch of an If-Zen-Els system, and another conditional branch instruction.
If the conditional branch instruction is the first type of instruction, the instruction branch from both the instruction sequence at the branch destination and the instruction sequence following the conditional branch instruction are copied.
Number of instructions are issued in parallel to a plurality of execution units, and if the conditional branch instruction is an instruction other than the first type of instruction, a plurality of instructions are issued from one of them in parallel to a plurality of execution units. When the conditional branch instruction is the first type of instruction, the execution result management means validates the execution result of one instruction sequence and invalidates the other according to the result of the branch success / failure determination. If the conditional branch instruction is not the first type of instruction, all of the execution results of the instruction sequence are made valid or invalid according to the result of the branch success / failure determination, and the other branch instructions are the conditional branch instructions of the loop. including.

The instruction type determining means converts an instruction other than the first type of branch instruction into a conditional branch instruction of the loop system.
A second type of instructions that, first determine the third type of instruction and the probability of not branched from the branch instruction is high conditional branch instruction, the instruction parallel issuing means, the second type of instructions In the case of the third type of instruction, the instructions of the instruction sequence following the conditional branch instruction are issued in parallel to the execution unit, and the instructions of the second type are issued. May be a conditional branch instruction of the loop system.

[0010] The processor is first for temporarily storing instructions of a subsequent instruction sequence further conditional branch instruction
Reading an instruction fetch buffer, a second instruction fetch buffer for temporarily storing the instruction of the branch destination instruction sequence of the conditional branch instruction, the instructions stored in the memory, Article
The instruction of the instruction sequence following the matter branch instruction first instruction fetch
The instruction buffer may include an instruction fetch unit that stores the instruction of the instruction sequence to which the conditional branch instruction is branched in the second instruction fetch buffer.

The instruction fetch means outputs a read address to a memory and increments the content thereof, and detects a conditional branch instruction from an instruction read from the memory according to the read address. a conditional branch instruction detecting means for, based on the conditional branch instruction detected by the conditional branch instruction detecting means, contents of the program counter every time calculating means for calculating a branch destination address, the instruction from the memory are read out Is stored in the first instruction fetch buffer, and if a conditional branch instruction is detected, the instruction of the subsequent instruction sequence is stored in the first instruction fetch buffer, and the branch obtained by the arithmetic means is calculated. Fetch for writing the destination address to the program counter and storing the instruction of the instruction sequence at the branch destination in the second instruction fetch buffer It may have and your means.

[0012] The instruction parallel issuing means decodes an instruction to generate a control signal to the execution unit, and sends one instruction from the first or second instruction fetch buffer to all decoding means. Transfer control means for transferring each instruction by the transfer control means, and mode addition means for adding, to each instruction transferred by the transfer control means, mode information indicating to which instruction sequence the instruction belongs. And the execution result management means
The execution result of the instruction follows the conditional branch instruction
Whether it belongs to the instruction sequence to be executed or to the instruction sequence at the branch destination.
Separate.

The mode information added by the mode adding means is 2-bit information, and the mode information of the instruction sequence following the conditional branch instruction is the mode information of the conditional branch instruction itself. first value a value obtained by adding the relative de information, mode of the branch destination instruction string - de information
The report may be a value obtained by adding the second value. Another instruction on which the conditional branch instruction depends is a PSR inside the processor.
(ProgramStatus Register) according to the execution result , wherein the branch determination means detects that the other instruction has been executed, and refers to the PSR to branch.
May be determined .

[0014] The processor further refers to a plurality of decryption results decrypted by the decryption means, and determines data dependence between the plurality of decrypted instructions, and execution. Score board management means for managing which register is being used by the instruction being executed in the unit, empty state detecting means for detecting the empty state of the execution unit, and each instruction decoded by the decoding means Issuing an issuable instruction from the instruction parallel issuing means to the execution unit on the basis of the result of determination by the data dependency determination means, the result of detection by the score board managing means, and the result of detection by the empty state detecting means; If the instruction decoded by the decoding unit is a conditional branch instruction, the instruction unit may include an instruction issue permission unit that permits the instruction parallel issue unit to issue the instruction to the branch determination unit.

The command issuance permitting means has no data dependency with respect to the previous command based on the detection result of the data dependency detecting means for each of the decoding results of the plurality of decoding means, and uses the information of the score board managing means. It satisfies that the register specified by the operand of the instruction is not used for the instruction being executed by the execution unit, and that the execution unit capable of executing the instruction is vacant from the detection result of the vacancy detection means. The processor according to claim 9, wherein it is determined that the instruction can be issued.

The processor further holds information indicating whether or not the instruction is being executed for each execution unit, and executes the execution unit management table referred to by the empty state detecting means.
And information indicating which register is being used by the instruction being executed by the execution unit.
And a score board referred to by a card management means.

[0017] The execution result management means, mode of conditional branch instruction issued by the instruction parallel issue means - initialization mode holds a de Information - - the de information initial mode and de holding means, is issued by the instruction parallel issue means Speculative execution type holding means for holding the type of the conditional branch instruction, and speculative execution state indicating means for holding a flag indicating that the condition judgment of the conditional branch instruction issued by the instruction parallel issuing means has not been determined yet. The instruction parallel issuing means issues the conditional branch instruction to the branch determination means, and simultaneously stores the mode information of the conditional branch instruction in the initial mode holding means and the type of the speculative branch instruction in the speculative execution type. The output to the holding unit and the flag of the speculative execution state instruction unit may be set.

[0018] Before you line result management unit includes an execution result of the instruction in the execution unit, mode of the instruction - and de information, temporary storage means for storing in correspondence with the information indicating the execution result storage destination Yes, and the execution result management unit, branch judgment means
Based on the determination result of the above, the initial mode holding means and the speculative execution
Validation of execution result of temporary storage means with reference to type holding means
Identify invalid and execute according to the information indicating the storage location of the execution result.
Transfer the row result from temporary storage to the storage location and execute it invalid
The result may be cleared . The temporary storage means is configured to store, as the information of the storage destination, a register number when the original storage destination is a register, and a memory address when the original storage destination is a memory. You may.

Further , the processor of the present invention can execute a plurality of executions.
Unit that has multiple instructions fetched from memory
A-processor to run in parallel in a plurality of execution units, is included in the plurality of instructions fetched from memory, the instruction type determination that determines the type of conditional branch instruction condition is dependent on the result of execution of other instructions Means, and until the success or failure of the branch is determined, depending on the type of the conditional branch instruction,
(A) Instruction sequence at branch destination, (b) Instruction sequence at branch destination and subsequent
(C) Any of the following instruction sequences
The instruction parallel issuing means for issuing a plurality of instructions to a plurality of execution units in parallel, and when another instruction on which the conditional branch depends is executed, the instruction type determining means determines the instruction.
A branch determining means for determining whether the branch of the conditional branch instruction is successful or not;
Execution result management means for identifying whether the execution result is valid or invalid by the plurality of execution units, wherein the instruction parallel issuing means decodes an instruction to generate a control signal to the execution unit; and Transfer control means for transferring instructions one by one from the first or second instruction fetch buffer to all decoding means, and each instruction transferred by the transfer control means indicating which instruction sequence the instruction belongs to Mo
Adding de information mode - possess a de adding means, said execution formation
The result management means determines that the execution result of the instruction is
Instruction sequence belonging to or following the instruction sequence following the branch instruction
Identify whether they belong to

[0020]

According to the above means, in the processor of the present invention, the instruction type determining means determines the type of the conditional branch instruction included in the instruction sequence before execution. Here, the type of conditional branch instruction is
Includes loop-type conditional branch instructions. In accordance with the determined type of the instruction, the instruction parallel issuing unit issues the instruction of the branch destination instruction sequence and / or the instruction of the succeeding instruction sequence to the execution unit in parallel to the execution unit. When the branch determination unit determines whether the branch of the conditional branch instruction is successful or not, the execution result management unit identifies whether the execution result of the instruction sequence is valid or invalid.

[0021] In addition, the instruction type management means is, if-Zen
The first type of instructions including a conditional branch of Els system-the
A second type of branch instruction including a loop type conditional branch instruction and a third type of branch instruction including other conditional branch instructions are determined. The instruction fetch means stores the instruction from the normal memory to the first instruction fetch means, and when the conditional branch instruction is detected by the conditional branch instruction detecting means, the instruction fetch means stores the instruction in the instruction sequence following the conditional branch instruction in the first instruction fetch means. The instruction of the instruction sequence at the branch destination is stored in the second instruction fetch buffer. With respect to the instructions stored in these instruction fetch buffers, the instruction parallel issuing means adds the mode by the mode adding means, and sends the instructions from the two instruction fetch buffers to the plurality of decoding means by the transfer control means. Take in.

Further, the instruction issuance permission means is provided for each of the instructions decoded by the plurality of decoding means, based on the judgment result of the data dependence judgment means, the score board management means, and the detection result of the empty state detection means. Issue of an issuable instruction from the instruction parallel issuing means to the execution unit, and if the instruction decoded by the decoding means is a conditional branch instruction, issue from the instruction parallel issuing means to the branch determining means. Allow At this time, when the conditional branch instruction is the first type of instruction, the instruction issuance permission unit permits the parallel execution of both the instruction sequence at the branch destination and the instruction sequence following the conditional branch instruction to the execution unit. In the case of the second type of instruction, the instruction of the instruction sequence of the branch destination is issued in parallel to the execution unit, and in the case of the third type of instruction, the instruction of the instruction sequence following the conditional branch instruction is executed in the execution unit. Allow parallel issuance.

The instruction parallel issuing means issues the conditional branch instruction to the branch determination means, and simultaneously holds the mode of the conditional branch instruction in the initial mode holding means and holds the type of the conditional branch instruction in the speculative execution type. Output to the means and sets a flag of the speculative execution state instructing means. When the branch determination unit determines whether or not to branch, the execution result management unit refers to the initial mode holding unit and the speculative execution type holding unit based on the determination result, and executes the execution result of the temporary storage unit. Valid / invalid is identified, the valid execution result is transferred to the original storage location, and the invalid execution result is cleared.

[0024]

FIG. 1 is a block diagram of a processor according to the present invention.
In FIG. 1, reference numeral 1 denotes a memory, which stores an instruction sequence and operand data constituting a program. An instruction fetch unit 2 prefetches an instruction from the memory 1 and stores an instruction fetch buffer A3 or an instruction fetch buffer B
Write to 4. The instruction fetch unit 2 detects whether the fetched instruction is a conditional branch instruction and switches the write destination instruction fetch buffer according to the detection result.

The branch instruction detected by the instruction fetch unit 2 will be described. For example, the programming language C
In general, if it is uncertain whether to branch or not
There are a branch operation in the case of the -then-else system, a loop in which the probability of branching is high, and a branch operation in the case of the probability of non-branch.
In the case of a switch statement, it depends on the implementation method, but if-then-
You can think the same as else. Therefore, in this embodiment, in accordance with the probability of branching in advance, a loop-type branch instruction that operates at high speed when the probability of branching is high, and an if-then that operates at high speed when the probability of branching is unknown. -else branch instructions,
Three types of branch instructions that operate at high speed when the probability of not taking a branch is high are provided in machine language instructions. A loop-type branch instruction is an instruction with a high probability of branching as a loop-oriented branch instruction (hereinafter abbreviated as Bcc_l), and it is improper whether an if-then-else-type branch instruction branches. This is a definite branch instruction (hereinafter abbreviated as Bcc_i). In addition, there is an instruction with a high probability of not branching (hereinafter abbreviated as Bcc_n).

When a branch instruction is detected by the instruction fetch unit 2, an instruction sequence following the branch instruction (an instruction sequence executed when the branch is not taken) and a branch destination instruction sequence (an instruction sequence executed when the branch is taken) ), And stores the instruction sequence following the branch instruction in the same instruction fetch buffer as before.
The instruction sequence at the branch destination is stored in another instruction fetch buffer. This read operation always fills the instruction fetch buffer A3 or B4 asynchronously with the decoding and execution of the instruction.

The instruction fetch buffer A3 stores the instruction read by the instruction fetch unit 2 in a FIFO (First In F
irst Out) memory. Instruction fetch buffer B4
Is a FIFO memory similar to 3. Reference numeral 5 denotes a selector, which switches instructions output from two instruction fetch buffers. The switching instruction is performed by the instruction decoding unit 7.

Reference numeral 6 denotes an instruction decoding buffer which stores instructions to be decoded, and has a storage capacity for six instructions in this embodiment. The storage capacity is desirably at least as many as the arithmetic units 8 to 11. Instruction decoding unit 7
Controls the transfer of instructions from the instruction fetch buffer to the instruction decoding buffer 6, decodes the instructions in the instruction decoding buffer, and issues instructions to the arithmetic unit.

Numeral 8 denotes an arithmetic unit A, which executes a load instruction and a store instruction. Of these, it is assumed that the execution of the load instruction takes two cycles for convenience of explanation. Reference numeral 9 denotes an arithmetic unit B, which processes an integer operation. Reference numeral 10 denotes an arithmetic unit C, which processes an integer operation. Numeral 11 denotes an arithmetic unit D, which processes a floating-point operation. Arithmetic unit A
In this embodiment, the execution of instructions 8 to D11 is completed in one cycle (two cycles for a load instruction) to simplify the description. Further, the number of pipeline stages of the unit is not defined here because it is not related to the gist of the present invention.

Reference numeral 12 denotes an arithmetic unit management table.
Information (bit) indicating that the operation unit is in use is stored for each operation unit. This bit is set by each operation unit when the execution of the instruction of the operation unit is started, and is cleared when the execution of the instruction of the operation unit is completed. Reference numeral 13 denotes an execution order management buffer, which stores the operation result of an instruction executed speculatively, the number of a register in which the result should be originally stored, and the mode of the instruction. The storage format of the execution order management buffer 13 has an area for storing a mode, a register number, and an operation result as shown in FIG.

Reference numeral 14 denotes an initial mode holding circuit, which holds the mode added to the branch instruction processed by the instruction decoding unit as an initial mode. A speculative execution type holding circuit 15 holds the type of the currently executed branch instruction (whether it is Bcc-l or Bcc-i). Reference numeral 16 denotes a speculative execution state instructing circuit, which holds a flag indicating whether or not the current state is a state of speculative execution.

Reference numeral 17 denotes an execution order management circuit.
Arithmetic units 8 to 1 according to the information obtained from
1 is stored in the register file 19 or the execution order management buffer 13. Specifically, when the speculation is not being executed, the operation result is written into the register file. When the speculation is being executed, the mode and the register number of the operation result writing destination (operand) are associated with the instruction being executed. And stores it in the execution order management buffer 13.
When the speculative execution is completed, the arithmetic result is transferred to the register file based on the arithmetic result and the register number stored in the execution order management buffer.

Reference numeral 18 denotes an instruction execution consistency maintaining circuit.
Whether the condition of the conditional branch instruction is satisfied or not is determined based on the result of the determination of the SR. Based on the result, the instruction decoding unit 7 is instructed to execute the instruction again, invalidating the inside of the execution order management buffer 13,
The transfer instruction of the execution order management circuit 17 is issued. More specifically, it is divided into the following cases according to the type of the conditional branch instruction.

(1) When speculative execution is performed for the Bcc-l instruction, only the instruction at the branch destination is executed. Is deleted from the execution order management buffer, and the instruction decoding unit is instructed to execute the instruction not to branch again. (2) When speculative execution is performed for the Bcc-i instruction, the instruction following the branch destination and the instruction following the branch destination are being executed. Therefore, when the branch direction is determined, the subsequent instruction or the branch destination The result of the instruction is deleted from the execution order management buffer.

(3) When speculative execution is performed for the Bcc-n instruction, only the instruction following the branch instruction is executed. The result of the executed instruction is deleted from the execution order management buffer, and the instruction decoding unit is instructed to execute the instruction on the branching side again. Reference numeral 19 denotes a register file, which has 32 registers and a PSR, and stores an instruction execution result.

Reference numeral 20 denotes a score board, which has a 2-bit flag for each register of the register file 19.
One indicates that an instruction being executed that is not speculative execution is using (reading or writing) the corresponding register.
The other indicates that the instruction being executed by speculative execution uses the corresponding register. FIG. 2 is a block diagram showing a detailed configuration of the instruction fetch unit 2 of FIG. In the figure, reference numeral 21 denotes a program counter, and a memory 1
, Outputs the address of the instruction to be read from, and increments the content each time the instruction is read.

Reference numeral 22 denotes a branch instruction detection circuit,
A conditional branch instruction is detected from the instruction read from the. 2
An arithmetic circuit 3 calculates a branch destination address based on the detected conditional branch instruction. 24 is a selector,
The outputs of the program counter 21 and the arithmetic circuit 23 are selected and output to the memory 1.

A fetch control unit 25 reads an instruction from the memory 1 and executes an instruction fetch buffer A3.
Alternatively, it controls writing of an instruction to the instruction fetch buffer B4. Specifically, usually, the program counter 2
1 is controlled so that addresses are sequentially output while incrementing, and instructions are stored in one instruction fetch buffer. When a conditional branch instruction is detected by the branch instruction detecting circuit 22, information on the branch destination address of the conditional branch instruction is input to the arithmetic circuit 23 to calculate the branch destination address so that the branch destination instruction can also be read. Control and store the instruction in the other instruction fetch buffer.

FIG. 3 is a block diagram showing a detailed configuration of the instruction decoding unit 7 of FIG. In the figure, reference numeral 31 denotes a branch instruction detection circuit which detects branch instructions (Bcc_l instruction and Bcc_i instruction) from the output of the selector 5 shown in Fig. 1. Reference numeral 32 denotes a transfer control circuit, which is an instruction fetch buffer A3 or an instruction fetch buffer B4. Is transferred to the instruction decoding buffer 6 via the selector 5. The operation of this transfer differs depending on the detection result of the branch instruction detection circuit 31.

First, when a branch instruction is not detected, the transfer control circuit 32 causes the selector 5 to select the output of the instruction fetch buffer A3 or the instruction fetch buffer B4 which contains the instruction. To transfer the instruction to the instruction decoding buffer 6. Second, when a Bcc_l instruction (a branch instruction directed to a loop, which has a high probability of branching) is detected, the instruction fetch buffer that is currently reading the instruction is switched to the other instruction fetch buffer, and the instruction decoding buffer is switched. Transfer the instruction to Only the instruction at the branch destination is transferred to the instruction decoding buffer 6.

Third, when a Bcc_i instruction (if-then-else branch instruction, branch probability is uncertain) is detected,
Instruction reading is alternately transferred from the currently used instruction fetch buffer and the other instruction fetch buffer.
The instruction following the instruction (the instruction executed when the branch is not taken) and the instruction at the branch destination are mixed (alternately) transferred to the instruction fetch buffer.

Fourth, when a Bcc_n instruction (with a high probability of not branching) is detected, the instruction is transferred from the instruction fetch buffer from which the instruction is currently being read to the instruction decoding buffer. Only instructions on the non-branched side are transferred to the instruction decoding buffer 6. A mode addition circuit 33 adds a mode to each instruction so that the control flow of the instruction by the branch instruction can be understood at the time of the above-mentioned transfer by the transfer control circuit 32, and stores it in the instruction decoding buffer 6.

The mode setting rules are as follows: (1) In the mode of the instruction sequence following the branch instruction, "+01" is added to the current mode. (2) The mode of the instruction string at the branch destination is "+" in the current mode.
10 "is added.

FIG. 4 is a mode explanatory diagram showing an example of a mode and an instruction flow. In the figure, solid arrows (↓) indicate instruction sequences, circles (丸) indicate conditional branch instructions, and broken arrows () indicate loop return destinations (Bcc_l instruction branch destinations).
And the number in "" indicates the mode. The numbers with circles (,,) indicate the number of loop repetitions (repeated three times in FIG. 2).

For example, the mode of the current instruction sequence is “00”
Then, the mode of the instruction sequence following the branch instruction is “+0
1 is added to “01”, and the mode of the instruction sequence at the branch destination is “01”.
+10 "is added and set as" 10 ".
In the loop processing, the mode changes each time the loop is repeated because the mode is set relatively.

Using this mode setting rule, the instruction sequence up to the branch instruction, the following instruction sequence, and the instruction sequence at the branch destination can be easily determined, and a new branch exists in the instruction sequence at the branch destination. Even in the case of branching, it is possible to determine the control flow. Reference numeral 34 denotes an instruction decoding circuit.
4a to 34f, and simultaneously decodes six instructions input from the instruction decoding buffer 6 of FIG. The number of DECs is
Here, the number is the same as the number of stages of the instruction decoding buffer 6, and preferably the same number or more as the arithmetic units 8 to 11.

Reference numeral 35 denotes a PSR change command detection circuit, which receives the decoding results of the decoders 34a to 34f and detects whether each command changes the contents of a PSR (Program Status Register). When the contents of the PSR are determined, the success or failure of the condition of the conditional branch instruction is determined, and the detection result is notified to the instruction execution consistency maintaining circuit 18. 36
Is a data dependency detection circuit, and the decoders 34a to 34a
Based on the decoding result input from 4f, it is detected whether or not there is a data dependency that the execution result of one instruction is used by another instruction. Specifically, the data dependency detection circuit 36 compares the decoded result register fields of the six decoded instructions, and sets the destination register of the instruction whose execution address is earlier to the instruction register of the later instruction. , It is determined that there is a data dependency.

Regarding the range for examining the data dependency,
The data dependency between the instructions in the instruction decoding buffer 6 and the instructions not yet taken into the instruction decoding buffer 6 is as follows:
No need to check. This is because the former and latter instructions are not executed simultaneously. It is sufficient to check the data dependency only for the instructions in the instruction decoding buffer 6. This is because they can be executed simultaneously. However, even in the instruction decoding buffer 6, as shown in Table 1, the data between the instruction (B) in the instruction sequence at the branch destination and the instruction (c) in the instruction sequence following the branch instruction is read. -Data dependencies are not checked. This is because (B) and (C) have an exclusive relationship. Table 1 shows whether or not there is a check of the data dependency of the instruction sequence in the embodiment of the present invention.

[0049]

[Table 1]

Reference numeral 37 denotes a scoreboard management circuit which determines the status of the register used in the execution of the instruction with reference to the scoreboard 20 and decodes the decoders 34a to 34f.
When there is an instruction to change the contents of the register after seeing the result of decoding, the flag of the score board 20 corresponding to the register is set. Reference numeral 38 denotes an empty state detection circuit, which determines which arithmetic unit is empty (not in use) by referring to the arithmetic unit management table 12. .

An instruction issuing circuit 39 includes a selector 39.
a to 39d, selectable issuable instructions among the instructions decoded by the instruction decoding circuit 34 in accordance with the instruction of the instruction issuance control circuit 40, and issue them to the arithmetic units 8 to 11 in parallel. At the same time, the instruction issuing circuit 39 stores, for each instruction to be issued, an identifier indicating whether or not it is speculative execution in the arithmetic unit. In this embodiment, this identifier is “0” indicating that speculation is not being executed, and “1” indicating that speculation is being executed.

The instruction issuance control circuit 40 includes
Of the instructions decoded by the instruction decoding circuit 34, and issues an instruction to the instruction issuing circuit 39 to issue the instruction. To determine whether an instruction can be issued, the following conditions are checked for each instruction, and it is determined that an instruction that satisfies all the conditions can be issued. There must be no data dependency between the previous instruction and the six instructions. (Check based on the detection result of the data dependency detection circuit 36.) The register specified by the operand of the instruction is not used for the instruction being executed by the arithmetic unit.
(Check based on the information from the score board management circuit 37.) The operation unit that can execute the instruction is vacant. (Check based on the detection result of the empty state detection circuit 38.) At the same time when the instruction is issued, the instruction issuance control circuit 40
The instruction issued from the instruction decoding buffer 6 is deleted, and the corresponding bit of the operation unit management table 12 is set (in use).

If the issuable instruction is a conditional branch instruction, the instruction is not issued to the arithmetic unit, the mode of the branch instruction is stored in the initial mode holding circuit 14, and the Bcc-i is stored in the speculative execution type holding circuit 15. Whether the instruction is an instruction, a Bcc-l instruction, or a Bcc-n, a speculative execution state indicating circuit 16 is provided with a flag indicating that speculative execution is being performed, and an instruction execution consistency maintaining circuit 18 is provided with a condition of the instruction. set. In this case, thereafter, the state becomes the speculative execution state.

The operation of the thus configured branch processing apparatus according to the embodiment of the present invention, which includes a Bcc-i instruction at first, will be described with reference to FIGS. FIG. 5 is an example of an instruction flow for explaining the operation of this embodiment for processing the Bcc-i instruction at high speed.
In FIG. 5, the arrow indicates the instruction execution order, and the instruction N-3
The arrow between the instruction and the instruction N-2 indicates that there is a data dependency, LD in parentheses indicates a load instruction, INT indicates an integer operation instruction, and FPU indicates a floating point operation instruction. Instruction N-2
Is an instruction that changes the PSR that is the basis of the branch instruction.

First, the operation of the instruction fetch unit 2 will be described. The instruction fetch unit 2 operates asynchronously with the processing following instruction decoding. The instruction fetch unit 2 reads an instruction from the memory 1 using the program counter 21,
The instruction is stored in the instruction fetch buffer A3. When reading from the memory 1, when the branch instruction detection circuit 22 detects a branch instruction, the instruction following the branch instruction is stored in the instruction fetch buffer A3, and the arithmetic circuit 23 calculates a branch destination address, and The instruction is stored in another instruction fetch buffer B4.

The operation of the instruction fetch unit 2 continues until one of the instruction fetch buffers becomes full when there is no branch instruction, and until both instruction fetch buffers become full when there is a branch instruction. Can be The instruction fetch buffer A3 and the instruction fetch buffer B4 are equivalent, and either one may be used first. In the following description, it is assumed that the instruction fetch buffer is always full.

In FIG. 5, the instructions executed before the instruction N-3 are irrelevant to the description of the present invention and will not be described. The instruction sequence up to the branch instruction and the instruction sequence following the branch instruction in the instruction sequence of FIG. 3 are sequentially stored in the instruction fetch buffer A3 by the instruction fetch unit 2, and the instruction sequence at the branch destination is stored in the instruction fetch buffer B4. Is stored. Hereinafter, description will be made in order.

(1) The instruction decoding unit 7 reads an instruction from the instruction fetch buffer A3, adds a mode to the instruction, and stores the instruction in the instruction decoding buffer 6. The instructions from N-3 to N + 2 in FIG. 6 stored in the instruction fetch buffer A3 are read out by the instruction
00 ”is stored in the instruction decoding buffer 6.
FIG. 6 shows the contents held in the instruction decoding buffer 6 at this time.

(2) In the instruction decoding section 7, the data dependency detection circuit 36 checks the data dependency between instructions, the score board management circuit 37 checks the register in use, and the empty state detection circuit 38 The operation unit management table 12 determines the availability of the operation units. In accordance with these results, the instruction issue control circuit 40 determines an instruction that can be issued, causes the instruction issue circuit 39 to issue the instruction with an identifier indicating whether or not the instruction is speculative execution, and decodes the instruction. Delete from buffer 6.

In FIG. 6, an instruction N-2 is an instruction N-3.
It is not issued at first because there is a data dependency. N-
Four of 3, N-1, N, and N + 1 are issued. Since it is not speculative execution, the identifier of each instruction is "0". The state of the arithmetic unit after these instructions are issued is shown in the first row of Table 2. Each operation unit sets a corresponding bit of the operation unit management table 12 when an instruction is input.
Table 2 shows the state of instruction execution in the arithmetic unit when the instruction flow of FIG. 5 is executed.

[0061]

[Table 2]

(3) After executing the instruction, the operation unit outputs the operation result to the execution order management circuit 17. Since the instruction is not a speculative execution instruction (the identifier is 0), the execution order management circuit writes the operation result directly to the register file 19. Usually, the instruction sequence without a branch instruction is (1) to
It is executed as in (3). (4) The instruction decoding buffer 6 corresponds to the instruction N-2 in FIG.
And the instruction N + 2 remain. Instruction decoding unit 7
Transfer control circuit 32 sequentially reads new instructions from the instruction fetch buffer A3 and stores them in the instruction decoding buffer 6. At this time, when the branch instruction detecting circuit 31 detects that the instruction read is the Bcc_i instruction, the transfer control circuit 3
2 alternately reads the instruction following the branch instruction from the instruction fetch buffer A3 (the instruction to be executed if the branch is not taken) and the branch destination instruction from the instruction fetch buffer B4 by switching the selector 5 alternately. Store in decryption buffer. At the same time, the mode addition circuit 33 sets the current mode to "00" in order to indicate whether or not the instruction is a branch destination instruction.
Are added to set “01”, and “+10” is added to the instruction at the branch destination and set as “10”. Then, the instruction decoding buffer stores the instruction as shown in FIG.

(5) The instruction decoding unit 7 determines an issueable instruction in the same manner as described in (2). Of the instructions issued in the previous cycle, the instruction N-3 issued to the operation unit A8 has not been completed yet because it is a load instruction which takes two cycles. Therefore, the instruction N-2 having a data dependency with this instruction is delayed in issuing another cycle of instruction. In this processing cycle, instructions N + 2, Bcc_i,
It is determined that the instructions N + 3 and M can be issued. The instruction issue control circuit 40 sends the instruction N + 2 to the operation unit D11, the Bcc_i instruction to the instruction execution consistency maintaining circuit 18, and the instruction N + 3 to the operation unit B via the instruction issue circuit 39.
In addition, the instruction M is issued to the arithmetic unit C10 with an identifier added thereto, and the instruction M is deleted from the instruction decoding buffer 6. The identifiers added to these instructions are 0,
0, 1, and 1. The state of each operation unit after the instruction is issued is shown in the second row of Table 2. Each issued instruction has the following (6)
-1) to (6-4).

(6-1) The operation unit D11 receives the instruction N
When +2 is issued, the corresponding bit of the operation unit management table 12 is set and the instruction is executed. When the execution of the instruction is completed in the arithmetic unit D11, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since the instruction N + 2 is not executed in the speculative execution mode (the identifier is 0), the execution order management circuit 17 does not store the operation result in the execution order management buffer 13 but writes it in the register file 19. (6-2) The Bcc-i instruction is not issued to the operation unit, but the instruction issue control circuit 40 stores the mode "00" of the branch instruction itself in the initial mode holding circuit 14 and holds the speculative execution type. The flag indicating that the instruction is a Bcc-i instruction in the circuit 15 and the speculative execution state instructing circuit 16 indicates that the instruction is being executed is set in the instruction execution consistency maintaining circuit 18 by the condition of the instruction. Thereafter, it enters a speculative execution state.

(6-3) The operation unit B9 sets the instruction N +
When 3 is issued, the corresponding bit of the arithmetic unit management table 12 is set, and the instruction is executed. When the execution of the instruction is completed in the arithmetic unit B9, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since this instruction is an instruction under speculative execution (identifier 1), the execution order management circuit 17 writes the register number of the write destination and the mode “01” in the execution order management buffer 13.
Write. (6-4) When the instruction M is issued, the arithmetic unit C10 sets the corresponding bit of the arithmetic unit management table 12, and executes the instruction. When the execution of the instruction is completed in the arithmetic unit B9, the execution result is stored in the execution order management circuit 17
Is output to At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since this instruction is an instruction under speculative execution (identifier 1), the execution order management circuit 17 writes the register number of the write destination and the mode “10” in the execution order management buffer 13.
Write. (7) At this point, the execution order management buffer 13 is stacked up to the second row in FIG.

(8) The instruction decoding buffer is as shown in FIG. In the next cycle, since the instruction N-3 has been completed, the instruction decoding unit 7 performs a series of processes to execute the instruction N-2,
Issue N + 4, M + 1. The state of each operation unit after the instruction is issued is shown in the third row of Table 2. When the execution of these instructions is completed, the execution order management buffer 13 is stacked up to the fourth line in FIG.

(9) As described above, the arithmetic unit executes the input instruction, and clears the corresponding bit of the arithmetic unit management table 12 when a new instruction can be processed. When it becomes possible to process a new instruction, the instruction decoding unit 7 restarts the instruction issuing process. (10) The instruction N-2 for changing the PSR is executed by the arithmetic unit B as shown in the third row of Table 2. When the instruction N-2 is completed and PSR is determined, the arithmetic unit B clears the flag of the speculative execution state instruction circuit 16. Even if the instruction N-2 is completed, the speculative execution is executed up to the fourth line in Table 2, and the instruction being speculatively executed up to the sixth line in FIG.

(11) The instruction execution consistency maintaining circuit 18
Since the flag of the speculative execution state instructing circuit 16 has been cleared, the speculative execution type holding circuit 15 determines whether or not to branch based on the Bcc_i instruction and the value of PSR. In this example, it is assumed that a branch occurs. Since the instruction execution consistency maintaining circuit 18 is a Bcc_i instruction, the operation result of the following instruction sequence (the instruction sequence on the non-branched side) in the execution order management buffer 13 is no longer necessary. "+01" is added to the initial mode "00" to invalidate the operation result of the instruction whose mode is "01". In FIG. 9, instructions N + 3, N + 4, N + 5 are invalidated (cleared). Further, the instruction decoding unit 7 is notified of the branch, and only the instruction at the branch destination is taken into the instruction decoding buffer 6 thereafter.

(12) The execution order management circuit 17 is notified by the instruction execution consistency maintaining circuit 18 that the branch has been determined and the speculative execution mode has ended. For the instruction sequence at the branch destination (the instruction whose mode is “10”) existing in the execution order management buffer 13, the operation result is stored in the corresponding register of the register file 19. As described above, the processing performed in the speculative execution in the case of the conditional branch instruction Bcc_i is the processing after the branch is determined, and
Maintains continuity. In addition, since about half of the speculation execution results are effective, the processing is performed at a correspondingly high speed.

Next, regarding the case where the Bcc-l instruction is included,
The operation will be described with reference to FIGS. 10 to 14 and Table 3. FIG. 10 is an example of an instruction flow for explaining the operation of this embodiment for processing the Bcc_1 instruction at high speed. The instruction execution order is as shown by the arrow. Instruction N + 4 and instruction N + 7
Is assumed to have a data dependency. The instruction N + 7 is an instruction for changing the PSR that is the basis for determining the branch of the conditional branch instruction. In the figure, there are instructions that have been executed up to instruction N, but they are not relevant to the description of the present invention and will not be described. The instruction sequence up to the branch instruction and the following instruction sequence in the instruction sequence of FIG. 10 are sequentially stored in the instruction fetch buffer A3 by the instruction fetch unit 2, and the branch destination instruction sequence is stored in the instruction fetch buffer B4. ing. Hereinafter, description will be made in order.

(1) The instruction decoding section 7 reads an instruction from the instruction fetch buffer A3, adds a mode to the instruction, and stores the instruction in the instruction decoding buffer 6. The mode of the stored instruction is “01”. Now, the instruction decoding buffer 6 is shown in FIG.
It is assumed that the state is 1. (2) In the instruction decoding section 7, the data dependency detection circuit 36 checks the data dependency between instructions, the scoreboard management circuit 37 checks the register in use, and the empty state detection circuit 38 manages the operation unit. The availability of the operation unit is determined from the table 12. In accordance with these results, the instruction issue control circuit 40 determines an instruction that can be issued, causes the instruction issue circuit 39 to issue the instruction with an identifier indicating whether or not the instruction is speculative execution, and decodes the instruction. Delete from buffer 6.

In FIG. 11, instruction N + 7 is equivalent to instruction N +
4 is not issued at first because of data dependency. N
+4, N + 5, N + 6, and N + 8 are issued. Since it is not speculative execution, the identifier of each instruction is "0". The state of the arithmetic unit after these instructions are issued is shown in the first row of Table 3. Table 3 shows the state of instruction execution in the arithmetic unit when the instruction flow of FIG. 8 is executed in the embodiment.

[0076]

[Table 3]

Each operation unit, when an instruction is input,
The corresponding bit of the arithmetic unit management table 12 is set. After executing the instruction, the operation unit outputs the operation result to the execution order management circuit 17. Since the instruction is not a speculative execution instruction (the identifier is 0), the execution order management circuit 17 directly writes the operation result to the register file 19.

(3) The instruction decoding buffer 6 is in a state where the instruction N + 7 and the instruction Bcc_l remain in FIG. The transfer control circuit 32 of the instruction decoding unit 7 reads a new instruction sequence from the instruction fetch buffer A3. When detecting that the read instruction is a Bcc_l instruction, the selector 5
To read only the instruction at the branch destination from the instruction fetch buffer B 4 and store it in the instruction decoding buffer 6. At the same time, the mode adding circuit 33 adds "+10" to the branch destination instruction and sets "11" to the branch destination instruction to indicate whether or not the instruction is the branch destination instruction. Set as Then, the instruction decoding buffer is stored as shown in FIG.

(4) The instruction decoding unit 7 determines an issueable instruction in the same manner as described in (2). Of the instructions issued in the previous cycle, the instruction N + 4 issued to the arithmetic unit A8 is a load instruction that takes two cycles, and the execution has not been completed yet. Therefore, the instruction N + 7 having a data dependency with this instruction is delayed in issuing another cycle of instruction. In this processing cycle, Bcc_l, instruction N, instruction N
+1 and instruction N + 3 can be issued. The instruction issuance control circuit 40 transmits the Bcc_
l instruction to instruction execution consistency maintaining circuit 18, instruction N to operation unit B9, instruction N + 1 to operation unit C10,
The instruction N + 3 is issued to the arithmetic unit D11 with an identifier added thereto, and is deleted from the instruction decoding buffer 6.
The identifiers added to these instructions are 0, 1,
1, 1.

Table 3 shows the state of each operation unit after the instruction is issued.
Is shown on the second line. Each issued instruction has the following (5-1)
This is executed as shown in (5-4). (5-1) The Bcc-l instruction is not issued to the operation unit, and the instruction issue control circuit 40 stores the mode "01" of the branch instruction itself in the initial mode holding circuit 14 and holds the speculative execution type. The flag indicating that the instruction is a Bcc-l instruction in the circuit 15 and the speculative execution state instructing circuit 16 indicates that the speculative execution is being performed, and the condition of the instruction is set in the instruction execution consistency maintaining circuit 18. Thereafter, it enters a speculative execution state.

(5-2) When the instruction N is issued, the operation unit B9 sets the corresponding bit of the operation unit management table 12 and executes the instruction. Arithmetic unit B
When the execution of the instruction is completed in step 9, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared. The execution order management circuit 17 writes the register number of the write destination and the mode “11” in the execution order management buffer 13 because this instruction is an instruction under speculative execution (identifier 1).

(5-3) The operation unit C10 executes the instruction N
When +1 is issued, the corresponding bit of the arithmetic unit management table 12 is set and the instruction is executed. When the execution of the instruction is completed in the arithmetic unit B9, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since this instruction is an instruction under speculative execution (identifier 1), the execution order management circuit 17 writes the register number of the write destination and the mode “11” in the execution order management buffer 13.
Write. (5-4) When the instruction N + 3 is issued, the operation unit D11 sets the corresponding bit of the operation unit management table 12, and executes the instruction. When the execution of the instruction is completed in the arithmetic unit D11, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since the instruction N + 2 is executed under speculative execution (the identifier is 1), the execution order management circuit 17 does not write the operation result in the register file 19 but stores it in the execution order management buffer 13. (6) At this point, FIG.
It will be piled up to the third line of 4.

(7) Also, the instruction decoding buffer 6 is
become that way. In the next cycle, since the instruction N + 4 has been completed, the instruction decoding unit 7 performs a series of processing and executes the instruction N +
7. Issue N + 2. The state of the arithmetic unit after the instruction is issued is shown in the third row of Table 3. When these instructions have been executed, up to the fourth line in FIG. 14 is stored in the execution order management buffer.

(8) As described above, the arithmetic unit executes the input instruction, and clears the corresponding bit of the arithmetic unit management table 12 when a new instruction can be processed. When it becomes possible to process a new instruction, the instruction decoding unit 7 restarts the instruction issuing process. (9) The instruction N + 7 for changing the PSR is executed by the arithmetic unit B as shown in the third row of Table 3. When the instruction N + 7 is completed and PSR is determined, the arithmetic unit B clears the flag of the speculative execution state instruction circuit 16. Even if the instruction N + 7 is completed, the speculative execution is executed up to the fourth line of Table 3.

(10) The instruction execution consistency maintaining circuit 18
Since the speculative execution state instructing circuit 16 has been cleared, the speculative execution type holding circuit 15 indicates that the instruction is a Bcc_l instruction, and the PSR
It is determined whether or not to branch based on the value of. Here, it is assumed that a branch occurs. (11) The execution order management circuit 17 is notified by the instruction execution consistency maintaining circuit 18 that the branch has been determined and the speculative execution mode has ended. Then, the execution order management buffer 1
For the instruction sequence of the branch destination (instruction whose mode is “11”) existing in 3, the operation result is stored in the corresponding register of the register file 19.

As described above, the speculative execution of the conditional branch instruction Bcc_l and the processing after the branch is determined can be executed with the consistency maintained as in the case where no speculative execution is performed. If it is determined in (10) that no branch occurs, the following is performed. (11) After determining that the branch is not taken, the instruction execution consistency maintaining circuit refers to the speculative execution type holding circuit 15 and finds that the instruction is a Bcc_l instruction. Disable. In FIG. 14, the instructions N, N + 1, N + 3, N + 2 are invalidated (cleared). Further, it notifies the instruction decoding unit 7 that no branching is performed, and causes the instruction decoding buffer 6 to perform the process again so that the subsequent instruction remaining in the instruction fetch buffer A is fetched into the instruction decoding buffer 6 again.

(12) The execution order management circuit 17 determines from the instruction execution consistency maintaining circuit 18 that no branch occurs,
The end of the speculative execution mode is notified. And
Since all the operation results of the instructions in the execution order management buffer are invalidated, nothing is performed. As described above, the processing performed in the speculative execution by the conditional branch instruction Bcc_l is not utilized in the processing after it is determined that the branch is not to be made, and does not contribute to speeding up. However, the conditional branch instruction Bcc_l has a low probability of not branching, so
The probability of occurrence of such a case is low, and the speed is increased when not all the speculative executions of the entire program but only the speculative executions are viewed. Also in this case, the processing before the conditional branch instruction maintains continuity with the processing after it is determined that the branch is not taken.

Finally, regarding the case where the Bcc-n instruction is included,
The operation will be described with reference to FIGS. 15 to 19 and Table 4. FIG. 15 is an example of an instruction flow for explaining the operation of this embodiment for processing the Bcc-n instruction at high speed. Bcc-l ahead
Up to (1) and (2) described in the description of the instruction, the same applies to the case of the Bcc_n instruction, and thus the description is omitted here.

(3) The instruction decoding buffer 6 is in a state where the instruction N + 7 and the instruction Bcc-n remain in FIG. The transfer control circuit 32 of the instruction decoding unit 7 reads a new instruction sequence from the instruction fetch buffer A3. When it is detected that the read instruction is a Bcc-n instruction, only the instruction following the branch instruction (on the non-branch side) is continuously read from the instruction fetch buffer A3, and the instruction decoding buffer 6 is read.
To be stored. At the same time, the mode adding circuit 33 sets the current mode to "0" to indicate whether or not the instruction is a branch destination instruction.
If "1" is set, "+01" is added to the instruction at the branch destination and set as "10", whereupon the instruction decoding buffer is stored as shown in FIG.

(4) The instruction decoding unit 7 determines which instructions can be issued. Of the instructions issued in the previous cycle, the instruction N + 4 issued to the arithmetic unit A8 is a load instruction that takes two cycles, and the execution has not been completed yet. Therefore, the instruction N + 7 having a data dependency with this instruction is delayed in issuing another cycle of instruction. In this processing cycle, Bcc-n, instruction N + 9, instruction N + 10, instruction N + 1
1 is determined to be can be issued. Instruction issue control circuit 4
0 indicates that the Bcc-n instruction is sent to the instruction execution consistency maintaining circuit 18 via the instruction issuing circuit 39 and the instruction N + 9 is sent to the operation unit B
9, the instruction N + 10 to the arithmetic unit C10, the instruction N +
11 is issued with an identifier added to the arithmetic unit D11, and is deleted from the instruction decoding buffer 6. The identifiers added to these instructions are 0, 1, 1, 1 in the same order.

Table 4 shows the state of each operation unit after the instruction is issued.
Is shown on the second line. Table 4 shows the state of instruction execution in the arithmetic unit when the instruction flow of FIG. 15 is executed in the embodiment.

[0094]

[Table 4]

Each issued instruction has the following (5-1) to
This is executed as in (5-4). (5-1) The Bcc-n instruction is not issued to the operation unit, but the instruction issue control circuit 40 stores the mode “01” of the branch instruction itself in the initial mode holding circuit 14 and holds the speculative execution type. A flag indicating that the instruction is a Bcc-n instruction in the circuit 15 and a speculative execution in the speculative execution state instructing circuit 16 are set in the instruction execution consistency maintaining circuit 18 with the condition of the instruction. Thereafter, it enters a speculative execution state.

(5-2) The operation unit B9 sets the instruction N +
When 9 is issued, the corresponding bit in the operation unit management table 12 is set, and the instruction is executed. When the execution of the instruction is completed in the arithmetic unit B9, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since this instruction is an instruction under speculative execution (identifier 1), the execution order management circuit 17 writes the register number of the write destination and the mode “10” in the execution order management buffer 13.
Write. (5-3) When the instruction N + 10 is issued, the operation unit C10 sets the corresponding bit of the operation unit management table 12, and executes the instruction. When the execution of the instruction is completed in the arithmetic unit B9, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since this instruction is an instruction under speculative execution (identifier 1), the execution order management circuit 17 writes the register number of the write destination and the mode “10” in the execution order management buffer 13.
Write. (5-4) When the instruction N + 11 is issued, the operation unit D11 sets the corresponding bit of the operation unit management table 12, and executes the instruction. Arithmetic unit D11
When the execution of the instruction ends, the execution result is output to the execution order management circuit 17. At the same time, the corresponding bit of the operation unit management table 12 is cleared.

Since the instruction N + 2 is executed under speculative execution (the identifier is 1), the execution order management circuit 17 stores the operation result in the execution order management buffer 13 without writing it in the register file 19. (6) At this point, FIG.
The third line of 9 will be stacked.

(7) Also, the instruction decoding buffer 6 is
become that way. In the next cycle, since the instruction N + 4 has been completed, the instruction decoding unit 7 performs a series of processing and executes the instruction N +
7, N + 12 and N + 13 are issued. The state of the arithmetic unit after the instruction is issued is shown in the third row of Table 4. At the end of execution of these instructions, the execution order
Up to the fifth line.

(8) As described above, the arithmetic unit executes the input instruction, and when a new instruction can be processed, the corresponding bit of the arithmetic unit management table 12 is cleared. When it becomes possible to process a new instruction, the instruction decoding unit 7 restarts the instruction issuing process. (9) The instruction N + 7 for changing the PSR is executed by the arithmetic unit B as shown in the third row of Table 4. When the instruction N + 7 is completed and PSR is determined, the arithmetic unit B clears the flag of the speculative execution state instruction circuit 16. Even if the instruction N + 7 is completed, the speculative execution is executed up to the fourth line of Table 4.

(10) The instruction execution consistency maintaining circuit 18
Since the speculative execution state instructing circuit 16 has been cleared, the speculative execution type holding circuit 15 indicates that the instruction is a Bcc-n instruction.
It is determined whether or not to branch based on the value of. Here, it is assumed that no branch occurs. (11) The execution order management circuit 17 is notified by the instruction execution consistency maintaining circuit 18 that it is determined not to branch and that the speculative execution mode has ended. Then, for an instruction sequence (instruction whose mode is “10”) following the branch instruction existing in the execution order management buffer 13, the operation result is stored in the corresponding register of the register file 19.

As described above, the processing performed by speculative execution by the conditional branch instruction Bcc_n maintains continuity with the processing after it is determined that no branch is performed. In addition, since all the speculative execution results are effective, the processing is performed most efficiently and at high speed. If it is decided to branch in (10), the following is performed. (11) After determining that the instruction execution consistency maintaining circuit branches, the instruction execution consistency maintaining circuit refers to the speculative execution type holding circuit 15 and determines that the instruction is a Bcc-n instruction. Disable all. In FIG. 19, all instructions after instruction N + 9 are invalidated (cleared). Further, the instruction decoding unit 7 is notified of the branch, and the instruction fetch buffer A is re-executed so that the instruction at the branch destination is fetched into the instruction decoding buffer 6 again.

(12) The execution order management circuit 17 determines from the instruction execution consistency maintaining circuit 18 that no branch is taken,
The end of the speculative execution mode is notified. And
Since all the operation results of the instructions in the execution order management buffer are invalidated, nothing is performed. As described above, the processing performed by the speculative execution by the conditional branch instruction Bcc_n is not utilized in the processing after the branch is determined, and does not contribute to speeding up. However, since the conditional branch instruction Bcc_n has a low probability of branching, the probability of occurrence of such a case is low, and instead of looking at only one speculative execution, looking at all speculative executions of the entire program together , Will be faster. Also in this case, the processing before the conditional branch instruction maintains continuity with the processing after the branch is determined.

In the present embodiment, the pipeline of the arithmetic unit is one stage for simplicity. Even in the case of a plurality of stages, it is only necessary to change the operation unit management table 12 and the like, but this is not related to the gist of the present invention. In the present embodiment, the order in which the instructions are loaded in the instruction decoding buffer 6 is alternately stacked. However, the order is reversed, and it is not necessary to alternate the instructions one by one. Further, the instruction decoding buffer 6 itself does not necessarily have to be provided. In this case, the instructions may be directly transferred from the instruction fetch buffers A3 and B4 to the respective decoders of the instruction decoding circuit 34 via the selector 5.

In this embodiment, the operation units A8 to D11
Although the functions are limited for the sake of simplicity of description, units having the same functions may be used. In the present embodiment, in order to distinguish whether the storage destination of the operation result is the register file 19 or the execution order management buffer 13, it is realized by adding an identifier to the instruction at the time of issuing the instruction. May be used instead of the PC value.
Further, the instruction decoding unit 7 may instruct the execution order management circuit 17 where to store the instruction without adding an identifier to the instruction.

In this embodiment, an instruction (an instruction whose operand is in a register) for finally storing the operation result of the operation unit in the register of the register file 19 is used for simplicity of explanation, but the present invention is not limited to this. Alternatively, an instruction for finally storing the operation result in the memory (an instruction having an operand in the memory) may be used. In this case, for example, the execution order management buffer 13 temporarily stores the operation result, information indicating the address of the memory where the operation result should be originally stored, and the mode.
Need only have a function of writing the operation result to the memory.

In this embodiment, since the speculative execution state holding circuit can have only one state, only one branch instruction is speculatively executed. Good. In this embodiment, the mode is added according to the following rules so that the control flow of the instruction can be understood each time the instruction is generated in the instruction decoding unit. For example, if the mode of the current instruction sequence is “00”, the mode of the subsequent instruction sequence is “+0”.
1 is added to “01”, and the mode of the instruction at the branch destination is “+”.
10 "is added and set as" 10 ". Using this rule, the instruction sequence up to the branch instruction, the following instruction sequence and the instruction sequence at the branch destination can be easily determined. This is just an example, and other methods are possible.

In this embodiment, since the speculative execution type holding circuit 15 can have only one state, the number of branch instructions on which speculative execution is based is limited to one. But,
An instruction for changing the PSR by increasing the types of modes for distinguishing instruction sequences and providing a plurality of initial mode holding circuits 14, speculative execution type holding circuits 15, speculative execution state instruction circuits 16, and instruction execution consistency maintaining circuits 18 And a branch instruction, the speculative execution of a plurality of branch instructions becomes possible.

In this embodiment, regarding the data dependency, the decryption unit issues an instruction by issuing out-of-order,
-order does not affect the gist of the present invention. As described above, the information processing apparatus according to the present invention includes Bcc-l, Bcc-i, Bc
By properly using the three types of branch instructions cn, the speed can be further increased in accordance with the probability of branching. For example, in a program written in the programming language C,
The compiler uses the Bcc_l instruction for for loops with generally high branch probabilities, and if-th
The Bcc_i instruction is used for en-else instructions. In addition, if the instruction sequence in the loop is scheduled so that it can be executed simultaneously, the effect is further enhanced.
Also, in the case of if-then-else instructions, the cost of deviating from one of them is large, and at the same time, even if the branch is predicted and speculatively executed, In many cases, only one instruction can be executed at a time. In such a case, the parallel execution rate does not increase, and the effect is greater when both instructions are executed.

[0111]

According to the processor of the present invention, even if the condition of the conditional branch instruction is not determined, the instruction of the instruction sequence executed speculatively is changed according to the type of the conditional branch instruction. There are few interlocks, and a program including branch processing can be executed at high speed. In particular, when a plurality of instructions are executed at the same time, the time difference between the instruction for changing the branch condition and the conditional branch instruction is reduced, and this effect is large.

More specifically, the following three cases are used properly. In the case of the first type of conditional branch instruction, the branch destination instruction is speculatively issued to a plurality of operation units, the operation results are temporarily stored, and the condition is determined and the branch is not performed. Is found, by executing the instruction sequence on the non-branch side, the pre-processing of the branch instruction becomes possible, and there is an effect that the branch processing can be sped up. This first type of conditional branch instruction is used when the probability of branching is high.

In the case of the second type of conditional branch instruction, the instruction at the branch destination and the instruction not branching are speculatively issued to a plurality of operation units, and the operation results are temporarily stored. At the same time, when the condition is determined, only the operation result on the determined side is made valid, so that the branch instruction can be pre-processed and the branch processing can be sped up. This second type of conditional branch instruction is used when the probability of branching is unknown.

In the case of the third type of conditional branch instruction, an instruction that does not branch speculatively is issued to a plurality of operation units, the operation results are temporarily stored, and the condition is determined. If it is determined that the branch is taken, the branch instruction is executed, so that the preceding processing of the branch instruction becomes possible, and the branch processing can be sped up. This third conditional branch instruction is used when there is a high probability of not taking a branch.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a processor according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a detailed configuration of an instruction fetch unit in the embodiment.

FIG. 3 is a block diagram illustrating a detailed configuration of an instruction decoding unit.

FIG. 4 is a mode explanatory diagram showing a mode added to an instruction flow in the embodiment.

FIG. 5 is an instruction flow diagram including a Bcc_i instruction in the embodiment.

FIG. 6 is an explanatory diagram (part 1) of an instruction decoding buffer when processing the instruction flow of FIG. 5 in the embodiment.

FIG. 7 is the same as above (No. 2).

FIG. 8 is the same as above (part 3).

FIG. 9 is an explanatory diagram of an execution order management buffer when processing the instruction flow of FIG. 5 in the embodiment;

FIG. 10 is an instruction flow diagram including a Bcc_l instruction in the embodiment.

FIG. 11 is an explanatory diagram (part 1) of the instruction decoding buffer 6 when processing the instruction flow of FIG. 10 in the embodiment.

FIG. 12 is the same as the above (No. 2);

FIG. 13 is the same as the above (part 3).

FIG. 14 is an explanatory diagram of an execution order management buffer when processing the instruction flow of FIG. 10 in the embodiment;

FIG. 15 is an instruction flow diagram including a Bcc_n instruction in the embodiment.

FIG. 16 is an explanatory diagram (1) of the instruction decoding buffer 6 when processing the instruction flow of FIG. 15 in the embodiment.

FIG. 17 is the same as the above (No. 2).

FIG. 18 is the same as the above (part 3).

FIG. 19 is an explanatory diagram of an execution order management buffer when processing the instruction flow of FIG. 15 in the embodiment.

[Explanation of symbols]

 Reference Signs List 1 memory 2 instruction fetch unit 3 instruction fetch buffer A 4 instruction fetch buffer B 5 selector 6 instruction decoding buffer 7 instruction decoding unit 8 operation unit A 9 operation unit B 10 operation unit C 11 operation unit D 12 operation unit management table 13 execution order Management buffer 14 Initial mode holding circuit 15 Speculative execution type holding circuit 16 Speculative execution state instruction circuit 17 Execution order management circuit 18 Instruction execution consistency maintaining circuit 19 Register file 20 Score board 21 Program counter 22 Branch instruction detecting circuit 23 Arithmetic circuit 31 Branch instruction detection circuit 32 Transfer control circuit 33 Mode addition circuit 34 Instruction decoding circuit 34a to 34f Decoder 36 Data dependency detection circuit 37 Score board management circuit 38 State detection circuit 39 Instruction issuing circuit 39a to 39 d selector 40 instruction issue control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-137048 (JP, A) JP-A-64-88843 (JP, A) JP-A-4-247522 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (16)

(57) [Claims] A plurality of execution units which are fetched from a memory;
Ri issued and the plurality of instructions a-processor to run parallel <br/> column in a plurality of execution units, is included in the plurality of instructions fetched from memory, conditions the execution result of another instruction Instruction type determining means for determining the type of the conditional branch instruction that depends on: (a) an instruction sequence at the branch destination; and (b) a branch destination until the success or failure of the branch is determined. Instruction
(C) of the following instruction sequence
From any, when the instruction parallel issue means for parallel issue multiple instructions to multiple execution units, other instructions the conditional branch depends is executed, life
Branch determining means for determining whether or not the branch of the conditional branch instruction determined by the instruction type determining means is successful; and determining the execution result of the plurality of execution units so as to match the result of determining whether or not the branch of the conditional branch instruction is successful . An execution result management means for determining whether the conditional branch instruction is valid or invalid, wherein one of the types of the conditional branch instruction is a loop-type conditional branch instruction. 2. The instruction type judging means discriminates between an instruction of a first type, which is a conditional branch of If Zen Els system, and another conditional branch instruction. When the branch instruction is the first type of instruction, the instruction is copied from both the instruction sequence at the branch destination and the instruction sequence following the conditional branch instruction.
Number of instructions are issued in parallel to a plurality of execution units, and if the conditional branch instruction is an instruction other than the first type of instruction, a plurality of instructions are issued from one of them in parallel to a plurality of execution units. When the conditional branch instruction is the first type of instruction, the execution result management means validates the execution result of one instruction sequence and invalidates the other according to the result of the branch success / failure determination. If the conditional branch instruction is other than the first type of instruction, all of the execution results of the instruction sequence are made valid or invalid according to the result of the branch success / failure judgment. The other branch instruction is the conditional branch instruction of the loop system. The processor of claim 1, comprising: 3. The method according to claim 1, wherein the instruction type determining means is configured to determine whether an instruction other than the first type of branch instruction is a second type of instruction that is a conditional branch instruction of the loop, and a probability of not branching from the first branch instruction. it is determined in the third type of instruction and a high conditional branch instruction, the instruction parallel issue unit, when the instruction second type, parallel issued to the execution unit instructions branch target instruction sequence In the case of the third type of instruction, instructions of an instruction sequence following the conditional branch instruction are issued in parallel to an execution unit, and the second type of instruction is the loop-type conditional branch instruction. Item 3. The processor according to Item 2. Wherein said processor is a first for temporarily storing instructions of a subsequent instruction sequence further conditional branch instruction
An instruction fetch buffer, a second instruction fetch buffer for temporarily storing an instruction in an instruction sequence to which a conditional branch instruction branches , and an instruction stored in a memory.
The instructions of the following instruction sequence are stored in the first instruction fetch buffer,
2. The processor according to claim 1, further comprising: an instruction fetch unit configured to store an instruction of an instruction sequence at a branch destination of the conditional branch instruction in a second instruction fetch buffer. 5. The instruction fetch means outputs a read address to a memory and increments the content thereof, and a conditional branch for detecting a conditional branch instruction from an instruction read from the memory in accordance with the read address. an instruction detecting means, on the basis of the conditional branch instruction detected by the conditional branch instruction detecting means increments and calculating means, the contents of the program counter every time the instruction is read out from the memory to compute the branch destination address The instruction is stored in the first instruction fetch buffer, and if a conditional branch instruction is detected, the instruction of the succeeding instruction string is stored in the first instruction fetch buffer, and the branch destination address obtained by the arithmetic means is stored in the first instruction fetch buffer. A fetch system that writes to the program counter and stores the instructions in the instruction sequence at the branch destination in the second instruction fetch buffer The processor according to claim 4, further comprising a means. 6. The parallel instruction issuing means includes: a plurality of decoding means for decoding an instruction to generate a control signal to an execution unit; and an instruction from a first or second instruction fetch buffer to all decoding means. Transfer control means for transferring one instruction at a time, and mode information indicating which instruction sequence the instruction belongs to is added to each instruction transferred by the transfer control means .
That mode - possess a de adding means, said execution result management means, execution of instructions by the mode information
Whether the result belongs to the instruction sequence following the conditional branch instruction or branches
5. The processor according to claim 4 , wherein whether the instruction belongs to the previous instruction sequence is identified . 7. The mode information added by the mode adding means is 2-bit information, and the mode information of the instruction sequence following the conditional branch instruction is the mode information of the conditional branch instruction itself. mode - a value obtained by adding the first value for de information, the branch target instruction sequence mode - de information
7. The processor according to claim 6, wherein the information is a value obtained by adding the second value. 8. Another instruction on which the conditional branch instruction depends is:
PSR (Program Status Register) inside the processor
An instruction to be changed in accordance with an execution result , wherein the branch determination unit determines that the branch is successful by detecting execution of the other instruction and referring to a PSR .
The processor of claim 6, wherein the that. 9. The data dependency determining means for determining data dependency between a plurality of decoded instructions with reference to a plurality of decoding results decoded by the decoding means. Score board management means for managing which register is being used by the instruction being executed by the execution unit; empty state detection means for detecting the empty state of the execution unit; For the instruction, issuance of an issuable instruction from the instruction parallel issuing means to the execution unit is permitted based on the result of determination by the data dependency determination means, the result of detection by the score board management means, and the result of detection by the empty state detecting means. 7. The apparatus according to claim 6, further comprising an instruction issuance permitting means for permitting issuance from the instruction parallel issuing means to the branch determining means when the instruction decoded by the decoding means is a conditional branch instruction. On the processor. 10. The command issuance permitting means has no data dependency with respect to the previous command from the detection result of the data dependency detecting means for each of the decoding results of the plurality of decoding means. Information that the register specified by the operand of the instruction is not used for the instruction being executed by the execution unit, and that the execution unit capable of executing the instruction is vacant from the detection result of the vacancy detection means, 10. The processor according to claim 9, wherein it is determined that an instruction satisfying the following condition can be issued. 11. The processor further stores information indicating whether an instruction is being executed for each execution unit, an execution unit management table referred to by an empty state detection means, and an execution unit. 10. The processor according to claim 9, further comprising: a score board for holding information indicating which register is used by the instruction therein, and being referred to by score board management means. 12. The method of claim 11, wherein the execution result management means, mode of conditional branch instruction issued by the instruction parallel issue means - initialization mode holds a de Information - - the de information initial mode and de holding means by the instruction parallel issue means Speculative execution type holding means for holding the type of the issued conditional branch instruction, and speculative execution state indicating means for holding a flag indicating that the condition judgment of the conditional branch instruction issued by the instruction parallel issuing means has not been determined yet The instruction parallel issuing unit issues the conditional branch instruction to the branch determination unit, and at the same time, speculates the mode information of the conditional branch instruction to the initial mode holding unit and speculates the type of the conditional branch instruction. 10. The processor according to claim 9, wherein the processor outputs the flag to the execution type holding unit and sets a flag of the speculation execution state instruction unit. 13. Before you line result management unit includes an execution result of the instruction in the execution unit, mode of the instruction - de
Information and, in correspondence with the information indicating the execution result storage destination to have a temporary storage means for storing the execution result management means, based on the determination result of the branch judgment means
The initial mode holding means and the speculative execution type holding means are
Reference to identify the valid / invalid of the execution result of the temporary storage means,
Temporarily records the execution result according to the information indicating the storage location of the execution result
Transfer from the storage device to the storage location and clear the invalid execution result
The processor of claim 12, wherein the to that. 14. The temporary storage means stores, as the storage destination information, a register number when the original storage destination is a register, and a memory address when the original storage destination is a memory. The processor of claim 13, wherein: 15. includes a plurality of execution units, a memory
A-processor for executing a plurality of instructions fetched into <br/> parallel in a plurality of execution units, is included in the plurality of instructions fetched from memory, the condition is dependent on the result of execution of other instructions Instruction type determining means for determining the type of a conditional branch instruction; and until the success or failure of the branch is determined, according to the type of the conditional branch instruction: (a) an instruction sequence at a branch destination;
(C) of the following instruction sequence
From any, when the instruction parallel issue means for parallel issue multiple instructions to multiple execution units, other instructions the conditional branch depends is executed, life
Branch determining means for determining whether or not the branch of the conditional branch instruction determined by the instruction type determining means is successful; and determining the execution result of the plurality of execution units so as to match the determination result of whether or not the branch of the conditional branch instruction is successful . Execution result management means for identifying validity / invalidity; the instruction parallel issuing means: a plurality of decoding means for decoding an instruction to generate a control signal to the execution unit; and a first or second instruction fetch buffer Transfer control means for transferring instructions one by one to all decoding means, and mode information indicating which instruction sequence the instruction belongs to is added to each instruction transferred by the transfer control means .
That mode - possess a de adding means, said execution result management means, execution of instructions by the mode information
Whether the result belongs to the instruction sequence following the conditional branch instruction or branches
A processor for identifying whether the instruction sequence belongs to the instruction sequence . 16. Mode information added by said mode adding means.
Distribution is a 2-bit information, the instruction sequence following the conditional branch instruction mode - de information of the conditional branch instruction itself mode - a value obtained by adding the first value for de information, branch target instruction sequence Mode
The processor according to claim 15, wherein the information is a value obtained by adding a second value.