JP3138911B2 - Radio-controlled clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio-controlled timepiece.

[0002]

2. Description of the Related Art At present, in Japan, a time code is superimposed and transmitted on a long-wave standard radio wave under the jurisdiction of the Ministry of Posts and Telecommunications. This signal is January 1 with one minute as one frame.
The time data from the cumulative number of days to the hour and minute is sent out serially in binary code. Specifically, one bit is a rectangular pulse of 1 Hz, and the weighting of “1” and “0” is represented by setting the pulse width to 500 ms and 800 ms, respectively.
A pulse of ms is used, and 40 kHz is used as a carrier.

When reading the time code, a so-called radio-controlled timepiece that corrects the time using this time code has a clock pulse (radio wave) having the same cycle (one second cycle) as a rectangular pulse obtained by demodulating a received pulse. The clock pulse generator built in the modified clock is synchronized with this rectangular pulse, bit information is read from the rectangular pulse in synchronization with the clock pulse, and time information is detected based on the read information. The display time is corrected according to the detected time information.

As a method of synchronizing a rectangular pulse and a clock pulse, a time from the rising of the clock pulse to the rising of the rectangular pulse is detected as a lag time,
In general, a method of offsetting a clock pulse by an amount corresponding to the shift is used.

[0005]

The signal on which the time code is superimposed is temporarily generated due to the direction of the receiving antenna, the state of the outside world, and analog elements around the receiving circuit, such as electromagnetic waves output from a microwave oven or the like. Often fluctuates in the time axis direction. For example, when sending, 1
Despite the rectangular pulse being transmitted in the second cycle, when receiving it, the rectangular pulse is temporarily detected in a cycle shorter than 1 second or detected in a cycle longer than 1 second There is.

When such fluctuations exist, there is a case where simply trying to synchronize by the above-mentioned method does not work. In this case, there is little deviation between the rectangular pulse and the clock pulse. As a specific example, for example, as shown in FIG. 5, while the rectangular pulse 5b is delayed by the time t1 with respect to the clock pulse 5a, the rectangular pulse 5b1 temporarily fluctuates and its rise is delayed, and Slightly after the rising edge of the clock pulse, the rising edge of the rectangular pulse does not exist in the period T1, and the determination is impossible or the error is determined to be zero.
In the cycle T2, it is determined that the delay is the time t2 (t2 << t1).

Also, in order to increase the detection accuracy, a difference between the clock pulse 5a and the rectangular pulse 5b is detected a plurality of times, and synchronization is performed using an average value of the differences, as described above. If the deviation is small and fluctuation occurs, the error included in the average value becomes large, and accurate synchronization cannot be achieved.

[0008]

According to the present invention, there is provided a receiving means for receiving a signal including time information based on bit information defined by a pulse width of a rectangular pulse output every predetermined time, A clock pulse having the same cycle is synchronized with the rectangular pulse, bit information is read from the rectangular pulse in synchronization with the clock pulse, the time information is detected based on the read information, and the time information is detected in accordance with the detected time information. The clock pulse is synchronized with the rectangular pulse, the output timing of the clock pulse and the rectangular pulse is out of a predetermined range. By correcting the output timing of the clock pulse by a specific time, the output timing of the clock pulse is corrected so as to be within the predetermined range. By giving an offset to the clock pulse by the offset time after this correction, the clock pulse and the rectangular pulse are synchronized, so that even if the rectangular pulse including time information fluctuates, the clock pulse and the rectangular pulse are surely synchronized. Can be synchronized.

[0009] In addition, the output timing of the clock pulse is shifted by the specific time when a difference between the output timings of the clock pulse and the rectangular pulse is detected a plurality of times and the average value of the shift is out of a predetermined range. Thus, correction is performed so as to be within the above-mentioned predetermined range, the corrected deviation is detected a plurality of times, and the clock pulse is offset by the average value of the corrected deviation, thereby giving the clock pulse an offset. Since the rectangular pulse is synchronized, even if the rectangular pulse including the time information fluctuates, the clock pulse and the rectangular pulse can be more reliably synchronized.

[0010]

The invention according to claim 1 of the present application is a receiving means for receiving a signal including time information based on bit information defined by a pulse width of a rectangular pulse output every predetermined time; A clock pulse having the same cycle as the rectangular pulse is synchronized with the rectangular pulse, bit information is read from the rectangular pulse in synchronization with the clock pulse, and the time information is detected based on the read information. In a radio-controlled timepiece provided with control means for correcting a display time according to time information, when synchronizing the clock pulse with the rectangular pulse, the control means controls the output timing of the clock pulse and the rectangular pulse. If the shift is out of the predetermined range, the output timing of the clock pulse is shifted by a specific time to thereby set the predetermined range. Corrected so as to be of displacement, by giving an offset to the clock pulse shifted time after the correction, it is assumed that synchronization of the clock pulse and the rectangular pulse.

According to a second aspect of the present invention, in the first aspect, the control means detects a difference in output timing between the clock pulse and the rectangular pulse a plurality of times, and an average value of the difference is determined by a predetermined value. If it is out of the range, the output timing of the clock pulse is shifted by the specific time so as to be corrected so as to be within the predetermined range, and the corrected shift is detected a plurality of times. The clock pulse is synchronized with the rectangular pulse by giving an offset to the clock pulse by an average value.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments shown in the drawings.

In FIG. 1, reference numeral 1 denotes an oscillation circuit which outputs a reference clock signal. 2 is a receiving circuit constituting a receiving means, which comprises an antenna, a detecting circuit, a demodulating circuit, etc., receives a signal in which a time code is superimposed on a long-wave standard radio wave under the jurisdiction of the Ministry of Posts and Telecommunications, shapes the waveform, It demodulates and serially outputs a rectangular pulse (hereinafter, referred to as a second signal) representing a time code. Note that, in this example, the operation time of the receiving circuit 2,
That is, the reception time is set from AM0: 58 to AM1: 06. This operation time is set by a cam (not shown) that rotates in conjunction with the time hands of the time display unit 3 and a detection switch (not shown). The time display unit 3 displays the current time. Reference numeral 4 denotes a control circuit constituting a control means, which comprises a CPU, a ROM, a RAM, and the like, and controls various operations. The control circuit 4 divides the frequency of the reference clock input from the oscillation circuit 1 and has the same cycle as the second signal, ie, 1
1 second clock pulse with second cycle and sampling clock pulse for sampling second signal (1 ms cycle)
And generate. Reference numeral 5 denotes a second signal synchronous clock pulse output circuit, which synchronizes with the second signal and outputs a synchronous clock pulse having the same cycle as the second signal. Reference numeral 6 denotes a differential data memory, which is composed of a RAM or the like, and stores a plurality of delay times of a second signal with respect to a one second clock pulse. Reference numeral 7 denotes an offset value memory, which is composed of a RAM or the like, and stores an offset value for synchronizing a one-second clock pulse with a second signal. Reference numeral 8 denotes a sampling data memory, which comprises a RAM or the like, and stores sampling data of a second signal. Reference numeral 9 denotes a counting memory, which is composed of a RAM or the like, and stores a duty ratio based on sampled data. Reference numeral 10 denotes a data memory, which includes a RAM or the like, and stores a bit determination result of the second signal. 11 is a marker counter. 12 is a data relocation memory, which is a RAM
And a plurality of stored bit determination results
It is rearranged and stored so that it can be handled as D time series data. Reference numeral 13 denotes a decode data memory, which comprises a RAM or the like and stores decoded time information. 14 is a general-purpose timer. Next, the operation will be described with reference to FIGS. Note that the marker counter 11 has been cleared, and the memories 6, 7, 8, 9, 10, 12, 1
3 is assumed to be initialized.

When the display time of the time display section 3 becomes AM 0:58 and the receiving circuit 2 starts operating, the control circuit 4 outputs a synchronous clock pulse synchronized with the second signal from the second signal synchronous clock pulse output circuit 5. (Step 2a).

The specific operation of step 2a will be specifically described with reference to FIG.

When the second signal is input to the control circuit 4 by the operation of the receiving circuit 2, the control circuit 4 measures the delay time (output timing shift) of the second signal with respect to the one-second clock pulse a plurality of times (for example, about 10 times). Then, the shift of the output timing (hereinafter, shift) is stored in the difference data memory 6 (step 3a).

The average value of the deviation is within a predetermined range (in this example, 20
It is between 0 ms and 800 ms. ) (Step 3b), that is, if the deviation is small,
When fluctuations occur in the second signal, it is determined that it is difficult to achieve accurate synchronization, and the generation timing of the one-second clock pulse is delayed by 500 ms (specific time), and the average deviation is in the range of 200 ms to 800 ms. (Step 3c), the difference data memory 6 is initialized, the process returns to step 3a, and the same operation as described above is performed.

The average value of the deviation is from 200 ms to 800 ms
If the difference is within the range (step 3b), it is determined that the deviation value stored in the difference data memory 6 can absorb the fluctuation of the second signal by taking its average value. The average value is calculated, and the offset value based on the calculated value is stored in the offset value memory 7 (step 3d). Then, a signal synchronized with the second signal can be output by delaying the generation timing of the one-second clock pulse by a time corresponding to the offset value. The control circuit 4 outputs the synchronized signal (hereinafter referred to as a synchronous clock pulse) from the second signal synchronous clock pulse output circuit 5 to the control circuit 4 (step 3e).

The reason why the average value of the deviation is set in the range of 200 ms to 800 ms will be described. FIG.
As shown by 5c, the shift from the rising of the clock pulse of 5a to the rising of the rectangular pulse is t3 (200
ms <t3 <800 ms), even if t4 (t4> t3) occurs due to fluctuations in the cycle T1,
The relationship between the rise of the rectangular pulse and the rise of the clock pulse does not reverse. That is, as shown in 5b, the rectangular pulse is slightly ahead of the clock pulse while the rectangular pulse is slightly behind the clock pulse due to the fluctuation, and the leading and trailing relation of both pulses is reversed. There is no. Therefore, even if there is fluctuation, the fluctuation of the shift due to it is only that much,
It does not appear as a large variation as in FIG. 5b.

As described above, when synchronizing the second signal and the one-second clock pulse, if the deviation is small and there is a possibility that the second signal may be significantly affected by the fluctuation, the region is not greatly affected by the fluctuation. Since the generation timing of the one-second clock pulse is shifted, the influence of fluctuation can be reduced when synchronizing.

Returning to FIG. 2, step 2 as described above
a, the synchronous clock pulse synchronized with the second signal is output to the second signal synchronous clock pulse output circuit 5.
, The bit information is read from the second signal in synchronization with the generation timing of the synchronous clock pulse (steps 2b and 2c).

Before specifically describing the specific operation of step 2c with reference to FIG. 4, the bit determination will be described.

The bit information of the second signal described above is defined as "1", "0", and "marker" according to the pulse width in a one-second cycle. The determination can be made based on the pulse width in the region. More specifically, as described above, the second signal is weighted with “1” and “0” with a pulse width of 500 m, respectively.
s, 800 ms, and 2 as a position marker
Since a pulse of 00 ms is used, a “marker” is used when the pulse width in the time domain is small or nonexistent around 500 ms after the rise of the pulse.
Can be determined as “0” when the pulse width is large, and “1” when the pulse width is intermediate. For example, in the case where a second signal having no fluctuation can be accurately detected, in a time region from 500 ms to several ms before and after, a “marker” where no pulse exists and a duty ratio of 1 /
It can be determined as “1” for about two pulses and “0” for all pulses. If there is no fluctuation, the second signal is the first 20 bits of any bit information.
0 ms becomes “1”, and the last 200 ms becomes “0”. The operation of step 2c described below utilizes these characteristics.

The control circuit 4 samples the second signal by the sampling clock pulse (1 ms cycle) from the time when 250 ms has elapsed after the generation of the synchronous clock pulse to the time when the next synchronous clock pulse is generated. Store in sampling memory 8 (step 4
a, 4b, 4c, 4d). That is, when there is no fluctuation or noise, sampling is started except for the first 200 ms which is all "1".

When the sampling is completed, a correction for removing a desired portion (in this example, 200 ms) after the sampled data is performed (step 4e), the corrected data is totalized, a duty ratio is obtained, and the totaling is performed. It is stored in the memory 9 (step 4f). That is, when there is no fluctuation or noise, the last 20 that becomes “0”
The duty ratio is obtained by removing the sampling data in the 0 ms portion.

The control circuit 4 makes a bit decision by comparing the stored duty ratio with a predetermined ratio (step 4g). In this example, the ratio of determining as a “marker” in consideration of fluctuation and noise is set to 0 to 0.1,
The ratio for judging "1" is 0.4 to 0.5, and the ratio for judging "0" is 0.9 to 1.0. If the ratio does not correspond to these, it is judged as "error".

The bit determination result is composed of two bits, and is divided into four types of "1", "0", "marker", and "error" and stored in the data memory 10 as described above (step 4h).

As described above, when performing the bit determination, the sampling data of a portion that is not necessary for the bit determination is deleted. Therefore, even if noise is mixed in the deleted portion, the noise is not affected. Can be reduced.

Further, since the sampling data in a time region longer than a time region of 500 ms before and after several ms from which bit determination can be performed when there is no fluctuation is used, the influence of the fluctuation can be reduced.

Returning to FIG. 2, step 2 as described above
When the operation of c is completed, that is, when the reading of the bit information of the second signal is completed, if the read bit information is “marker”, the marker counter 11 is incremented,
When a "marker" is input for two consecutive seconds, the marker counter 11 is cleared (steps 2d, 2e, 2f, 2).
g). One minute is set to 1 by clearing the marker counter 11.
The storage of the time code of the time information as a frame is started.

When the time information of one frame (one minute) is stored by repeating the operation from step 2c to step 2g (step 2h), the one-minute bit information stored in the data memory 10 is stored in the BCD mode. The data is rearranged in the data rearrangement memory 12 so that it can be treated as sequence data, decoded, and the decoding result is stored in the decoder data memory 13 (step 2i).

When the above operation is repeated and time information for two consecutive minutes is stored in the decode data memory 13 (step 2j), it is determined whether or not the time difference between the continuous time information is one minute (step 2k). If it has reached one minute, the elapsed time is added to the decoded time to obtain a new current time (step 2m), and the display time of the time display unit 3 is corrected based on the current time (step 2m). Step 2n).

In step 2k, if the time difference between the continuous time information is not 1 minute, it is determined that the reception has not been correctly performed due to fluctuations or the like, and if not more than 6 minutes have elapsed since the start of the reception. (Step 2p), reduce the removed part of the sampling data (Step 2q)
Returning to step 2c, the same operation as described above is performed. In addition,
In this example, as a specific operation of step 2q, the part to be removed is changed from the last 200 ms to the last 190 ms,
Every time Step 2q is repeated to the last 180 ms, the removal area is reduced by 10 ms. Needless to say, the comparison value of the duty ratio for determining the bit information is changed according to the size of the used portion of the sampling data.

In step 2p, if six minutes have elapsed since the start of the reception, it is determined that accurate reception cannot be performed even if the reception is further performed, and the operation is terminated.

When reception cannot be performed accurately as described above, by increasing the sampling area, the influence of fluctuation can be reduced, and accurate reception becomes possible.

In the above description, the operating time of the receiving circuit 2 is A
Although set from M0: 58 to AM1: 06, this can be changed as appropriate.

In the above description, the time series contents of two consecutive frames are used to determine whether the time information has been correctly received. However, this is not limited to two minutes and may be changed as appropriate. It is possible.

In the above description, when the average value of the delay time of the second signal with respect to the one-second clock pulse deviates from a predetermined range (200 ms to 800 ms in this example), the generation timing of the one-second clock pulse is set to 500 ms.
The delay time is set to fall within the predetermined range, but the delay time is not limited to 500 ms, and may be changed as appropriate as long as the time falls within the predetermined range. Also, 2
The predetermined range from 00 ms to 800 ms can be appropriately changed.

In the above description, the ratios for initially performing bit determination are 0 to 0.1, 0.4 to 0.5,
The ratio is set to 0.9 to 1.0, but this ratio can be changed as appropriate.

When the time information cannot be received correctly, the sampling data removal area is reduced by 10 ms, but this amount can be changed as appropriate.

[0041]

According to the present invention, when synchronizing a rectangular pulse and a clock pulse, if the deviation is small and there is a possibility of being significantly affected by the fluctuation of the rectangular pulse, the effect of the fluctuation is not great. Since the generation timing of the clock pulse is shifted to the region, accurate synchronization can be achieved.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG. 1;

FIG. 3 is a flowchart for explaining the operation of FIG. 1;

FIG. 4 is a flowchart for explaining the operation of FIG. 1;

FIG. 5 is an explanatory diagram for explaining a problem due to fluctuation.

[Explanation of symbols]

 2 receiving means 4 control means

Claims (2)

(57) [Claims] 1. A receiving means for receiving a signal including time information based on bit information defined by a pulse width of a rectangular pulse output every predetermined time, and a clock pulse having the same cycle as the rectangular pulse is transmitted to the rectangular pulse. Synchronize with the pulse,
Control means for reading the bit information from the rectangular pulse in synchronization with the clock pulse, detecting the time information based on the read information, and correcting the display time according to the detected time information. In the modified timepiece, the control means, when synchronizing the clock pulse with the rectangular pulse, adjusts the output timing of the clock pulse when the output timing of the clock pulse and the rectangular pulse is out of a predetermined range. The clock pulse and the rectangular pulse are synchronized by correcting the clock pulse by shifting by a specific time so that the clock pulse is offset within the predetermined range, and by giving an offset to the clock pulse by the corrected offset time. Characterized radio-controlled watch. 2. The control means according to claim 1, wherein said control means detects a difference between output timings of said clock pulse and said rectangular pulse a plurality of times, and, when an average value of the difference is out of a predetermined range, said control means. The output timing of the clock pulse is shifted by the specific time to correct the shift so as to be within the predetermined range. The corrected shift is detected a plurality of times, and the average of the corrected shift is offset to the clock pulse. , The clock pulse and the rectangular pulse are synchronized with each other.