JP3136573B2 - Decoding device and processing device for variable length code - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding compressed image data having a variable bit width at a high speed, and an apparatus for aligning variable-length codewords with the number of transmission bits without gaps.

[0002]

2. Description of the Related Art In the prior art, decoding of variable-length code data is performed by loading serial data from a code memory or a reception line into a shift register, and performing decoding after parallel conversion. In order to speed up this decoding, an apparatus disclosed in Japanese Patent Application Laid-Open No. 62-135015 reads the code data length being decoded from a memory,
The shift register is shifted a number of times equal to the code length to simplify and speed up decoding of the code.

However, since the code data is serially transferred to the shift register and shifted one bit at a time, if there are n bits of code data, it is necessary to start decoding at least n clocks and code data having a short run length is required. If they are consecutive, they cannot be decoded in real time. That is, code 1
There is a problem that several clocks are required between the end of decoding of the code and the start of decoding of the next code.

Japanese Patent Application Laid-Open No. 1-99388 discloses a technique in which a shift register is divided into two stages and a CPU divides a shift and loads from a memory. However, the shift must be interrupted and the data must be loaded when the register becomes 32 bits empty during the shift, and the decoding is interrupted during that time. Further, in Japanese Patent Application Laid-Open No. 2-254824, a barrel shifter is used.
A technique of performing code cueing with one clock is disclosed.
6 and 7 show the contents of the disclosure.

However, the configuration of the invention described in this publication has the following problems since the barrel shifter is divided into two stages. That is, first, the circuit configuration becomes large because two-stage latches are required. Second, decoding must be temporarily performed because the shift must be divided into several times just to open one barrel shifter to load data. Interruption reduces the processing speed of the entire decoding. Third, when data is loaded, the shift is stopped, so that decoding is temporarily interrupted, and the processing speed of the entire decoding is reduced.

On the other hand, in order to transmit variable-length codewords without gaps, JP-A-2-277319 and JP-A-3-106127 disclose two shifters for the number of transmission bits, A device is disclosed in which a register is provided and the data is output to the outside when the data has been transmitted for the transmission bits (see FIG. 13). However, JP-A-2-27
No. 7319 has a problem that the operating frequency is suppressed because both edges of the clock must be used.

This problem has been solved by using an OR circuit in Japanese Patent Application Laid-Open No. 3-106127. However, all unnecessary bits in the shifter must be grounded because of the OR circuit. However, there is a problem that the circuit scale becomes large. In addition, recent semiconductor technologies have increased the bit width of transmission bits, such as 16 or 32 bits. However, in the conventional technology, a shifter of up to 31 bits is required in this case, which increases the shifter scale and shift processing time. The problem of increase, and the shifter →
There is a problem that the delay of the critical path from the OR circuit to the selector and the adder to the selector increases.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to eliminate the drawbacks of the prior art and to make the decoding process continuous with a small configuration.
Another object of the present invention is to provide a high-speed decoding device. Further, an object of the present invention is to use a simple decoder and a multiplexer without using a shifter in a process of packing code words without gaps, thereby achieving high-speed alignment processing and increasing the number of transmission bits. The purpose is to perform variable-length code alignment with little reduction in processing speed and with a small-scale circuit.

[0009]

In order to achieve the above object, the present invention provides a shift register having a structure in which a plurality of bits of data can be loaded into an arbitrary position in a shift register and a plurality of bits are set to one. Be able to shift by clock. Then, immediately after the decoding of one code is completed, the next decoding can be started.

Further, in order to achieve the second object, the present invention has the same number of latches as the number of transmission bits for transmitting variable-length codewords without gaps, and has an enable function. Register means, arithmetic means means for counting by accumulating each code length to the number of latches holding the code data in said register means, and inputting the code data to said register means from above. Decoder means for generating an enable signal to the latch in the register means based on the output value of the arithmetic means means and the code length of the input code data; multiplexer means for selecting code data to be input to the latch; Selector means for selecting an output of the register means, and a select input of the selector means is constituted by the decoder means.

[0011]

1 shows a block diagram of the present invention. here,
1 is n-bit code data, 2 is a demultiplexer, 3 is a shift register, 4 is a decoder, 4a is a decoding decoder, 4b is a code bit length decoder, 5 is an arithmetic unit, 6 is an accumulator, 7 is a load signal, 8 is Shift signal, 9 is code bit length, 10 is effective bit length in shift register,
11 is a code data request signal, 12 is a data load position selection signal, 13 is a control signal, 14 is decoded data or run length, and 15 is a decoder.

The n-bit code data of 1 is loaded into the shift register of 3 through the demultiplexer of 2 by the load signal of 7. At this time, the effective bit length in the shift register 3 is held in the accumulator 6.
When loading the first sign data, the shift register 3
Since no data is contained in the shift register 3, the effective bit length of 0 is 0, and the 15 decoders output 12 position selection signals and 7 load signals so that data is loaded from the most significant bit of the shift register 3. Is done.

The loaded data is input to four decoders. 4a indicates decoded data, and 4b indicates a code bit length decoder. In 4a, a run length is output in the case of a predetermined decoding process or a code having a run length such as an MH code.
Outputs the code bit length. The arithmetic unit of No. 5 calculates the effective bit length in the shift register. For example, 10
If the current effective bit length is m, the code bit length of 9 is L, and the code data length loaded into the 1 shift register is n, m + n-L is calculated. The operation result is stored in the accumulator 6, and when the shift register 3 becomes n bits empty by the 15 decoder, the data request signal 11 is output to the outside.

As a result, in the shift register 3, the head of the code data is always located at the most significant bit, and the next code data is also packed without gaps. Is started. FIG. 2 shows an embodiment of the present invention. The description of the same reference numerals as those in FIG. 1 is omitted (the same applies to the description of other drawings below).

Here, 16 is a clock, 17 is a code valid flag, 18 is code data (maximum number of bits of code length),
23 indicates a unit block, 24 indicates a decoding end signal, 25 indicates an external data load signal, and 26 indicates coded data divided into the number of bits of one block. FIG. 2 shows an embodiment of the present invention.

For example, consider decoding of coded data having three data lengths of 4, 8, and 12 bits and including a run length. Further, it is assumed that the transfer bus width of the code data of 1 is 16 bits and the shift register of 3 is 48 bits. 1
Is expanded to 48 bits by the demultiplexer of 2. The 3 shift registers are composed of 4 bits × 12 stages, and shift and load are performed every 4 bits. The previously developed code data is simultaneously loaded into four blocks in the shift register 3 by 16 bits with a load signal of 7. At the next clock, the data in the shift register 3 has a maximum code length of 12 bits of 4a and a run length decoder 4a.
b is output to the code length decoder. At this time, the number of valid data blocks in the current shift register 3 held in the accumulator 6 is input to the decoder 4b,
It is determined whether the data input to a and 4b is valid, and a sign valid flag of 17 is output.

For example, in the shift register 3,
If the block contains only 8 bits of data, the number of valid blocks 2 is input to 4b from the accumulator of 6. If the code data of 18 is not 4 or 8 bits, the flag of 17 is not set and the shift register is 3 bits.
It stops until data is loaded to the block. Conversely, code data less than the number of effective blocks is 4a, 4
b, the code data length from 4b to 9 is output to the arithmetic unit having the value of 5, and the shift value of 8 (= code data length) is shifted by 3 together with the decoding end signal of the current code data of 24. Sent to register 3. Then, new code data shifted to the top of the shift register 3 at the next clock is output to 4a and 4b.

At this time, the number of effective blocks in the shift register 3 is transferred from the arithmetic unit 5 to the accumulator 6. Next, in order to load one code data into the next block of the effective block in the shift register 3, the load position is calculated by 15 decoders, and 25 data load signals are inputted, and at the same time, 7 load signals are outputted. . FIG.
Shows a configuration example of one block in a shift register used in the present invention.

Here, 19 is a data line, 19-n is a data line from a register lower than n blocks, 20 is a multiplexer, 21 is a selector, 22 is a register, and 7-n n
It shows a load signal to the block lower register and load code data to the 26-nn block lower register. According to the shift value of 8, the data of 19-0 to n is selected by the multiplexer of 20-1. For example, if the shift value is 2, the data line 10-2 from the lower block of the second block is selected. 20-0 and 20-2 are multiplexers for loading data. When the shift value is 0, the code data of 26-0 is selected by the selector 21 by the load signal of 7-0, and is latched in the register 22 by the next clock. When the shift value is n, n
The data 26-n to be loaded in the lower block is 7-n.
By selecting with n, the load data is also latched in the register in a shifted form. With these configurations, loading and shifting can be performed simultaneously, and the shift register 3 always outputs code data from the highest order.

When the shift register has a vacant space corresponding to the bit length of 1 code data, 15 decoders output 11 load requests to the outside. From the outside, 1 code data is transferred together with 25 load signals, and 15 decoders output 7 shift register load signals in synchronization with 25 load signals. At the same time, in the arithmetic unit of 5, the number of loaded blocks is added to the number of effective blocks held in the accumulator of 6.

The arithmetic unit 5 outputs the shift signal 8 and the shift register 3 outputs the code data to the decoder 4a, and then outputs the shift value φ until the decoding of the code is completed. to continue. At the same time as the decoding end signal of 24, a shift signal of 8 is transmitted with the code length of 9 as a shift value, and immediate code data is output from the shift register. Thus, decoding can be continued without interruption between code data.

Even if the code data is in 1-bit units like the MH code, one block of the shift register shown in FIG. 3 is made in 1-bit units, and the input of 20 multiplexers is operated according to the code length. Can respond. FIG.
7 shows a part of a modification of the present invention. Here, 27 is a 32-bit data load signal, 28 is a data request signal, 29 is a control circuit, 30 is a buffer, 31 is a selector, and 32 is 16
A bit data load signal 33 indicates a data selection signal.

It is assumed that the bus width of the external code data is 32 bits. In the above example, since data cannot be loaded until the shift register has 32 bits available, the number of stages of the shift register must be increased in order to perform decoding in real time. This solution is the present embodiment. 1 of 32
The bit width code data is temporarily stored in 30 buffers. By the data request signal of 11, the control circuit of 29
The upper 16 bits of data are first transferred to the demultiplexer 2 by the 33 select signals, and 32 load signals are output at the same time. Next, when a data request signal comes, the lower 16-bit data is transferred and 28 data request signals are output to the outside. Thus, since the data is transferred to the shift register in 16-bit units, the number of stages of the shift register can be reduced.

This configuration is merely an example, and the number of data transfer bits can be further reduced by dividing the 30 buffers into three and four stages. FIG. 5 shows another modification when serial data transfer is performed. Here, 34 is a serial-parallel converter, 35 is a FIFO (First-In First-Out), and 36 is serial code data.

The 36 1-bit code data is converted into an n-bit length by the serial-parallel converter 34 and sent to the FIFO 35. The control circuit 29 reads data from the FIFO in accordance with the data request signal 11 and transfers the data to the demultiplexer so that the shift register used for decoding the variable length code can be loaded into an arbitrary position. Also,
The number of effective bits or blocks in the shift register is stored in the accumulator so that shift and load can be performed simultaneously.

FIG. 8 shows a schematic configuration of the present invention. Assume that the maximum number of bits of the code length is 8, and the number of transfer bits after alignment is 32. Eight bits of code data of 21 are input to a multiplexer of 22 in synchronization with an enable signal of 29. At the same time, the code data length 210 is input to the 25 arithmetic units, added to the current accumulated code length value 211, and held in the 26 registers. The input enable signal of the code length accumulated value 29 of 211 and the code data length of 210 are decoded by a decoder of 27 and a latch enable signal of 212 is generated.

The symbols are input to and held in the 23 latches in a form in which codes are sequentially packed. Further, in this embodiment, 64 latches are prepared in this embodiment, and when the 32 latches are stored, they are selected by the selector 24 and output to the outside in synchronization with the alignment end signal 214. FIG.
Shows an embodiment of the code data input unit in FIG.

The 8 bits of the code data of 21 are converted to the MSB (Most
Significant Bit) to LSB (Least Significant Bi)
Until t), it is indicated by 7 to 0. Also, 22 multiplexers are changed from MSB to 22-0, 22-01,.
, 22-63, and 23 latches from the MSB to 23-0, 23-1,.
1,... 23-63. The code data of 1 is sequentially sent to multiplexers 22-0 to 22-63 by 1
The data is input in a bit-shifted configuration. The lower three bits of the total code length of 211 are input to the select input of the multiplexer.

For example, when the three bits of the total code length 211 are 0
In the case of 10 (b), as shown in FIG.
1076543221076 in the order of input to ~ 23-63
・ ・FIG. 11 shows an EN (ENABLE) signal generation diagram of the registers 23-0 to 23-63 at this time. Since the lower three bits of the total code length 211 are 010 (b), the total code length is 2 or 10 or 18 (d).
As shown in FIG. 11D, 212-2, 3, 4,...
, 63 are enabled (ENABLE) and 23-
Data is loaded into registers 2, 3, 4, 5,..., 63. That is, 1 from the beginning of the vacant register
The MSB-LSB of the code data is loaded. At the same time, the number of bits of the code data loaded and the total code length are added and stored in the register 6 and used for loading the next code data.

According to the embodiment, for example, the code length is 4 (d)
Even if it is the same, data is not loaded into the register only for 4 bits, but only the register buried from the MSB of each of the 3 32-bit registers is disabled (DISABLE), and the other bits and the other 32 bi are used.
All t registers are enabled. As a result, the decoder circuit 27 does not depend on the code length of the input data, and outputs to the outside in FIG. 11 when either of the two 32-bit registers is filled, as shown in FIG.
14 of the alignment end signals are generated, and the alignment data is output to the outside.

FIG. 12 shows the overall timing. The select signal 213 to the selector 24 in FIG.
, And an alignment end signal 214 is generated at the transition point of the select signal 213. In this embodiment, three registers are provided for the number of transfer bits × 2. However, the present invention is not limited to this, and one block of registers can be subdivided to reduce the number of registers. For example, it is also possible to prepare a total of three blocks with the transfer bit fraction ÷ 2 as one block, and to output it together with an end signal to the outside when two of them are filled, by changing the decoder of 27 and the selector of 24. , The number of registers can be reduced.

In this embodiment, the barrel shifter for aligning the code data is constituted by an n-to-1 multiplexer, the register for temporarily storing the alignment data is divided into blocks, and the enable signal to each register is transmitted. A decoder for generation is provided.

[0033]

According to the present invention, one code data is shifted by the code data length in the shift register at the same time as the completion of decoding, and the next code data is output from the shift register. You can do it.
Also, since data can be externally loaded into the shift register during decoding, there is no run during decoding of run length, and decoding does not stop halfway even if code data is continuously input.

Further, according to the present invention, if the code data in the shift register is not complete for one code, the code valid flag is lowered and the data is waited for being loaded. Even if the transfer is stopped, the operation can be stopped without causing an error during the decoding. On the other hand, in the conventional example, assuming that the number of transfer bits is 32, first, a maximum of 31 bits are shifted in the barrel shifter section. This is equivalent to the processing time of a 32-to-1 multiplexer, and the empty bits must be filled with 0, thus increasing the circuit scale. Further, after the shift, the signal is input to the register after passing through the OR circuit and the SEL circuit, so that the entire processing time is delayed.

On the other hand, in the present invention, the code data is 8 bits.
Since the signal is latched into the register only by passing through the one-to-one multiplexer, high-speed processing can be performed. As for the enable signal to the register, it is not necessary to judge the code length of the input code data in the decoder as the generation unit, so that it can be configured with a simple gate circuit and can be processed at high speed. Therefore, the entire alignment processing time is shortened by the present invention, and the circuit scale is also reduced.

Further, even if the number of transfer bits increases, the processing time is almost the same.

[Brief description of the drawings]

FIG. 1 shows the invention in a block diagram.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows a configuration example of one block in a shift register of the present invention.

FIG. 4 shows a part of a modification of the data input unit of the present invention.

FIG. 5 shows a part of a modification of the data input unit of the present invention.

FIG. 6 shows a configuration of a conventional barrel shifter.

FIG. 7 shows the processing contents of the conventional barrel shifter of FIG.

FIG. 8 shows an embodiment of an alignment circuit according to the present invention.

FIG. 9 shows an embodiment of a code data input unit in FIG.

FIG. 10 shows a state diagram at the register input of the code data.

FIG. 11 shows an enable signal generation diagram of a register.

FIG. 12 is an overall timing chart.

FIG. 13 is a configuration example of a conventional code data alignment circuit.

[Explanation of symbols]

 Reference Signs List 1 n-bit code data 2 demultiplexer 3 shift register 4a decoding decoder 4b code bit length decoder 5 arithmetic unit 6 accumulator 7 load signal 8 shift signal 9 code bit length 10 effective bit length in shift register 11 code data request signal 12 data load Position selection signal 13 Control signal 14 Decoded data or run length 15 Decoder 21 Variable length code data 22 Multiplexer 23 Latch 24 Selector 25 Operation unit 26 Register 27 Decoder 29 Code data input enable signal 210 Code data length 211 Cumulative code data length 212 Latch enable Signal 213 Select signal 214 Alignment end signal 215 Alignment data 216 Transfer bit length register

Claims (3)

(57) [Claims] 1. A shift register having a function of simultaneously loading all bits of variable-length code data and a function of shifting n bits of code data length by one clock, and capable of performing shift and load simultaneously, and a shift register output from the shift register. Sign from sign data
A decoder for outputting a bit length and decoded data ; the code data length, the code bit length, and a currently valid bit.
The Editor, a calculator for calculating the effective bit length of the shift register, the effective bit in the shift register output from said arithmetic unit
The door length, variable length code, characterized in that it comprises an accumulator for holding as the current effective bit length, and a demultiplexer for loading code data based on the output value of the accumulator to a predetermined position of said shift register Decoding device. 2. A buffer for temporarily storing a variable length code is provided at a stage preceding the demultiplexer, and a control circuit for dividing code data loaded in the buffer and transferring the code data to the demultiplexer is provided. 2. The decoding device according to claim 1, wherein the number of stages is reduced. 3. A total number of code data lengths having the same number of latches as the number of transmission bits and having an enable function for transmitting variable-length code data without gaps.
Register means for registering the code data, the code data length of the code data and the current accumulated code data.
From data length, and calculator means for calculating the accumulated code data length, in order to enter the code data packed from the upper to the register means, the code data length, the accumulated code data
From the long and the input enable signal to generate a latch enable signal to <br/> latches in the register means and Arai
A decoder means for outputting an instrument end signal, and a multiplexer means for selecting the code data to be input to the latch, and selects the output of said register means and said Alignment
Variable-length code processing apparatus that a selector means for outputting the alignment data in accordance with the preparative end signal, comprising the.