JP3130880B2 - Hierarchical layout design method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a hierarchical layout design method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art At present, in a semiconductor integrated circuit (LSI),
The increase in circuit scale, the improvement in integration due to the miniaturization of semiconductor elements, and the increase in the speed of operation signals have made the layout design more difficult.

In the current LSI design, logic circuits are connected to each other to design the functions required of the LSI. From the logic design, each logic circuit and the wiring of the connection are arranged on an actual semiconductor chip. A layout process is performed to determine whether or not to implement the design, and a verification process for verifying the validity of the connection relationship after the designed layout (hereinafter, referred to as a netlist) and the netlist after the logic circuit. In general, the design is performed by extracting (adding annotating) timing information obtained by extracting parasitic parasitic resistance and capacitance, calculating delay, to the logic simulation, and verifying the timing by repeating back annotation.

Here, in the logic design, a hierarchical design is performed for each logic unit having each function (hereinafter, referred to as a macro cell in the description of the logic design) and assembling them. In the layout design, the arrangement of macrocells (hereinafter, referred to as blocks in the layout design) configuring each function and the arrangement of elements (basic circuits such as inverters and NAND circuits) configuring each logic circuit and wiring connecting them are described. Place.

First, this will be described with reference to FIG. 11 as a conventional basic technique. Here, FIG. 11 is a plan view showing the block arrangement on the semiconductor chip and the wiring arrangement between these blocks.

As shown in FIG. 11, for example, blocks 102, 103 and 104 which are to be macro cells on a logic circuit are arranged in an upper hierarchy 101 such as a semiconductor chip. Here, elements 105, 105a, 107, 109, and 109a are formed in the blocks 102, 103, and 104, respectively. These blocks 102,
Terminals 106, 103 are located at predetermined positions on the boundaries between 103, 104.
106a, 108, 108a, 110 and 110a are respectively formed.

[0007] Wiring (referred to as a net in the logical design) for connecting the blocks is performed by automatic layout. In this automatic layout, the terminal 1 of the block 102
06a and the terminal 108 of the block 103 are connected by a wiring 111. Then, the terminal 108a of the block 103 and the terminal 110a of the block 104 are connected by the wiring 112. Further, the terminal 106 of the block 102 and the terminal 110 of the block 104 are connected to the wiring 1 so as to bypass the block 103.
Connect at 13.

Here, by arranging the wiring between the blocks, a parasitic resistance / capacitance (hereinafter referred to as an RC component) is generated,
Since a signal propagation delay occurs in a wiring for operating each logic circuit, it is important to design the wiring to be short.

Therefore, in the layout design, when there is a block irrelevant to the connection on the optimum wiring path connecting the blocks, a passing wiring is made to pass over the block. As described above, when a passing wiring passes over a block, at the time of layout design of the block, a logically unnecessary netlist that did not exist at the time of logic design is dropped (embedded) into a macro cell corresponding to the block. Do.

In addition, RC attached to wiring after layout design
By extracting the components and annotating the timing information calculated with the delay to the logic simulation, back annotation for performing logic verification including more accurate timing is performed.

However, since the netlist of each hierarchy is changed by dropping the passing wiring, there arises a problem that the timing information cannot be annotated to the logical side netlist.

Therefore, as a method of solving this problem,
In the technique described in Japanese Patent Application Laid-Open No. 4-333260, a netlist of passing wirings passing through a block is created in advance from connection information of a logic circuit, and a layout in the block is created together with a netlist in a macro cell corresponding to the block. A netlist for design was created. Another solution is to solve the problem by performing a hierarchical development process on the entire block of the passing wiring, which is the difference between the netlists at the time of logic design and layout design.

[0013]

However, the above-mentioned conventional techniques have the following three major problems. That is, the first problem is that, in the verification of the netlist after the logic design and the wiring connection after the layout design performed for each hierarchy, the netlist of the passing wiring added at the time of the layout design is the macro cell corresponding to the block. , The connection becomes inconsistent and connection verification cannot be completed normally.

The second problem is that since a netlist of passing wirings passing over blocks is created in advance in the netlist of the logic circuit prior to the layout design, an optimal netlist in the layout design is not always required. This means that the list has not been created.

A third problem is that, when the difference between the passing wirings on the block is solved by hierarchical expansion, it is impossible to perform verification and back annotation for each macro cell and between macro cells, which is an advantage of hierarchical design. That is.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem that, in a hierarchical layout design of a semiconductor integrated circuit, a mismatch in connection verification for each hierarchy due to a passage wiring embedded in a macro cell is solved. Is to provide. It is still another object of the present invention to provide a layout design method for a semiconductor integrated circuit, in which the netlists at the time of the logic design and after the layout design match, enabling connection verification of the netlist and accurate back annotation including the passing wiring. It is in.

[0017]

For this purpose, in the layout design method of a semiconductor integrated circuit according to the present invention, a block corresponding to a macro cell having a predetermined logic function is arranged in an upper hierarchy, and the blocks are connected in the upper hierarchy. In the hierarchical layout design for wiring, after the step of arranging blocks on the upper hierarchy, a step of automatically laying out connection wiring so that a wiring path between the blocks is shortened, and after the automatic layout step, wiring is placed thereon. A step of generating a terminal at the boundary of the passing block for a block to be passed, that is, a passing wiring path on the passing block, and embedding a passing wiring portion of the block in the block; Corresponding to a new macro cell with the layer having the upper layer and the passing block as the lower layer Including a hierarchical generation process of generating a lock, and a step of hierarchical expansion process the new macro cell in the top layer.

Here, after the automatic layout step, the elements and wirings constituting the block are arranged in the block, and after this step, the hierarchy generation processing is performed.

Alternatively, an element and a wiring are previously arranged in a block of a cell as the logical unit, and then the block is arranged on the semiconductor chip. Here, the wiring route in the block is fixed, and another wiring terminal in the block is fixed, and the other wiring is rearranged.

Further, according to the present invention, after the hierarchical expansion processing,
A resistance simulation and a parasitic capacitance of the wiring are extracted from a wiring path between the blocks, and a logic simulation of the semiconductor integrated circuit is performed. Here, the logic simulation is performed for each macro cell corresponding to the block having the intra-block passing wiring path to adjust the resistance and the parasitic capacitance.

Alternatively, in the semiconductor integrated circuit layout designing method according to the present invention, in the hierarchical layout method for a semiconductor integrated circuit, a wiring passing through a block, that is, a passing wiring is buried in a lower hierarchy and information is added to a net list of the lower hierarchy. In order to match the process and the netlist information of the embedded wiring with the netlist of the logical design, a hierarchical operation is performed on the netlist, and the netlist of the embedded wiring is lifted to a higher hierarchy.

Here, in the layout of the embedded wiring in the block, a resistance formed on the wiring,
Attach the parasitic capacitance to the logic design netlist.

After the hierarchical operation on the netlist, a logic simulation of the semiconductor integrated circuit is performed.

In the layout design method for a semiconductor integrated circuit according to the present invention, a wiring area for a passing wiring is previously secured in the block, and the buried wiring is rearranged thereon.

As described above, according to the present invention, in the design of a semiconductor integrated circuit, in the automatic layout design for wiring connection between blocks corresponding to macro cells, if a passing wiring path in a block occurs, this passing wiring portion is blocked. Embed once inside. Then, the wiring in the block is arranged, and the final design in the block is performed. After this, a predetermined hierarchical development is performed, and the layout data for layout design and the circuit data for logic design of the pass-through wiring once embedded in the block are lifted to the uppermost hierarchy.

In this way, before and after the layout design, the physical arrangement such as the terminal position of each block boundary does not change, and the function of the macro cell in the logical design can be kept unchanged. Become. Then, the above-described problem is solved, and the above-described netlists at the time of the logic design and after the layout design match, and accurate back annotation including connection verification of the netlist and passing wiring can be performed.

[0027]

Next, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2
Fig. 4 is a flowchart showing a process which is a feature of the method of the present invention.

As shown in FIG. 1, according to the present invention, each macro cell after the hierarchical layout and the netlist of the upper hierarchy, R
First, an input process 1 for reading a C component or the like is performed. In the input process 1, a netlist of the hierarchy in which the passing wiring is generated, an RC component input, a netlist in a macro cell having the passing wiring, and an RC component are input.

Then, a hierarchy rearrangement process 2 for performing a hierarchy rearrangement for raising a passing wiring from a macro cell having a passing wiring to an upper hierarchy, and an output process 3 for outputting a netlist and RC components of the circuit after the hierarchy rearranging process 2 are performed. Have.

Next, the structure of the hierarchy rearrangement processing 2 for raising the passing wiring to the upper hierarchy will be described with reference to FIG.

In the hierarchy rearrangement process 2, as shown in FIG. 2, first, a macro cell having a passing wiring is designated, that is, a hierarchy designation process 21 is performed. Then, the macro cell name change processing 22 of the macro cell having the passing wiring is performed.

Next, in the hierarchy of the macro cell having the passing wiring, processing for separating and inputting a group of elements not related to the passing wiring and a group of nets and elements related to the passing wiring, that is, a processing 23 for specifying a passing wiring separation. I do.

Then, a hierarchy generation process 24 is performed in which a hierarchy composed of the above-mentioned cell group not connected to the passing wiring is set as a new macro cell. Here, the macro cell formed in the hierarchy generation processing 24 is formed one layer below the macro cell after the macro cell name change processing 22. Then, the terminal names of the terminals generated in the newly generated macro cell are the same as the terminal names of the macro cell after the macro cell name change processing 22.

Finally, the macro cell having the passing wiring, that is, the macro cell after the macro cell name change processing 22 is set to 1
By expanding the hierarchy, the passing wiring is raised to a higher hierarchy. That is, the hierarchical expansion processing 25 shown in FIG. 2 is performed.

Next, a detailed description will be given with reference to FIGS. Here, FIG.
6 are plan views of the LSI showing the physical information of the layout design in the order of the processing steps.

As shown in FIG. 3, blocks 32, 33, and 34, which become macro cells on a logic circuit, are arranged in the upper hierarchy 31. Here, terminals 35, 35a, 36, 36a, 3 are located at predetermined positions on the boundaries between the blocks 32, 33, 34.
7, 37a are respectively formed. However, specific elements have not yet been automatically laid out or arranged and wired (not formed) in each block.

Then, connection wiring between blocks arranged in the upper hierarchy 31 is performed by automatic layout. In this automatic layout, the terminal 35a of the block 32 and the terminal 36 of the block 33 are connected by the wiring 38. Then, the terminal 36 a of the block 33 and the terminal 37 a of the block 34 are connected by the wiring 39.

Then, the terminal 35 of the block 32 and the terminal 37 of the block 34 are connected by a passing wiring 40 so as to pass over the block 33. This means that
This is because the wiring length for connection is designed to be the shortest. Here, the block 33 corresponds to the macro cell having the passing wiring described in FIG.

Next, as shown in FIG. 4, the blocks 32 and 34 on the upper hierarchy 31 are left as they are, and the block 33 having the passing wiring 40 is changed to a block 41. here,
In the block 41, terminals 42 and 42a are newly formed where the passing wiring 40 described with reference to FIG. Also, the terminals 42,
The portion cut off at 42a is buried and the buried wiring 4
3 are formed. The terminals 36 and 36a are the same as those described in FIG.

Next, as shown in FIG.
Automatic layout in the block including the arrangement of
And an RC component composed of C1.

Then, a new block 44 is formed in a region where the embedding 43 is not formed. This new block 44 corresponds to the new macro cell formed in the hierarchy generation processing 24 described with reference to FIG. Here, the terminals 36 and 36a in the block 41 are copied to the block 44 as they are without changing their names.
In the block 44, specific elements 45 or wirings connecting these elements are formed, and R2 and C2 as RC components thereof are extracted.

Further, similarly, the other blocks 32,
Elements 46, 46a, 47, and 47a are also formed in 34.

Next, the data relating to the block 41 arranged in the upper hierarchy 31 is deleted from the automatic layout, and the terminals 36 and 36a and the terminals 42 and 42a of the block 41 are eliminated. Such processing is shown in FIG.
This corresponds to the hierarchical development processing 25 described in FIG.

As described above, as shown in FIG. 6, for example, blocks 32, 33 and 34 which are to be macro cells on a logic circuit are arranged in the upper hierarchy 31 such as a semiconductor chip. Here, each of the elements 4
Cell groups such as 6, 46a, 45, 47, 47a are formed.

Then, the blocks are connected to each other at the shortest distance from each other. That is, block 3
The terminal 35a of the second block and the terminal 36 of the block 33 are connected by a wiring 38, the terminal 36a of the block 33 and the terminal 37a of the block 34 are connected by a wiring 39.
2 and the terminal 37 of the block 34
0 is connected.

Further, the extracted R1 and R1
The C component is stored by being added to the data of the netlist of the upper hierarchy. Further, the RC components R2 and C2 are added to the data of the netlist of the block 33 as the lower hierarchy and stored.

Then, a final logic simulation of the semiconductor integrated circuit is performed. Here, since the information of the passing wiring is lifted from the netlist of the macrocell of the block having the passing wiring route to the netlist of the upper hierarchy, the logic simulation is performed for each of the upper hierarchy and the macrocell.

According to the method of this embodiment, it is possible to easily verify the net list after the logic design and the wiring connection after the layout design performed for each hierarchy. This is because the netlist of passing wiring added at the time of layout design does not exist in the macro cell corresponding to the block, and the connection terminals completely match after the logic design and after the layout design. is there.

As described above, according to the present invention, the netlists at the time of the logic design and after the layout design match, and the connection verification of the netlist and the accurate back annotation including the passing wiring can be performed.

Further, according to the present invention, the verification of the netlist after logic design and the wiring connection after layout design performed for each macrocell can be performed independently of other macrocells. The response becomes easy. That is, the short TAT (Turn Arrow) of the design
nd Time) is promoted.

In the above-described first embodiment, a case has been described in which, after the arrangement and wiring of the blocks are formed in the upper hierarchy, elements are formed in the blocks. Hereinafter, such a method is referred to as a top-down method.

Next, a case where the method of the present invention is applied to the bottom-up method in the second embodiment will be described with reference to FIGS. Here, FIGS. 7 to 10
2 is a plan view of an LSI showing a layout design in a process order. FIG.

As shown in FIG. 7, blocks 52, 53 and 54 are arranged in the upper hierarchy 51. Here, each block 5
2, 53, 54, the elements 55, 55a, 56
And 57, 57a are formed respectively. Also,
The terminals 58, 58a,
59, 59a, 60, 60a are respectively formed. This point is significantly different from the first embodiment.

Hereinafter, as in the first embodiment, connection wiring between blocks arranged in the upper hierarchy 51 is performed by automatic layout. That is, the terminal 58 a of the block 52 and the terminal 59 of the block 53 are connected by the wiring 61. Then, the terminal 59a of the block 53 and the terminal 60a of the block 54 are connected by the wiring 62.

Further, the terminal 58 of the block 52 and the terminal 60 of the block 54 are connected by a passing wiring 63 so as to pass over the block 53. In the block 53, a region for disposing the passing wiring 63 is roughly reserved in advance.

Next, as shown in FIG. 8, the blocks 52 and 54 on the upper hierarchy 51 are left as they are, and the block 53 having the passing wiring 63 is changed to a block 64. here,
In the block 53, the terminal 6
5, 65a is newly formed. Further, portions of the passing wiring 63 cut out by these terminals are buried to form a buried wiring 66. Here, the wiring connecting the elements in the block 64 is rearranged including the embedded wiring 66.

Thus, as shown in FIG. 8, the RC component composed of R3 and C3 of the embedded wiring 66 is extracted. Similarly, RC after the rearrangement of the wiring connecting element 56
The difference between the component and the RC component before rearrangement is R4,
Extracted as C4.

Next, as shown in FIG. 9, a new block 67 is formed one layer below the block 64. Here, the new block 67 includes the element 56 and the block 6
The terminals 59 and 59a which were in 4 are copied to the block 67 without any change in their names. It should be noted that all the element groups existing in the block 64 are moved to the block 67. The logical function of the macro cell corresponding to the block 67 is set to be the same as that of the macro cell corresponding to the previous block 53.

Next, the data relating to the block 64 arranged in the upper hierarchy 51 is deleted from the upper hierarchy 51 by changing the netlist. That is, the terminals 59 and 59a of the block 64 and the terminal 6
5,65a disappears.

As described above, as shown in FIG.
In the upper hierarchy 51, blocks 52, 53 and 54 which are to be macro cells on a logic circuit are arranged. Here, the elements 55, 55a, 56, 5
Cell groups such as 7, 57a are formed.

The blocks are connected and connected to each other so as to be the shortest distance from each other. That is, block 5
The second terminal 58a and the terminal 59 of the block 53 are connected. Here, RC components R4 and C4 are connected to this wiring. Also, the terminal 59a of the block 53
And the terminal 60a of the block 54 are connected by wiring. Then, as shown in FIG. 10, RC components of R4 and C4 may be formed in this wiring, or these RC components may be combined into one. Further, the terminal 5 of the block 52
8 and the terminal 60 of the block 54 are connected by the passing wiring 66.

The RC extracted as described above
The components are added to the data of the netlist of the upper hierarchy and stored.

Even in the case of the method of the second embodiment,
The same effect as described in the first embodiment is obtained.

As described above, in the description of the embodiment of the present invention, 3
A case has been described in which three macro cells, that is, three blocks, are arranged, and wiring between them is automatically laid out. The present invention is not limited to such a number of blocks. Further, even when a large number of passing wirings are formed on one block, a hierarchical layout is made in the same manner as described in the above embodiment.

[0065]

As described above, according to the layout design method of the semiconductor integrated circuit of the present invention, after the step of arranging the blocks on the upper hierarchy, the connection wiring is automatically reduced so that the wiring path between the blocks is shortened. A step of laying out, and after the automatic layout step, for a block through which wiring passes, that is, for a passing wiring path on a passing block, a terminal is generated at the boundary of the passing block, and a passing wiring portion of this block is generated. A step of embedding in a block, a layer having the terminal and the embedded wiring as an upper layer, and a layer generation processing step of generating a block corresponding to a new macro cell having a passing block as a lower layer; And performing a hierarchical expansion process at the uppermost layer.

According to the hierarchical layout design method of the present invention, it is possible to easily verify the netlist after the logic design and the wiring connection after the layout design for each macro cell.

Then, the netlist at the time of the logic design and the netlist after the layout design match, and the connection verification of the netlist and the accurate back annotation including the passing wiring can be performed.

This is because the netlist of the passing wiring added at the time of the layout design does not exist in the macro cell corresponding to the block, and the connection terminals completely match after the logic design and after the layout design. It is because you will be.

Further, according to the present invention, the verification of the netlist after the logic design and the wiring connection after the layout design performed for each macrocell can be performed independently of the other macrocells, so that the design can be performed quickly. And the TAT of the design is shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout design for explaining the present invention.

FIG. 2 is a flowchart illustrating a part of the flowchart in detail.

FIG. 3 is a plan view of an upper hierarchy for explaining a layout design process according to the first embodiment of this invention;

FIG. 4 is a plan view of an upper hierarchy for explaining a next process after the layout design process shown in FIG. 3;

FIG. 5 is a plan view of a layout for explaining a next process after the layout design process shown in FIG. 4;

FIG. 6 is a plan view of a layout for explaining a next process after the layout design process shown in FIG. 5;

FIG. 7 is a plan view of a layout for explaining a layout design process according to a second embodiment of the present invention.

FIG. 8 is a plan view of a layout for explaining a next process after the layout design process shown in FIG. 7;

FIG. 9 is a plan view of a layout for explaining a next process after the layout design process shown in FIG. 8;

FIG. 10 is a plan view of a layout for explaining the next process after the layout design process shown in FIG. 9;

FIG. 11 is a layout plan view for explaining a conventional layout design process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input processing 2 Hierarchical rearrangement processing 3 Output processing 21 Hierarchical specification processing 22 Macro cell name change processing 23 Passing wiring separation specification processing 24 Hierarchical generation processing 25 Hierarchical development processing 31, 51, 101 Upper hierarchy 32, 33, 34, 41, 44, 52, 53, 54, 6
4, 67, 102 103, 104 blocks (lower hierarchy) 45, 46, 46a, 47, 47a, 55, 55a, 5
6, 57, 57a 105, 105a, 107, 109,
109a element 35, 35a, 36, 36a, 37, 37a, 58, 5
8a, 59, 59a60, 60a, 106, 106a,
108, 108a, 110, 110a terminals 38, 39, 61, 62, 111, 112, 113
Wiring 40, 63 Passing wiring 43, 66 Embedded wiring R1, R2, R3, R4 Parasitic resistance C1, C2, C3, C4 Parasitic capacitance

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (10)

(57) [Claims] In a hierarchical layout design for arranging blocks corresponding to macro cells having a predetermined logic function in an upper hierarchy and connecting and wiring the blocks in the upper hierarchy, after arranging the blocks on the upper hierarchy, A step of automatically laying out connection wiring so that a wiring path between the blocks is shortened; and, after the automatic layout step, a block through which a wiring passes, that is, a passing wiring path on a passing block; Generating a terminal at the boundary of the block, embedding a passing wiring portion of the block in the block, and setting a layer having the terminal and the embedded wiring to an upper layer and a new macro cell having the passing block as a lower layer. A layer generation processing step of generating a corresponding block, and a hierarchical expansion of the new macro cell at the top layer And a step of performing an open process. 2. The method according to claim 1, further comprising, after the hierarchical generation processing step, arranging elements and wiring constituting the block in the block. 3. The method according to claim 1, further comprising arranging elements and wirings in the block in advance, and then arranging the block in the upper hierarchy. 4. The hierarchical layout design method for a semiconductor integrated circuit according to claim 3, wherein a route of the wiring on the block is fixed, and another wiring terminal in the block is fixed to rearrange the other wiring. 4. The method of designing a hierarchical layout of a semiconductor integrated circuit according to claim 3, wherein: 5. The logic simulation of a semiconductor integrated circuit by extracting a resistance and a parasitic capacitance of the wiring from a wiring path between the blocks after the hierarchical development processing. Item 5. The hierarchical layout design method for a semiconductor integrated circuit according to Item 4. 6. The hierarchical layout design method for a semiconductor integrated circuit according to claim 5, wherein said logic simulation is performed for each macro cell of a block having a passing wiring path on said block to adjust said resistance and parasitic capacitance. . 7. A layer layout method for a semiconductor integrated circuit, wherein a wiring passing over a block, that is, a passing wiring is embedded in a lower hierarchy and information is added to a lower layer netlist, and the netlist information of the embedded wiring is logically converted. A hierarchical layout design method for a semiconductor integrated circuit, wherein a hierarchical operation is performed on a netlist to raise the netlist of the embedded wiring to an upper hierarchy in order to match the netlist of the design. 8. The semiconductor integrated circuit according to claim 7, wherein, in a layout of the embedded wiring in the block, a resistance and a parasitic capacitance formed in the wiring are pasted to a netlist of a logic design. Hierarchical layout design method. 9. After the hierarchical operation on the netlist,
9. The hierarchical layout design method for a semiconductor integrated circuit according to claim 7, wherein a logic simulation of the semiconductor integrated circuit is performed. 10. The semiconductor according to claim 7, wherein a wiring area for a passing wiring is previously secured in the block, and the embedded wiring is rearranged. Hierarchical layout design method for integrated circuits.